1
2
3
4
5
6#ifndef __QLA_DEF_H
7#define __QLA_DEF_H
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/module.h>
13#include <linux/list.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/dmapool.h>
19#include <linux/mempool.h>
20#include <linux/spinlock.h>
21#include <linux/completion.h>
22#include <linux/interrupt.h>
23#include <linux/workqueue.h>
24#include <linux/firmware.h>
25#include <linux/aer.h>
26#include <linux/mutex.h>
27#include <linux/btree.h>
28
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
33#include <scsi/scsi_transport_fc.h>
34#include <scsi/scsi_bsg_fc.h>
35
36#include <uapi/scsi/fc/fc_els.h>
37
38
39typedef struct {
40 uint8_t domain;
41 uint8_t area;
42 uint8_t al_pa;
43} be_id_t;
44
45
46typedef struct {
47 uint8_t al_pa;
48 uint8_t area;
49 uint8_t domain;
50} le_id_t;
51
52
53
54
55typedef union {
56 uint32_t b24 : 24;
57 struct {
58#ifdef __BIG_ENDIAN
59 uint8_t domain;
60 uint8_t area;
61 uint8_t al_pa;
62#elif defined(__LITTLE_ENDIAN)
63 uint8_t al_pa;
64 uint8_t area;
65 uint8_t domain;
66#else
67#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
68#endif
69 uint8_t rsvd_1;
70 } b;
71} port_id_t;
72#define INVALID_PORT_ID 0xFFFFFF
73
74#include "qla_bsg.h"
75#include "qla_dsd.h"
76#include "qla_nx.h"
77#include "qla_nx2.h"
78#include "qla_nvme.h"
79#define QLA2XXX_DRIVER_NAME "qla2xxx"
80#define QLA2XXX_APIDEV "ql2xapidev"
81#define QLA2XXX_MANUFACTURER "QLogic Corporation"
82
83
84
85
86
87
88#define MAILBOX_REGISTER_COUNT_2100 8
89#define MAILBOX_REGISTER_COUNT_2200 24
90#define MAILBOX_REGISTER_COUNT 32
91
92#define QLA2200A_RISC_ROM_VER 4
93#define FPM_2300 6
94#define FPM_2310 7
95
96#include "qla_settings.h"
97
98#define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
99
100
101
102
103#define BIT_0 0x1
104#define BIT_1 0x2
105#define BIT_2 0x4
106#define BIT_3 0x8
107#define BIT_4 0x10
108#define BIT_5 0x20
109#define BIT_6 0x40
110#define BIT_7 0x80
111#define BIT_8 0x100
112#define BIT_9 0x200
113#define BIT_10 0x400
114#define BIT_11 0x800
115#define BIT_12 0x1000
116#define BIT_13 0x2000
117#define BIT_14 0x4000
118#define BIT_15 0x8000
119#define BIT_16 0x10000
120#define BIT_17 0x20000
121#define BIT_18 0x40000
122#define BIT_19 0x80000
123#define BIT_20 0x100000
124#define BIT_21 0x200000
125#define BIT_22 0x400000
126#define BIT_23 0x800000
127#define BIT_24 0x1000000
128#define BIT_25 0x2000000
129#define BIT_26 0x4000000
130#define BIT_27 0x8000000
131#define BIT_28 0x10000000
132#define BIT_29 0x20000000
133#define BIT_30 0x40000000
134#define BIT_31 0x80000000
135
136#define LSB(x) ((uint8_t)(x))
137#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
138
139#define LSW(x) ((uint16_t)(x))
140#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
141
142#define LSD(x) ((uint32_t)((uint64_t)(x)))
143#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
144
145static inline uint32_t make_handle(uint16_t x, uint16_t y)
146{
147 return ((uint32_t)x << 16) | y;
148}
149
150
151
152
153
154static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
155{
156 return readb(addr);
157}
158
159static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
160{
161 return readw(addr);
162}
163
164static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
165{
166 return readl(addr);
167}
168
169static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
170{
171 return readb_relaxed(addr);
172}
173
174static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
175{
176 return readw_relaxed(addr);
177}
178
179static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
180{
181 return readl_relaxed(addr);
182}
183
184static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
185{
186 return writeb(data, addr);
187}
188
189static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
190{
191 return writew(data, addr);
192}
193
194static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
195{
196 return writel(data, addr);
197}
198
199
200
201
202#define QLA83XX_LED_PORT0 0x00201320
203#define QLA83XX_LED_PORT1 0x00201328
204#define QLA83XX_IDC_DEV_STATE 0x22102384
205#define QLA83XX_IDC_MAJOR_VERSION 0x22102380
206#define QLA83XX_IDC_MINOR_VERSION 0x22102398
207#define QLA83XX_IDC_DRV_PRESENCE 0x22102388
208#define QLA83XX_IDC_DRIVER_ACK 0x2210238c
209#define QLA83XX_IDC_CONTROL 0x22102390
210#define QLA83XX_IDC_AUDIT 0x22102394
211#define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
212#define QLA83XX_DRIVER_LOCKID 0x22102104
213#define QLA83XX_DRIVER_LOCK 0x8111c028
214#define QLA83XX_DRIVER_UNLOCK 0x8111c02c
215#define QLA83XX_FLASH_LOCKID 0x22102100
216#define QLA83XX_FLASH_LOCK 0x8111c010
217#define QLA83XX_FLASH_UNLOCK 0x8111c014
218#define QLA83XX_DEV_PARTINFO1 0x221023e0
219#define QLA83XX_DEV_PARTINFO2 0x221023e4
220#define QLA83XX_FW_HEARTBEAT 0x221020b0
221#define QLA83XX_PEG_HALT_STATUS1 0x221020a8
222#define QLA83XX_PEG_HALT_STATUS2 0x221020ac
223
224
225#define IDC_DEVICE_STATE_CHANGE BIT_0
226#define IDC_PEG_HALT_STATUS_CHANGE BIT_1
227#define IDC_NIC_FW_REPORTED_FAILURE BIT_2
228#define IDC_HEARTBEAT_FAILURE BIT_3
229
230
231#define ERR_LEVEL_NON_FATAL 0x1
232#define ERR_LEVEL_RECOVERABLE_FATAL 0x2
233#define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
234
235
236#define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
237#define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
238
239
240#define QLA83XX_NIC_CORE_RESET 0x1
241#define QLA83XX_IDC_STATE_HANDLER 0x2
242#define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
243
244
245#define QLA83XX_IDC_RESET_DISABLED BIT_0
246#define QLA83XX_IDC_GRACEFUL_RESET BIT_1
247
248
249#define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
250#define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
251#define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
252
253
254#define QLA83XX_CLASS_TYPE_NONE 0x0
255#define QLA83XX_CLASS_TYPE_NIC 0x1
256#define QLA83XX_CLASS_TYPE_FCOE 0x2
257#define QLA83XX_CLASS_TYPE_ISCSI 0x3
258
259
260#define IDC_LOCK_RECOVERY_STAGE1 0x1
261
262
263#define IDC_LOCK_RECOVERY_STAGE2 0x2
264
265
266#define IDC_AUDIT_TIMESTAMP 0x0
267
268
269
270#define IDC_AUDIT_COMPLETION 0x1
271
272
273
274
275#define PORT_0_2031 0x00201340
276#define PORT_1_2031 0x00201350
277#define LASER_ON_2031 0x01800100
278#define LASER_OFF_2031 0x01800180
279
280
281
282
283
284#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
285#define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
286
287
288
289
290#define WWN_SIZE 8
291#define MAX_FIBRE_DEVICES_2100 512
292#define MAX_FIBRE_DEVICES_2400 2048
293#define MAX_FIBRE_DEVICES_LOOP 128
294#define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
295#define LOOPID_MAP_SIZE (ha->max_fibre_devices)
296#define MAX_FIBRE_LUNS 0xFFFF
297#define MAX_HOST_COUNT 16
298
299
300
301
302#define MAX_BUSES 1
303#define MIN_LUNS 8
304#define MAX_LUNS MAX_FIBRE_LUNS
305#define MAX_CMDS_PER_LUN 255
306
307
308
309
310#define SNS_LAST_LOOP_ID_2100 0xfe
311#define SNS_LAST_LOOP_ID_2300 0x7ff
312
313#define LAST_LOCAL_LOOP_ID 0x7d
314#define SNS_FL_PORT 0x7e
315#define FABRIC_CONTROLLER 0x7f
316#define SIMPLE_NAME_SERVER 0x80
317#define SNS_FIRST_LOOP_ID 0x81
318#define MANAGEMENT_SERVER 0xfe
319#define BROADCAST 0xff
320
321
322
323
324
325#define NPH_LAST_HANDLE 0x7ee
326#define NPH_MGMT_SERVER 0x7ef
327#define NPH_SNS 0x7fc
328#define NPH_FABRIC_CONTROLLER 0x7fd
329#define NPH_F_PORT 0x7fe
330#define NPH_IP_BROADCAST 0x7ff
331
332#define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
333
334#define MAX_CMDSZ 16
335#include "qla_fw.h"
336
337struct name_list_extended {
338 struct get_name_list_extended *l;
339 dma_addr_t ldma;
340 struct list_head fcports;
341 u32 size;
342 u8 sent;
343};
344
345struct els_reject {
346 struct fc_els_ls_rjt *c;
347 dma_addr_t cdma;
348 u16 size;
349};
350
351
352
353
354#define PORT_RETRY_TIME 1
355#define LOOP_DOWN_TIMEOUT 60
356#define LOOP_DOWN_TIME 255
357#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
358
359#define DEFAULT_OUTSTANDING_COMMANDS 4096
360#define MIN_OUTSTANDING_COMMANDS 128
361
362
363#define REQUEST_ENTRY_CNT_2100 128
364#define REQUEST_ENTRY_CNT_2200 2048
365#define REQUEST_ENTRY_CNT_24XX 2048
366#define REQUEST_ENTRY_CNT_83XX 8192
367#define RESPONSE_ENTRY_CNT_83XX 4096
368#define RESPONSE_ENTRY_CNT_2100 64
369#define RESPONSE_ENTRY_CNT_2300 512
370#define RESPONSE_ENTRY_CNT_MQ 128
371#define ATIO_ENTRY_CNT_24XX 4096
372#define RESPONSE_ENTRY_CNT_FX00 256
373#define FW_DEF_EXCHANGES_CNT 2048
374#define FW_MAX_EXCHANGES_CNT (32 * 1024)
375#define REDUCE_EXCHANGES_CNT (8 * 1024)
376
377#define SET_DID_STATUS(stat_var, status) (stat_var = status << 16)
378
379struct req_que;
380struct qla_tgt_sess;
381
382
383
384
385struct srb_cmd {
386 struct scsi_cmnd *cmd;
387 uint32_t request_sense_length;
388 uint32_t fw_sense_length;
389 uint8_t *request_sense_ptr;
390 struct ct6_dsd *ct6_ctx;
391 struct crc_context *crc_ctx;
392};
393
394
395
396
397#define SRB_DMA_VALID BIT_0
398#define SRB_FCP_CMND_DMA_VALID BIT_12
399#define SRB_CRC_CTX_DMA_VALID BIT_2
400#define SRB_CRC_PROT_DMA_VALID BIT_4
401#define SRB_CRC_CTX_DSD_VALID BIT_5
402#define SRB_WAKEUP_ON_COMP BIT_6
403#define SRB_DIF_BUNDL_DMA_VALID BIT_7
404#define SRB_EDIF_CLEANUP_DELETE BIT_9
405
406
407#define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
408#define ISP_REG16_DISCONNECT 0xFFFF
409
410static inline le_id_t be_id_to_le(be_id_t id)
411{
412 le_id_t res;
413
414 res.domain = id.domain;
415 res.area = id.area;
416 res.al_pa = id.al_pa;
417
418 return res;
419}
420
421static inline be_id_t le_id_to_be(le_id_t id)
422{
423 be_id_t res;
424
425 res.domain = id.domain;
426 res.area = id.area;
427 res.al_pa = id.al_pa;
428
429 return res;
430}
431
432static inline port_id_t be_to_port_id(be_id_t id)
433{
434 port_id_t res;
435
436 res.b.domain = id.domain;
437 res.b.area = id.area;
438 res.b.al_pa = id.al_pa;
439 res.b.rsvd_1 = 0;
440
441 return res;
442}
443
444static inline be_id_t port_id_to_be_id(port_id_t port_id)
445{
446 be_id_t res;
447
448 res.domain = port_id.b.domain;
449 res.area = port_id.b.area;
450 res.al_pa = port_id.b.al_pa;
451
452 return res;
453}
454
455struct els_logo_payload {
456 uint8_t opcode;
457 uint8_t rsvd[3];
458 uint8_t s_id[3];
459 uint8_t rsvd1[1];
460 uint8_t wwpn[WWN_SIZE];
461};
462
463struct els_plogi_payload {
464 uint8_t opcode;
465 uint8_t rsvd[3];
466 __be32 data[112 / 4];
467};
468
469struct ct_arg {
470 void *iocb;
471 u16 nport_handle;
472 dma_addr_t req_dma;
473 dma_addr_t rsp_dma;
474 u32 req_size;
475 u32 rsp_size;
476 u32 req_allocated_size;
477 u32 rsp_allocated_size;
478 void *req;
479 void *rsp;
480 port_id_t id;
481};
482
483
484
485
486struct srb_iocb {
487 union {
488 struct {
489 uint16_t flags;
490#define SRB_LOGIN_RETRIED BIT_0
491#define SRB_LOGIN_COND_PLOGI BIT_1
492#define SRB_LOGIN_SKIP_PRLI BIT_2
493#define SRB_LOGIN_NVME_PRLI BIT_3
494#define SRB_LOGIN_PRLI_ONLY BIT_4
495#define SRB_LOGIN_FCSP BIT_5
496 uint16_t data[2];
497 u32 iop[2];
498 } logio;
499 struct {
500#define ELS_DCMD_TIMEOUT 20
501#define ELS_DCMD_LOGO 0x5
502 uint32_t flags;
503 uint32_t els_cmd;
504 struct completion comp;
505 struct els_logo_payload *els_logo_pyld;
506 dma_addr_t els_logo_pyld_dma;
507 } els_logo;
508 struct els_plogi {
509#define ELS_DCMD_PLOGI 0x3
510 uint32_t flags;
511 uint32_t els_cmd;
512 struct completion comp;
513 struct els_plogi_payload *els_plogi_pyld;
514 struct els_plogi_payload *els_resp_pyld;
515 u32 tx_size;
516 u32 rx_size;
517 dma_addr_t els_plogi_pyld_dma;
518 dma_addr_t els_resp_pyld_dma;
519 __le32 fw_status[3];
520 __le16 comp_status;
521 __le16 len;
522 } els_plogi;
523 struct {
524
525
526
527
528
529 uint64_t lun;
530 uint32_t flags;
531 uint32_t data;
532 struct completion comp;
533 __le16 comp_status;
534 } tmf;
535 struct {
536#define SRB_FXDISC_REQ_DMA_VALID BIT_0
537#define SRB_FXDISC_RESP_DMA_VALID BIT_1
538#define SRB_FXDISC_REQ_DWRD_VALID BIT_2
539#define SRB_FXDISC_RSP_DWRD_VALID BIT_3
540#define FXDISC_TIMEOUT 20
541 uint8_t flags;
542 uint32_t req_len;
543 uint32_t rsp_len;
544 void *req_addr;
545 void *rsp_addr;
546 dma_addr_t req_dma_handle;
547 dma_addr_t rsp_dma_handle;
548 __le32 adapter_id;
549 __le32 adapter_id_hi;
550 __le16 req_func_type;
551 __le32 req_data;
552 __le32 req_data_extra;
553 __le32 result;
554 __le32 seq_number;
555 __le16 fw_flags;
556 struct completion fxiocb_comp;
557 __le32 reserved_0;
558 uint8_t reserved_1;
559 } fxiocb;
560 struct {
561 uint32_t cmd_hndl;
562 __le16 comp_status;
563 __le16 req_que_no;
564 struct completion comp;
565 } abt;
566 struct ct_arg ctarg;
567#define MAX_IOCB_MB_REG 28
568#define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
569 struct {
570 u16 in_mb[MAX_IOCB_MB_REG];
571 u16 out_mb[MAX_IOCB_MB_REG];
572 void *out, *in;
573 dma_addr_t out_dma, in_dma;
574 struct completion comp;
575 int rc;
576 } mbx;
577 struct {
578 struct imm_ntfy_from_isp *ntfy;
579 } nack;
580 struct {
581 __le16 comp_status;
582 __le16 rsp_pyld_len;
583 uint8_t aen_op;
584 void *desc;
585
586
587 int cmd_len;
588 int rsp_len;
589 dma_addr_t cmd_dma;
590 dma_addr_t rsp_dma;
591 enum nvmefc_fcp_datadir dir;
592 uint32_t dl;
593 uint32_t timeout_sec;
594 struct list_head entry;
595 } nvme;
596 struct {
597 u16 cmd;
598 u16 vp_index;
599 } ctrlvp;
600 struct {
601 struct edif_sa_ctl *sa_ctl;
602 struct qla_sa_update_frame sa_frame;
603 } sa_update;
604 } u;
605
606 struct timer_list timer;
607 void (*timeout)(void *);
608};
609
610
611#define SRB_LOGIN_CMD 1
612#define SRB_LOGOUT_CMD 2
613#define SRB_ELS_CMD_RPT 3
614#define SRB_ELS_CMD_HST 4
615#define SRB_CT_CMD 5
616#define SRB_ADISC_CMD 6
617#define SRB_TM_CMD 7
618#define SRB_SCSI_CMD 8
619#define SRB_BIDI_CMD 9
620#define SRB_FXIOCB_DCMD 10
621#define SRB_FXIOCB_BCMD 11
622#define SRB_ABT_CMD 12
623#define SRB_ELS_DCMD 13
624#define SRB_MB_IOCB 14
625#define SRB_CT_PTHRU_CMD 15
626#define SRB_NACK_PLOGI 16
627#define SRB_NACK_PRLI 17
628#define SRB_NACK_LOGO 18
629#define SRB_NVME_CMD 19
630#define SRB_NVME_LS 20
631#define SRB_PRLI_CMD 21
632#define SRB_CTRL_VP 22
633#define SRB_PRLO_CMD 23
634#define SRB_SA_UPDATE 25
635#define SRB_ELS_CMD_HST_NOLOGIN 26
636#define SRB_SA_REPLACE 27
637
638struct qla_els_pt_arg {
639 u8 els_opcode;
640 u8 vp_idx;
641 __le16 nport_handle;
642 u16 control_flags;
643 __le32 rx_xchg_address;
644 port_id_t did;
645 u32 tx_len, tx_byte_count, rx_len, rx_byte_count;
646 dma_addr_t tx_addr, rx_addr;
647
648};
649
650enum {
651 TYPE_SRB,
652 TYPE_TGT_CMD,
653 TYPE_TGT_TMCMD,
654};
655
656struct iocb_resource {
657 u8 res_type;
658 u8 pad;
659 u16 iocb_cnt;
660};
661
662struct bsg_cmd {
663 struct bsg_job *bsg_job;
664 union {
665 struct qla_els_pt_arg els_arg;
666 } u;
667};
668
669typedef struct srb {
670
671
672
673
674 uint8_t cmd_type;
675 uint8_t pad[3];
676 struct iocb_resource iores;
677 struct kref cmd_kref;
678 void *priv;
679 wait_queue_head_t nvme_ls_waitq;
680 struct fc_port *fcport;
681 struct scsi_qla_host *vha;
682 unsigned int start_timer:1;
683
684 uint32_t handle;
685 uint16_t flags;
686 uint16_t type;
687 const char *name;
688 int iocbs;
689 struct qla_qpair *qpair;
690 struct srb *cmd_sp;
691 struct list_head elem;
692 u32 gen1;
693 u32 gen2;
694 int rc;
695 int retry_count;
696 struct completion *comp;
697 union {
698 struct srb_iocb iocb_cmd;
699 struct bsg_job *bsg_job;
700 struct srb_cmd scmd;
701 struct bsg_cmd bsg_cmd;
702 } u;
703 struct {
704 bool remapped;
705 struct {
706 dma_addr_t dma;
707 void *buf;
708 uint len;
709 } req;
710 struct {
711 dma_addr_t dma;
712 void *buf;
713 uint len;
714 } rsp;
715 } remap;
716
717
718
719
720
721 void (*done)(struct srb *sp, int res);
722
723 void (*free)(struct srb *sp);
724
725
726
727
728 void (*put_fn)(struct kref *kref);
729} srb_t;
730
731#define GET_CMD_SP(sp) (sp->u.scmd.cmd)
732
733#define GET_CMD_SENSE_LEN(sp) \
734 (sp->u.scmd.request_sense_length)
735#define SET_CMD_SENSE_LEN(sp, len) \
736 (sp->u.scmd.request_sense_length = len)
737#define GET_CMD_SENSE_PTR(sp) \
738 (sp->u.scmd.request_sense_ptr)
739#define SET_CMD_SENSE_PTR(sp, ptr) \
740 (sp->u.scmd.request_sense_ptr = ptr)
741#define GET_FW_SENSE_LEN(sp) \
742 (sp->u.scmd.fw_sense_length)
743#define SET_FW_SENSE_LEN(sp, len) \
744 (sp->u.scmd.fw_sense_length = len)
745
746struct msg_echo_lb {
747 dma_addr_t send_dma;
748 dma_addr_t rcv_dma;
749 uint16_t req_sg_cnt;
750 uint16_t rsp_sg_cnt;
751 uint16_t options;
752 uint32_t transfer_size;
753 uint32_t iteration_count;
754};
755
756
757
758
759struct device_reg_2xxx {
760 __le16 flash_address;
761 __le16 flash_data;
762 __le16 unused_1[1];
763 __le16 ctrl_status;
764#define CSR_FLASH_64K_BANK BIT_3
765#define CSR_FLASH_ENABLE BIT_1
766#define CSR_ISP_SOFT_RESET BIT_0
767
768 __le16 ictrl;
769#define ICR_EN_INT BIT_15
770#define ICR_EN_RISC BIT_3
771
772 __le16 istatus;
773#define ISR_RISC_INT BIT_3
774
775 __le16 semaphore;
776 __le16 nvram;
777#define NVR_DESELECT 0
778#define NVR_BUSY BIT_15
779#define NVR_WRT_ENABLE BIT_14
780#define NVR_PR_ENABLE BIT_13
781#define NVR_DATA_IN BIT_3
782#define NVR_DATA_OUT BIT_2
783#define NVR_SELECT BIT_1
784#define NVR_CLOCK BIT_0
785
786#define NVR_WAIT_CNT 20000
787
788 union {
789 struct {
790 __le16 mailbox0;
791 __le16 mailbox1;
792 __le16 mailbox2;
793 __le16 mailbox3;
794 __le16 mailbox4;
795 __le16 mailbox5;
796 __le16 mailbox6;
797 __le16 mailbox7;
798 __le16 unused_2[59];
799 } __attribute__((packed)) isp2100;
800 struct {
801
802 __le16 req_q_in;
803 __le16 req_q_out;
804
805 __le16 rsp_q_in;
806 __le16 rsp_q_out;
807
808
809 __le32 host_status;
810#define HSR_RISC_INT BIT_15
811#define HSR_RISC_PAUSED BIT_8
812
813
814 __le16 host_semaphore;
815 __le16 unused_3[17];
816 __le16 mailbox0;
817 __le16 mailbox1;
818 __le16 mailbox2;
819 __le16 mailbox3;
820 __le16 mailbox4;
821 __le16 mailbox5;
822 __le16 mailbox6;
823 __le16 mailbox7;
824 __le16 mailbox8;
825 __le16 mailbox9;
826 __le16 mailbox10;
827 __le16 mailbox11;
828 __le16 mailbox12;
829 __le16 mailbox13;
830 __le16 mailbox14;
831 __le16 mailbox15;
832 __le16 mailbox16;
833 __le16 mailbox17;
834 __le16 mailbox18;
835 __le16 mailbox19;
836 __le16 mailbox20;
837 __le16 mailbox21;
838 __le16 mailbox22;
839 __le16 mailbox23;
840 __le16 mailbox24;
841 __le16 mailbox25;
842 __le16 mailbox26;
843 __le16 mailbox27;
844 __le16 mailbox28;
845 __le16 mailbox29;
846 __le16 mailbox30;
847 __le16 mailbox31;
848 __le16 fb_cmd;
849 __le16 unused_4[10];
850 } __attribute__((packed)) isp2300;
851 } u;
852
853 __le16 fpm_diag_config;
854 __le16 unused_5[0x4];
855 __le16 risc_hw;
856 __le16 unused_5_1;
857 __le16 pcr;
858 __le16 unused_6[0x5];
859 __le16 mctr;
860 __le16 unused_7[0x3];
861 __le16 fb_cmd_2100;
862 __le16 unused_8[0x3];
863 __le16 hccr;
864#define HCCR_HOST_INT BIT_7
865#define HCCR_RISC_PAUSE BIT_5
866
867#define HCCR_RESET_RISC 0x1000
868#define HCCR_PAUSE_RISC 0x2000
869#define HCCR_RELEASE_RISC 0x3000
870#define HCCR_SET_HOST_INT 0x5000
871#define HCCR_CLR_HOST_INT 0x6000
872#define HCCR_CLR_RISC_INT 0x7000
873#define HCCR_DISABLE_PARITY_PAUSE 0x4001
874#define HCCR_ENABLE_PARITY 0xA000
875
876 __le16 unused_9[5];
877 __le16 gpiod;
878 __le16 gpioe;
879#define GPIO_LED_MASK 0x00C0
880#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
881#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
882#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
883#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
884#define GPIO_LED_ALL_OFF 0x0000
885#define GPIO_LED_RED_ON_OTHER_OFF 0x0001
886#define GPIO_LED_RGA_ON 0x00C1
887
888 union {
889 struct {
890 __le16 unused_10[8];
891 __le16 mailbox8;
892 __le16 mailbox9;
893 __le16 mailbox10;
894 __le16 mailbox11;
895 __le16 mailbox12;
896 __le16 mailbox13;
897 __le16 mailbox14;
898 __le16 mailbox15;
899 __le16 mailbox16;
900 __le16 mailbox17;
901 __le16 mailbox18;
902 __le16 mailbox19;
903 __le16 mailbox20;
904 __le16 mailbox21;
905 __le16 mailbox22;
906 __le16 mailbox23;
907 } __attribute__((packed)) isp2200;
908 } u_end;
909};
910
911struct device_reg_25xxmq {
912 __le32 req_q_in;
913 __le32 req_q_out;
914 __le32 rsp_q_in;
915 __le32 rsp_q_out;
916 __le32 atio_q_in;
917 __le32 atio_q_out;
918};
919
920
921struct device_reg_fx00 {
922 __le32 mailbox0;
923 __le32 mailbox1;
924 __le32 mailbox2;
925 __le32 mailbox3;
926 __le32 mailbox4;
927 __le32 mailbox5;
928 __le32 mailbox6;
929 __le32 mailbox7;
930 __le32 mailbox8;
931 __le32 mailbox9;
932 __le32 mailbox10;
933 __le32 mailbox11;
934 __le32 mailbox12;
935 __le32 mailbox13;
936 __le32 mailbox14;
937 __le32 mailbox15;
938 __le32 mailbox16;
939 __le32 mailbox17;
940 __le32 mailbox18;
941 __le32 mailbox19;
942 __le32 mailbox20;
943 __le32 mailbox21;
944 __le32 mailbox22;
945 __le32 mailbox23;
946 __le32 mailbox24;
947 __le32 mailbox25;
948 __le32 mailbox26;
949 __le32 mailbox27;
950 __le32 mailbox28;
951 __le32 mailbox29;
952 __le32 mailbox30;
953 __le32 mailbox31;
954 __le32 aenmailbox0;
955 __le32 aenmailbox1;
956 __le32 aenmailbox2;
957 __le32 aenmailbox3;
958 __le32 aenmailbox4;
959 __le32 aenmailbox5;
960 __le32 aenmailbox6;
961 __le32 aenmailbox7;
962
963 __le32 req_q_in;
964 __le32 req_q_out;
965
966 __le32 rsp_q_in;
967 __le32 rsp_q_out;
968
969 __le32 initval0;
970 __le32 initval1;
971 __le32 initval2;
972 __le32 initval3;
973 __le32 initval4;
974 __le32 initval5;
975 __le32 initval6;
976 __le32 initval7;
977 __le32 fwheartbeat;
978 __le32 pseudoaen;
979};
980
981
982
983typedef union {
984 struct device_reg_2xxx isp;
985 struct device_reg_24xx isp24;
986 struct device_reg_25xxmq isp25mq;
987 struct device_reg_82xx isp82;
988 struct device_reg_fx00 ispfx00;
989} __iomem device_reg_t;
990
991#define ISP_REQ_Q_IN(ha, reg) \
992 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
993 &(reg)->u.isp2100.mailbox4 : \
994 &(reg)->u.isp2300.req_q_in)
995#define ISP_REQ_Q_OUT(ha, reg) \
996 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
997 &(reg)->u.isp2100.mailbox4 : \
998 &(reg)->u.isp2300.req_q_out)
999#define ISP_RSP_Q_IN(ha, reg) \
1000 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1001 &(reg)->u.isp2100.mailbox5 : \
1002 &(reg)->u.isp2300.rsp_q_in)
1003#define ISP_RSP_Q_OUT(ha, reg) \
1004 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1005 &(reg)->u.isp2100.mailbox5 : \
1006 &(reg)->u.isp2300.rsp_q_out)
1007
1008#define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
1009#define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
1010
1011#define MAILBOX_REG(ha, reg, num) \
1012 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1013 (num < 8 ? \
1014 &(reg)->u.isp2100.mailbox0 + (num) : \
1015 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
1016 &(reg)->u.isp2300.mailbox0 + (num))
1017#define RD_MAILBOX_REG(ha, reg, num) \
1018 rd_reg_word(MAILBOX_REG(ha, reg, num))
1019#define WRT_MAILBOX_REG(ha, reg, num, data) \
1020 wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
1021
1022#define FB_CMD_REG(ha, reg) \
1023 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1024 &(reg)->fb_cmd_2100 : \
1025 &(reg)->u.isp2300.fb_cmd)
1026#define RD_FB_CMD_REG(ha, reg) \
1027 rd_reg_word(FB_CMD_REG(ha, reg))
1028#define WRT_FB_CMD_REG(ha, reg, data) \
1029 wrt_reg_word(FB_CMD_REG(ha, reg), data)
1030
1031typedef struct {
1032 uint32_t out_mb;
1033 uint32_t in_mb;
1034 uint16_t mb[MAILBOX_REGISTER_COUNT];
1035 long buf_size;
1036 void *bufp;
1037 uint32_t tov;
1038 uint8_t flags;
1039#define MBX_DMA_IN BIT_0
1040#define MBX_DMA_OUT BIT_1
1041#define IOCTL_CMD BIT_2
1042} mbx_cmd_t;
1043
1044struct mbx_cmd_32 {
1045 uint32_t out_mb;
1046 uint32_t in_mb;
1047 uint32_t mb[MAILBOX_REGISTER_COUNT];
1048 long buf_size;
1049 void *bufp;
1050 uint32_t tov;
1051 uint8_t flags;
1052#define MBX_DMA_IN BIT_0
1053#define MBX_DMA_OUT BIT_1
1054#define IOCTL_CMD BIT_2
1055};
1056
1057
1058#define MBX_TOV_SECONDS 30
1059
1060
1061
1062
1063#define PROD_ID_1 0x4953
1064#define PROD_ID_2 0x0000
1065#define PROD_ID_2a 0x5020
1066#define PROD_ID_3 0x2020
1067
1068
1069
1070
1071#define MBS_FRM_ALIVE 0
1072#define MBS_CHKSUM_ERR 1
1073#define MBS_BUSY 4
1074
1075
1076
1077
1078#define MBS_COMMAND_COMPLETE 0x4000
1079#define MBS_INVALID_COMMAND 0x4001
1080#define MBS_HOST_INTERFACE_ERROR 0x4002
1081#define MBS_TEST_FAILED 0x4003
1082#define MBS_COMMAND_ERROR 0x4005
1083#define MBS_COMMAND_PARAMETER_ERROR 0x4006
1084#define MBS_PORT_ID_USED 0x4007
1085#define MBS_LOOP_ID_USED 0x4008
1086#define MBS_ALL_IDS_IN_USE 0x4009
1087#define MBS_NOT_LOGGED_IN 0x400A
1088#define MBS_LINK_DOWN_ERROR 0x400B
1089#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1090
1091static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
1092{
1093 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1094}
1095
1096
1097
1098
1099#define MBA_ASYNC_EVENT 0x8000
1100#define MBA_RESET 0x8001
1101#define MBA_SYSTEM_ERR 0x8002
1102#define MBA_REQ_TRANSFER_ERR 0x8003
1103#define MBA_RSP_TRANSFER_ERR 0x8004
1104#define MBA_WAKEUP_THRES 0x8005
1105#define MBA_LIP_OCCURRED 0x8010
1106
1107#define MBA_LOOP_UP 0x8011
1108#define MBA_LOOP_DOWN 0x8012
1109#define MBA_LIP_RESET 0x8013
1110#define MBA_PORT_UPDATE 0x8014
1111#define MBA_RSCN_UPDATE 0x8015
1112#define MBA_LIP_F8 0x8016
1113#define MBA_LOOP_INIT_ERR 0x8017
1114#define MBA_FABRIC_AUTH_REQ 0x801b
1115#define MBA_CONGN_NOTI_RECV 0x801e
1116#define MBA_SCSI_COMPLETION 0x8020
1117#define MBA_CTIO_COMPLETION 0x8021
1118#define MBA_IP_COMPLETION 0x8022
1119#define MBA_IP_RECEIVE 0x8023
1120#define MBA_IP_BROADCAST 0x8024
1121#define MBA_IP_LOW_WATER_MARK 0x8025
1122#define MBA_IP_RCV_BUFFER_EMPTY 0x8026
1123#define MBA_IP_HDR_DATA_SPLIT 0x8027
1124
1125#define MBA_TRACE_NOTIFICATION 0x8028
1126#define MBA_POINT_TO_POINT 0x8030
1127#define MBA_CMPLT_1_16BIT 0x8031
1128#define MBA_CMPLT_2_16BIT 0x8032
1129#define MBA_CMPLT_3_16BIT 0x8033
1130#define MBA_CMPLT_4_16BIT 0x8034
1131#define MBA_CMPLT_5_16BIT 0x8035
1132#define MBA_CHG_IN_CONNECTION 0x8036
1133#define MBA_RIO_RESPONSE 0x8040
1134#define MBA_ZIO_RESPONSE 0x8040
1135#define MBA_CMPLT_2_32BIT 0x8042
1136#define MBA_BYPASS_NOTIFICATION 0x8043
1137#define MBA_DISCARD_RND_FRAME 0x8048
1138#define MBA_REJECTED_FCP_CMD 0x8049
1139#define MBA_FW_NOT_STARTED 0x8050
1140#define MBA_FW_STARTING 0x8051
1141#define MBA_FW_RESTART_CMPLT 0x8060
1142#define MBA_INIT_REQUIRED 0x8061
1143#define MBA_SHUTDOWN_REQUESTED 0x8062
1144#define MBA_TEMPERATURE_ALERT 0x8070
1145#define MBA_DPORT_DIAGNOSTICS 0x8080
1146#define MBA_TRANS_INSERT 0x8130
1147#define MBA_TRANS_REMOVE 0x8131
1148#define MBA_FW_INIT_FAILURE 0x8401
1149#define MBA_MIRROR_LUN_CHANGE 0x8402
1150
1151#define MBA_FW_POLL_STATE 0x8600
1152#define MBA_FW_RESET_FCT 0x8502
1153#define MBA_FW_INIT_INPROGRESS 0x8500
1154
1155#define MBA_IDC_AEN 0x8200
1156
1157
1158#define INTR_ROM_MB_SUCCESS 0x1
1159#define INTR_ROM_MB_FAILED 0x2
1160#define INTR_MB_SUCCESS 0x10
1161#define INTR_MB_FAILED 0x11
1162#define INTR_ASYNC_EVENT 0x12
1163#define INTR_RSP_QUE_UPDATE 0x13
1164#define INTR_RSP_QUE_UPDATE_83XX 0x14
1165#define INTR_ATIO_QUE_UPDATE 0x1C
1166#define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1167#define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1168
1169
1170#define MBS_LB_RESET 0x17
1171
1172
1173
1174#define FO1_AE_ON_LIPF8 BIT_0
1175#define FO1_AE_ALL_LIP_RESET BIT_1
1176#define FO1_CTIO_RETRY BIT_3
1177#define FO1_DISABLE_LIP_F7_SW BIT_4
1178#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1179#define FO1_DISABLE_GPIO6_7 BIT_6
1180#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1181#define FO1_SET_EMPHASIS_SWING BIT_8
1182#define FO1_AE_AUTO_BYPASS BIT_9
1183#define FO1_ENABLE_PURE_IOCB BIT_10
1184#define FO1_AE_PLOGI_RJT BIT_11
1185#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1186#define FO1_AE_QUEUE_FULL BIT_13
1187
1188#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1189#define FO2_REV_LOOPBACK BIT_1
1190
1191#define FO3_ENABLE_EMERG_IOCB BIT_0
1192#define FO3_AE_RND_ERROR BIT_1
1193
1194
1195#define ADD_FO_COUNT 3
1196#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
1197#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1198
1199#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1200
1201#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1202
1203
1204
1205
1206#define MBC_LOAD_RAM 1
1207#define MBC_EXECUTE_FIRMWARE 2
1208#define MBC_READ_RAM_WORD 5
1209#define MBC_MAILBOX_REGISTER_TEST 6
1210#define MBC_VERIFY_CHECKSUM 7
1211#define MBC_GET_FIRMWARE_VERSION 8
1212#define MBC_LOAD_RISC_RAM 9
1213#define MBC_DUMP_RISC_RAM 0xa
1214#define MBC_SECURE_FLASH_UPDATE 0xa
1215#define MBC_LOAD_RISC_RAM_EXTENDED 0xb
1216#define MBC_DUMP_RISC_RAM_EXTENDED 0xc
1217#define MBC_WRITE_RAM_WORD_EXTENDED 0xd
1218#define MBC_READ_RAM_EXTENDED 0xf
1219#define MBC_IOCB_COMMAND 0x12
1220#define MBC_STOP_FIRMWARE 0x14
1221#define MBC_ABORT_COMMAND 0x15
1222#define MBC_ABORT_DEVICE 0x16
1223#define MBC_ABORT_TARGET 0x17
1224#define MBC_RESET 0x18
1225#define MBC_GET_ADAPTER_LOOP_ID 0x20
1226#define MBC_GET_SET_ZIO_THRESHOLD 0x21
1227#define MBC_GET_RETRY_COUNT 0x22
1228#define MBC_DISABLE_VI 0x24
1229#define MBC_ENABLE_VI 0x25
1230#define MBC_GET_FIRMWARE_OPTION 0x28
1231#define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34
1232#define MBC_SET_FIRMWARE_OPTION 0x38
1233#define MBC_SET_GET_FC_LED_CONFIG 0x3b
1234#define MBC_LOOP_PORT_BYPASS 0x40
1235#define MBC_LOOP_PORT_ENABLE 0x41
1236#define MBC_GET_RESOURCE_COUNTS 0x42
1237#define MBC_NON_PARTICIPATE 0x43
1238#define MBC_DIAGNOSTIC_ECHO 0x44
1239#define MBC_DIAGNOSTIC_LOOP_BACK 0x45
1240#define MBC_ONLINE_SELF_TEST 0x46
1241#define MBC_ENHANCED_GET_PORT_DATABASE 0x47
1242#define MBC_CONFIGURE_VF 0x4b
1243#define MBC_RESET_LINK_STATUS 0x52
1244#define MBC_IOCB_COMMAND_A64 0x54
1245#define MBC_PORT_LOGOUT 0x56
1246#define MBC_SEND_RNID_ELS 0x57
1247#define MBC_SET_RNID_PARAMS 0x59
1248#define MBC_GET_RNID_PARAMS 0x5a
1249#define MBC_DATA_RATE 0x5d
1250#define MBC_INITIALIZE_FIRMWARE 0x60
1251#define MBC_INITIATE_LIP 0x62
1252
1253#define MBC_GET_FC_AL_POSITION_MAP 0x63
1254#define MBC_GET_PORT_DATABASE 0x64
1255#define MBC_CLEAR_ACA 0x65
1256#define MBC_TARGET_RESET 0x66
1257#define MBC_CLEAR_TASK_SET 0x67
1258#define MBC_ABORT_TASK_SET 0x68
1259#define MBC_GET_FIRMWARE_STATE 0x69
1260#define MBC_GET_PORT_NAME 0x6a
1261#define MBC_GET_LINK_STATUS 0x6b
1262#define MBC_LIP_RESET 0x6c
1263#define MBC_SEND_SNS_COMMAND 0x6e
1264
1265#define MBC_LOGIN_FABRIC_PORT 0x6f
1266#define MBC_SEND_CHANGE_REQUEST 0x70
1267#define MBC_LOGOUT_FABRIC_PORT 0x71
1268#define MBC_LIP_FULL_LOGIN 0x72
1269#define MBC_LOGIN_LOOP_PORT 0x74
1270#define MBC_PORT_NODE_NAME_LIST 0x75
1271#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
1272#define MBC_UNLOAD_IP 0x79
1273#define MBC_GET_ID_LIST 0x7C
1274#define MBC_SEND_LFA_COMMAND 0x7D
1275#define MBC_LUN_RESET 0x7E
1276
1277
1278
1279
1280
1281#define MBC_MR_DRV_SHUTDOWN 0x6A
1282
1283
1284
1285
1286#define MBC_WRITE_SERDES 0x3
1287#define MBC_READ_SERDES 0x4
1288#define MBC_LOAD_DUMP_MPI_RAM 0x5
1289#define MBC_SERDES_PARAMS 0x10
1290#define MBC_GET_IOCB_STATUS 0x12
1291#define MBC_PORT_PARAMS 0x1A
1292#define MBC_GET_TIMEOUT_PARAMS 0x22
1293#define MBC_TRACE_CONTROL 0x27
1294#define MBC_GEN_SYSTEM_ERROR 0x2a
1295#define MBC_WRITE_SFP 0x30
1296#define MBC_READ_SFP 0x31
1297#define MBC_SET_TIMEOUT_PARAMS 0x32
1298#define MBC_DPORT_DIAGNOSTICS 0x47
1299#define MBC_MID_INITIALIZE_FIRMWARE 0x48
1300#define MBC_MID_GET_VP_DATABASE 0x49
1301#define MBC_MID_GET_VP_ENTRY 0x4a
1302#define MBC_HOST_MEMORY_COPY 0x53
1303#define MBC_SEND_RNFT_ELS 0x5e
1304#define MBC_GET_LINK_PRIV_STATS 0x6d
1305#define MBC_LINK_INITIALIZATION 0x72
1306#define MBC_SET_VENDOR_ID 0x76
1307#define MBC_PORT_RESET 0x120
1308#define MBC_SET_PORT_CONFIG 0x122
1309#define MBC_GET_PORT_CONFIG 0x123
1310
1311
1312
1313
1314#define MBC_WRITE_MPI_REGISTER 0x01
1315
1316
1317
1318
1319#define MBC_SET_GET_ETH_SERDES_REG 0x150
1320#define HCS_WRITE_SERDES 0x3
1321#define HCS_READ_SERDES 0x4
1322
1323
1324#define FCAL_MAP_SIZE 128
1325
1326
1327#define MBX_31 BIT_31
1328#define MBX_30 BIT_30
1329#define MBX_29 BIT_29
1330#define MBX_28 BIT_28
1331#define MBX_27 BIT_27
1332#define MBX_26 BIT_26
1333#define MBX_25 BIT_25
1334#define MBX_24 BIT_24
1335#define MBX_23 BIT_23
1336#define MBX_22 BIT_22
1337#define MBX_21 BIT_21
1338#define MBX_20 BIT_20
1339#define MBX_19 BIT_19
1340#define MBX_18 BIT_18
1341#define MBX_17 BIT_17
1342#define MBX_16 BIT_16
1343#define MBX_15 BIT_15
1344#define MBX_14 BIT_14
1345#define MBX_13 BIT_13
1346#define MBX_12 BIT_12
1347#define MBX_11 BIT_11
1348#define MBX_10 BIT_10
1349#define MBX_9 BIT_9
1350#define MBX_8 BIT_8
1351#define MBX_7 BIT_7
1352#define MBX_6 BIT_6
1353#define MBX_5 BIT_5
1354#define MBX_4 BIT_4
1355#define MBX_3 BIT_3
1356#define MBX_2 BIT_2
1357#define MBX_1 BIT_1
1358#define MBX_0 BIT_0
1359
1360#define RNID_TYPE_ELS_CMD 0x5
1361#define RNID_TYPE_PORT_LOGIN 0x7
1362#define RNID_BUFFER_CREDITS 0x8
1363#define RNID_TYPE_SET_VERSION 0x9
1364#define RNID_TYPE_ASIC_TEMP 0xC
1365
1366#define ELS_CMD_MAP_SIZE 32
1367
1368
1369
1370
1371#define FSTATE_CONFIG_WAIT 0
1372#define FSTATE_WAIT_AL_PA 1
1373#define FSTATE_WAIT_LOGIN 2
1374#define FSTATE_READY 3
1375#define FSTATE_LOSS_OF_SYNC 4
1376#define FSTATE_ERROR 5
1377#define FSTATE_REINIT 6
1378#define FSTATE_NON_PART 7
1379
1380#define FSTATE_CONFIG_CORRECT 0
1381#define FSTATE_P2P_RCV_LIP 1
1382#define FSTATE_P2P_CHOOSE_LOOP 2
1383#define FSTATE_P2P_RCV_UNIDEN_LIP 3
1384#define FSTATE_FATAL_ERROR 4
1385#define FSTATE_LOOP_BACK_CONN 5
1386
1387#define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1388#define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1389#define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1390#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1391#define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1392#define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1393#define QLA27XX_DEFAULT_IMAGE 0
1394#define QLA27XX_PRIMARY_IMAGE 1
1395#define QLA27XX_SECONDARY_IMAGE 2
1396
1397
1398
1399
1400
1401#define PORT_DATABASE_SIZE 128
1402typedef struct {
1403 uint8_t options;
1404 uint8_t control;
1405 uint8_t master_state;
1406 uint8_t slave_state;
1407 uint8_t reserved[2];
1408 uint8_t hard_address;
1409 uint8_t reserved_1;
1410 uint8_t port_id[4];
1411 uint8_t node_name[WWN_SIZE];
1412 uint8_t port_name[WWN_SIZE];
1413 __le16 execution_throttle;
1414 uint16_t execution_count;
1415 uint8_t reset_count;
1416 uint8_t reserved_2;
1417 uint16_t resource_allocation;
1418 uint16_t current_allocation;
1419 uint16_t queue_head;
1420 uint16_t queue_tail;
1421 uint16_t transmit_execution_list_next;
1422 uint16_t transmit_execution_list_previous;
1423 uint16_t common_features;
1424 uint16_t total_concurrent_sequences;
1425 uint16_t RO_by_information_category;
1426 uint8_t recipient;
1427 uint8_t initiator;
1428 uint16_t receive_data_size;
1429 uint16_t concurrent_sequences;
1430 uint16_t open_sequences_per_exchange;
1431 uint16_t lun_abort_flags;
1432 uint16_t lun_stop_flags;
1433 uint16_t stop_queue_head;
1434 uint16_t stop_queue_tail;
1435 uint16_t port_retry_timer;
1436 uint16_t next_sequence_id;
1437 uint16_t frame_count;
1438 uint16_t PRLI_payload_length;
1439 uint8_t prli_svc_param_word_0[2];
1440
1441 uint8_t prli_svc_param_word_3[2];
1442
1443 uint16_t loop_id;
1444 uint16_t extended_lun_info_list_pointer;
1445 uint16_t extended_lun_stop_list_pointer;
1446} port_database_t;
1447
1448
1449
1450
1451#define PD_STATE_DISCOVERY 0
1452#define PD_STATE_WAIT_DISCOVERY_ACK 1
1453#define PD_STATE_PORT_LOGIN 2
1454#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1455#define PD_STATE_PROCESS_LOGIN 4
1456#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1457#define PD_STATE_PORT_LOGGED_IN 6
1458#define PD_STATE_PORT_UNAVAILABLE 7
1459#define PD_STATE_PROCESS_LOGOUT 8
1460#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1461#define PD_STATE_PORT_LOGOUT 10
1462#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1463
1464
1465#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1466#define QLA_ZIO_DISABLED 0
1467#define QLA_ZIO_DEFAULT_TIMER 2
1468
1469
1470
1471
1472
1473#define ICB_VERSION 1
1474typedef struct {
1475 uint8_t version;
1476 uint8_t reserved_1;
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497 uint8_t firmware_options[2];
1498
1499 __le16 frame_payload_size;
1500 __le16 max_iocb_allocation;
1501 __le16 execution_throttle;
1502 uint8_t retry_count;
1503 uint8_t retry_delay;
1504 uint8_t port_name[WWN_SIZE];
1505 uint16_t hard_address;
1506 uint8_t inquiry_data;
1507 uint8_t login_timeout;
1508 uint8_t node_name[WWN_SIZE];
1509
1510 __le16 request_q_outpointer;
1511 __le16 response_q_inpointer;
1512 __le16 request_q_length;
1513 __le16 response_q_length;
1514 __le64 request_q_address __packed;
1515 __le64 response_q_address __packed;
1516
1517 __le16 lun_enables;
1518 uint8_t command_resource_count;
1519 uint8_t immediate_notify_resource_count;
1520 __le16 timeout;
1521 uint8_t reserved_2[2];
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542 uint8_t add_firmware_options[2];
1543
1544 uint8_t response_accumulation_timer;
1545 uint8_t interrupt_delay_timer;
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566 uint8_t special_options[2];
1567
1568 uint8_t reserved_3[26];
1569} init_cb_t;
1570
1571
1572struct init_sf_cb {
1573 uint8_t format;
1574 uint8_t reserved0;
1575
1576
1577
1578
1579
1580
1581 __le16 flags;
1582 uint8_t reserved1[32];
1583 uint16_t discard_OHRB_timeout_value;
1584 uint16_t remote_write_opt_queue_num;
1585 uint8_t reserved2[40];
1586 uint8_t scm_related_parameter[16];
1587 uint8_t reserved3[32];
1588};
1589
1590
1591
1592
1593#define GLSO_SEND_RPS BIT_0
1594#define GLSO_USE_DID BIT_3
1595
1596struct link_statistics {
1597 __le32 link_fail_cnt;
1598 __le32 loss_sync_cnt;
1599 __le32 loss_sig_cnt;
1600 __le32 prim_seq_err_cnt;
1601 __le32 inval_xmit_word_cnt;
1602 __le32 inval_crc_cnt;
1603 __le32 lip_cnt;
1604 __le32 link_up_cnt;
1605 __le32 link_down_loop_init_tmo;
1606 __le32 link_down_los;
1607 __le32 link_down_loss_rcv_clk;
1608 uint32_t reserved0[5];
1609 __le32 port_cfg_chg;
1610 uint32_t reserved1[11];
1611 __le32 rsp_q_full;
1612 __le32 atio_q_full;
1613 __le32 drop_ae;
1614 __le32 els_proto_err;
1615 __le32 reserved2;
1616 __le32 tx_frames;
1617 __le32 rx_frames;
1618 __le32 discarded_frames;
1619 __le32 dropped_frames;
1620 uint32_t reserved3;
1621 __le32 nos_rcvd;
1622 uint32_t reserved4[4];
1623 __le32 tx_prjt;
1624 __le32 rcv_exfail;
1625 __le32 rcv_abts;
1626 __le32 seq_frm_miss;
1627 __le32 corr_err;
1628 __le32 mb_rqst;
1629 __le32 nport_full;
1630 __le32 eofa;
1631 uint32_t reserved5;
1632 __le64 fpm_recv_word_cnt;
1633 __le64 fpm_disc_word_cnt;
1634 __le64 fpm_xmit_word_cnt;
1635 uint32_t reserved6[70];
1636};
1637
1638
1639
1640
1641#define NV_START_BIT BIT_2
1642#define NV_WRITE_OP (BIT_26+BIT_24)
1643#define NV_READ_OP (BIT_26+BIT_25)
1644#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1645#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1646#define NV_DELAY_COUNT 10
1647
1648
1649
1650
1651typedef struct {
1652
1653
1654
1655 uint8_t id[4];
1656 uint8_t nvram_version;
1657 uint8_t reserved_0;
1658
1659
1660
1661
1662 uint8_t parameter_block_version;
1663 uint8_t reserved_1;
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684 uint8_t firmware_options[2];
1685
1686 __le16 frame_payload_size;
1687 __le16 max_iocb_allocation;
1688 __le16 execution_throttle;
1689 uint8_t retry_count;
1690 uint8_t retry_delay;
1691 uint8_t port_name[WWN_SIZE];
1692 uint16_t hard_address;
1693 uint8_t inquiry_data;
1694 uint8_t login_timeout;
1695 uint8_t node_name[WWN_SIZE];
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716 uint8_t add_firmware_options[2];
1717
1718 uint8_t response_accumulation_timer;
1719 uint8_t interrupt_delay_timer;
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740 uint8_t special_options[2];
1741
1742
1743 uint8_t reserved_2[22];
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782 uint8_t seriallink_options[4];
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805 uint8_t host_p[2];
1806
1807 uint8_t boot_node_name[WWN_SIZE];
1808 uint8_t boot_lun_number;
1809 uint8_t reset_delay;
1810 uint8_t port_down_retry_count;
1811 uint8_t boot_id_number;
1812 __le16 max_luns_per_target;
1813 uint8_t fcode_boot_port_name[WWN_SIZE];
1814 uint8_t alternate_port_name[WWN_SIZE];
1815 uint8_t alternate_node_name[WWN_SIZE];
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827 uint8_t efi_parameters;
1828
1829 uint8_t link_down_timeout;
1830
1831 uint8_t adapter_id[16];
1832
1833 uint8_t alt1_boot_node_name[WWN_SIZE];
1834 uint16_t alt1_boot_lun_number;
1835 uint8_t alt2_boot_node_name[WWN_SIZE];
1836 uint16_t alt2_boot_lun_number;
1837 uint8_t alt3_boot_node_name[WWN_SIZE];
1838 uint16_t alt3_boot_lun_number;
1839 uint8_t alt4_boot_node_name[WWN_SIZE];
1840 uint16_t alt4_boot_lun_number;
1841 uint8_t alt5_boot_node_name[WWN_SIZE];
1842 uint16_t alt5_boot_lun_number;
1843 uint8_t alt6_boot_node_name[WWN_SIZE];
1844 uint16_t alt6_boot_lun_number;
1845 uint8_t alt7_boot_node_name[WWN_SIZE];
1846 uint16_t alt7_boot_lun_number;
1847
1848 uint8_t reserved_3[2];
1849
1850
1851 uint8_t model_number[16];
1852
1853
1854 uint8_t oem_specific[16];
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877 uint8_t adapter_features[2];
1878
1879 uint8_t reserved_4[16];
1880
1881
1882 uint16_t subsystem_vendor_id_2200;
1883
1884
1885 uint16_t subsystem_device_id_2200;
1886
1887 uint8_t reserved_5;
1888 uint8_t checksum;
1889} nvram_t;
1890
1891
1892
1893
1894typedef struct {
1895 uint8_t entry_type;
1896 uint8_t entry_count;
1897 uint8_t sys_define;
1898 uint8_t entry_status;
1899 uint32_t handle;
1900 uint8_t data[52];
1901 uint32_t signature;
1902#define RESPONSE_PROCESSED 0xDEADDEAD
1903} response_t;
1904
1905
1906
1907
1908struct atio {
1909 uint8_t entry_type;
1910 uint8_t entry_count;
1911 __le16 attr_n_length;
1912 uint8_t data[56];
1913 uint32_t signature;
1914#define ATIO_PROCESSED 0xDEADDEAD
1915};
1916
1917typedef union {
1918 __le16 extended;
1919 struct {
1920 uint8_t reserved;
1921 uint8_t standard;
1922 } id;
1923} target_id_t;
1924
1925#define SET_TARGET_ID(ha, to, from) \
1926do { \
1927 if (HAS_EXTENDED_IDS(ha)) \
1928 to.extended = cpu_to_le16(from); \
1929 else \
1930 to.id.standard = (uint8_t)from; \
1931} while (0)
1932
1933
1934
1935
1936#define COMMAND_TYPE 0x11
1937typedef struct {
1938 uint8_t entry_type;
1939 uint8_t entry_count;
1940 uint8_t sys_define;
1941 uint8_t entry_status;
1942 uint32_t handle;
1943 target_id_t target;
1944 __le16 lun;
1945 __le16 control_flags;
1946#define CF_WRITE BIT_6
1947#define CF_READ BIT_5
1948#define CF_SIMPLE_TAG BIT_3
1949#define CF_ORDERED_TAG BIT_2
1950#define CF_HEAD_TAG BIT_1
1951 uint16_t reserved_1;
1952 __le16 timeout;
1953 __le16 dseg_count;
1954 uint8_t scsi_cdb[MAX_CMDSZ];
1955 __le32 byte_count;
1956 union {
1957 struct dsd32 dsd32[3];
1958 struct dsd64 dsd64[2];
1959 };
1960} cmd_entry_t;
1961
1962
1963
1964
1965#define COMMAND_A64_TYPE 0x19
1966typedef struct {
1967 uint8_t entry_type;
1968 uint8_t entry_count;
1969 uint8_t sys_define;
1970 uint8_t entry_status;
1971 uint32_t handle;
1972 target_id_t target;
1973 __le16 lun;
1974 __le16 control_flags;
1975 uint16_t reserved_1;
1976 __le16 timeout;
1977 __le16 dseg_count;
1978 uint8_t scsi_cdb[MAX_CMDSZ];
1979 uint32_t byte_count;
1980 struct dsd64 dsd[2];
1981} cmd_a64_entry_t, request_t;
1982
1983
1984
1985
1986#define CONTINUE_TYPE 0x02
1987typedef struct {
1988 uint8_t entry_type;
1989 uint8_t entry_count;
1990 uint8_t sys_define;
1991 uint8_t entry_status;
1992 uint32_t reserved;
1993 struct dsd32 dsd[7];
1994} cont_entry_t;
1995
1996
1997
1998
1999#define CONTINUE_A64_TYPE 0x0A
2000typedef struct {
2001 uint8_t entry_type;
2002 uint8_t entry_count;
2003 uint8_t sys_define;
2004 uint8_t entry_status;
2005 struct dsd64 dsd[5];
2006} cont_a64_entry_t;
2007
2008#define PO_MODE_DIF_INSERT 0
2009#define PO_MODE_DIF_REMOVE 1
2010#define PO_MODE_DIF_PASS 2
2011#define PO_MODE_DIF_REPLACE 3
2012#define PO_MODE_DIF_TCP_CKSUM 6
2013#define PO_ENABLE_INCR_GUARD_SEED BIT_3
2014#define PO_DISABLE_GUARD_CHECK BIT_4
2015#define PO_DISABLE_INCR_REF_TAG BIT_5
2016#define PO_DIS_HEADER_MODE BIT_7
2017#define PO_ENABLE_DIF_BUNDLING BIT_8
2018#define PO_DIS_FRAME_MODE BIT_9
2019#define PO_DIS_VALD_APP_ESC BIT_10
2020#define PO_DIS_VALD_APP_REF_ESC BIT_11
2021
2022#define PO_DIS_APP_TAG_REPL BIT_12
2023#define PO_DIS_REF_TAG_REPL BIT_13
2024#define PO_DIS_APP_TAG_VALD BIT_14
2025#define PO_DIS_REF_TAG_VALD BIT_15
2026
2027
2028
2029
2030struct crc_context {
2031 uint32_t handle;
2032 __le32 ref_tag;
2033 __le16 app_tag;
2034 uint8_t ref_tag_mask[4];
2035 uint8_t app_tag_mask[2];
2036 __le16 guard_seed;
2037 __le16 prot_opts;
2038 __le16 blk_size;
2039 __le16 runt_blk_guard;
2040
2041 __le32 byte_count;
2042
2043 union {
2044 struct {
2045 uint32_t reserved_1;
2046 uint16_t reserved_2;
2047 uint16_t reserved_3;
2048 uint32_t reserved_4;
2049 struct dsd64 data_dsd[1];
2050 uint32_t reserved_5[2];
2051 uint32_t reserved_6;
2052 } nobundling;
2053 struct {
2054 __le32 dif_byte_count;
2055
2056 uint16_t reserved_1;
2057 __le16 dseg_count;
2058 uint32_t reserved_2;
2059 struct dsd64 data_dsd[1];
2060 struct dsd64 dif_dsd;
2061 } bundling;
2062 } u;
2063
2064 struct fcp_cmnd fcp_cmnd;
2065 dma_addr_t crc_ctx_dma;
2066
2067 struct list_head dsd_list;
2068
2069
2070 struct list_head ldif_dsd_list;
2071 u8 no_ldif_dsd;
2072
2073 struct list_head ldif_dma_hndl_list;
2074 u32 dif_bundl_len;
2075 u8 no_dif_bundl;
2076
2077};
2078
2079#define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
2080#define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
2081
2082
2083
2084
2085#define STATUS_TYPE 0x03
2086typedef struct {
2087 uint8_t entry_type;
2088 uint8_t entry_count;
2089 uint8_t sys_define;
2090 uint8_t entry_status;
2091 uint32_t handle;
2092 __le16 scsi_status;
2093 __le16 comp_status;
2094 __le16 state_flags;
2095 __le16 status_flags;
2096 __le16 rsp_info_len;
2097 __le16 req_sense_length;
2098 __le32 residual_length;
2099 uint8_t rsp_info[8];
2100 uint8_t req_sense_data[32];
2101} sts_entry_t;
2102
2103
2104
2105
2106#define RF_RQ_DMA_ERROR BIT_6
2107#define RF_INV_E_ORDER BIT_5
2108#define RF_INV_E_COUNT BIT_4
2109#define RF_INV_E_PARAM BIT_3
2110#define RF_INV_E_TYPE BIT_2
2111#define RF_BUSY BIT_1
2112#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
2113 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
2114#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
2115 RF_INV_E_TYPE)
2116
2117
2118
2119
2120#define SS_MASK 0xfff
2121#define SS_RESIDUAL_UNDER BIT_11
2122#define SS_RESIDUAL_OVER BIT_10
2123#define SS_SENSE_LEN_VALID BIT_9
2124#define SS_RESPONSE_INFO_LEN_VALID BIT_8
2125#define SS_SCSI_STATUS_BYTE 0xff
2126
2127#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2128#define SS_BUSY_CONDITION BIT_3
2129#define SS_CONDITION_MET BIT_2
2130#define SS_CHECK_CONDITION BIT_1
2131
2132
2133
2134
2135#define CS_COMPLETE 0x0
2136#define CS_INCOMPLETE 0x1
2137#define CS_DMA 0x2
2138#define CS_TRANSPORT 0x3
2139#define CS_RESET 0x4
2140#define CS_ABORTED 0x5
2141#define CS_TIMEOUT 0x6
2142#define CS_DATA_OVERRUN 0x7
2143#define CS_DIF_ERROR 0xC
2144
2145#define CS_DATA_UNDERRUN 0x15
2146#define CS_QUEUE_FULL 0x1C
2147#define CS_PORT_UNAVAILABLE 0x28
2148
2149#define CS_PORT_LOGGED_OUT 0x29
2150#define CS_PORT_CONFIG_CHG 0x2A
2151#define CS_PORT_BUSY 0x2B
2152#define CS_COMPLETE_CHKCOND 0x30
2153#define CS_IOCB_ERROR 0x31
2154
2155#define CS_REJECT_RECEIVED 0x4E
2156#define CS_BAD_PAYLOAD 0x80
2157#define CS_UNKNOWN 0x81
2158#define CS_RETRY 0x82
2159#define CS_LOOP_DOWN_ABORT 0x83
2160
2161#define CS_BIDIR_RD_OVERRUN 0x700
2162#define CS_BIDIR_RD_WR_OVERRUN 0x707
2163#define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2164#define CS_BIDIR_RD_UNDERRUN 0x1500
2165#define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2166#define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2167#define CS_BIDIR_DMA 0x200
2168
2169
2170
2171#define SF_ABTS_TERMINATED BIT_10
2172#define SF_LOGOUT_SENT BIT_13
2173
2174
2175
2176
2177#define STATUS_CONT_TYPE 0x10
2178typedef struct {
2179 uint8_t entry_type;
2180 uint8_t entry_count;
2181 uint8_t sys_define;
2182 uint8_t entry_status;
2183 uint8_t data[60];
2184} sts_cont_entry_t;
2185
2186
2187
2188
2189
2190#define STATUS_TYPE_21 0x21
2191typedef struct {
2192 uint8_t entry_type;
2193 uint8_t entry_count;
2194 uint8_t handle_count;
2195 uint8_t entry_status;
2196 uint32_t handle[15];
2197} sts21_entry_t;
2198
2199
2200
2201
2202
2203#define STATUS_TYPE_22 0x22
2204typedef struct {
2205 uint8_t entry_type;
2206 uint8_t entry_count;
2207 uint8_t handle_count;
2208 uint8_t entry_status;
2209 uint16_t handle[30];
2210} sts22_entry_t;
2211
2212
2213
2214
2215#define MARKER_TYPE 0x04
2216typedef struct {
2217 uint8_t entry_type;
2218 uint8_t entry_count;
2219 uint8_t handle_count;
2220 uint8_t entry_status;
2221 uint32_t sys_define_2;
2222 target_id_t target;
2223 uint8_t modifier;
2224#define MK_SYNC_ID_LUN 0
2225#define MK_SYNC_ID 1
2226#define MK_SYNC_ALL 2
2227#define MK_SYNC_LIP 3
2228
2229
2230 uint8_t reserved_1;
2231 __le16 sequence_number;
2232 __le16 lun;
2233 uint8_t reserved_2[48];
2234} mrk_entry_t;
2235
2236
2237
2238
2239#define MS_IOCB_TYPE 0x29
2240typedef struct {
2241 uint8_t entry_type;
2242 uint8_t entry_count;
2243 uint8_t handle_count;
2244 uint8_t entry_status;
2245 uint32_t handle1;
2246 target_id_t loop_id;
2247 __le16 status;
2248 __le16 control_flags;
2249 uint16_t reserved2;
2250 __le16 timeout;
2251 __le16 cmd_dsd_count;
2252 __le16 total_dsd_count;
2253 uint8_t type;
2254 uint8_t r_ctl;
2255 __le16 rx_id;
2256 uint16_t reserved3;
2257 uint32_t handle2;
2258 __le32 rsp_bytecount;
2259 __le32 req_bytecount;
2260 struct dsd64 req_dsd;
2261 struct dsd64 rsp_dsd;
2262} ms_iocb_entry_t;
2263
2264#define SCM_EDC_ACC_RECEIVED BIT_6
2265#define SCM_RDF_ACC_RECEIVED BIT_7
2266
2267
2268
2269
2270#define MBX_IOCB_TYPE 0x39
2271struct mbx_entry {
2272 uint8_t entry_type;
2273 uint8_t entry_count;
2274 uint8_t sys_define1;
2275
2276#define SOURCE_SCSI 0x00
2277#define SOURCE_IP 0x01
2278#define SOURCE_VI 0x02
2279#define SOURCE_SCTP 0x03
2280#define SOURCE_MP 0x04
2281#define SOURCE_MPIOCTL 0x05
2282#define SOURCE_ASYNC_IOCB 0x07
2283
2284 uint8_t entry_status;
2285
2286 uint32_t handle;
2287 target_id_t loop_id;
2288
2289 __le16 status;
2290 __le16 state_flags;
2291 __le16 status_flags;
2292
2293 uint32_t sys_define2[2];
2294
2295 __le16 mb0;
2296 __le16 mb1;
2297 __le16 mb2;
2298 __le16 mb3;
2299 __le16 mb6;
2300 __le16 mb7;
2301 __le16 mb9;
2302 __le16 mb10;
2303 uint32_t reserved_2[2];
2304 uint8_t node_name[WWN_SIZE];
2305 uint8_t port_name[WWN_SIZE];
2306};
2307
2308#ifndef IMMED_NOTIFY_TYPE
2309#define IMMED_NOTIFY_TYPE 0x0D
2310
2311
2312
2313
2314
2315
2316
2317struct imm_ntfy_from_isp {
2318 uint8_t entry_type;
2319 uint8_t entry_count;
2320 uint8_t sys_define;
2321 uint8_t entry_status;
2322 union {
2323 struct {
2324 __le32 sys_define_2;
2325 target_id_t target;
2326 __le16 lun;
2327 uint8_t target_id;
2328 uint8_t reserved_1;
2329 __le16 status_modifier;
2330 __le16 status;
2331 __le16 task_flags;
2332 __le16 seq_id;
2333 __le16 srr_rx_id;
2334 __le32 srr_rel_offs;
2335 __le16 srr_ui;
2336#define SRR_IU_DATA_IN 0x1
2337#define SRR_IU_DATA_OUT 0x5
2338#define SRR_IU_STATUS 0x7
2339 __le16 srr_ox_id;
2340 uint8_t reserved_2[28];
2341 } isp2x;
2342 struct {
2343 uint32_t reserved;
2344 __le16 nport_handle;
2345 uint16_t reserved_2;
2346 __le16 flags;
2347#define NOTIFY24XX_FLAGS_FCSP BIT_5
2348#define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2349#define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2350 __le16 srr_rx_id;
2351 __le16 status;
2352 uint8_t status_subcode;
2353 uint8_t fw_handle;
2354 __le32 exchange_address;
2355 __le32 srr_rel_offs;
2356 __le16 srr_ui;
2357 __le16 srr_ox_id;
2358 union {
2359 struct {
2360 uint8_t node_name[8];
2361 } plogi;
2362 struct {
2363
2364 __le16 wd3_lo;
2365 uint8_t resv0[6];
2366 } prli;
2367 struct {
2368 uint8_t port_id[3];
2369 uint8_t resv1;
2370 __le16 nport_handle;
2371 uint16_t resv2;
2372 } req_els;
2373 } u;
2374 uint8_t port_name[8];
2375 uint8_t resv3[3];
2376 uint8_t vp_index;
2377 uint32_t reserved_5;
2378 uint8_t port_id[3];
2379 uint8_t reserved_6;
2380 } isp24;
2381 } u;
2382 uint16_t reserved_7;
2383 __le16 ox_id;
2384} __packed;
2385#endif
2386
2387
2388
2389
2390#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2391#define REQUEST_ENTRY_SIZE (sizeof(request_t))
2392
2393
2394
2395
2396
2397
2398typedef struct {
2399 port_id_t d_id;
2400 uint8_t node_name[WWN_SIZE];
2401 uint8_t port_name[WWN_SIZE];
2402 uint8_t fabric_port_name[WWN_SIZE];
2403 uint16_t fp_speed;
2404 uint8_t fc4_type;
2405 uint8_t fc4_features;
2406} sw_info_t;
2407
2408
2409#define FC4_TYPE_FCP_SCSI 0x08
2410#define FC4_TYPE_NVME 0x28
2411#define FC4_TYPE_OTHER 0x0
2412#define FC4_TYPE_UNKNOWN 0xff
2413
2414
2415struct mbx_24xx_entry {
2416 uint8_t entry_type;
2417 uint8_t entry_count;
2418 uint8_t sys_define1;
2419 uint8_t entry_status;
2420 uint32_t handle;
2421 uint16_t mb[28];
2422};
2423
2424#define IOCB_SIZE 64
2425
2426
2427
2428
2429typedef enum {
2430 FCT_UNKNOWN,
2431 FCT_BROADCAST = 0x01,
2432 FCT_INITIATOR = 0x02,
2433 FCT_TARGET = 0x04,
2434 FCT_NVME_INITIATOR = 0x10,
2435 FCT_NVME_TARGET = 0x20,
2436 FCT_NVME_DISCOVERY = 0x40,
2437 FCT_NVME = 0xf0,
2438} fc_port_type_t;
2439
2440enum qla_sess_deletion {
2441 QLA_SESS_DELETION_NONE = 0,
2442 QLA_SESS_DELETION_IN_PROGRESS,
2443 QLA_SESS_DELETED,
2444};
2445
2446enum qlt_plogi_link_t {
2447 QLT_PLOGI_LINK_SAME_WWN,
2448 QLT_PLOGI_LINK_CONFLICT,
2449 QLT_PLOGI_LINK_MAX
2450};
2451
2452struct qlt_plogi_ack_t {
2453 struct list_head list;
2454 struct imm_ntfy_from_isp iocb;
2455 port_id_t id;
2456 int ref_count;
2457 void *fcport;
2458};
2459
2460struct ct_sns_desc {
2461 struct ct_sns_pkt *ct_sns;
2462 dma_addr_t ct_sns_dma;
2463};
2464
2465enum discovery_state {
2466 DSC_DELETED,
2467 DSC_GNN_ID,
2468 DSC_GNL,
2469 DSC_LOGIN_PEND,
2470 DSC_LOGIN_FAILED,
2471 DSC_GPDB,
2472 DSC_UPD_FCPORT,
2473 DSC_LOGIN_COMPLETE,
2474 DSC_ADISC,
2475 DSC_DELETE_PEND,
2476 DSC_LOGIN_AUTH_PEND,
2477};
2478
2479enum login_state {
2480 DSC_LS_LLIOCB_SENT = 2,
2481 DSC_LS_PLOGI_PEND,
2482 DSC_LS_PLOGI_COMP,
2483 DSC_LS_PRLI_PEND,
2484 DSC_LS_PRLI_COMP,
2485 DSC_LS_PORT_UNAVAIL,
2486 DSC_LS_PRLO_PEND = 9,
2487 DSC_LS_LOGO_PEND,
2488};
2489
2490enum rscn_addr_format {
2491 RSCN_PORT_ADDR,
2492 RSCN_AREA_ADDR,
2493 RSCN_DOM_ADDR,
2494 RSCN_FAB_ADDR,
2495};
2496
2497
2498
2499
2500typedef struct fc_port {
2501 struct list_head list;
2502 struct scsi_qla_host *vha;
2503
2504 unsigned int conf_compl_supported:1;
2505 unsigned int deleted:2;
2506 unsigned int free_pending:1;
2507 unsigned int local:1;
2508 unsigned int logout_on_delete:1;
2509 unsigned int logo_ack_needed:1;
2510 unsigned int keep_nport_handle:1;
2511 unsigned int send_els_logo:1;
2512 unsigned int login_pause:1;
2513 unsigned int login_succ:1;
2514 unsigned int query:1;
2515 unsigned int id_changed:1;
2516 unsigned int scan_needed:1;
2517 unsigned int n2n_flag:1;
2518 unsigned int explicit_logout:1;
2519 unsigned int prli_pend_timer:1;
2520 unsigned int do_prli_nvme:1;
2521
2522 uint8_t nvme_flag;
2523
2524 uint8_t node_name[WWN_SIZE];
2525 uint8_t port_name[WWN_SIZE];
2526 port_id_t d_id;
2527 uint16_t loop_id;
2528 uint16_t old_loop_id;
2529
2530 struct completion nvme_del_done;
2531 uint32_t nvme_prli_service_param;
2532#define NVME_PRLI_SP_PI_CTRL BIT_9
2533#define NVME_PRLI_SP_SLER BIT_8
2534#define NVME_PRLI_SP_CONF BIT_7
2535#define NVME_PRLI_SP_INITIATOR BIT_5
2536#define NVME_PRLI_SP_TARGET BIT_4
2537#define NVME_PRLI_SP_DISCOVERY BIT_3
2538#define NVME_PRLI_SP_FIRST_BURST BIT_0
2539
2540 uint32_t nvme_first_burst_size;
2541#define NVME_FLAG_REGISTERED 4
2542#define NVME_FLAG_DELETING 2
2543#define NVME_FLAG_RESETTING 1
2544
2545 struct fc_port *conflict;
2546 unsigned char logout_completed;
2547 int generation;
2548
2549 struct se_session *se_sess;
2550 struct list_head sess_cmd_list;
2551 spinlock_t sess_cmd_lock;
2552 struct kref sess_kref;
2553 struct qla_tgt *tgt;
2554 unsigned long expires;
2555 struct list_head del_list_entry;
2556 struct work_struct free_work;
2557 struct work_struct reg_work;
2558 uint64_t jiffies_at_registration;
2559 unsigned long prli_expired;
2560 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2561
2562 uint16_t tgt_id;
2563 uint16_t old_tgt_id;
2564 uint16_t sec_since_registration;
2565
2566 uint8_t fcp_prio;
2567
2568 uint8_t fabric_port_name[WWN_SIZE];
2569 uint16_t fp_speed;
2570
2571 fc_port_type_t port_type;
2572
2573 atomic_t state;
2574 uint32_t flags;
2575
2576 int login_retry;
2577
2578 struct fc_rport *rport, *drport;
2579 u32 supported_classes;
2580
2581 uint8_t fc4_type;
2582 uint8_t fc4_features;
2583 uint8_t scan_state;
2584
2585 unsigned long last_queue_full;
2586 unsigned long last_ramp_up;
2587
2588 uint16_t port_id;
2589
2590 struct nvme_fc_remote_port *nvme_remote_port;
2591
2592 unsigned long retry_delay_timestamp;
2593 struct qla_tgt_sess *tgt_session;
2594 struct ct_sns_desc ct_desc;
2595 enum discovery_state disc_state;
2596 atomic_t shadow_disc_state;
2597 enum discovery_state next_disc_state;
2598 enum login_state fw_login_state;
2599 unsigned long dm_login_expire;
2600 unsigned long plogi_nack_done_deadline;
2601
2602 u32 login_gen, last_login_gen;
2603 u32 rscn_gen, last_rscn_gen;
2604 u32 chip_reset;
2605 struct list_head gnl_entry;
2606 struct work_struct del_work;
2607 u8 iocb[IOCB_SIZE];
2608 u8 current_login_state;
2609 u8 last_login_state;
2610 u16 n2n_link_reset_cnt;
2611 u16 n2n_chip_reset;
2612
2613 struct dentry *dfs_rport_dir;
2614
2615 u64 tgt_short_link_down_cnt;
2616 u64 tgt_link_down_time;
2617 u64 dev_loss_tmo;
2618
2619
2620
2621 struct {
2622 uint32_t enable:1;
2623 uint32_t app_stop:2;
2624 uint32_t app_started:1;
2625 uint32_t aes_gmac:1;
2626 uint32_t app_sess_online:1;
2627 uint32_t tx_sa_set:1;
2628 uint32_t rx_sa_set:1;
2629 uint32_t tx_sa_pending:1;
2630 uint32_t rx_sa_pending:1;
2631 uint32_t tx_rekey_cnt;
2632 uint32_t rx_rekey_cnt;
2633 uint64_t tx_bytes;
2634 uint64_t rx_bytes;
2635 uint8_t auth_state;
2636 uint16_t authok:1;
2637 uint16_t rekey_cnt;
2638 struct list_head edif_indx_list;
2639 spinlock_t indx_list_lock;
2640
2641 struct list_head tx_sa_list;
2642 struct list_head rx_sa_list;
2643 spinlock_t sa_list_lock;
2644 } edif;
2645} fc_port_t;
2646
2647enum {
2648 FC4_PRIORITY_NVME = 1,
2649 FC4_PRIORITY_FCP = 2,
2650};
2651
2652#define QLA_FCPORT_SCAN 1
2653#define QLA_FCPORT_FOUND 2
2654
2655struct event_arg {
2656 fc_port_t *fcport;
2657 srb_t *sp;
2658 port_id_t id;
2659 u16 data[2], rc;
2660 u8 port_name[WWN_SIZE];
2661 u32 iop[2];
2662};
2663
2664#include "qla_mr.h"
2665
2666
2667
2668
2669#define FCS_UNCONFIGURED 1
2670#define FCS_DEVICE_DEAD 2
2671#define FCS_DEVICE_LOST 3
2672#define FCS_ONLINE 4
2673
2674extern const char *const port_state_str[5];
2675
2676static const char * const port_dstate_str[] = {
2677 "DELETED",
2678 "GNN_ID",
2679 "GNL",
2680 "LOGIN_PEND",
2681 "LOGIN_FAILED",
2682 "GPDB",
2683 "UPD_FCPORT",
2684 "LOGIN_COMPLETE",
2685 "ADISC",
2686 "DELETE_PEND",
2687 "LOGIN_AUTH_PEND",
2688};
2689
2690
2691
2692
2693#define FCF_FABRIC_DEVICE BIT_0
2694#define FCF_LOGIN_NEEDED BIT_1
2695#define FCF_FCP2_DEVICE BIT_2
2696#define FCF_ASYNC_SENT BIT_3
2697#define FCF_CONF_COMP_SUPPORTED BIT_4
2698#define FCF_ASYNC_ACTIVE BIT_5
2699#define FCF_FCSP_DEVICE BIT_6
2700#define FCF_EDIF_DELETE BIT_7
2701
2702
2703#define FC_NO_LOOP_ID 0x1000
2704
2705
2706
2707
2708
2709
2710
2711#define CT_REJECT_RESPONSE 0x8001
2712#define CT_ACCEPT_RESPONSE 0x8002
2713#define CT_REASON_INVALID_COMMAND_CODE 0x01
2714#define CT_REASON_CANNOT_PERFORM 0x09
2715#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2716#define CT_EXPL_ALREADY_REGISTERED 0x10
2717#define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2718#define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2719#define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2720#define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2721#define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2722#define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2723#define CT_EXPL_HBA_NOT_REGISTERED 0x17
2724#define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2725#define CT_EXPL_PORT_NOT_REGISTERED 0x21
2726#define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2727#define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2728
2729#define NS_N_PORT_TYPE 0x01
2730#define NS_NL_PORT_TYPE 0x02
2731#define NS_NX_PORT_TYPE 0x7F
2732
2733#define GA_NXT_CMD 0x100
2734#define GA_NXT_REQ_SIZE (16 + 4)
2735#define GA_NXT_RSP_SIZE (16 + 620)
2736
2737#define GPN_FT_CMD 0x172
2738#define GPN_FT_REQ_SIZE (16 + 4)
2739#define GNN_FT_CMD 0x173
2740#define GNN_FT_REQ_SIZE (16 + 4)
2741
2742#define GID_PT_CMD 0x1A1
2743#define GID_PT_REQ_SIZE (16 + 4)
2744
2745#define GPN_ID_CMD 0x112
2746#define GPN_ID_REQ_SIZE (16 + 4)
2747#define GPN_ID_RSP_SIZE (16 + 8)
2748
2749#define GNN_ID_CMD 0x113
2750#define GNN_ID_REQ_SIZE (16 + 4)
2751#define GNN_ID_RSP_SIZE (16 + 8)
2752
2753#define GFT_ID_CMD 0x117
2754#define GFT_ID_REQ_SIZE (16 + 4)
2755#define GFT_ID_RSP_SIZE (16 + 32)
2756
2757#define GID_PN_CMD 0x121
2758#define GID_PN_REQ_SIZE (16 + 8)
2759#define GID_PN_RSP_SIZE (16 + 4)
2760
2761#define RFT_ID_CMD 0x217
2762#define RFT_ID_REQ_SIZE (16 + 4 + 32)
2763#define RFT_ID_RSP_SIZE 16
2764
2765#define RFF_ID_CMD 0x21F
2766#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2767#define RFF_ID_RSP_SIZE 16
2768
2769#define RNN_ID_CMD 0x213
2770#define RNN_ID_REQ_SIZE (16 + 4 + 8)
2771#define RNN_ID_RSP_SIZE 16
2772
2773#define RSNN_NN_CMD 0x239
2774#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2775#define RSNN_NN_RSP_SIZE 16
2776
2777#define GFPN_ID_CMD 0x11C
2778#define GFPN_ID_REQ_SIZE (16 + 4)
2779#define GFPN_ID_RSP_SIZE (16 + 8)
2780
2781#define GPSC_CMD 0x127
2782#define GPSC_REQ_SIZE (16 + 8)
2783#define GPSC_RSP_SIZE (16 + 2 + 2)
2784
2785#define GFF_ID_CMD 0x011F
2786#define GFF_ID_REQ_SIZE (16 + 4)
2787#define GFF_ID_RSP_SIZE (16 + 128)
2788
2789
2790
2791
2792#define FDMI1_HBA_ATTR_COUNT 10
2793#define FDMI2_HBA_ATTR_COUNT 17
2794
2795#define FDMI_HBA_NODE_NAME 0x1
2796#define FDMI_HBA_MANUFACTURER 0x2
2797#define FDMI_HBA_SERIAL_NUMBER 0x3
2798#define FDMI_HBA_MODEL 0x4
2799#define FDMI_HBA_MODEL_DESCRIPTION 0x5
2800#define FDMI_HBA_HARDWARE_VERSION 0x6
2801#define FDMI_HBA_DRIVER_VERSION 0x7
2802#define FDMI_HBA_OPTION_ROM_VERSION 0x8
2803#define FDMI_HBA_FIRMWARE_VERSION 0x9
2804#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2805#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2806
2807#define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2808#define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
2809#define FDMI_HBA_NUM_PORTS 0xe
2810#define FDMI_HBA_FABRIC_NAME 0xf
2811#define FDMI_HBA_BOOT_BIOS_NAME 0x10
2812#define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
2813
2814struct ct_fdmi_hba_attr {
2815 __be16 type;
2816 __be16 len;
2817 union {
2818 uint8_t node_name[WWN_SIZE];
2819 uint8_t manufacturer[64];
2820 uint8_t serial_num[32];
2821 uint8_t model[16+1];
2822 uint8_t model_desc[80];
2823 uint8_t hw_version[32];
2824 uint8_t driver_version[32];
2825 uint8_t orom_version[16];
2826 uint8_t fw_version[32];
2827 uint8_t os_version[128];
2828 __be32 max_ct_len;
2829
2830 uint8_t sym_name[256];
2831 __be32 vendor_specific_info;
2832 __be32 num_ports;
2833 uint8_t fabric_name[WWN_SIZE];
2834 uint8_t bios_name[32];
2835 uint8_t vendor_identifier[8];
2836 } a;
2837};
2838
2839struct ct_fdmi1_hba_attributes {
2840 __be32 count;
2841 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
2842};
2843
2844struct ct_fdmi2_hba_attributes {
2845 __be32 count;
2846 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
2847};
2848
2849
2850
2851
2852#define FDMI1_PORT_ATTR_COUNT 6
2853#define FDMI2_PORT_ATTR_COUNT 16
2854#define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
2855
2856#define FDMI_PORT_FC4_TYPES 0x1
2857#define FDMI_PORT_SUPPORT_SPEED 0x2
2858#define FDMI_PORT_CURRENT_SPEED 0x3
2859#define FDMI_PORT_MAX_FRAME_SIZE 0x4
2860#define FDMI_PORT_OS_DEVICE_NAME 0x5
2861#define FDMI_PORT_HOST_NAME 0x6
2862
2863#define FDMI_PORT_NODE_NAME 0x7
2864#define FDMI_PORT_NAME 0x8
2865#define FDMI_PORT_SYM_NAME 0x9
2866#define FDMI_PORT_TYPE 0xa
2867#define FDMI_PORT_SUPP_COS 0xb
2868#define FDMI_PORT_FABRIC_NAME 0xc
2869#define FDMI_PORT_FC4_TYPE 0xd
2870#define FDMI_PORT_STATE 0x101
2871#define FDMI_PORT_COUNT 0x102
2872#define FDMI_PORT_IDENTIFIER 0x103
2873
2874#define FDMI_SMARTSAN_SERVICE 0xF100
2875#define FDMI_SMARTSAN_GUID 0xF101
2876#define FDMI_SMARTSAN_VERSION 0xF102
2877#define FDMI_SMARTSAN_PROD_NAME 0xF103
2878#define FDMI_SMARTSAN_PORT_INFO 0xF104
2879#define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
2880#define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
2881
2882#define FDMI_PORT_SPEED_1GB 0x1
2883#define FDMI_PORT_SPEED_2GB 0x2
2884#define FDMI_PORT_SPEED_10GB 0x4
2885#define FDMI_PORT_SPEED_4GB 0x8
2886#define FDMI_PORT_SPEED_8GB 0x10
2887#define FDMI_PORT_SPEED_16GB 0x20
2888#define FDMI_PORT_SPEED_32GB 0x40
2889#define FDMI_PORT_SPEED_64GB 0x80
2890#define FDMI_PORT_SPEED_UNKNOWN 0x8000
2891
2892#define FC_CLASS_2 0x04
2893#define FC_CLASS_3 0x08
2894#define FC_CLASS_2_3 0x0C
2895
2896struct ct_fdmi_port_attr {
2897 __be16 type;
2898 __be16 len;
2899 union {
2900 uint8_t fc4_types[32];
2901 __be32 sup_speed;
2902 __be32 cur_speed;
2903 __be32 max_frame_size;
2904 uint8_t os_dev_name[32];
2905 uint8_t host_name[256];
2906
2907 uint8_t node_name[WWN_SIZE];
2908 uint8_t port_name[WWN_SIZE];
2909 uint8_t port_sym_name[128];
2910 __be32 port_type;
2911 __be32 port_supported_cos;
2912 uint8_t fabric_name[WWN_SIZE];
2913 uint8_t port_fc4_type[32];
2914 __be32 port_state;
2915 __be32 num_ports;
2916 __be32 port_id;
2917
2918 uint8_t smartsan_service[24];
2919 uint8_t smartsan_guid[16];
2920 uint8_t smartsan_version[24];
2921 uint8_t smartsan_prod_name[16];
2922 __be32 smartsan_port_info;
2923 __be32 smartsan_qos_support;
2924 __be32 smartsan_security_support;
2925 } a;
2926};
2927
2928struct ct_fdmi1_port_attributes {
2929 __be32 count;
2930 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
2931};
2932
2933struct ct_fdmi2_port_attributes {
2934 __be32 count;
2935 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2936};
2937
2938#define FDMI_ATTR_TYPELEN(obj) \
2939 (sizeof((obj)->type) + sizeof((obj)->len))
2940
2941#define FDMI_ATTR_ALIGNMENT(len) \
2942 (4 - ((len) & 3))
2943
2944
2945#define CALLOPT_FDMI1 0
2946#define CALLOPT_FDMI2 1
2947#define CALLOPT_FDMI2_SMARTSAN 2
2948
2949
2950#define GRHL_CMD 0x100
2951#define GHAT_CMD 0x101
2952#define GRPL_CMD 0x102
2953#define GPAT_CMD 0x110
2954
2955#define RHBA_CMD 0x200
2956#define RHBA_RSP_SIZE 16
2957
2958#define RHAT_CMD 0x201
2959
2960#define RPRT_CMD 0x210
2961#define RPRT_RSP_SIZE 24
2962
2963#define RPA_CMD 0x211
2964#define RPA_RSP_SIZE 16
2965#define SMARTSAN_RPA_RSP_SIZE 24
2966
2967#define DHBA_CMD 0x300
2968#define DHBA_REQ_SIZE (16 + 8)
2969#define DHBA_RSP_SIZE 16
2970
2971#define DHAT_CMD 0x301
2972#define DPRT_CMD 0x310
2973#define DPA_CMD 0x311
2974
2975
2976struct ct_cmd_hdr {
2977 uint8_t revision;
2978 uint8_t in_id[3];
2979 uint8_t gs_type;
2980 uint8_t gs_subtype;
2981 uint8_t options;
2982 uint8_t reserved;
2983};
2984
2985
2986struct ct_sns_req {
2987 struct ct_cmd_hdr header;
2988 __be16 command;
2989 __be16 max_rsp_size;
2990 uint8_t fragment_id;
2991 uint8_t reserved[3];
2992
2993 union {
2994
2995 struct {
2996 uint8_t reserved;
2997 be_id_t port_id;
2998 } port_id;
2999
3000 struct {
3001 uint8_t reserved;
3002 uint8_t domain;
3003 uint8_t area;
3004 uint8_t port_type;
3005 } gpn_ft;
3006
3007 struct {
3008 uint8_t port_type;
3009 uint8_t domain;
3010 uint8_t area;
3011 uint8_t reserved;
3012 } gid_pt;
3013
3014 struct {
3015 uint8_t reserved;
3016 be_id_t port_id;
3017 uint8_t fc4_types[32];
3018 } rft_id;
3019
3020 struct {
3021 uint8_t reserved;
3022 be_id_t port_id;
3023 uint16_t reserved2;
3024 uint8_t fc4_feature;
3025 uint8_t fc4_type;
3026 } rff_id;
3027
3028 struct {
3029 uint8_t reserved;
3030 be_id_t port_id;
3031 uint8_t node_name[8];
3032 } rnn_id;
3033
3034 struct {
3035 uint8_t node_name[8];
3036 uint8_t name_len;
3037 uint8_t sym_node_name[255];
3038 } rsnn_nn;
3039
3040 struct {
3041 uint8_t hba_identifier[8];
3042 } ghat;
3043
3044 struct {
3045 uint8_t hba_identifier[8];
3046 __be32 entry_count;
3047 uint8_t port_name[8];
3048 struct ct_fdmi2_hba_attributes attrs;
3049 } rhba;
3050
3051 struct {
3052 uint8_t hba_identifier[8];
3053 struct ct_fdmi1_hba_attributes attrs;
3054 } rhat;
3055
3056 struct {
3057 uint8_t port_name[8];
3058 struct ct_fdmi2_port_attributes attrs;
3059 } rpa;
3060
3061 struct {
3062 uint8_t hba_identifier[8];
3063 uint8_t port_name[8];
3064 struct ct_fdmi2_port_attributes attrs;
3065 } rprt;
3066
3067 struct {
3068 uint8_t port_name[8];
3069 } dhba;
3070
3071 struct {
3072 uint8_t port_name[8];
3073 } dhat;
3074
3075 struct {
3076 uint8_t port_name[8];
3077 } dprt;
3078
3079 struct {
3080 uint8_t port_name[8];
3081 } dpa;
3082
3083 struct {
3084 uint8_t port_name[8];
3085 } gpsc;
3086
3087 struct {
3088 uint8_t reserved;
3089 uint8_t port_id[3];
3090 } gff_id;
3091
3092 struct {
3093 uint8_t port_name[8];
3094 } gid_pn;
3095 } req;
3096};
3097
3098
3099struct ct_rsp_hdr {
3100 struct ct_cmd_hdr header;
3101 __be16 response;
3102 uint16_t residual;
3103 uint8_t fragment_id;
3104 uint8_t reason_code;
3105 uint8_t explanation_code;
3106 uint8_t vendor_unique;
3107};
3108
3109struct ct_sns_gid_pt_data {
3110 uint8_t control_byte;
3111 be_id_t port_id;
3112};
3113
3114
3115struct ct_sns_gpnft_rsp {
3116 struct {
3117 struct ct_cmd_hdr header;
3118 uint16_t response;
3119 uint16_t residual;
3120 uint8_t fragment_id;
3121 uint8_t reason_code;
3122 uint8_t explanation_code;
3123 uint8_t vendor_unique;
3124 };
3125
3126 struct ct_sns_gpn_ft_data {
3127 u8 control_byte;
3128 u8 port_id[3];
3129 u32 reserved;
3130 u8 port_name[8];
3131 } entries[1];
3132};
3133
3134
3135struct ct_sns_rsp {
3136 struct ct_rsp_hdr header;
3137
3138 union {
3139 struct {
3140 uint8_t port_type;
3141 be_id_t port_id;
3142 uint8_t port_name[8];
3143 uint8_t sym_port_name_len;
3144 uint8_t sym_port_name[255];
3145 uint8_t node_name[8];
3146 uint8_t sym_node_name_len;
3147 uint8_t sym_node_name[255];
3148 uint8_t init_proc_assoc[8];
3149 uint8_t node_ip_addr[16];
3150 uint8_t class_of_service[4];
3151 uint8_t fc4_types[32];
3152 uint8_t ip_address[16];
3153 uint8_t fabric_port_name[8];
3154 uint8_t reserved;
3155 uint8_t hard_address[3];
3156 } ga_nxt;
3157
3158 struct {
3159
3160 struct ct_sns_gid_pt_data
3161 entries[MAX_FIBRE_DEVICES_MAX];
3162 } gid_pt;
3163
3164 struct {
3165 uint8_t port_name[8];
3166 } gpn_id;
3167
3168 struct {
3169 uint8_t node_name[8];
3170 } gnn_id;
3171
3172 struct {
3173 uint8_t fc4_types[32];
3174 } gft_id;
3175
3176 struct {
3177 uint32_t entry_count;
3178 uint8_t port_name[8];
3179 struct ct_fdmi1_hba_attributes attrs;
3180 } ghat;
3181
3182 struct {
3183 uint8_t port_name[8];
3184 } gfpn_id;
3185
3186 struct {
3187 __be16 speeds;
3188 __be16 speed;
3189 } gpsc;
3190
3191#define GFF_FCP_SCSI_OFFSET 7
3192#define GFF_NVME_OFFSET 23
3193 struct {
3194 uint8_t fc4_features[128];
3195 } gff_id;
3196 struct {
3197 uint8_t reserved;
3198 uint8_t port_id[3];
3199 } gid_pn;
3200 } rsp;
3201};
3202
3203struct ct_sns_pkt {
3204 union {
3205 struct ct_sns_req req;
3206 struct ct_sns_rsp rsp;
3207 } p;
3208};
3209
3210struct ct_sns_gpnft_pkt {
3211 union {
3212 struct ct_sns_req req;
3213 struct ct_sns_gpnft_rsp rsp;
3214 } p;
3215};
3216
3217enum scan_flags_t {
3218 SF_SCANNING = BIT_0,
3219 SF_QUEUED = BIT_1,
3220};
3221
3222enum fc4type_t {
3223 FS_FC4TYPE_FCP = BIT_0,
3224 FS_FC4TYPE_NVME = BIT_1,
3225 FS_FCP_IS_N2N = BIT_7,
3226};
3227
3228struct fab_scan_rp {
3229 port_id_t id;
3230 enum fc4type_t fc4type;
3231 u8 port_name[8];
3232 u8 node_name[8];
3233};
3234
3235struct fab_scan {
3236 struct fab_scan_rp *l;
3237 u32 size;
3238 u16 scan_retry;
3239#define MAX_SCAN_RETRIES 5
3240 enum scan_flags_t scan_flags;
3241 struct delayed_work scan_work;
3242};
3243
3244
3245
3246
3247#define RFT_ID_SNS_SCMD_LEN 22
3248#define RFT_ID_SNS_CMD_SIZE 60
3249#define RFT_ID_SNS_DATA_SIZE 16
3250
3251#define RNN_ID_SNS_SCMD_LEN 10
3252#define RNN_ID_SNS_CMD_SIZE 36
3253#define RNN_ID_SNS_DATA_SIZE 16
3254
3255#define GA_NXT_SNS_SCMD_LEN 6
3256#define GA_NXT_SNS_CMD_SIZE 28
3257#define GA_NXT_SNS_DATA_SIZE (620 + 16)
3258
3259#define GID_PT_SNS_SCMD_LEN 6
3260#define GID_PT_SNS_CMD_SIZE 28
3261
3262
3263
3264
3265#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3266
3267#define GPN_ID_SNS_SCMD_LEN 6
3268#define GPN_ID_SNS_CMD_SIZE 28
3269#define GPN_ID_SNS_DATA_SIZE (8 + 16)
3270
3271#define GNN_ID_SNS_SCMD_LEN 6
3272#define GNN_ID_SNS_CMD_SIZE 28
3273#define GNN_ID_SNS_DATA_SIZE (8 + 16)
3274
3275struct sns_cmd_pkt {
3276 union {
3277 struct {
3278 __le16 buffer_length;
3279 __le16 reserved_1;
3280 __le64 buffer_address __packed;
3281 __le16 subcommand_length;
3282 __le16 reserved_2;
3283 __le16 subcommand;
3284 __le16 size;
3285 uint32_t reserved_3;
3286 uint8_t param[36];
3287 } cmd;
3288
3289 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3290 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3291 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3292 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3293 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3294 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3295 } p;
3296};
3297
3298struct fw_blob {
3299 char *name;
3300 uint32_t segs[4];
3301 const struct firmware *fw;
3302};
3303
3304
3305struct gid_list_info {
3306 uint8_t al_pa;
3307 uint8_t area;
3308 uint8_t domain;
3309 uint8_t loop_id_2100;
3310 __le16 loop_id;
3311 uint16_t reserved_1;
3312};
3313
3314
3315typedef struct vport_info {
3316 uint8_t port_name[WWN_SIZE];
3317 uint8_t node_name[WWN_SIZE];
3318 int vp_id;
3319 uint16_t loop_id;
3320 unsigned long host_no;
3321 uint8_t port_id[3];
3322 int loop_state;
3323} vport_info_t;
3324
3325typedef struct vport_params {
3326 uint8_t port_name[WWN_SIZE];
3327 uint8_t node_name[WWN_SIZE];
3328 uint32_t options;
3329#define VP_OPTS_RETRY_ENABLE BIT_0
3330#define VP_OPTS_VP_DISABLE BIT_1
3331} vport_params_t;
3332
3333
3334#define VP_RET_CODE_OK 0
3335#define VP_RET_CODE_FATAL 1
3336#define VP_RET_CODE_WRONG_ID 2
3337#define VP_RET_CODE_WWPN 3
3338#define VP_RET_CODE_RESOURCES 4
3339#define VP_RET_CODE_NO_MEM 5
3340#define VP_RET_CODE_NOT_FOUND 6
3341
3342struct qla_hw_data;
3343struct rsp_que;
3344
3345
3346
3347struct isp_operations {
3348
3349 int (*pci_config) (struct scsi_qla_host *);
3350 int (*reset_chip)(struct scsi_qla_host *);
3351 int (*chip_diag) (struct scsi_qla_host *);
3352 void (*config_rings) (struct scsi_qla_host *);
3353 int (*reset_adapter)(struct scsi_qla_host *);
3354 int (*nvram_config) (struct scsi_qla_host *);
3355 void (*update_fw_options) (struct scsi_qla_host *);
3356 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3357
3358 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3359 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3360
3361 irq_handler_t intr_handler;
3362 void (*enable_intrs) (struct qla_hw_data *);
3363 void (*disable_intrs) (struct qla_hw_data *);
3364
3365 int (*abort_command) (srb_t *);
3366 int (*target_reset) (struct fc_port *, uint64_t, int);
3367 int (*lun_reset) (struct fc_port *, uint64_t, int);
3368 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3369 uint8_t, uint8_t, uint16_t *, uint8_t);
3370 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3371 uint8_t, uint8_t);
3372
3373 uint16_t (*calc_req_entries) (uint16_t);
3374 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3375 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3376 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3377 uint32_t);
3378
3379 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3380 uint32_t, uint32_t);
3381 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3382 uint32_t);
3383
3384 void (*fw_dump)(struct scsi_qla_host *vha);
3385 void (*mpi_fw_dump)(struct scsi_qla_host *, int);
3386
3387
3388 int (*beacon_on) (struct scsi_qla_host *);
3389 int (*beacon_off) (struct scsi_qla_host *);
3390
3391 void (*beacon_blink) (struct scsi_qla_host *);
3392
3393 void *(*read_optrom)(struct scsi_qla_host *, void *,
3394 uint32_t, uint32_t);
3395 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3396 uint32_t);
3397
3398 int (*get_flash_version) (struct scsi_qla_host *, void *);
3399 int (*start_scsi) (srb_t *);
3400 int (*start_scsi_mq) (srb_t *);
3401
3402
3403 int (*abort_isp) (struct scsi_qla_host *);
3404
3405 int (*iospace_config)(struct qla_hw_data *);
3406 int (*initialize_adapter)(struct scsi_qla_host *);
3407};
3408
3409
3410
3411#define QLA_MSIX_CHIP_REV_24XX 3
3412#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3413#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3414
3415#define QLA_BASE_VECTORS 2
3416#define QLA_MSIX_RSP_Q 0x01
3417#define QLA_ATIO_VECTOR 0x02
3418#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3419#define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
3420
3421#define QLA_MIDX_DEFAULT 0
3422#define QLA_MIDX_RSP_Q 1
3423#define QLA_PCI_MSIX_CONTROL 0xa2
3424#define QLA_83XX_PCI_MSIX_CONTROL 0x92
3425
3426struct scsi_qla_host;
3427
3428
3429#define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1
3430
3431struct qla_msix_entry {
3432 int have_irq;
3433 int in_use;
3434 uint32_t vector;
3435 uint16_t entry;
3436 char name[30];
3437 void *handle;
3438 int cpuid;
3439};
3440
3441#define WATCH_INTERVAL 1
3442
3443
3444enum qla_work_type {
3445 QLA_EVT_AEN,
3446 QLA_EVT_IDC_ACK,
3447 QLA_EVT_ASYNC_LOGIN,
3448 QLA_EVT_ASYNC_LOGOUT,
3449 QLA_EVT_ASYNC_ADISC,
3450 QLA_EVT_UEVENT,
3451 QLA_EVT_AENFX,
3452 QLA_EVT_GPNID,
3453 QLA_EVT_UNMAP,
3454 QLA_EVT_NEW_SESS,
3455 QLA_EVT_GPDB,
3456 QLA_EVT_PRLI,
3457 QLA_EVT_GPSC,
3458 QLA_EVT_GNL,
3459 QLA_EVT_NACK,
3460 QLA_EVT_RELOGIN,
3461 QLA_EVT_ASYNC_PRLO,
3462 QLA_EVT_ASYNC_PRLO_DONE,
3463 QLA_EVT_GPNFT,
3464 QLA_EVT_GPNFT_DONE,
3465 QLA_EVT_GNNFT_DONE,
3466 QLA_EVT_GNNID,
3467 QLA_EVT_GFPNID,
3468 QLA_EVT_SP_RETRY,
3469 QLA_EVT_IIDMA,
3470 QLA_EVT_ELS_PLOGI,
3471 QLA_EVT_SA_REPLACE,
3472};
3473
3474
3475struct qla_work_evt {
3476 struct list_head list;
3477 enum qla_work_type type;
3478 u32 flags;
3479#define QLA_EVT_FLAG_FREE 0x1
3480
3481 union {
3482 struct {
3483 enum fc_host_event_code code;
3484 u32 data;
3485 } aen;
3486 struct {
3487#define QLA_IDC_ACK_REGS 7
3488 uint16_t mb[QLA_IDC_ACK_REGS];
3489 } idc_ack;
3490 struct {
3491 struct fc_port *fcport;
3492#define QLA_LOGIO_LOGIN_RETRIED BIT_0
3493 u16 data[2];
3494 } logio;
3495 struct {
3496 u32 code;
3497#define QLA_UEVENT_CODE_FW_DUMP 0
3498 } uevent;
3499 struct {
3500 uint32_t evtcode;
3501 uint32_t mbx[8];
3502 uint32_t count;
3503 } aenfx;
3504 struct {
3505 srb_t *sp;
3506 } iosb;
3507 struct {
3508 port_id_t id;
3509 } gpnid;
3510 struct {
3511 port_id_t id;
3512 u8 port_name[8];
3513 u8 node_name[8];
3514 void *pla;
3515 u8 fc4_type;
3516 } new_sess;
3517 struct {
3518 fc_port_t *fcport;
3519 u8 opt;
3520 } fcport;
3521 struct {
3522 fc_port_t *fcport;
3523 u8 iocb[IOCB_SIZE];
3524 int type;
3525 } nack;
3526 struct {
3527 u8 fc4_type;
3528 srb_t *sp;
3529 } gpnft;
3530 struct {
3531 struct edif_sa_ctl *sa_ctl;
3532 fc_port_t *fcport;
3533 uint16_t nport_handle;
3534 } sa_update;
3535 } u;
3536};
3537
3538struct qla_chip_state_84xx {
3539 struct list_head list;
3540 struct kref kref;
3541
3542 void *bus;
3543 spinlock_t access_lock;
3544 struct mutex fw_update_mutex;
3545 uint32_t fw_update;
3546 uint32_t op_fw_version;
3547 uint32_t op_fw_size;
3548 uint32_t op_fw_seq_size;
3549 uint32_t diag_fw_version;
3550 uint32_t gold_fw_version;
3551};
3552
3553struct qla_dif_statistics {
3554 uint64_t dif_input_bytes;
3555 uint64_t dif_output_bytes;
3556 uint64_t dif_input_requests;
3557 uint64_t dif_output_requests;
3558 uint32_t dif_guard_err;
3559 uint32_t dif_ref_tag_err;
3560 uint32_t dif_app_tag_err;
3561};
3562
3563struct qla_statistics {
3564 uint32_t total_isp_aborts;
3565 uint64_t input_bytes;
3566 uint64_t output_bytes;
3567 uint64_t input_requests;
3568 uint64_t output_requests;
3569 uint32_t control_requests;
3570
3571 uint64_t jiffies_at_last_reset;
3572 uint32_t stat_max_pend_cmds;
3573 uint32_t stat_max_qfull_cmds_alloc;
3574 uint32_t stat_max_qfull_cmds_dropped;
3575
3576 struct qla_dif_statistics qla_dif_stats;
3577};
3578
3579struct bidi_statistics {
3580 unsigned long long io_count;
3581 unsigned long long transfer_bytes;
3582};
3583
3584struct qla_tc_param {
3585 struct scsi_qla_host *vha;
3586 uint32_t blk_sz;
3587 uint32_t bufflen;
3588 struct scatterlist *sg;
3589 struct scatterlist *prot_sg;
3590 struct crc_context *ctx;
3591 uint8_t *ctx_dsd_alloced;
3592};
3593
3594
3595#define MBC_INITIALIZE_MULTIQ 0x1f
3596#define QLA_QUE_PAGE 0X1000
3597#define QLA_MQ_SIZE 32
3598#define QLA_MAX_QUEUES 256
3599#define ISP_QUE_REG(ha, id) \
3600 ((ha->mqenable || IS_QLA83XX(ha) || \
3601 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3602 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3603 ((void __iomem *)ha->iobase))
3604#define QLA_REQ_QUE_ID(tag) \
3605 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3606#define QLA_DEFAULT_QUE_QOS 5
3607#define QLA_PRECONFIG_VPORTS 32
3608#define QLA_MAX_VPORTS_QLA24XX 128
3609#define QLA_MAX_VPORTS_QLA25XX 256
3610
3611struct qla_tgt_counters {
3612 uint64_t qla_core_sbt_cmd;
3613 uint64_t core_qla_que_buf;
3614 uint64_t qla_core_ret_ctio;
3615 uint64_t core_qla_snd_status;
3616 uint64_t qla_core_ret_sta_ctio;
3617 uint64_t core_qla_free_cmd;
3618 uint64_t num_q_full_sent;
3619 uint64_t num_alloc_iocb_failed;
3620 uint64_t num_term_xchg_sent;
3621};
3622
3623struct qla_counters {
3624 uint64_t input_bytes;
3625 uint64_t input_requests;
3626 uint64_t output_bytes;
3627 uint64_t output_requests;
3628
3629};
3630
3631struct qla_qpair;
3632
3633
3634struct rsp_que {
3635 dma_addr_t dma;
3636 response_t *ring;
3637 response_t *ring_ptr;
3638 __le32 __iomem *rsp_q_in;
3639 __le32 __iomem *rsp_q_out;
3640 uint16_t ring_index;
3641 uint16_t out_ptr;
3642 uint16_t *in_ptr;
3643 uint16_t length;
3644 uint16_t options;
3645 uint16_t rid;
3646 uint16_t id;
3647 uint16_t vp_idx;
3648 struct qla_hw_data *hw;
3649 struct qla_msix_entry *msix;
3650 struct req_que *req;
3651 srb_t *status_srb;
3652 struct qla_qpair *qpair;
3653
3654 dma_addr_t dma_fx00;
3655 response_t *ring_fx00;
3656 uint16_t length_fx00;
3657 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3658};
3659
3660
3661struct req_que {
3662 dma_addr_t dma;
3663 request_t *ring;
3664 request_t *ring_ptr;
3665 __le32 __iomem *req_q_in;
3666 __le32 __iomem *req_q_out;
3667 uint16_t ring_index;
3668 uint16_t in_ptr;
3669 uint16_t *out_ptr;
3670 uint16_t cnt;
3671 uint16_t length;
3672 uint16_t options;
3673 uint16_t rid;
3674 uint16_t id;
3675 uint16_t qos;
3676 uint16_t vp_idx;
3677 struct rsp_que *rsp;
3678 srb_t **outstanding_cmds;
3679 uint32_t current_outstanding_cmd;
3680 uint16_t num_outstanding_cmds;
3681 int max_q_depth;
3682
3683 dma_addr_t dma_fx00;
3684 request_t *ring_fx00;
3685 uint16_t length_fx00;
3686 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3687};
3688
3689struct qla_fw_resources {
3690 u16 iocbs_total;
3691 u16 iocbs_limit;
3692 u16 iocbs_qp_limit;
3693 u16 iocbs_used;
3694};
3695
3696#define QLA_IOCB_PCT_LIMIT 95
3697
3698
3699struct qla_qpair {
3700 spinlock_t qp_lock;
3701 atomic_t ref_count;
3702 uint32_t lun_cnt;
3703
3704
3705
3706
3707 spinlock_t *qp_lock_ptr;
3708 struct scsi_qla_host *vha;
3709 u32 chip_reset;
3710
3711
3712
3713
3714
3715
3716 uint32_t online:1;
3717
3718 uint32_t difdix_supported:1;
3719 uint32_t delete_in_progress:1;
3720 uint32_t fw_started:1;
3721 uint32_t enable_class_2:1;
3722 uint32_t enable_explicit_conf:1;
3723 uint32_t use_shadow_reg:1;
3724 uint32_t rcv_intr:1;
3725
3726 uint16_t id;
3727 uint16_t vp_idx;
3728 mempool_t *srb_mempool;
3729
3730 struct pci_dev *pdev;
3731 void (*reqq_start_iocbs)(struct qla_qpair *);
3732
3733
3734 struct req_que *req;
3735 struct rsp_que *rsp;
3736 struct atio_que *atio;
3737 struct qla_msix_entry *msix;
3738 struct qla_hw_data *hw;
3739 struct work_struct q_work;
3740 struct qla_counters counters;
3741
3742 struct list_head qp_list_elem;
3743 struct list_head hints_list;
3744
3745 uint16_t retry_term_cnt;
3746 __le32 retry_term_exchg_addr;
3747 uint64_t retry_term_jiff;
3748 struct qla_tgt_counters tgt_counters;
3749 uint16_t cpuid;
3750 struct qla_fw_resources fwres ____cacheline_aligned;
3751 u32 cmd_cnt;
3752 u32 cmd_completion_cnt;
3753};
3754
3755
3756struct qlfc_fw {
3757 void *fw_buf;
3758 dma_addr_t fw_dma;
3759 uint32_t len;
3760};
3761
3762struct rdp_req_payload {
3763 uint32_t els_request;
3764 uint32_t desc_list_len;
3765
3766
3767 struct {
3768 uint32_t desc_tag;
3769 uint32_t desc_len;
3770 uint8_t reserved;
3771 uint8_t nport_id[3];
3772 } npiv_desc;
3773};
3774
3775struct rdp_rsp_payload {
3776 struct {
3777 __be32 cmd;
3778 __be32 len;
3779 } hdr;
3780
3781
3782 struct {
3783 __be32 desc_tag;
3784 __be32 desc_len;
3785 __be32 req_payload_word_0;
3786 } ls_req_info_desc;
3787
3788
3789 struct {
3790 __be32 desc_tag;
3791 __be32 desc_len;
3792 __be32 req_payload_word_0;
3793 } ls_req_info_desc2;
3794
3795
3796 struct {
3797 __be32 desc_tag;
3798 __be32 desc_len;
3799 __be16 temperature;
3800 __be16 vcc;
3801 __be16 tx_bias;
3802 __be16 tx_power;
3803 __be16 rx_power;
3804 __be16 sfp_flags;
3805 } sfp_diag_desc;
3806
3807
3808 struct {
3809 __be32 desc_tag;
3810 __be32 desc_len;
3811 __be16 speed_capab;
3812 __be16 operating_speed;
3813 } port_speed_desc;
3814
3815
3816 struct {
3817 __be32 desc_tag;
3818 __be32 desc_len;
3819 __be32 link_fail_cnt;
3820 __be32 loss_sync_cnt;
3821 __be32 loss_sig_cnt;
3822 __be32 prim_seq_err_cnt;
3823 __be32 inval_xmit_word_cnt;
3824 __be32 inval_crc_cnt;
3825 uint8_t pn_port_phy_type;
3826 uint8_t reserved[3];
3827 } ls_err_desc;
3828
3829
3830 struct {
3831 __be32 desc_tag;
3832 __be32 desc_len;
3833 uint8_t WWNN[WWN_SIZE];
3834 uint8_t WWPN[WWN_SIZE];
3835 } port_name_diag_desc;
3836
3837
3838 struct {
3839 __be32 desc_tag;
3840 __be32 desc_len;
3841 uint8_t WWNN[WWN_SIZE];
3842 uint8_t WWPN[WWN_SIZE];
3843 } port_name_direct_desc;
3844
3845
3846 struct {
3847 __be32 desc_tag;
3848 __be32 desc_len;
3849 __be32 fcport_b2b;
3850 __be32 attached_fcport_b2b;
3851 __be32 fcport_rtt;
3852 } buffer_credit_desc;
3853
3854
3855 struct {
3856 __be32 desc_tag;
3857 __be32 desc_len;
3858 __be16 high_alarm;
3859 __be16 low_alarm;
3860 __be16 high_warn;
3861 __be16 low_warn;
3862 __be32 element_flags;
3863 } optical_elmt_desc[5];
3864
3865
3866 struct {
3867 __be32 desc_tag;
3868 __be32 desc_len;
3869 uint8_t vendor_name[16];
3870 uint8_t part_number[16];
3871 uint8_t serial_number[16];
3872 uint8_t revision[4];
3873 uint8_t date[8];
3874 } optical_prod_desc;
3875};
3876
3877#define RDP_DESC_LEN(obj) \
3878 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
3879
3880#define RDP_PORT_SPEED_1GB BIT_15
3881#define RDP_PORT_SPEED_2GB BIT_14
3882#define RDP_PORT_SPEED_4GB BIT_13
3883#define RDP_PORT_SPEED_10GB BIT_12
3884#define RDP_PORT_SPEED_8GB BIT_11
3885#define RDP_PORT_SPEED_16GB BIT_10
3886#define RDP_PORT_SPEED_32GB BIT_9
3887#define RDP_PORT_SPEED_64GB BIT_8
3888#define RDP_PORT_SPEED_UNKNOWN BIT_0
3889
3890struct scsi_qlt_host {
3891 void *target_lport_ptr;
3892 struct mutex tgt_mutex;
3893 struct mutex tgt_host_action_mutex;
3894 struct qla_tgt *qla_tgt;
3895};
3896
3897struct qlt_hw_data {
3898
3899 uint32_t node_name_set:1;
3900
3901 dma_addr_t atio_dma;
3902 struct atio *atio_ring;
3903 struct atio *atio_ring_ptr;
3904 uint16_t atio_ring_index;
3905 uint16_t atio_q_length;
3906 __le32 __iomem *atio_q_in;
3907 __le32 __iomem *atio_q_out;
3908
3909 const struct qla_tgt_func_tmpl *tgt_ops;
3910 struct qla_tgt_vp_map *tgt_vp_map;
3911
3912 int saved_set;
3913 __le16 saved_exchange_count;
3914 __le32 saved_firmware_options_1;
3915 __le32 saved_firmware_options_2;
3916 __le32 saved_firmware_options_3;
3917 uint8_t saved_firmware_options[2];
3918 uint8_t saved_add_firmware_options[2];
3919
3920 uint8_t tgt_node_name[WWN_SIZE];
3921
3922 struct dentry *dfs_tgt_sess;
3923 struct dentry *dfs_tgt_port_database;
3924 struct dentry *dfs_naqp;
3925
3926 struct list_head q_full_list;
3927 uint32_t num_pend_cmds;
3928 uint32_t num_qfull_cmds_alloc;
3929 uint32_t num_qfull_cmds_dropped;
3930 spinlock_t q_full_lock;
3931 uint32_t leak_exchg_thresh_hold;
3932 spinlock_t sess_lock;
3933 int num_act_qpairs;
3934#define DEFAULT_NAQP 2
3935 spinlock_t atio_lock ____cacheline_aligned;
3936};
3937
3938#define MAX_QFULL_CMDS_ALLOC 8192
3939#define Q_FULL_THRESH_HOLD_PERCENT 90
3940#define Q_FULL_THRESH_HOLD(ha) \
3941 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3942
3943#define LEAK_EXCHG_THRESH_HOLD_PERCENT 75
3944
3945struct qla_hw_data_stat {
3946 u32 num_fw_dump;
3947 u32 num_mpi_reset;
3948};
3949
3950
3951typedef enum {
3952 QLA_PCI_RESUME,
3953 QLA_PCI_ERR_DETECTED,
3954 QLA_PCI_MMIO_ENABLED,
3955 QLA_PCI_SLOT_RESET,
3956} pci_error_state_t;
3957
3958
3959
3960struct qla_hw_data {
3961 struct pci_dev *pdev;
3962
3963#define SRB_MIN_REQ 128
3964 mempool_t *srb_mempool;
3965
3966 volatile struct {
3967 uint32_t mbox_int :1;
3968 uint32_t mbox_busy :1;
3969 uint32_t disable_risc_code_load :1;
3970 uint32_t enable_64bit_addressing :1;
3971 uint32_t enable_lip_reset :1;
3972 uint32_t enable_target_reset :1;
3973 uint32_t enable_lip_full_login :1;
3974 uint32_t enable_led_scheme :1;
3975
3976 uint32_t msi_enabled :1;
3977 uint32_t msix_enabled :1;
3978 uint32_t disable_serdes :1;
3979 uint32_t gpsc_supported :1;
3980 uint32_t npiv_supported :1;
3981 uint32_t pci_channel_io_perm_failure :1;
3982 uint32_t fce_enabled :1;
3983 uint32_t fac_supported :1;
3984
3985 uint32_t chip_reset_done :1;
3986 uint32_t running_gold_fw :1;
3987 uint32_t eeh_busy :1;
3988 uint32_t disable_msix_handshake :1;
3989 uint32_t fcp_prio_enabled :1;
3990 uint32_t isp82xx_fw_hung:1;
3991 uint32_t nic_core_hung:1;
3992
3993 uint32_t quiesce_owner:1;
3994 uint32_t nic_core_reset_hdlr_active:1;
3995 uint32_t nic_core_reset_owner:1;
3996 uint32_t isp82xx_no_md_cap:1;
3997 uint32_t host_shutting_down:1;
3998 uint32_t idc_compl_status:1;
3999 uint32_t mr_reset_hdlr_active:1;
4000 uint32_t mr_intr_valid:1;
4001
4002 uint32_t dport_enabled:1;
4003 uint32_t fawwpn_enabled:1;
4004 uint32_t exlogins_enabled:1;
4005 uint32_t exchoffld_enabled:1;
4006
4007 uint32_t lip_ae:1;
4008 uint32_t n2n_ae:1;
4009 uint32_t fw_started:1;
4010 uint32_t fw_init_done:1;
4011
4012 uint32_t lr_detected:1;
4013
4014 uint32_t rida_fmt2:1;
4015 uint32_t purge_mbox:1;
4016 uint32_t n2n_bigger:1;
4017 uint32_t secure_adapter:1;
4018 uint32_t secure_fw:1;
4019
4020 uint32_t scm_supported_a:1;
4021
4022 uint32_t scm_supported_f:1;
4023
4024 uint32_t scm_enabled:1;
4025 uint32_t edif_hw:1;
4026 uint32_t edif_enabled:1;
4027 uint32_t n2n_fw_acc_sec:1;
4028 uint32_t plogi_template_valid:1;
4029 uint32_t port_isolated:1;
4030 } flags;
4031
4032 uint16_t max_exchg;
4033 uint16_t lr_distance;
4034#define LR_DISTANCE_5K 1
4035#define LR_DISTANCE_10K 0
4036
4037
4038
4039
4040
4041
4042
4043
4044 spinlock_t hardware_lock ____cacheline_aligned;
4045 int bars;
4046 int mem_only;
4047 device_reg_t *iobase;
4048 resource_size_t pio_address;
4049
4050#define MIN_IOBASE_LEN 0x100
4051 dma_addr_t bar0_hdl;
4052
4053 void __iomem *cregbase;
4054 dma_addr_t bar2_hdl;
4055#define BAR0_LEN_FX00 (1024 * 1024)
4056#define BAR2_LEN_FX00 (128 * 1024)
4057
4058 uint32_t rqstq_intr_code;
4059 uint32_t mbx_intr_code;
4060 uint32_t req_que_len;
4061 uint32_t rsp_que_len;
4062 uint32_t req_que_off;
4063 uint32_t rsp_que_off;
4064
4065
4066 device_reg_t *mqiobase;
4067 device_reg_t *msixbase;
4068 uint16_t msix_count;
4069 uint8_t mqenable;
4070 struct req_que **req_q_map;
4071 struct rsp_que **rsp_q_map;
4072 struct qla_qpair **queue_pair_map;
4073 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
4074 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
4075 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
4076 / sizeof(unsigned long)];
4077 uint8_t max_req_queues;
4078 uint8_t max_rsp_queues;
4079 uint8_t max_qpairs;
4080 uint8_t num_qpairs;
4081 struct qla_qpair *base_qpair;
4082 struct qla_npiv_entry *npiv_info;
4083 uint16_t nvram_npiv_size;
4084
4085 uint16_t switch_cap;
4086#define FLOGI_SEQ_DEL BIT_8
4087#define FLOGI_MID_SUPPORT BIT_10
4088#define FLOGI_VSAN_SUPPORT BIT_12
4089#define FLOGI_SP_SUPPORT BIT_13
4090
4091 uint8_t port_no;
4092 uint8_t exch_starvation;
4093
4094
4095 uint8_t loop_down_abort_time;
4096 atomic_t loop_down_timer;
4097 uint8_t link_down_timeout;
4098 uint16_t max_loop_id;
4099 uint16_t max_fibre_devices;
4100
4101 uint16_t fb_rev;
4102 uint16_t min_external_loopid;
4103
4104#define PORT_SPEED_UNKNOWN 0xFFFF
4105#define PORT_SPEED_1GB 0x00
4106#define PORT_SPEED_2GB 0x01
4107#define PORT_SPEED_AUTO 0x02
4108#define PORT_SPEED_4GB 0x03
4109#define PORT_SPEED_8GB 0x04
4110#define PORT_SPEED_16GB 0x05
4111#define PORT_SPEED_32GB 0x06
4112#define PORT_SPEED_64GB 0x07
4113#define PORT_SPEED_10GB 0x13
4114 uint16_t link_data_rate;
4115 uint16_t set_data_rate;
4116
4117 uint8_t current_topology;
4118 uint8_t prev_topology;
4119#define ISP_CFG_NL 1
4120#define ISP_CFG_N 2
4121#define ISP_CFG_FL 4
4122#define ISP_CFG_F 8
4123
4124 uint8_t operating_mode;
4125#define LOOP 0
4126#define P2P 1
4127#define LOOP_P2P 2
4128#define P2P_LOOP 3
4129 uint8_t interrupts_on;
4130 uint32_t isp_abort_cnt;
4131#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
4132#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
4133#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
4134#define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
4135#define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
4136#define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
4137#define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
4138#define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
4139#define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
4140#define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
4141#define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
4142#define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
4143#define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
4144
4145 uint32_t isp_type;
4146#define DT_ISP2100 BIT_0
4147#define DT_ISP2200 BIT_1
4148#define DT_ISP2300 BIT_2
4149#define DT_ISP2312 BIT_3
4150#define DT_ISP2322 BIT_4
4151#define DT_ISP6312 BIT_5
4152#define DT_ISP6322 BIT_6
4153#define DT_ISP2422 BIT_7
4154#define DT_ISP2432 BIT_8
4155#define DT_ISP5422 BIT_9
4156#define DT_ISP5432 BIT_10
4157#define DT_ISP2532 BIT_11
4158#define DT_ISP8432 BIT_12
4159#define DT_ISP8001 BIT_13
4160#define DT_ISP8021 BIT_14
4161#define DT_ISP2031 BIT_15
4162#define DT_ISP8031 BIT_16
4163#define DT_ISPFX00 BIT_17
4164#define DT_ISP8044 BIT_18
4165#define DT_ISP2071 BIT_19
4166#define DT_ISP2271 BIT_20
4167#define DT_ISP2261 BIT_21
4168#define DT_ISP2061 BIT_22
4169#define DT_ISP2081 BIT_23
4170#define DT_ISP2089 BIT_24
4171#define DT_ISP2281 BIT_25
4172#define DT_ISP2289 BIT_26
4173#define DT_ISP_LAST (DT_ISP2289 << 1)
4174
4175 uint32_t device_type;
4176#define DT_T10_PI BIT_25
4177#define DT_IIDMA BIT_26
4178#define DT_FWI2 BIT_27
4179#define DT_ZIO_SUPPORTED BIT_28
4180#define DT_OEM_001 BIT_29
4181#define DT_ISP2200A BIT_30
4182#define DT_EXTENDED_IDS BIT_31
4183
4184#define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
4185#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
4186#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
4187#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
4188#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
4189#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
4190#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
4191#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
4192#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
4193#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
4194#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
4195#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
4196#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
4197#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
4198#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
4199#define IS_QLA81XX(ha) (IS_QLA8001(ha))
4200#define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
4201#define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
4202#define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
4203#define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
4204#define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
4205#define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
4206#define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
4207#define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
4208#define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
4209#define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
4210
4211#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
4212 IS_QLA6312(ha) || IS_QLA6322(ha))
4213#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
4214#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
4215#define IS_QLA25XX(ha) (IS_QLA2532(ha))
4216#define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
4217#define IS_QLA84XX(ha) (IS_QLA8432(ha))
4218#define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
4219#define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
4220#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
4221 IS_QLA84XX(ha))
4222#define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
4223 IS_QLA8031(ha) || IS_QLA8044(ha))
4224#define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
4225#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
4226 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
4227 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
4228 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
4229 IS_QLA28XX(ha))
4230#define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4231 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4232#define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
4233#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4234 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4235#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4236 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4237#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
4238
4239#define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
4240#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
4241#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4242#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
4243#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
4244#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
4245#define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
4246#define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \
4247 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4248#define IS_BIDI_CAPABLE(ha) \
4249 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4250
4251#define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
4252 ((ha)->fw_attributes_ext[0] & BIT_0))
4253#define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14)
4254#define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS)
4255#define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD)
4256#define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp))
4257#define QLA_LS_ABTS_WAIT_ENABLED(_sp) \
4258 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4259#define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \
4260 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4261#define QLA_ABTS_WAIT_ENABLED(_sp) \
4262 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4263
4264#define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4265#define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4266#define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
4267#define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4268 IS_QLA28XX(ha))
4269#define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
4270 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
4271#define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4272 IS_QLA28XX(ha))
4273#define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
4274#define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4275#define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4276 IS_QLA28XX(ha))
4277#define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4278 IS_QLA28XX(ha))
4279#define IS_EXCHG_OFFLD_CAPABLE(ha) \
4280 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4281#define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
4282 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4283 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4284#define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
4285 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4286
4287#define IS_ZIO_THRESHOLD_CAPABLE(ha) \
4288 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\
4289 (ha->zio_mode == QLA_ZIO_MODE_6))
4290
4291
4292 uint8_t serial0;
4293 uint8_t serial1;
4294 uint8_t serial2;
4295
4296
4297#define MAX_NVRAM_SIZE 4096
4298#define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
4299 uint16_t nvram_size;
4300 uint16_t nvram_base;
4301 void *nvram;
4302 uint16_t vpd_size;
4303 uint16_t vpd_base;
4304 void *vpd;
4305
4306 uint16_t loop_reset_delay;
4307 uint8_t retry_count;
4308 uint8_t login_timeout;
4309 uint16_t r_a_tov;
4310 int port_down_retry_count;
4311 uint8_t mbx_count;
4312 uint8_t aen_mbx_count;
4313 atomic_t num_pend_mbx_stage1;
4314 atomic_t num_pend_mbx_stage2;
4315 atomic_t num_pend_mbx_stage3;
4316 uint16_t frame_payload_size;
4317
4318 uint32_t login_retry_count;
4319
4320 ms_iocb_entry_t *ms_iocb;
4321 dma_addr_t ms_iocb_dma;
4322 struct ct_sns_pkt *ct_sns;
4323 dma_addr_t ct_sns_dma;
4324
4325 struct sns_cmd_pkt *sns_cmd;
4326 dma_addr_t sns_cmd_dma;
4327
4328#define SFP_DEV_SIZE 512
4329#define SFP_BLOCK_SIZE 64
4330#define SFP_RTDI_LEN SFP_BLOCK_SIZE
4331
4332 void *sfp_data;
4333 dma_addr_t sfp_data_dma;
4334
4335 struct qla_flt_header *flt;
4336 dma_addr_t flt_dma;
4337
4338#define XGMAC_DATA_SIZE 4096
4339 void *xgmac_data;
4340 dma_addr_t xgmac_data_dma;
4341
4342#define DCBX_TLV_DATA_SIZE 4096
4343 void *dcbx_tlv;
4344 dma_addr_t dcbx_tlv_dma;
4345
4346 struct task_struct *dpc_thread;
4347 uint8_t dpc_active;
4348
4349 dma_addr_t gid_list_dma;
4350 struct gid_list_info *gid_list;
4351 int gid_list_info_size;
4352
4353
4354#define DMA_POOL_SIZE 256
4355 struct dma_pool *s_dma_pool;
4356
4357 dma_addr_t init_cb_dma;
4358 init_cb_t *init_cb;
4359 int init_cb_size;
4360 dma_addr_t ex_init_cb_dma;
4361 struct ex_init_cb_81xx *ex_init_cb;
4362 dma_addr_t sf_init_cb_dma;
4363 struct init_sf_cb *sf_init_cb;
4364
4365 void *scm_fpin_els_buff;
4366 uint64_t scm_fpin_els_buff_size;
4367 bool scm_fpin_valid;
4368 bool scm_fpin_payload_size;
4369
4370 void *async_pd;
4371 dma_addr_t async_pd_dma;
4372
4373#define ENABLE_EXTENDED_LOGIN BIT_7
4374
4375
4376 void *exlogin_buf;
4377 dma_addr_t exlogin_buf_dma;
4378 uint32_t exlogin_size;
4379
4380#define ENABLE_EXCHANGE_OFFLD BIT_2
4381
4382
4383 void *exchoffld_buf;
4384 dma_addr_t exchoffld_buf_dma;
4385 int exchoffld_size;
4386 int exchoffld_count;
4387
4388
4389 struct fc_els_flogi plogi_els_payld;
4390#define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
4391
4392 void *swl;
4393
4394
4395 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4396 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4397 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4398
4399 mbx_cmd_t *mcp;
4400 struct mbx_cmd_32 *mcp32;
4401
4402 unsigned long mbx_cmd_flags;
4403#define MBX_INTERRUPT 1
4404#define MBX_INTR_WAIT 2
4405#define MBX_UPDATE_FLASH_ACTIVE 3
4406
4407 struct mutex vport_lock;
4408 spinlock_t vport_slock;
4409 struct mutex mq_lock;
4410 struct completion mbx_cmd_comp;
4411 struct completion mbx_intr_comp;
4412 struct completion dcbx_comp;
4413 struct completion lb_portup_comp;
4414
4415#define DCBX_COMP_TIMEOUT 20
4416#define LB_PORTUP_COMP_TIMEOUT 10
4417
4418 int notify_dcbx_comp;
4419 int notify_lb_portup_comp;
4420 struct mutex selflogin_lock;
4421
4422
4423 uint16_t fw_major_version;
4424 uint16_t fw_minor_version;
4425 uint16_t fw_subminor_version;
4426 uint16_t fw_attributes;
4427 uint16_t fw_attributes_h;
4428#define FW_ATTR_H_NVME_FBURST BIT_1
4429#define FW_ATTR_H_NVME BIT_10
4430#define FW_ATTR_H_NVME_UPDATED BIT_14
4431
4432
4433#define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
4434
4435#define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
4436
4437#define FW_ATTR_EXT0_SCM_CISCO 0x00002000
4438#define FW_ATTR_EXT0_NVME2 BIT_13
4439#define FW_ATTR_EXT0_EDIF BIT_5
4440 uint16_t fw_attributes_ext[2];
4441 uint32_t fw_memory_size;
4442 uint32_t fw_transfer_size;
4443 uint32_t fw_srisc_address;
4444#define RISC_START_ADDRESS_2100 0x1000
4445#define RISC_START_ADDRESS_2300 0x800
4446#define RISC_START_ADDRESS_2400 0x100000
4447
4448 uint16_t orig_fw_tgt_xcb_count;
4449 uint16_t cur_fw_tgt_xcb_count;
4450 uint16_t orig_fw_xcb_count;
4451 uint16_t cur_fw_xcb_count;
4452 uint16_t orig_fw_iocb_count;
4453 uint16_t cur_fw_iocb_count;
4454 uint16_t fw_max_fcf_count;
4455
4456 uint32_t fw_shared_ram_start;
4457 uint32_t fw_shared_ram_end;
4458 uint32_t fw_ddr_ram_start;
4459 uint32_t fw_ddr_ram_end;
4460
4461 uint16_t fw_options[16];
4462 uint8_t fw_seriallink_options[4];
4463 __le16 fw_seriallink_options24[4];
4464
4465 uint8_t serdes_version[3];
4466 uint8_t mpi_version[3];
4467 uint32_t mpi_capabilities;
4468 uint8_t phy_version[3];
4469 uint8_t pep_version[3];
4470
4471
4472 struct fwdt {
4473 void *template;
4474 ulong length;
4475 ulong dump_size;
4476 } fwdt[2];
4477 struct qla2xxx_fw_dump *fw_dump;
4478 uint32_t fw_dump_len;
4479 u32 fw_dump_alloc_len;
4480 bool fw_dumped;
4481 unsigned long fw_dump_cap_flags;
4482#define RISC_PAUSE_CMPL 0
4483#define DMA_SHUTDOWN_CMPL 1
4484#define ISP_RESET_CMPL 2
4485#define RISC_RDY_AFT_RESET 3
4486#define RISC_SRAM_DUMP_CMPL 4
4487#define RISC_EXT_MEM_DUMP_CMPL 5
4488#define ISP_MBX_RDY 6
4489#define ISP_SOFT_RESET_CMPL 7
4490 int fw_dump_reading;
4491 void *mpi_fw_dump;
4492 u32 mpi_fw_dump_len;
4493 unsigned int mpi_fw_dump_reading:1;
4494 unsigned int mpi_fw_dumped:1;
4495 int prev_minidump_failed;
4496 dma_addr_t eft_dma;
4497 void *eft;
4498
4499#define MCTP_DUMP_SIZE 0x086064
4500 dma_addr_t mctp_dump_dma;
4501 void *mctp_dump;
4502 int mctp_dumped;
4503 int mctp_dump_reading;
4504 uint32_t chain_offset;
4505 struct dentry *dfs_dir;
4506 struct dentry *dfs_fce;
4507 struct dentry *dfs_tgt_counters;
4508 struct dentry *dfs_fw_resource_cnt;
4509
4510 dma_addr_t fce_dma;
4511 void *fce;
4512 uint32_t fce_bufs;
4513 uint16_t fce_mb[8];
4514 uint64_t fce_wr, fce_rd;
4515 struct mutex fce_mutex;
4516
4517 uint32_t pci_attr;
4518 uint16_t chip_revision;
4519
4520 uint16_t product_id[4];
4521
4522 uint8_t model_number[16+1];
4523 char model_desc[80];
4524 uint8_t adapter_id[16+1];
4525
4526
4527 char *optrom_buffer;
4528 uint32_t optrom_size;
4529 int optrom_state;
4530#define QLA_SWAITING 0
4531#define QLA_SREADING 1
4532#define QLA_SWRITING 2
4533 uint32_t optrom_region_start;
4534 uint32_t optrom_region_size;
4535 struct mutex optrom_mutex;
4536
4537
4538#define ROM_CODE_TYPE_BIOS 0
4539#define ROM_CODE_TYPE_FCODE 1
4540#define ROM_CODE_TYPE_EFI 3
4541 uint8_t bios_revision[2];
4542 uint8_t efi_revision[2];
4543 uint8_t fcode_revision[16];
4544 uint32_t fw_revision[4];
4545
4546 uint32_t gold_fw_version[4];
4547
4548
4549 uint32_t flash_conf_off;
4550 uint32_t flash_data_off;
4551 uint32_t nvram_conf_off;
4552 uint32_t nvram_data_off;
4553
4554 uint32_t fdt_wrt_disable;
4555 uint32_t fdt_wrt_enable;
4556 uint32_t fdt_erase_cmd;
4557 uint32_t fdt_block_size;
4558 uint32_t fdt_unprotect_sec_cmd;
4559 uint32_t fdt_protect_sec_cmd;
4560 uint32_t fdt_wrt_sts_reg_cmd;
4561
4562 struct {
4563 uint32_t flt_region_flt;
4564 uint32_t flt_region_fdt;
4565 uint32_t flt_region_boot;
4566 uint32_t flt_region_boot_sec;
4567 uint32_t flt_region_fw;
4568 uint32_t flt_region_fw_sec;
4569 uint32_t flt_region_vpd_nvram;
4570 uint32_t flt_region_vpd_nvram_sec;
4571 uint32_t flt_region_vpd;
4572 uint32_t flt_region_vpd_sec;
4573 uint32_t flt_region_nvram;
4574 uint32_t flt_region_nvram_sec;
4575 uint32_t flt_region_npiv_conf;
4576 uint32_t flt_region_gold_fw;
4577 uint32_t flt_region_fcp_prio;
4578 uint32_t flt_region_bootload;
4579 uint32_t flt_region_img_status_pri;
4580 uint32_t flt_region_img_status_sec;
4581 uint32_t flt_region_aux_img_status_pri;
4582 uint32_t flt_region_aux_img_status_sec;
4583 };
4584 uint8_t active_image;
4585
4586
4587 uint16_t beacon_blink_led;
4588 uint8_t beacon_color_state;
4589#define QLA_LED_GRN_ON 0x01
4590#define QLA_LED_YLW_ON 0x02
4591#define QLA_LED_ABR_ON 0x04
4592#define QLA_LED_ALL_ON 0x07
4593
4594 uint16_t zio_mode;
4595 uint16_t zio_timer;
4596
4597 struct qla_msix_entry *msix_entries;
4598
4599 struct list_head vp_list;
4600 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4601 sizeof(unsigned long)];
4602 uint16_t num_vhosts;
4603 uint16_t num_vsans;
4604 uint16_t max_npiv_vports;
4605 int cur_vport_count;
4606
4607 struct qla_chip_state_84xx *cs84xx;
4608 struct isp_operations *isp_ops;
4609 struct workqueue_struct *wq;
4610 struct qlfc_fw fw_buf;
4611
4612
4613 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4614
4615 struct dma_pool *dl_dma_pool;
4616#define DSD_LIST_DMA_POOL_SIZE 512
4617
4618 struct dma_pool *fcp_cmnd_dma_pool;
4619 mempool_t *ctx_mempool;
4620#define FCP_CMND_DMA_POOL_SIZE 512
4621
4622 void __iomem *nx_pcibase;
4623 void __iomem *nxdb_rd_ptr;
4624 void __iomem *nxdb_wr_ptr;
4625
4626 uint32_t crb_win;
4627 uint32_t curr_window;
4628 uint32_t ddr_mn_window;
4629 unsigned long mn_win_crb;
4630 unsigned long ms_win_crb;
4631 int qdr_sn_window;
4632 uint32_t fcoe_dev_init_timeout;
4633 uint32_t fcoe_reset_timeout;
4634 rwlock_t hw_lock;
4635 uint16_t portnum;
4636 int link_width;
4637 struct fw_blob *hablob;
4638 struct qla82xx_legacy_intr_set nx_legacy_intr;
4639
4640 uint16_t gbl_dsd_inuse;
4641 uint16_t gbl_dsd_avail;
4642 struct list_head gbl_dsd_list;
4643#define NUM_DSD_CHAIN 4096
4644
4645 uint8_t fw_type;
4646 uint32_t file_prd_off;
4647
4648 uint32_t md_template_size;
4649 void *md_tmplt_hdr;
4650 dma_addr_t md_tmplt_hdr_dma;
4651 void *md_dump;
4652 uint32_t md_dump_size;
4653
4654 void *loop_id_map;
4655
4656
4657 uint32_t idc_audit_ts;
4658 uint32_t idc_extend_tmo;
4659
4660
4661 struct workqueue_struct *dpc_lp_wq;
4662 struct work_struct idc_aen;
4663
4664 struct workqueue_struct *dpc_hp_wq;
4665 struct work_struct nic_core_reset;
4666 struct work_struct idc_state_handler;
4667 struct work_struct nic_core_unrecoverable;
4668 struct work_struct board_disable;
4669
4670 struct mr_data_fx00 mr;
4671 uint32_t chip_reset;
4672
4673 struct qlt_hw_data tgt;
4674 int allow_cna_fw_dump;
4675 uint32_t fw_ability_mask;
4676 uint16_t min_supported_speed;
4677 uint16_t max_supported_speed;
4678
4679
4680 struct dma_pool *dif_bundl_pool;
4681 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4682 struct {
4683 struct {
4684 struct list_head head;
4685 uint count;
4686 } good;
4687 struct {
4688 struct list_head head;
4689 uint count;
4690 } unusable;
4691 } pool;
4692
4693 unsigned long long dif_bundle_crossed_pages;
4694 unsigned long long dif_bundle_reads;
4695 unsigned long long dif_bundle_writes;
4696 unsigned long long dif_bundle_kallocs;
4697 unsigned long long dif_bundle_dma_allocs;
4698
4699 atomic_t nvme_active_aen_cnt;
4700 uint16_t nvme_last_rptd_aen;
4701
4702 uint8_t fc4_type_priority;
4703
4704 atomic_t zio_threshold;
4705 uint16_t last_zio_threshold;
4706
4707#define DEFAULT_ZIO_THRESHOLD 5
4708
4709 struct qla_hw_data_stat stat;
4710 pci_error_state_t pci_error_state;
4711 u64 prev_cmd_cnt;
4712 struct dma_pool *purex_dma_pool;
4713 struct btree_head32 host_map;
4714
4715#define EDIF_NUM_SA_INDEX 512
4716#define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX
4717 void *edif_rx_sa_id_map;
4718 void *edif_tx_sa_id_map;
4719 spinlock_t sadb_fp_lock;
4720
4721 struct list_head sadb_tx_index_list;
4722 struct list_head sadb_rx_index_list;
4723 spinlock_t sadb_lock;
4724 struct els_reject elsrej;
4725 u8 edif_post_stop_cnt_down;
4726};
4727
4728#define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
4729
4730struct active_regions {
4731 uint8_t global;
4732 struct {
4733 uint8_t board_config;
4734 uint8_t vpd_nvram;
4735 uint8_t npiv_config_0_1;
4736 uint8_t npiv_config_2_3;
4737 } aux;
4738};
4739
4740#define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4741#define FW_ABILITY_MAX_SPEED_16G 0x0
4742#define FW_ABILITY_MAX_SPEED_32G 0x1
4743#define FW_ABILITY_MAX_SPEED(ha) \
4744 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4745
4746#define QLA_GET_DATA_RATE 0
4747#define QLA_SET_DATA_RATE_NOLR 1
4748#define QLA_SET_DATA_RATE_LR 2
4749
4750#define QLA_DEFAULT_PAYLOAD_SIZE 64
4751
4752
4753
4754
4755
4756struct purex_item {
4757 struct list_head list;
4758 struct scsi_qla_host *vha;
4759 void (*process_item)(struct scsi_qla_host *vha,
4760 struct purex_item *pkt);
4761 atomic_t in_use;
4762 uint16_t size;
4763 struct {
4764 uint8_t iocb[64];
4765 } iocb;
4766};
4767
4768#include "qla_edif.h"
4769
4770#define SCM_FLAG_RDF_REJECT 0x00
4771#define SCM_FLAG_RDF_COMPLETED 0x01
4772
4773#define QLA_CON_PRIMITIVE_RECEIVED 0x1
4774#define QLA_CONGESTION_ARB_WARNING 0x1
4775#define QLA_CONGESTION_ARB_ALARM 0X2
4776
4777
4778
4779
4780typedef struct scsi_qla_host {
4781 struct list_head list;
4782 struct list_head vp_fcports;
4783 struct list_head work_list;
4784 spinlock_t work_lock;
4785 struct work_struct iocb_work;
4786
4787
4788 struct Scsi_Host *host;
4789 unsigned long host_no;
4790 uint8_t host_str[16];
4791
4792 volatile struct {
4793 uint32_t init_done :1;
4794 uint32_t online :1;
4795 uint32_t reset_active :1;
4796
4797 uint32_t management_server_logged_in :1;
4798 uint32_t process_response_queue :1;
4799 uint32_t difdix_supported:1;
4800 uint32_t delete_progress:1;
4801
4802 uint32_t fw_tgt_reported:1;
4803 uint32_t bbcr_enable:1;
4804 uint32_t qpairs_available:1;
4805 uint32_t qpairs_req_created:1;
4806 uint32_t qpairs_rsp_created:1;
4807 uint32_t nvme_enabled:1;
4808 uint32_t nvme_first_burst:1;
4809 uint32_t nvme2_enabled:1;
4810 } flags;
4811
4812 atomic_t loop_state;
4813#define LOOP_TIMEOUT 1
4814#define LOOP_DOWN 2
4815#define LOOP_UP 3
4816#define LOOP_UPDATE 4
4817#define LOOP_READY 5
4818#define LOOP_DEAD 6
4819
4820 unsigned long relogin_jif;
4821 unsigned long dpc_flags;
4822#define RESET_MARKER_NEEDED 0
4823#define RESET_ACTIVE 1
4824#define ISP_ABORT_NEEDED 2
4825#define ABORT_ISP_ACTIVE 3
4826#define LOOP_RESYNC_NEEDED 4
4827#define LOOP_RESYNC_ACTIVE 5
4828#define LOCAL_LOOP_UPDATE 6
4829#define RSCN_UPDATE 7
4830#define RELOGIN_NEEDED 8
4831#define REGISTER_FC4_NEEDED 9
4832#define ISP_ABORT_RETRY 10
4833#define BEACON_BLINK_NEEDED 11
4834#define REGISTER_FDMI_NEEDED 12
4835#define FCPORT_UPDATE_NEEDED 13
4836#define VP_DPC_NEEDED 14
4837#define UNLOADING 15
4838#define NPIV_CONFIG_NEEDED 16
4839#define ISP_UNRECOVERABLE 17
4840#define FCOE_CTX_RESET_NEEDED 18
4841#define MPI_RESET_NEEDED 19
4842#define ISP_QUIESCE_NEEDED 20
4843#define N2N_LINK_RESET 21
4844#define PORT_UPDATE_NEEDED 22
4845#define FX00_RESET_RECOVERY 23
4846#define FX00_TARGET_SCAN 24
4847#define FX00_CRITEMP_RECOVERY 25
4848#define FX00_HOST_INFO_RESEND 26
4849#define QPAIR_ONLINE_CHECK_NEEDED 27
4850#define DO_EEH_RECOVERY 28
4851#define DETECT_SFP_CHANGE 29
4852#define N2N_LOGIN_NEEDED 30
4853#define IOCB_WORK_ACTIVE 31
4854#define SET_ZIO_THRESHOLD_NEEDED 32
4855#define ISP_ABORT_TO_ROM 33
4856#define VPORT_DELETE 34
4857#define HEARTBEAT_CHK 38
4858
4859#define PROCESS_PUREX_IOCB 63
4860
4861 unsigned long pci_flags;
4862#define PFLG_DISCONNECTED 0
4863#define PFLG_DRIVER_REMOVING 1
4864#define PFLG_DRIVER_PROBING 2
4865
4866 uint32_t device_flags;
4867#define SWITCH_FOUND BIT_0
4868#define DFLG_NO_CABLE BIT_1
4869#define DFLG_DEV_FAILED BIT_5
4870
4871
4872 uint16_t loop_id;
4873 uint16_t self_login_loop_id;
4874
4875
4876 fc_port_t bidir_fcport;
4877
4878
4879
4880
4881 port_id_t d_id;
4882 uint8_t marker_needed;
4883 uint16_t mgmt_svr_loop_id;
4884
4885
4886
4887
4888 uint8_t loop_down_abort_time;
4889 atomic_t loop_down_timer;
4890 uint8_t link_down_timeout;
4891
4892 uint32_t timer_active;
4893 struct timer_list timer;
4894
4895 uint8_t node_name[WWN_SIZE];
4896 uint8_t port_name[WWN_SIZE];
4897 uint8_t fabric_node_name[WWN_SIZE];
4898 uint8_t fabric_port_name[WWN_SIZE];
4899
4900 struct nvme_fc_local_port *nvme_local_port;
4901 struct completion nvme_del_done;
4902
4903 uint16_t fcoe_vlan_id;
4904 uint16_t fcoe_fcf_idx;
4905 uint8_t fcoe_vn_port_mac[6];
4906
4907
4908 struct list_head qla_cmd_list;
4909 struct list_head qla_sess_op_cmd_list;
4910 struct list_head unknown_atio_list;
4911 spinlock_t cmd_list_lock;
4912 struct delayed_work unknown_atio_work;
4913
4914
4915 atomic_t generation_tick;
4916
4917 int total_fcport_update_gen;
4918
4919 struct list_head logo_list;
4920
4921 struct list_head plogi_ack_list;
4922
4923 struct list_head qp_list;
4924
4925 uint32_t vp_abort_cnt;
4926
4927 struct fc_vport *fc_vport;
4928 uint16_t vp_idx;
4929 struct qla_qpair *qpair;
4930
4931 unsigned long vp_flags;
4932#define VP_IDX_ACQUIRED 0
4933#define VP_CREATE_NEEDED 1
4934#define VP_BIND_NEEDED 2
4935#define VP_DELETE_NEEDED 3
4936#define VP_SCR_NEEDED 4
4937#define VP_CONFIG_OK 5
4938 atomic_t vp_state;
4939#define VP_OFFLINE 0
4940#define VP_ACTIVE 1
4941#define VP_FAILED 2
4942
4943 uint16_t vp_err_state;
4944 uint16_t vp_prev_err_state;
4945#define VP_ERR_UNKWN 0
4946#define VP_ERR_PORTDWN 1
4947#define VP_ERR_FAB_UNSUPPORTED 2
4948#define VP_ERR_FAB_NORESOURCES 3
4949#define VP_ERR_FAB_LOGOUT 4
4950#define VP_ERR_ADAP_NORESOURCES 5
4951 struct qla_hw_data *hw;
4952 struct scsi_qlt_host vha_tgt;
4953 struct req_que *req;
4954 int fw_heartbeat_counter;
4955 int seconds_since_last_heartbeat;
4956 struct fc_host_statistics fc_host_stat;
4957 struct qla_statistics qla_stats;
4958 struct bidi_statistics bidi_stats;
4959 atomic_t vref_count;
4960 struct qla8044_reset_template reset_tmplt;
4961 uint16_t bbcr;
4962
4963 uint16_t u_ql2xexchoffld;
4964 uint16_t u_ql2xiniexchg;
4965 uint16_t qlini_mode;
4966 uint16_t ql2xexchoffld;
4967 uint16_t ql2xiniexchg;
4968
4969 struct dentry *dfs_rport_root;
4970
4971 struct purex_list {
4972 struct list_head head;
4973 spinlock_t lock;
4974 } purex_list;
4975 struct purex_item default_item;
4976
4977 struct name_list_extended gnl;
4978
4979 int fcport_count;
4980 wait_queue_head_t fcport_waitQ;
4981 wait_queue_head_t vref_waitq;
4982 uint8_t min_supported_speed;
4983 uint8_t n2n_node_name[WWN_SIZE];
4984 uint8_t n2n_port_name[WWN_SIZE];
4985 uint16_t n2n_id;
4986 __le16 dport_data[4];
4987 struct list_head gpnid_list;
4988 struct fab_scan scan;
4989 uint8_t scm_fabric_connection_flags;
4990
4991 unsigned int irq_offset;
4992
4993 u64 hw_err_cnt;
4994 u64 interface_err_cnt;
4995 u64 cmd_timeout_cnt;
4996 u64 reset_cmd_err_cnt;
4997 u64 link_down_time;
4998 u64 short_link_down_cnt;
4999 struct edif_dbell e_dbell;
5000 struct pur_core pur_cinfo;
5001} scsi_qla_host_t;
5002
5003struct qla27xx_image_status {
5004 uint8_t image_status_mask;
5005 __le16 generation;
5006 uint8_t ver_major;
5007 uint8_t ver_minor;
5008 uint8_t bitmap;
5009 uint8_t reserved[2];
5010 __le32 checksum;
5011 __le32 signature;
5012} __packed;
5013
5014
5015#define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
5016#define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
5017#define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
5018#define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
5019
5020#define SET_VP_IDX 1
5021#define SET_AL_PA 2
5022#define RESET_VP_IDX 3
5023#define RESET_AL_PA 4
5024struct qla_tgt_vp_map {
5025 uint8_t idx;
5026 scsi_qla_host_t *vha;
5027};
5028
5029struct qla2_sgx {
5030 dma_addr_t dma_addr;
5031 uint32_t dma_len;
5032
5033 uint32_t tot_bytes;
5034 struct scatterlist *cur_sg;
5035
5036
5037 uint32_t bytes_consumed;
5038 uint32_t num_bytes;
5039 uint32_t tot_partial;
5040
5041
5042 uint32_t num_sg;
5043 srb_t *sp;
5044};
5045
5046#define QLA_FW_STARTED(_ha) { \
5047 int i; \
5048 _ha->flags.fw_started = 1; \
5049 _ha->base_qpair->fw_started = 1; \
5050 for (i = 0; i < _ha->max_qpairs; i++) { \
5051 if (_ha->queue_pair_map[i]) \
5052 _ha->queue_pair_map[i]->fw_started = 1; \
5053 } \
5054}
5055
5056#define QLA_FW_STOPPED(_ha) { \
5057 int i; \
5058 _ha->flags.fw_started = 0; \
5059 _ha->base_qpair->fw_started = 0; \
5060 for (i = 0; i < _ha->max_qpairs; i++) { \
5061 if (_ha->queue_pair_map[i]) \
5062 _ha->queue_pair_map[i]->fw_started = 0; \
5063 } \
5064}
5065
5066
5067#define SFUB_CHECKSUM_SIZE 4
5068
5069struct secure_flash_update_block {
5070 uint32_t block_info;
5071 uint32_t signature_lo;
5072 uint32_t signature_hi;
5073 uint32_t signature_upper[0x3e];
5074};
5075
5076struct secure_flash_update_block_pk {
5077 uint32_t block_info;
5078 uint32_t signature_lo;
5079 uint32_t signature_hi;
5080 uint32_t signature_upper[0x3e];
5081 uint32_t public_key[0x41];
5082};
5083
5084
5085
5086
5087#define LOOP_TRANSITION(ha) \
5088 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5089 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
5090 atomic_read(&ha->loop_state) == LOOP_DOWN)
5091
5092#define STATE_TRANSITION(ha) \
5093 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5094 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
5095
5096#define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
5097 atomic_inc(&__vha->vref_count); \
5098 mb(); \
5099 if (__vha->flags.delete_progress) { \
5100 atomic_dec(&__vha->vref_count); \
5101 wake_up(&__vha->vref_waitq); \
5102 __bail = 1; \
5103 } else { \
5104 __bail = 0; \
5105 } \
5106} while (0)
5107
5108#define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
5109 atomic_dec(&__vha->vref_count); \
5110 wake_up(&__vha->vref_waitq); \
5111} while (0) \
5112
5113#define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
5114 atomic_inc(&__qpair->ref_count); \
5115 mb(); \
5116 if (__qpair->delete_in_progress) { \
5117 atomic_dec(&__qpair->ref_count); \
5118 __bail = 1; \
5119 } else { \
5120 __bail = 0; \
5121 } \
5122} while (0)
5123
5124#define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
5125 atomic_dec(&__qpair->ref_count)
5126
5127#define QLA_ENA_CONF(_ha) {\
5128 int i;\
5129 _ha->base_qpair->enable_explicit_conf = 1; \
5130 for (i = 0; i < _ha->max_qpairs; i++) { \
5131 if (_ha->queue_pair_map[i]) \
5132 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
5133 } \
5134}
5135
5136#define QLA_DIS_CONF(_ha) {\
5137 int i;\
5138 _ha->base_qpair->enable_explicit_conf = 0; \
5139 for (i = 0; i < _ha->max_qpairs; i++) { \
5140 if (_ha->queue_pair_map[i]) \
5141 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
5142 } \
5143}
5144
5145
5146
5147
5148#define MBS_MASK 0x3fff
5149
5150#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
5151#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
5152#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
5153#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
5154#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
5155#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
5156#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
5157#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
5158#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
5159#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
5160
5161#define QLA_FUNCTION_TIMEOUT 0x100
5162#define QLA_FUNCTION_PARAMETER_ERROR 0x101
5163#define QLA_FUNCTION_FAILED 0x102
5164#define QLA_MEMORY_ALLOC_FAILED 0x103
5165#define QLA_LOCK_TIMEOUT 0x104
5166#define QLA_ABORTED 0x105
5167#define QLA_SUSPENDED 0x106
5168#define QLA_BUSY 0x107
5169#define QLA_ALREADY_REGISTERED 0x109
5170#define QLA_OS_TIMER_EXPIRED 0x10a
5171#define QLA_ERR_NO_QPAIR 0x10b
5172#define QLA_ERR_NOT_FOUND 0x10c
5173#define QLA_ERR_FROM_FW 0x10d
5174
5175#define NVRAM_DELAY() udelay(10)
5176
5177
5178
5179
5180#define OPTROM_SIZE_2300 0x20000
5181#define OPTROM_SIZE_2322 0x100000
5182#define OPTROM_SIZE_24XX 0x100000
5183#define OPTROM_SIZE_25XX 0x200000
5184#define OPTROM_SIZE_81XX 0x400000
5185#define OPTROM_SIZE_82XX 0x800000
5186#define OPTROM_SIZE_83XX 0x1000000
5187#define OPTROM_SIZE_28XX 0x2000000
5188
5189#define OPTROM_BURST_SIZE 0x1000
5190#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
5191
5192#define QLA_DSDS_PER_IOCB 37
5193
5194#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
5195
5196#define QLA_SG_ALL 1024
5197
5198enum nexus_wait_type {
5199 WAIT_HOST = 0,
5200 WAIT_TARGET,
5201 WAIT_LUN,
5202};
5203
5204#define INVALID_EDIF_SA_INDEX 0xffff
5205#define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe
5206
5207#define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE
5208
5209
5210struct edif_list_entry {
5211 uint16_t handle;
5212 uint32_t update_sa_index;
5213 uint32_t delete_sa_index;
5214 uint32_t count;
5215#define EDIF_ENTRY_FLAGS_CLEANUP 0x01
5216 uint32_t flags;
5217 fc_port_t *fcport;
5218 struct timer_list timer;
5219 struct list_head next;
5220};
5221
5222#define EDIF_TX_INDX_BASE 512
5223#define EDIF_RX_INDX_BASE 0
5224#define EDIF_RX_DELETE_FILTER_COUNT 3
5225
5226
5227
5228struct sa_index_pair {
5229 uint16_t sa_index;
5230 uint32_t spi;
5231};
5232
5233
5234struct edif_sa_index_entry {
5235 struct sa_index_pair sa_pair[2];
5236 fc_port_t *fcport;
5237 uint16_t handle;
5238 struct list_head next;
5239};
5240
5241
5242struct sff_8247_a0 {
5243 u8 txid;
5244 u8 ext_txid;
5245 u8 connector;
5246
5247 u8 eth_infi_cc3;
5248 u8 sonet_cc4[2];
5249 u8 eth_cc6;
5250
5251#define FC_LL_VL BIT_7
5252#define FC_LL_S BIT_6
5253#define FC_LL_I BIT_5
5254#define FC_LL_L BIT_4
5255#define FC_LL_M BIT_3
5256#define FC_LL_SA BIT_2
5257#define FC_LL_LC BIT_1
5258#define FC_LL_EL BIT_0
5259 u8 fc_ll_cc7;
5260
5261#define FC_TEC_EL BIT_7
5262#define FC_TEC_SN BIT_6
5263#define FC_TEC_SL BIT_5
5264#define FC_TEC_LL BIT_4
5265#define FC_TEC_ACT BIT_3
5266#define FC_TEC_PAS BIT_2
5267 u8 fc_tec_cc8;
5268
5269#define FC_MED_TW BIT_7
5270#define FC_MED_TP BIT_6
5271#define FC_MED_MI BIT_5
5272#define FC_MED_TV BIT_4
5273#define FC_MED_M6 BIT_3
5274#define FC_MED_M5 BIT_2
5275#define FC_MED_SM BIT_0
5276 u8 fc_med_cc9;
5277
5278#define FC_SP_12 BIT_7
5279#define FC_SP_8 BIT_6
5280#define FC_SP_16 BIT_5
5281#define FC_SP_4 BIT_4
5282#define FC_SP_32 BIT_3
5283#define FC_SP_2 BIT_2
5284#define FC_SP_1 BIT_0
5285 u8 fc_sp_cc10;
5286 u8 encode;
5287 u8 bitrate;
5288 u8 rate_id;
5289 u8 length_km;
5290 u8 length_100m;
5291 u8 length_50um_10m;
5292 u8 length_62um_10m;
5293 u8 length_om4_10m;
5294 u8 length_om3_10m;
5295#define SFF_VEN_NAME_LEN 16
5296 u8 vendor_name[SFF_VEN_NAME_LEN];
5297 u8 tx_compat;
5298 u8 vendor_oui[3];
5299#define SFF_PART_NAME_LEN 16
5300 u8 vendor_pn[SFF_PART_NAME_LEN];
5301 u8 vendor_rev[4];
5302 u8 wavelength[2];
5303 u8 resv;
5304 u8 cc_base;
5305 u8 options[2];
5306 u8 br_max;
5307 u8 br_min;
5308 u8 vendor_sn[16];
5309 u8 date_code[8];
5310 u8 diag;
5311 u8 enh_options;
5312 u8 sff_revision;
5313 u8 cc_ext;
5314 u8 vendor_specific[32];
5315 u8 resv2[128];
5316};
5317
5318
5319#define IS_BPM_CAPABLE(ha) \
5320 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
5321 IS_QLA27XX(ha) || IS_QLA28XX(ha))
5322#define IS_BPM_RANGE_CAPABLE(ha) \
5323 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5324#define IS_BPM_ENABLED(vha) \
5325 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
5326
5327#define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
5328
5329#define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
5330 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
5331
5332#define SAVE_TOPO(_ha) { \
5333 if (_ha->current_topology) \
5334 _ha->prev_topology = _ha->current_topology; \
5335}
5336
5337#define N2N_TOPO(ha) \
5338 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
5339 ha->current_topology == ISP_CFG_N || \
5340 !ha->current_topology)
5341
5342#define QLA_N2N_WAIT_TIME 5
5343
5344#define NVME_TYPE(fcport) \
5345 (fcport->fc4_type & FS_FC4TYPE_NVME) \
5346
5347#define FCP_TYPE(fcport) \
5348 (fcport->fc4_type & FS_FC4TYPE_FCP) \
5349
5350#define NVME_ONLY_TARGET(fcport) \
5351 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
5352
5353#define NVME_FCP_TARGET(fcport) \
5354 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
5355
5356#define NVME_PRIORITY(ha, fcport) \
5357 (NVME_FCP_TARGET(fcport) && \
5358 (ha->fc4_type_priority == FC4_PRIORITY_NVME))
5359
5360#define NVME_TARGET(ha, fcport) \
5361 (fcport->do_prli_nvme || \
5362 NVME_ONLY_TARGET(fcport)) \
5363
5364#define PRLI_PHASE(_cls) \
5365 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
5366
5367enum ql_vnd_host_stat_action {
5368 QLA_STOP = 0,
5369 QLA_START,
5370 QLA_CLEAR,
5371};
5372
5373struct ql_vnd_mng_host_stats_param {
5374 u32 stat_type;
5375 enum ql_vnd_host_stat_action action;
5376} __packed;
5377
5378struct ql_vnd_mng_host_stats_resp {
5379 u32 status;
5380} __packed;
5381
5382struct ql_vnd_stats_param {
5383 u32 stat_type;
5384} __packed;
5385
5386struct ql_vnd_tgt_stats_param {
5387 s32 tgt_id;
5388 u32 stat_type;
5389} __packed;
5390
5391enum ql_vnd_host_port_action {
5392 QLA_ENABLE = 0,
5393 QLA_DISABLE,
5394};
5395
5396struct ql_vnd_mng_host_port_param {
5397 enum ql_vnd_host_port_action action;
5398} __packed;
5399
5400struct ql_vnd_mng_host_port_resp {
5401 u32 status;
5402} __packed;
5403
5404struct ql_vnd_stat_entry {
5405 u32 stat_type;
5406 u32 tgt_num;
5407 u64 cnt;
5408} __packed;
5409
5410struct ql_vnd_stats {
5411 u64 entry_count;
5412 u64 rservd;
5413 struct ql_vnd_stat_entry entry[0];
5414} __packed;
5415
5416struct ql_vnd_host_stats_resp {
5417 u32 status;
5418 struct ql_vnd_stats stats;
5419} __packed;
5420
5421struct ql_vnd_tgt_stats_resp {
5422 u32 status;
5423 struct ql_vnd_stats stats;
5424} __packed;
5425
5426#include "qla_target.h"
5427#include "qla_gbl.h"
5428#include "qla_dbg.h"
5429#include "qla_inline.h"
5430#endif
5431