LXR linux/drivers/scsi/qla2xxx/qla

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * QLogic Fibre Channel HBA Driver
   4 * Copyright (c)  2003-2014 QLogic Corporation
   5 */
   6#ifndef __QLA_FW_H
   7#define __QLA_FW_H
   8
   9#include <linux/nvme.h>
  10#include <linux/nvme-fc.h>
  11
  12#include "qla_dsd.h"
  13
  14#define MBS_CHECKSUM_ERROR      0x4010
  15#define MBS_INVALID_PRODUCT_KEY 0x4020
  16
  17/*
  18 * Firmware Options.
  19 */
  20#define FO1_ENABLE_PUREX        BIT_10
  21#define FO1_DISABLE_LED_CTRL    BIT_6
  22#define FO1_ENABLE_8016         BIT_0
  23#define FO2_ENABLE_SEL_CLASS2   BIT_5
  24#define FO3_NO_ABTS_ON_LINKDOWN BIT_14
  25#define FO3_HOLD_STS_IOCB       BIT_12
  26
  27/*
  28 * Port Database structure definition for ISP 24xx.
  29 */
  30#define PDO_FORCE_ADISC         BIT_1
  31#define PDO_FORCE_PLOGI         BIT_0
  32
  33struct buffer_credit_24xx {
  34        u32 parameter[28];
  35};
  36
  37#define PORT_DATABASE_24XX_SIZE         64
  38struct port_database_24xx {
  39        uint16_t flags;
  40#define PDF_TASK_RETRY_ID       BIT_14
  41#define PDF_FC_TAPE             BIT_7
  42#define PDF_ACK0_CAPABLE        BIT_6
  43#define PDF_FCP2_CONF           BIT_5
  44#define PDF_CLASS_2             BIT_4
  45#define PDF_HARD_ADDR           BIT_1
  46
  47        /*
  48         * for NVMe, the login_state field has been
  49         * split into nibbles.
  50         * The lower nibble is for FCP.
  51         * The upper nibble is for NVMe.
  52         */
  53        uint8_t current_login_state;
  54        uint8_t last_login_state;
  55#define PDS_PLOGI_PENDING       0x03
  56#define PDS_PLOGI_COMPLETE      0x04
  57#define PDS_PRLI_PENDING        0x05
  58#define PDS_PRLI_COMPLETE       0x06
  59#define PDS_PORT_UNAVAILABLE    0x07
  60#define PDS_PRLO_PENDING        0x09
  61#define PDS_LOGO_PENDING        0x11
  62#define PDS_PRLI2_PENDING       0x12
  63
  64        uint8_t hard_address[3];
  65        uint8_t reserved_1;
  66
  67        uint8_t port_id[3];
  68        uint8_t sequence_id;
  69
  70        uint16_t port_timer;
  71
  72        uint16_t nport_handle;                  /* N_PORT handle. */
  73
  74        uint16_t receive_data_size;
  75        uint16_t reserved_2;
  76
  77        uint8_t prli_svc_param_word_0[2];       /* Big endian */
  78                                                /* Bits 15-0 of word 0 */
  79        uint8_t prli_svc_param_word_3[2];       /* Big endian */
  80                                                /* Bits 15-0 of word 3 */
  81
  82        uint8_t port_name[WWN_SIZE];
  83        uint8_t node_name[WWN_SIZE];
  84
  85        uint8_t reserved_3[2];
  86        uint16_t nvme_first_burst_size;
  87        uint16_t prli_nvme_svc_param_word_0;    /* Bits 15-0 of word 0 */
  88        uint16_t prli_nvme_svc_param_word_3;    /* Bits 15-0 of word 3 */
  89        uint8_t secure_login;
  90        uint8_t reserved_4[14];
  91};
  92
  93/*
  94 * MB 75h returns a list of DB entries similar to port_database_24xx(64B).
  95 * However, in this case it returns 1st 40 bytes.
  96 */
  97struct get_name_list_extended {
  98        __le16 flags;
  99        u8 current_login_state;
 100        u8 last_login_state;
 101        u8 hard_address[3];
 102        u8 reserved_1;
 103        u8 port_id[3];
 104        u8 sequence_id;
 105        __le16 port_timer;
 106        __le16 nport_handle;                    /* N_PORT handle. */
 107        __le16 receive_data_size;
 108        __le16 reserved_2;
 109
 110        /* PRLI SVC Param are Big endian */
 111        u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
 112        u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
 113        u8 port_name[WWN_SIZE];
 114        u8 node_name[WWN_SIZE];
 115};
 116
 117/* MB 75h: This is the short version of the database */
 118struct get_name_list {
 119        u8 port_node_name[WWN_SIZE]; /* B7 most sig, B0 least sig */
 120        __le16 nport_handle;
 121        u8 reserved;
 122};
 123
 124struct vp_database_24xx {
 125        uint16_t vp_status;
 126        uint8_t  options;
 127        uint8_t  id;
 128        uint8_t  port_name[WWN_SIZE];
 129        uint8_t  node_name[WWN_SIZE];
 130        uint16_t port_id_low;
 131        uint16_t port_id_high;
 132};
 133
 134struct nvram_24xx {
 135        /* NVRAM header. */
 136        uint8_t id[4];
 137        __le16  nvram_version;
 138        uint16_t reserved_0;
 139
 140        /* Firmware Initialization Control Block. */
 141        __le16  version;
 142        uint16_t reserved_1;
 143        __le16  frame_payload_size;
 144        __le16  execution_throttle;
 145        __le16  exchange_count;
 146        __le16  hard_address;
 147
 148        uint8_t port_name[WWN_SIZE];
 149        uint8_t node_name[WWN_SIZE];
 150
 151        __le16  login_retry_count;
 152        __le16  link_down_on_nos;
 153        __le16  interrupt_delay_timer;
 154        __le16  login_timeout;
 155
 156        __le32  firmware_options_1;
 157        __le32  firmware_options_2;
 158        __le32  firmware_options_3;
 159
 160        /* Offset 56. */
 161
 162        /*
 163         * BIT 0     = Control Enable
 164         * BIT 1-15  =
 165         *
 166         * BIT 0-7   = Reserved
 167         * BIT 8-10  = Output Swing 1G
 168         * BIT 11-13 = Output Emphasis 1G
 169         * BIT 14-15 = Reserved
 170         *
 171         * BIT 0-7   = Reserved
 172         * BIT 8-10  = Output Swing 2G
 173         * BIT 11-13 = Output Emphasis 2G
 174         * BIT 14-15 = Reserved
 175         *
 176         * BIT 0-7   = Reserved
 177         * BIT 8-10  = Output Swing 4G
 178         * BIT 11-13 = Output Emphasis 4G
 179         * BIT 14-15 = Reserved
 180         */
 181        __le16  seriallink_options[4];
 182
 183        uint16_t reserved_2[16];
 184
 185        /* Offset 96. */
 186        uint16_t reserved_3[16];
 187
 188        /* PCIe table entries. */
 189        uint16_t reserved_4[16];
 190
 191        /* Offset 160. */
 192        uint16_t reserved_5[16];
 193
 194        /* Offset 192. */
 195        uint16_t reserved_6[16];
 196
 197        /* Offset 224. */
 198        uint16_t reserved_7[16];
 199
 200        /*
 201         * BIT 0  = Enable spinup delay
 202         * BIT 1  = Disable BIOS
 203         * BIT 2  = Enable Memory Map BIOS
 204         * BIT 3  = Enable Selectable Boot
 205         * BIT 4  = Disable RISC code load
 206         * BIT 5  = Disable Serdes
 207         * BIT 6  =
 208         * BIT 7  =
 209         *
 210         * BIT 8  =
 211         * BIT 9  =
 212         * BIT 10 = Enable lip full login
 213         * BIT 11 = Enable target reset
 214         * BIT 12 =
 215         * BIT 13 =
 216         * BIT 14 =
 217         * BIT 15 = Enable alternate WWN
 218         *
 219         * BIT 16-31 =
 220         */
 221        __le32  host_p;
 222
 223        uint8_t alternate_port_name[WWN_SIZE];
 224        uint8_t alternate_node_name[WWN_SIZE];
 225
 226        uint8_t boot_port_name[WWN_SIZE];
 227        __le16  boot_lun_number;
 228        uint16_t reserved_8;
 229
 230        uint8_t alt1_boot_port_name[WWN_SIZE];
 231        __le16  alt1_boot_lun_number;
 232        uint16_t reserved_9;
 233
 234        uint8_t alt2_boot_port_name[WWN_SIZE];
 235        __le16  alt2_boot_lun_number;
 236        uint16_t reserved_10;
 237
 238        uint8_t alt3_boot_port_name[WWN_SIZE];
 239        __le16  alt3_boot_lun_number;
 240        uint16_t reserved_11;
 241
 242        /*
 243         * BIT 0 = Selective Login
 244         * BIT 1 = Alt-Boot Enable
 245         * BIT 2 = Reserved
 246         * BIT 3 = Boot Order List
 247         * BIT 4 = Reserved
 248         * BIT 5 = Selective LUN
 249         * BIT 6 = Reserved
 250         * BIT 7-31 =
 251         */
 252        __le32  efi_parameters;
 253
 254        uint8_t reset_delay;
 255        uint8_t reserved_12;
 256        uint16_t reserved_13;
 257
 258        __le16  boot_id_number;
 259        uint16_t reserved_14;
 260
 261        __le16  max_luns_per_target;
 262        uint16_t reserved_15;
 263
 264        __le16  port_down_retry_count;
 265        __le16  link_down_timeout;
 266
 267        /* FCode parameters. */
 268        __le16  fcode_parameter;
 269
 270        uint16_t reserved_16[3];
 271
 272        /* Offset 352. */
 273        uint8_t prev_drv_ver_major;
 274        uint8_t prev_drv_ver_submajob;
 275        uint8_t prev_drv_ver_minor;
 276        uint8_t prev_drv_ver_subminor;
 277
 278        __le16  prev_bios_ver_major;
 279        __le16  prev_bios_ver_minor;
 280
 281        __le16  prev_efi_ver_major;
 282        __le16  prev_efi_ver_minor;
 283
 284        __le16  prev_fw_ver_major;
 285        uint8_t prev_fw_ver_minor;
 286        uint8_t prev_fw_ver_subminor;
 287
 288        uint16_t reserved_17[8];
 289
 290        /* Offset 384. */
 291        uint16_t reserved_18[16];
 292
 293        /* Offset 416. */
 294        uint16_t reserved_19[16];
 295
 296        /* Offset 448. */
 297        uint16_t reserved_20[16];
 298
 299        /* Offset 480. */
 300        uint8_t model_name[16];
 301
 302        uint16_t reserved_21[2];
 303
 304        /* Offset 500. */
 305        /* HW Parameter Block. */
 306        uint16_t pcie_table_sig;
 307        uint16_t pcie_table_offset;
 308
 309        uint16_t subsystem_vendor_id;
 310        uint16_t subsystem_device_id;
 311
 312        __le32  checksum;
 313};
 314
 315/*
 316 * ISP Initialization Control Block.
 317 * Little endian except where noted.
 318 */
 319#define ICB_VERSION 1
 320struct init_cb_24xx {
 321        __le16  version;
 322        uint16_t reserved_1;
 323
 324        __le16  frame_payload_size;
 325        __le16  execution_throttle;
 326        __le16  exchange_count;
 327
 328        __le16  hard_address;
 329
 330        uint8_t port_name[WWN_SIZE];            /* Big endian. */
 331        uint8_t node_name[WWN_SIZE];            /* Big endian. */
 332
 333        __le16  response_q_inpointer;
 334        __le16  request_q_outpointer;
 335
 336        __le16  login_retry_count;
 337
 338        __le16  prio_request_q_outpointer;
 339
 340        __le16  response_q_length;
 341        __le16  request_q_length;
 342
 343        __le16  link_down_on_nos;               /* Milliseconds. */
 344
 345        __le16  prio_request_q_length;
 346
 347        __le64   request_q_address __packed;
 348        __le64   response_q_address __packed;
 349        __le64   prio_request_q_address __packed;
 350
 351        __le16  msix;
 352        __le16  msix_atio;
 353        uint8_t reserved_2[4];
 354
 355        __le16  atio_q_inpointer;
 356        __le16  atio_q_length;
 357        __le64  atio_q_address __packed;
 358
 359        __le16  interrupt_delay_timer;          /* 100us increments. */
 360        __le16  login_timeout;
 361
 362        /*
 363         * BIT 0  = Enable Hard Loop Id
 364         * BIT 1  = Enable Fairness
 365         * BIT 2  = Enable Full-Duplex
 366         * BIT 3  = Reserved
 367         * BIT 4  = Enable Target Mode
 368         * BIT 5  = Disable Initiator Mode
 369         * BIT 6  = Acquire FA-WWN
 370         * BIT 7  = Enable D-port Diagnostics
 371         *
 372         * BIT 8  = Reserved
 373         * BIT 9  = Non Participating LIP
 374         * BIT 10 = Descending Loop ID Search
 375         * BIT 11 = Acquire Loop ID in LIPA
 376         * BIT 12 = Reserved
 377         * BIT 13 = Full Login after LIP
 378         * BIT 14 = Node Name Option
 379         * BIT 15-31 = Reserved
 380         */
 381        __le32  firmware_options_1;
 382
 383        /*
 384         * BIT 0  = Operation Mode bit 0
 385         * BIT 1  = Operation Mode bit 1
 386         * BIT 2  = Operation Mode bit 2
 387         * BIT 3  = Operation Mode bit 3
 388         * BIT 4  = Connection Options bit 0
 389         * BIT 5  = Connection Options bit 1
 390         * BIT 6  = Connection Options bit 2
 391         * BIT 7  = Enable Non part on LIHA failure
 392         *
 393         * BIT 8  = Enable Class 2
 394         * BIT 9  = Enable ACK0
 395         * BIT 10 = Reserved
 396         * BIT 11 = Enable FC-SP Security
 397         * BIT 12 = FC Tape Enable
 398         * BIT 13 = Reserved
 399         * BIT 14 = Enable Target PRLI Control
 400         * BIT 15-31 = Reserved
 401         */
 402        __le32  firmware_options_2;
 403
 404        /*
 405         * BIT 0  = Reserved
 406         * BIT 1  = Soft ID only
 407         * BIT 2  = Reserved
 408         * BIT 3  = Reserved
 409         * BIT 4  = FCP RSP Payload bit 0
 410         * BIT 5  = FCP RSP Payload bit 1
 411         * BIT 6  = Enable Receive Out-of-Order data frame handling
 412         * BIT 7  = Disable Automatic PLOGI on Local Loop
 413         *
 414         * BIT 8  = Reserved
 415         * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
 416         * BIT 10 = Reserved
 417         * BIT 11 = Reserved
 418         * BIT 12 = Reserved
 419         * BIT 13 = Data Rate bit 0
 420         * BIT 14 = Data Rate bit 1
 421         * BIT 15 = Data Rate bit 2
 422         * BIT 16 = Enable 75 ohm Termination Select
 423         * BIT 17-28 = Reserved
 424         * BIT 29 = Enable response queue 0 in index shadowing
 425         * BIT 30 = Enable request queue 0 out index shadowing
 426         * BIT 31 = Reserved
 427         */
 428        __le32  firmware_options_3;
 429        __le16   qos;
 430        __le16   rid;
 431        uint8_t  reserved_3[20];
 432};
 433
 434/*
 435 * ISP queue - command entry structure definition.
 436 */
 437#define COMMAND_BIDIRECTIONAL 0x75
 438struct cmd_bidir {
 439        uint8_t entry_type;             /* Entry type. */
 440        uint8_t entry_count;            /* Entry count. */
 441        uint8_t sys_define;             /* System defined */
 442        uint8_t entry_status;           /* Entry status. */
 443
 444        uint32_t handle;                /* System handle. */
 445
 446        __le16  nport_handle;           /* N_PORT handle. */
 447
 448        __le16  timeout;                /* Command timeout. */
 449
 450        __le16  wr_dseg_count;          /* Write Data segment count. */
 451        __le16  rd_dseg_count;          /* Read Data segment count. */
 452
 453        struct scsi_lun lun;            /* FCP LUN (BE). */
 454
 455        __le16  control_flags;          /* Control flags. */
 456#define BD_WRAP_BACK                    BIT_3
 457#define BD_READ_DATA                    BIT_1
 458#define BD_WRITE_DATA                   BIT_0
 459
 460        __le16  fcp_cmnd_dseg_len;              /* Data segment length. */
 461        __le64   fcp_cmnd_dseg_address __packed;/* Data segment address. */
 462
 463        uint16_t reserved[2];                   /* Reserved */
 464
 465        __le32  rd_byte_count;                  /* Total Byte count Read. */
 466        __le32  wr_byte_count;                  /* Total Byte count write. */
 467
 468        uint8_t port_id[3];                     /* PortID of destination port.*/
 469        uint8_t vp_index;
 470
 471        struct dsd64 fcp_dsd;
 472};
 473
 474#define COMMAND_TYPE_6  0x48            /* Command Type 6 entry */
 475struct cmd_type_6 {
 476        uint8_t entry_type;             /* Entry type. */
 477        uint8_t entry_count;            /* Entry count. */
 478        uint8_t sys_define;             /* System defined. */
 479        uint8_t entry_status;           /* Entry Status. */
 480
 481        uint32_t handle;                /* System handle. */
 482
 483        __le16  nport_handle;           /* N_PORT handle. */
 484        __le16  timeout;                /* Command timeout. */
 485
 486        __le16  dseg_count;             /* Data segment count. */
 487
 488        __le16  fcp_rsp_dsd_len;        /* FCP_RSP DSD length. */
 489
 490        struct scsi_lun lun;            /* FCP LUN (BE). */
 491
 492        __le16  control_flags;          /* Control flags. */
 493#define CF_NEW_SA                       BIT_12
 494#define CF_EN_EDIF                      BIT_9
 495#define CF_ADDITIONAL_PARAM_BLK         BIT_8
 496#define CF_DIF_SEG_DESCR_ENABLE         BIT_3
 497#define CF_DATA_SEG_DESCR_ENABLE        BIT_2
 498#define CF_READ_DATA                    BIT_1
 499#define CF_WRITE_DATA                   BIT_0
 500
 501        __le16  fcp_cmnd_dseg_len;      /* Data segment length. */
 502                                        /* Data segment address. */
 503        __le64   fcp_cmnd_dseg_address __packed;
 504                                        /* Data segment address. */
 505        __le64   fcp_rsp_dseg_address __packed;
 506
 507        __le32  byte_count;             /* Total byte count. */
 508
 509        uint8_t port_id[3];             /* PortID of destination port. */
 510        uint8_t vp_index;
 511
 512        struct dsd64 fcp_dsd;
 513};
 514
 515#define COMMAND_TYPE_7  0x18            /* Command Type 7 entry */
 516struct cmd_type_7 {
 517        uint8_t entry_type;             /* Entry type. */
 518        uint8_t entry_count;            /* Entry count. */
 519        uint8_t sys_define;             /* System defined. */
 520        uint8_t entry_status;           /* Entry Status. */
 521
 522        uint32_t handle;                /* System handle. */
 523
 524        __le16  nport_handle;           /* N_PORT handle. */
 525        __le16  timeout;                /* Command timeout. */
 526#define FW_MAX_TIMEOUT          0x1999
 527
 528        __le16  dseg_count;             /* Data segment count. */
 529        uint16_t reserved_1;
 530
 531        struct scsi_lun lun;            /* FCP LUN (BE). */
 532
 533        __le16  task_mgmt_flags;        /* Task management flags. */
 534#define TMF_CLEAR_ACA           BIT_14
 535#define TMF_TARGET_RESET        BIT_13
 536#define TMF_LUN_RESET           BIT_12
 537#define TMF_CLEAR_TASK_SET      BIT_10
 538#define TMF_ABORT_TASK_SET      BIT_9
 539#define TMF_DSD_LIST_ENABLE     BIT_2
 540#define TMF_READ_DATA           BIT_1
 541#define TMF_WRITE_DATA          BIT_0
 542
 543        uint8_t task;
 544#define TSK_SIMPLE              0
 545#define TSK_HEAD_OF_QUEUE       1
 546#define TSK_ORDERED             2
 547#define TSK_ACA                 4
 548#define TSK_UNTAGGED            5
 549
 550        uint8_t crn;
 551
 552        uint8_t fcp_cdb[MAX_CMDSZ];     /* SCSI command words. */
 553        __le32  byte_count;             /* Total byte count. */
 554
 555        uint8_t port_id[3];             /* PortID of destination port. */
 556        uint8_t vp_index;
 557
 558        struct dsd64 dsd;
 559};
 560
 561#define COMMAND_TYPE_CRC_2      0x6A    /* Command Type CRC_2 (Type 6)
 562                                         * (T10-DIF) */
 563struct cmd_type_crc_2 {
 564        uint8_t entry_type;             /* Entry type. */
 565        uint8_t entry_count;            /* Entry count. */
 566        uint8_t sys_define;             /* System defined. */
 567        uint8_t entry_status;           /* Entry Status. */
 568
 569        uint32_t handle;                /* System handle. */
 570
 571        __le16  nport_handle;           /* N_PORT handle. */
 572        __le16  timeout;                /* Command timeout. */
 573
 574        __le16  dseg_count;             /* Data segment count. */
 575
 576        __le16  fcp_rsp_dseg_len;       /* FCP_RSP DSD length. */
 577
 578        struct scsi_lun lun;            /* FCP LUN (BE). */
 579
 580        __le16  control_flags;          /* Control flags. */
 581
 582        __le16  fcp_cmnd_dseg_len;      /* Data segment length. */
 583        __le64   fcp_cmnd_dseg_address __packed;
 584                                        /* Data segment address. */
 585        __le64   fcp_rsp_dseg_address __packed;
 586
 587        __le32  byte_count;             /* Total byte count. */
 588
 589        uint8_t port_id[3];             /* PortID of destination port. */
 590        uint8_t vp_index;
 591
 592        __le64   crc_context_address __packed;  /* Data segment address. */
 593        __le16  crc_context_len;                /* Data segment length. */
 594        uint16_t reserved_1;                    /* MUST be set to 0. */
 595};
 596
 597
 598/*
 599 * ISP queue - status entry structure definition.
 600 */
 601#define STATUS_TYPE     0x03            /* Status entry. */
 602struct sts_entry_24xx {
 603        uint8_t entry_type;             /* Entry type. */
 604        uint8_t entry_count;            /* Entry count. */
 605        uint8_t sys_define;             /* System defined. */
 606        uint8_t entry_status;           /* Entry Status. */
 607
 608        uint32_t handle;                /* System handle. */
 609
 610        __le16  comp_status;            /* Completion status. */
 611        __le16  ox_id;                  /* OX_ID used by the firmware. */
 612
 613        __le32  residual_len;           /* FW calc residual transfer length. */
 614
 615        union {
 616                __le16 reserved_1;
 617                __le16  nvme_rsp_pyld_len;
 618                __le16 edif_sa_index;    /* edif sa_index used for initiator read data */
 619        };
 620
 621        __le16  state_flags;            /* State flags. */
 622#define SF_TRANSFERRED_DATA     BIT_11
 623#define SF_NVME_ERSP            BIT_6
 624#define SF_FCP_RSP_DMA          BIT_0
 625
 626        __le16  status_qualifier;
 627        __le16  scsi_status;            /* SCSI status. */
 628#define SS_CONFIRMATION_REQ             BIT_12
 629
 630        __le32  rsp_residual_count;     /* FCP RSP residual count. */
 631
 632        __le32  sense_len;              /* FCP SENSE length. */
 633
 634        union {
 635                struct {
 636                        __le32  rsp_data_len;   /* FCP response data length  */
 637                        uint8_t data[28];       /* FCP rsp/sense information */
 638                };
 639                struct nvme_fc_ersp_iu nvme_ersp;
 640                uint8_t nvme_ersp_data[32];
 641        };
 642
 643        /*
 644         * If DIF Error is set in comp_status, these additional fields are
 645         * defined:
 646         *
 647         * !!! NOTE: Firmware sends expected/actual DIF data in big endian
 648         * format; but all of the "data" field gets swab32-d in the beginning
 649         * of qla2x00_status_entry().
 650         *
 651         * &data[10] : uint8_t report_runt_bg[2];       - computed guard
 652         * &data[12] : uint8_t actual_dif[8];           - DIF Data received
 653         * &data[20] : uint8_t expected_dif[8];         - DIF Data computed
 654        */
 655};
 656
 657
 658/*
 659 * Status entry completion status
 660 */
 661#define CS_DATA_REASSEMBLY_ERROR 0x11   /* Data Reassembly Error.. */
 662#define CS_ABTS_BY_TARGET       0x13    /* Target send ABTS to abort IOCB. */
 663#define CS_FW_RESOURCE          0x2C    /* Firmware Resource Unavailable. */
 664#define CS_TASK_MGMT_OVERRUN    0x30    /* Task management overrun (8+). */
 665#define CS_ABORT_BY_TARGET      0x47    /* Abort By Target. */
 666
 667/*
 668 * ISP queue - marker entry structure definition.
 669 */
 670#define MARKER_TYPE     0x04            /* Marker entry. */
 671struct mrk_entry_24xx {
 672        uint8_t entry_type;             /* Entry type. */
 673        uint8_t entry_count;            /* Entry count. */
 674        uint8_t handle_count;           /* Handle count. */
 675        uint8_t entry_status;           /* Entry Status. */
 676
 677        uint32_t handle;                /* System handle. */
 678
 679        __le16  nport_handle;           /* N_PORT handle. */
 680
 681        uint8_t modifier;               /* Modifier (7-0). */
 682#define MK_SYNC_ID_LUN  0               /* Synchronize ID/LUN */
 683#define MK_SYNC_ID      1               /* Synchronize ID */
 684#define MK_SYNC_ALL     2               /* Synchronize all ID/LUN */
 685        uint8_t reserved_1;
 686
 687        uint8_t reserved_2;
 688        uint8_t vp_index;
 689
 690        uint16_t reserved_3;
 691
 692        uint8_t lun[8];                 /* FCP LUN (BE). */
 693        uint8_t reserved_4[40];
 694};
 695
 696/*
 697 * ISP queue - CT Pass-Through entry structure definition.
 698 */
 699#define CT_IOCB_TYPE            0x29    /* CT Pass-Through IOCB entry */
 700struct ct_entry_24xx {
 701        uint8_t entry_type;             /* Entry type. */
 702        uint8_t entry_count;            /* Entry count. */
 703        uint8_t sys_define;             /* System Defined. */
 704        uint8_t entry_status;           /* Entry Status. */
 705
 706        uint32_t handle;                /* System handle. */
 707
 708        __le16  comp_status;            /* Completion status. */
 709
 710        __le16  nport_handle;           /* N_PORT handle. */
 711
 712        __le16  cmd_dsd_count;
 713
 714        uint8_t vp_index;
 715        uint8_t reserved_1;
 716
 717        __le16  timeout;                /* Command timeout. */
 718        uint16_t reserved_2;
 719
 720        __le16  rsp_dsd_count;
 721
 722        uint8_t reserved_3[10];
 723
 724        __le32  rsp_byte_count;
 725        __le32  cmd_byte_count;
 726
 727        struct dsd64 dsd[2];
 728};
 729
 730#define PURX_ELS_HEADER_SIZE    0x18
 731
 732/*
 733 * ISP queue - PUREX IOCB entry structure definition
 734 */
 735#define PUREX_IOCB_TYPE         0x51    /* CT Pass Through IOCB entry */
 736struct purex_entry_24xx {
 737        uint8_t entry_type;             /* Entry type. */
 738        uint8_t entry_count;            /* Entry count. */
 739        uint8_t sys_define;             /* System defined. */
 740        uint8_t entry_status;           /* Entry Status. */
 741
 742        __le16  reserved1;
 743        uint8_t vp_idx;
 744        uint8_t reserved2;
 745
 746        __le16  status_flags;
 747        __le16  nport_handle;
 748
 749        __le16  frame_size;
 750        __le16  trunc_frame_size;
 751
 752        __le32  rx_xchg_addr;
 753
 754        uint8_t d_id[3];
 755        uint8_t r_ctl;
 756
 757        uint8_t s_id[3];
 758        uint8_t cs_ctl;
 759
 760        uint8_t f_ctl[3];
 761        uint8_t type;
 762
 763        __le16  seq_cnt;
 764        uint8_t df_ctl;
 765        uint8_t seq_id;
 766
 767        __le16  rx_id;
 768        __le16  ox_id;
 769        __le32  param;
 770
 771        uint8_t els_frame_payload[20];
 772};
 773
 774/*
 775 * ISP queue - ELS Pass-Through entry structure definition.
 776 */
 777#define ELS_IOCB_TYPE           0x53    /* ELS Pass-Through IOCB entry */
 778struct els_entry_24xx {
 779        uint8_t entry_type;             /* Entry type. */
 780        uint8_t entry_count;            /* Entry count. */
 781        uint8_t sys_define;             /* System Defined. */
 782        uint8_t entry_status;           /* Entry Status. */
 783
 784        uint32_t handle;                /* System handle. */
 785
 786        __le16  comp_status;            /* response only */
 787        __le16  nport_handle;
 788
 789        __le16  tx_dsd_count;
 790
 791        uint8_t vp_index;
 792        uint8_t sof_type;
 793#define EST_SOFI3               (1 << 4)
 794#define EST_SOFI2               (3 << 4)
 795
 796        __le32  rx_xchg_address;        /* Receive exchange address. */
 797        __le16  rx_dsd_count;
 798
 799        uint8_t opcode;
 800        uint8_t reserved_2;
 801
 802        uint8_t d_id[3];
 803        uint8_t s_id[3];
 804
 805        __le16  control_flags;          /* Control flags. */
 806#define ECF_PAYLOAD_DESCR_MASK  (BIT_15|BIT_14|BIT_13)
 807#define EPD_ELS_COMMAND         (0 << 13)
 808#define EPD_ELS_ACC             (1 << 13)
 809#define EPD_ELS_RJT             (2 << 13)
 810#define EPD_RX_XCHG             (3 << 13)
 811#define ECF_CLR_PASSTHRU_PEND   BIT_12
 812#define ECF_INCL_FRAME_HDR      BIT_11
 813#define ECF_SEC_LOGIN           BIT_3
 814
 815        union {
 816                struct {
 817                        __le32   rx_byte_count;
 818                        __le32   tx_byte_count;
 819
 820                        __le64   tx_address __packed;   /* DSD 0 address. */
 821                        __le32   tx_len;                /* DSD 0 length. */
 822
 823                        __le64   rx_address __packed;   /* DSD 1 address. */
 824                        __le32   rx_len;                /* DSD 1 length. */
 825                };
 826                struct {
 827                        __le32  total_byte_count;
 828                        __le32  error_subcode_1;
 829                        __le32  error_subcode_2;
 830                        __le32  error_subcode_3;
 831                };
 832        };
 833};
 834
 835struct els_sts_entry_24xx {
 836        uint8_t entry_type;             /* Entry type. */
 837        uint8_t entry_count;            /* Entry count. */
 838        uint8_t sys_define;             /* System Defined. */
 839        uint8_t entry_status;           /* Entry Status. */
 840
 841        __le32  handle;         /* System handle. */
 842
 843        __le16  comp_status;
 844
 845        __le16  nport_handle;           /* N_PORT handle. */
 846
 847        __le16  reserved_1;
 848
 849        uint8_t vp_index;
 850        uint8_t sof_type;
 851
 852        __le32  rx_xchg_address;        /* Receive exchange address. */
 853        __le16  reserved_2;
 854
 855        uint8_t opcode;
 856        uint8_t reserved_3;
 857
 858        uint8_t d_id[3];
 859        uint8_t s_id[3];
 860
 861        __le16  control_flags;          /* Control flags. */
 862        __le32  total_byte_count;
 863        __le32  error_subcode_1;
 864        __le32  error_subcode_2;
 865        __le32  error_subcode_3;
 866
 867        __le32  reserved_4[4];
 868};
 869/*
 870 * ISP queue - Mailbox Command entry structure definition.
 871 */
 872#define MBX_IOCB_TYPE   0x39
 873struct mbx_entry_24xx {
 874        uint8_t entry_type;             /* Entry type. */
 875        uint8_t entry_count;            /* Entry count. */
 876        uint8_t handle_count;           /* Handle count. */
 877        uint8_t entry_status;           /* Entry Status. */
 878
 879        uint32_t handle;                /* System handle. */
 880
 881        uint16_t mbx[28];
 882};
 883
 884
 885#define LOGINOUT_PORT_IOCB_TYPE 0x52    /* Login/Logout Port entry. */
 886struct logio_entry_24xx {
 887        uint8_t entry_type;             /* Entry type. */
 888        uint8_t entry_count;            /* Entry count. */
 889        uint8_t sys_define;             /* System defined. */
 890        uint8_t entry_status;           /* Entry Status. */
 891
 892        uint32_t handle;                /* System handle. */
 893
 894        __le16  comp_status;            /* Completion status. */
 895#define CS_LOGIO_ERROR          0x31    /* Login/Logout IOCB error. */
 896
 897        __le16  nport_handle;           /* N_PORT handle. */
 898
 899        __le16  control_flags;          /* Control flags. */
 900                                        /* Modifiers. */
 901#define LCF_INCLUDE_SNS         BIT_10  /* Include SNS (FFFFFC) during LOGO. */
 902#define LCF_FCP2_OVERRIDE       BIT_9   /* Set/Reset word 3 of PRLI. */
 903#define LCF_CLASS_2             BIT_8   /* Enable class 2 during PLOGI. */
 904#define LCF_FREE_NPORT          BIT_7   /* Release NPORT handle after LOGO. */
 905#define LCF_COMMON_FEAT         BIT_7   /* PLOGI - Set Common Features Field */
 906#define LCF_EXPL_LOGO           BIT_6   /* Perform an explicit LOGO. */
 907#define LCF_NVME_PRLI           BIT_6   /* Perform NVME FC4 PRLI */
 908#define LCF_SKIP_PRLI           BIT_5   /* Skip PRLI after PLOGI. */
 909#define LCF_IMPL_LOGO_ALL       BIT_5   /* Implicit LOGO to all ports. */
 910#define LCF_COND_PLOGI          BIT_4   /* PLOGI only if not logged-in. */
 911#define LCF_IMPL_LOGO           BIT_4   /* Perform an implicit LOGO. */
 912#define LCF_IMPL_PRLO           BIT_4   /* Perform an implicit PRLO. */
 913                                        /* Commands. */
 914#define LCF_COMMAND_PLOGI       0x00    /* PLOGI. */
 915#define LCF_COMMAND_PRLI        0x01    /* PRLI. */
 916#define LCF_COMMAND_PDISC       0x02    /* PDISC. */
 917#define LCF_COMMAND_ADISC       0x03    /* ADISC. */
 918#define LCF_COMMAND_LOGO        0x08    /* LOGO. */
 919#define LCF_COMMAND_PRLO        0x09    /* PRLO. */
 920#define LCF_COMMAND_TPRLO       0x0A    /* TPRLO. */
 921
 922        uint8_t vp_index;
 923        uint8_t reserved_1;
 924
 925        uint8_t port_id[3];             /* PortID of destination port. */
 926
 927        uint8_t rsp_size;               /* Response size in 32bit words. */
 928
 929        __le32  io_parameter[11];       /* General I/O parameters. */
 930#define LIO_COMM_FEAT_FCSP      BIT_21
 931#define LIO_COMM_FEAT_CIO       BIT_31
 932#define LSC_SCODE_NOLINK        0x01
 933#define LSC_SCODE_NOIOCB        0x02
 934#define LSC_SCODE_NOXCB         0x03
 935#define LSC_SCODE_CMD_FAILED    0x04
 936#define LSC_SCODE_NOFABRIC      0x05
 937#define LSC_SCODE_FW_NOT_READY  0x07
 938#define LSC_SCODE_NOT_LOGGED_IN 0x09
 939#define LSC_SCODE_NOPCB         0x0A
 940
 941#define LSC_SCODE_ELS_REJECT    0x18
 942#define LSC_SCODE_CMD_PARAM_ERR 0x19
 943#define LSC_SCODE_PORTID_USED   0x1A
 944#define LSC_SCODE_NPORT_USED    0x1B
 945#define LSC_SCODE_NONPORT       0x1C
 946#define LSC_SCODE_LOGGED_IN     0x1D
 947#define LSC_SCODE_NOFLOGI_ACC   0x1F
 948};
 949
 950#define TSK_MGMT_IOCB_TYPE      0x14
 951struct tsk_mgmt_entry {
 952        uint8_t entry_type;             /* Entry type. */
 953        uint8_t entry_count;            /* Entry count. */
 954        uint8_t handle_count;           /* Handle count. */
 955        uint8_t entry_status;           /* Entry Status. */
 956
 957        uint32_t handle;                /* System handle. */
 958
 959        __le16  nport_handle;           /* N_PORT handle. */
 960
 961        uint16_t reserved_1;
 962
 963        __le16  delay;                  /* Activity delay in seconds. */
 964
 965        __le16  timeout;                /* Command timeout. */
 966
 967        struct scsi_lun lun;            /* FCP LUN (BE). */
 968
 969        __le32  control_flags;          /* Control Flags. */
 970#define TCF_NOTMCMD_TO_TARGET   BIT_31
 971#define TCF_LUN_RESET           BIT_4
 972#define TCF_ABORT_TASK_SET      BIT_3
 973#define TCF_CLEAR_TASK_SET      BIT_2
 974#define TCF_TARGET_RESET        BIT_1
 975#define TCF_CLEAR_ACA           BIT_0
 976
 977        uint8_t reserved_2[20];
 978
 979        uint8_t port_id[3];             /* PortID of destination port. */
 980        uint8_t vp_index;
 981
 982        uint8_t reserved_3[12];
 983};
 984
 985#define ABORT_IOCB_TYPE 0x33
 986struct abort_entry_24xx {
 987        uint8_t entry_type;             /* Entry type. */
 988        uint8_t entry_count;            /* Entry count. */
 989        uint8_t handle_count;           /* Handle count. */
 990        uint8_t entry_status;           /* Entry Status. */
 991
 992        uint32_t handle;                /* System handle. */
 993
 994        union {
 995                __le16 nport_handle;            /* N_PORT handle. */
 996                __le16 comp_status;             /* Completion status. */
 997        };
 998
 999        __le16  options;                /* Options. */
1000#define AOF_NO_ABTS             BIT_0   /* Do not send any ABTS. */

1001#define AOF_NO_RRQ              BIT_1   /* Do not send RRQ. */
1002#define AOF_ABTS_TIMEOUT        BIT_2   /* Disable logout on ABTS timeout. */
1003#define AOF_ABTS_RTY_CNT        BIT_3   /* Use driver specified retry count. */
1004#define AOF_RSP_TIMEOUT         BIT_4   /* Use specified response timeout. */
1005
1006
1007        uint32_t handle_to_abort;       /* System handle to abort. */
1008
1009        __le16  req_que_no;
1010        uint8_t reserved_1[30];
1011
1012        uint8_t port_id[3];             /* PortID of destination port. */
1013        uint8_t vp_index;
1014        u8      reserved_2[4];
1015        union {
1016                struct {
1017                        __le16 abts_rty_cnt;
1018                        __le16 rsp_timeout;
1019                } drv;
1020                struct {
1021                        u8      ba_rjt_vendorUnique;
1022                        u8      ba_rjt_reasonCodeExpl;
1023                        u8      ba_rjt_reasonCode;
1024                        u8      reserved_3;
1025                } fw;
1026        };
1027        u8      reserved_4[4];
1028};
1029
1030#define ABTS_RCV_TYPE           0x54
1031#define ABTS_RSP_TYPE           0x55
1032struct abts_entry_24xx {
1033        uint8_t entry_type;
1034        uint8_t entry_count;
1035        uint8_t handle_count;
1036        uint8_t entry_status;
1037
1038        __le32  handle;         /* type 0x55 only */
1039
1040        __le16  comp_status;            /* type 0x55 only */
1041        __le16  nport_handle;           /* type 0x54 only */
1042
1043        __le16  control_flags;          /* type 0x55 only */
1044        uint8_t vp_idx;
1045        uint8_t sof_type;               /* sof_type is upper nibble */
1046
1047        __le32  rx_xch_addr;
1048
1049        uint8_t d_id[3];
1050        uint8_t r_ctl;
1051
1052        uint8_t s_id[3];
1053        uint8_t cs_ctl;
1054
1055        uint8_t f_ctl[3];
1056        uint8_t type;
1057
1058        __le16  seq_cnt;
1059        uint8_t df_ctl;
1060        uint8_t seq_id;
1061
1062        __le16  rx_id;
1063        __le16  ox_id;
1064
1065        __le32  param;
1066
1067        union {
1068                struct {
1069                        __le32  subcode3;
1070                        __le32  rsvd;
1071                        __le32  subcode1;
1072                        __le32  subcode2;
1073                } error;
1074                struct {
1075                        __le16  rsrvd1;
1076                        uint8_t last_seq_id;
1077                        uint8_t seq_id_valid;
1078                        __le16  aborted_rx_id;
1079                        __le16  aborted_ox_id;
1080                        __le16  high_seq_cnt;
1081                        __le16  low_seq_cnt;
1082                } ba_acc;
1083                struct {
1084                        uint8_t vendor_unique;
1085                        uint8_t explanation;
1086                        uint8_t reason;
1087                } ba_rjt;
1088        } payload;
1089
1090        __le32  rx_xch_addr_to_abort;
1091} __packed;
1092
1093/* ABTS payload explanation values */
1094#define BA_RJT_EXP_NO_ADDITIONAL        0
1095#define BA_RJT_EXP_INV_OX_RX_ID         3
1096#define BA_RJT_EXP_SEQ_ABORTED          5
1097
1098/* ABTS payload reason values */
1099#define BA_RJT_RSN_INV_CMD_CODE         1
1100#define BA_RJT_RSN_LOGICAL_ERROR        3
1101#define BA_RJT_RSN_LOGICAL_BUSY         5
1102#define BA_RJT_RSN_PROTOCOL_ERROR       7
1103#define BA_RJT_RSN_UNABLE_TO_PERFORM    9
1104#define BA_RJT_RSN_VENDOR_SPECIFIC      0xff
1105
1106/* FC_F values */
1107#define FC_TYPE_BLD             0x000           /* Basic link data */
1108#define FC_F_CTL_RSP_CNTXT      0x800000        /* Responder of exchange */
1109#define FC_F_CTL_LAST_SEQ       0x100000        /* Last sequence */
1110#define FC_F_CTL_END_SEQ        0x80000         /* Last sequence */
1111#define FC_F_CTL_SEQ_INIT       0x010000        /* Sequence initiative */
1112#define FC_ROUTING_BLD          0x80            /* Basic link data frame */
1113#define FC_R_CTL_BLD_BA_ACC     0x04            /* BA_ACC (basic accept) */
1114
1115/*
1116 * ISP I/O Register Set structure definitions.
1117 */
1118struct device_reg_24xx {
1119        __le32  flash_addr;             /* Flash/NVRAM BIOS address. */
1120#define FARX_DATA_FLAG  BIT_31
1121#define FARX_ACCESS_FLASH_CONF  0x7FFD0000
1122#define FARX_ACCESS_FLASH_DATA  0x7FF00000
1123#define FARX_ACCESS_NVRAM_CONF  0x7FFF0000
1124#define FARX_ACCESS_NVRAM_DATA  0x7FFE0000
1125
1126#define FA_NVRAM_FUNC0_ADDR     0x80
1127#define FA_NVRAM_FUNC1_ADDR     0x180
1128
1129#define FA_NVRAM_VPD_SIZE       0x200
1130#define FA_NVRAM_VPD0_ADDR      0x00
1131#define FA_NVRAM_VPD1_ADDR      0x100
1132
1133#define FA_BOOT_CODE_ADDR       0x00000
1134                                        /*
1135                                         * RISC code begins at offset 512KB
1136                                         * within flash. Consisting of two
1137                                         * contiguous RISC code segments.
1138                                         */
1139#define FA_RISC_CODE_ADDR       0x20000
1140#define FA_RISC_CODE_SEGMENTS   2
1141
1142#define FA_FLASH_DESCR_ADDR_24  0x11000
1143#define FA_FLASH_LAYOUT_ADDR_24 0x11400
1144#define FA_NPIV_CONF0_ADDR_24   0x16000
1145#define FA_NPIV_CONF1_ADDR_24   0x17000
1146
1147#define FA_FW_AREA_ADDR         0x40000
1148#define FA_VPD_NVRAM_ADDR       0x48000
1149#define FA_FEATURE_ADDR         0x4C000
1150#define FA_FLASH_DESCR_ADDR     0x50000
1151#define FA_FLASH_LAYOUT_ADDR    0x50400
1152#define FA_HW_EVENT0_ADDR       0x54000
1153#define FA_HW_EVENT1_ADDR       0x54400
1154#define FA_HW_EVENT_SIZE        0x200
1155#define FA_HW_EVENT_ENTRY_SIZE  4
1156#define FA_NPIV_CONF0_ADDR      0x5C000
1157#define FA_NPIV_CONF1_ADDR      0x5D000
1158#define FA_FCP_PRIO0_ADDR       0x10000
1159#define FA_FCP_PRIO1_ADDR       0x12000
1160
1161/*
1162 * Flash Error Log Event Codes.
1163 */
1164#define HW_EVENT_RESET_ERR      0xF00B
1165#define HW_EVENT_ISP_ERR        0xF020
1166#define HW_EVENT_PARITY_ERR     0xF022
1167#define HW_EVENT_NVRAM_CHKSUM_ERR       0xF023
1168#define HW_EVENT_FLASH_FW_ERR   0xF024
1169
1170        __le32  flash_data;             /* Flash/NVRAM BIOS data. */
1171
1172        __le32  ctrl_status;            /* Control/Status. */
1173#define CSRX_FLASH_ACCESS_ERROR BIT_18  /* Flash/NVRAM Access Error. */
1174#define CSRX_DMA_ACTIVE         BIT_17  /* DMA Active status. */
1175#define CSRX_DMA_SHUTDOWN       BIT_16  /* DMA Shutdown control status. */
1176#define CSRX_FUNCTION           BIT_15  /* Function number. */
1177                                        /* PCI-X Bus Mode. */
1178#define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
1179#define PBM_PCI_33MHZ           (0 << 8)
1180#define PBM_PCIX_M1_66MHZ       (1 << 8)
1181#define PBM_PCIX_M1_100MHZ      (2 << 8)
1182#define PBM_PCIX_M1_133MHZ      (3 << 8)
1183#define PBM_PCIX_M2_66MHZ       (5 << 8)
1184#define PBM_PCIX_M2_100MHZ      (6 << 8)
1185#define PBM_PCIX_M2_133MHZ      (7 << 8)
1186#define PBM_PCI_66MHZ           (8 << 8)
1187                                        /* Max Write Burst byte count. */
1188#define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
1189#define MWB_512_BYTES           (0 << 4)
1190#define MWB_1024_BYTES          (1 << 4)
1191#define MWB_2048_BYTES          (2 << 4)
1192#define MWB_4096_BYTES          (3 << 4)
1193
1194#define CSRX_64BIT_SLOT         BIT_2   /* PCI 64-Bit Bus Slot. */
1195#define CSRX_FLASH_ENABLE       BIT_1   /* Flash BIOS Read/Write enable. */
1196#define CSRX_ISP_SOFT_RESET     BIT_0   /* ISP soft reset. */
1197
1198        __le32  ictrl;                  /* Interrupt control. */
1199#define ICRX_EN_RISC_INT        BIT_3   /* Enable RISC interrupts on PCI. */
1200
1201        __le32  istatus;                /* Interrupt status. */
1202#define ISRX_RISC_INT           BIT_3   /* RISC interrupt. */
1203
1204        __le32  unused_1[2];            /* Gap. */
1205
1206                                        /* Request Queue. */
1207        __le32  req_q_in;               /*  In-Pointer. */
1208        __le32  req_q_out;              /*  Out-Pointer. */
1209                                        /* Response Queue. */
1210        __le32  rsp_q_in;               /*  In-Pointer. */
1211        __le32  rsp_q_out;              /*  Out-Pointer. */
1212                                        /* Priority Request Queue. */
1213        __le32  preq_q_in;              /*  In-Pointer. */
1214        __le32  preq_q_out;             /*  Out-Pointer. */
1215
1216        __le32  unused_2[2];            /* Gap. */
1217
1218                                        /* ATIO Queue. */
1219        __le32  atio_q_in;              /*  In-Pointer. */
1220        __le32  atio_q_out;             /*  Out-Pointer. */
1221
1222        __le32  host_status;
1223#define HSRX_RISC_INT           BIT_15  /* RISC to Host interrupt. */
1224#define HSRX_RISC_PAUSED        BIT_8   /* RISC Paused. */
1225
1226        __le32  hccr;                   /* Host command & control register. */
1227                                        /* HCCR statuses. */
1228#define HCCRX_HOST_INT          BIT_6   /* Host to RISC interrupt bit. */
1229#define HCCRX_RISC_RESET        BIT_5   /* RISC Reset mode bit. */
1230                                        /* HCCR commands. */
1231                                        /* NOOP. */
1232#define HCCRX_NOOP              0x00000000
1233                                        /* Set RISC Reset. */
1234#define HCCRX_SET_RISC_RESET    0x10000000
1235                                        /* Clear RISC Reset. */
1236#define HCCRX_CLR_RISC_RESET    0x20000000
1237                                        /* Set RISC Pause. */
1238#define HCCRX_SET_RISC_PAUSE    0x30000000
1239                                        /* Releases RISC Pause. */
1240#define HCCRX_REL_RISC_PAUSE    0x40000000
1241                                        /* Set HOST to RISC interrupt. */
1242#define HCCRX_SET_HOST_INT      0x50000000
1243                                        /* Clear HOST to RISC interrupt. */
1244#define HCCRX_CLR_HOST_INT      0x60000000
1245                                        /* Clear RISC to PCI interrupt. */
1246#define HCCRX_CLR_RISC_INT      0xA0000000
1247
1248        __le32  gpiod;                  /* GPIO Data register. */
1249
1250                                        /* LED update mask. */
1251#define GPDX_LED_UPDATE_MASK    (BIT_20|BIT_19|BIT_18)
1252                                        /* Data update mask. */
1253#define GPDX_DATA_UPDATE_MASK   (BIT_17|BIT_16)
1254                                        /* Data update mask. */
1255#define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1256                                        /* LED control mask. */
1257#define GPDX_LED_COLOR_MASK     (BIT_4|BIT_3|BIT_2)
1258                                        /* LED bit values. Color names as
1259                                         * referenced in fw spec.
1260                                         */
1261#define GPDX_LED_YELLOW_ON      BIT_2
1262#define GPDX_LED_GREEN_ON       BIT_3
1263#define GPDX_LED_AMBER_ON       BIT_4
1264                                        /* Data in/out. */
1265#define GPDX_DATA_INOUT         (BIT_1|BIT_0)
1266
1267        __le32  gpioe;                  /* GPIO Enable register. */
1268                                        /* Enable update mask. */
1269#define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
1270                                        /* Enable update mask. */
1271#define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16)
1272                                        /* Enable. */
1273#define GPEX_ENABLE             (BIT_1|BIT_0)
1274
1275        __le32  iobase_addr;            /* I/O Bus Base Address register. */
1276
1277        __le32  unused_3[10];           /* Gap. */
1278
1279        __le16  mailbox0;
1280        __le16  mailbox1;
1281        __le16  mailbox2;
1282        __le16  mailbox3;
1283        __le16  mailbox4;
1284        __le16  mailbox5;
1285        __le16  mailbox6;
1286        __le16  mailbox7;
1287        __le16  mailbox8;
1288        __le16  mailbox9;
1289        __le16  mailbox10;
1290        __le16  mailbox11;
1291        __le16  mailbox12;
1292        __le16  mailbox13;
1293        __le16  mailbox14;
1294        __le16  mailbox15;
1295        __le16  mailbox16;
1296        __le16  mailbox17;
1297        __le16  mailbox18;
1298        __le16  mailbox19;
1299        __le16  mailbox20;
1300        __le16  mailbox21;
1301        __le16  mailbox22;
1302        __le16  mailbox23;
1303        __le16  mailbox24;
1304        __le16  mailbox25;
1305        __le16  mailbox26;
1306        __le16  mailbox27;
1307        __le16  mailbox28;
1308        __le16  mailbox29;
1309        __le16  mailbox30;
1310        __le16  mailbox31;
1311
1312        __le32  iobase_window;
1313        __le32  iobase_c4;
1314        __le32  iobase_c8;
1315        __le32  unused_4_1[6];          /* Gap. */
1316        __le32  iobase_q;
1317        __le32  unused_5[2];            /* Gap. */
1318        __le32  iobase_select;
1319        __le32  unused_6[2];            /* Gap. */
1320        __le32  iobase_sdata;
1321};
1322/* RISC-RISC semaphore register PCI offet */
1323#define RISC_REGISTER_BASE_OFFSET       0x7010
1324#define RISC_REGISTER_WINDOW_OFFSET     0x6
1325
1326/* RISC-RISC semaphore/flag register (risc address 0x7016) */
1327
1328#define RISC_SEMAPHORE          0x1UL
1329#define RISC_SEMAPHORE_WE       (RISC_SEMAPHORE << 16)
1330#define RISC_SEMAPHORE_CLR      (RISC_SEMAPHORE_WE | 0x0UL)
1331#define RISC_SEMAPHORE_SET      (RISC_SEMAPHORE_WE | RISC_SEMAPHORE)
1332
1333#define RISC_SEMAPHORE_FORCE            0x8000UL
1334#define RISC_SEMAPHORE_FORCE_WE         (RISC_SEMAPHORE_FORCE << 16)
1335#define RISC_SEMAPHORE_FORCE_CLR        (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1336#define RISC_SEMAPHORE_FORCE_SET        \
1337                (RISC_SEMAPHORE_FORCE_WE | RISC_SEMAPHORE_FORCE)
1338
1339/* RISC semaphore timeouts (ms) */
1340#define TIMEOUT_SEMAPHORE               2500
1341#define TIMEOUT_SEMAPHORE_FORCE         2000
1342#define TIMEOUT_TOTAL_ELAPSED           4500
1343
1344/* Trace Control *************************************************************/
1345
1346#define TC_AEN_DISABLE          0
1347
1348#define TC_EFT_ENABLE           4
1349#define TC_EFT_DISABLE          5
1350
1351#define TC_FCE_ENABLE           8
1352#define TC_FCE_OPTIONS          0
1353#define TC_FCE_DEFAULT_RX_SIZE  2112
1354#define TC_FCE_DEFAULT_TX_SIZE  2112
1355#define TC_FCE_DISABLE          9
1356#define TC_FCE_DISABLE_TRACE    BIT_0
1357
1358/* MID Support ***************************************************************/
1359
1360#define MIN_MULTI_ID_FABRIC     64      /* Must be power-of-2. */
1361#define MAX_MULTI_ID_FABRIC     256     /* ... */
1362
1363struct mid_conf_entry_24xx {
1364        uint16_t reserved_1;
1365
1366        /*
1367         * BIT 0  = Enable Hard Loop Id
1368         * BIT 1  = Acquire Loop ID in LIPA
1369         * BIT 2  = ID not Acquired
1370         * BIT 3  = Enable VP
1371         * BIT 4  = Enable Initiator Mode
1372         * BIT 5  = Disable Target Mode
1373         * BIT 6-7 = Reserved
1374         */
1375        uint8_t options;
1376
1377        uint8_t hard_address;
1378
1379        uint8_t port_name[WWN_SIZE];
1380        uint8_t node_name[WWN_SIZE];
1381};
1382
1383struct mid_init_cb_24xx {
1384        struct init_cb_24xx init_cb;
1385
1386        __le16  count;
1387        __le16  options;
1388
1389        struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1390};
1391
1392
1393struct mid_db_entry_24xx {
1394        uint16_t status;
1395#define MDBS_NON_PARTIC         BIT_3
1396#define MDBS_ID_ACQUIRED        BIT_1
1397#define MDBS_ENABLED            BIT_0
1398
1399        uint8_t options;
1400        uint8_t hard_address;
1401
1402        uint8_t port_name[WWN_SIZE];
1403        uint8_t node_name[WWN_SIZE];
1404
1405        uint8_t port_id[3];
1406        uint8_t reserved_1;
1407};
1408
1409/*
1410 * Virtual Port Control IOCB
1411 */
1412#define VP_CTRL_IOCB_TYPE       0x30    /* Virtual Port Control entry. */
1413struct vp_ctrl_entry_24xx {
1414        uint8_t entry_type;             /* Entry type. */
1415        uint8_t entry_count;            /* Entry count. */
1416        uint8_t sys_define;             /* System defined. */
1417        uint8_t entry_status;           /* Entry Status. */
1418
1419        uint32_t handle;                /* System handle. */
1420
1421        __le16  vp_idx_failed;
1422
1423        __le16  comp_status;            /* Completion status. */
1424#define CS_VCE_IOCB_ERROR       0x01    /* Error processing IOCB */
1425#define CS_VCE_ACQ_ID_ERROR     0x02    /* Error while acquireing ID. */
1426#define CS_VCE_BUSY             0x05    /* Firmware not ready to accept cmd. */
1427
1428        __le16  command;
1429#define VCE_COMMAND_ENABLE_VPS  0x00    /* Enable VPs. */
1430#define VCE_COMMAND_DISABLE_VPS 0x08    /* Disable VPs. */
1431#define VCE_COMMAND_DISABLE_VPS_REINIT  0x09 /* Disable VPs and reinit link. */
1432#define VCE_COMMAND_DISABLE_VPS_LOGO    0x0a /* Disable VPs and LOGO ports. */
1433#define VCE_COMMAND_DISABLE_VPS_LOGO_ALL        0x0b /* Disable VPs and LOGO ports. */
1434
1435        __le16  vp_count;
1436
1437        uint8_t vp_idx_map[16];
1438        __le16  flags;
1439        __le16  id;
1440        uint16_t reserved_4;
1441        __le16  hopct;
1442        uint8_t reserved_5[24];
1443};
1444
1445/*
1446 * Modify Virtual Port Configuration IOCB
1447 */
1448#define VP_CONFIG_IOCB_TYPE     0x31    /* Virtual Port Config entry. */
1449struct vp_config_entry_24xx {
1450        uint8_t entry_type;             /* Entry type. */
1451        uint8_t entry_count;            /* Entry count. */
1452        uint8_t handle_count;
1453        uint8_t entry_status;           /* Entry Status. */
1454
1455        uint32_t handle;                /* System handle. */
1456
1457        __le16  flags;
1458#define CS_VF_BIND_VPORTS_TO_VF         BIT_0
1459#define CS_VF_SET_QOS_OF_VPORTS         BIT_1
1460#define CS_VF_SET_HOPS_OF_VPORTS        BIT_2
1461
1462        __le16  comp_status;            /* Completion status. */
1463#define CS_VCT_STS_ERROR        0x01    /* Specified VPs were not disabled. */
1464#define CS_VCT_CNT_ERROR        0x02    /* Invalid VP count. */
1465#define CS_VCT_ERROR            0x03    /* Unknown error. */
1466#define CS_VCT_IDX_ERROR        0x02    /* Invalid VP index. */
1467#define CS_VCT_BUSY             0x05    /* Firmware not ready to accept cmd. */
1468
1469        uint8_t command;
1470#define VCT_COMMAND_MOD_VPS     0x00    /* Modify VP configurations. */
1471#define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1472
1473        uint8_t vp_count;
1474
1475        uint8_t vp_index1;
1476        uint8_t vp_index2;
1477
1478        uint8_t options_idx1;
1479        uint8_t hard_address_idx1;
1480        uint16_t reserved_vp1;
1481        uint8_t port_name_idx1[WWN_SIZE];
1482        uint8_t node_name_idx1[WWN_SIZE];
1483
1484        uint8_t options_idx2;
1485        uint8_t hard_address_idx2;
1486        uint16_t reserved_vp2;
1487        uint8_t port_name_idx2[WWN_SIZE];
1488        uint8_t node_name_idx2[WWN_SIZE];
1489        __le16  id;
1490        uint16_t reserved_4;
1491        __le16  hopct;
1492        uint8_t reserved_5[2];
1493};
1494
1495#define VP_RPT_ID_IOCB_TYPE     0x32    /* Report ID Acquisition entry. */
1496enum VP_STATUS {
1497        VP_STAT_COMPL,
1498        VP_STAT_FAIL,
1499        VP_STAT_ID_CHG,
1500        VP_STAT_SNS_TO,                         /* timeout */
1501        VP_STAT_SNS_RJT,
1502        VP_STAT_SCR_TO,                         /* timeout */
1503        VP_STAT_SCR_RJT,
1504};
1505
1506enum VP_FLAGS {
1507        VP_FLAGS_CON_FLOOP = 1,
1508        VP_FLAGS_CON_P2P = 2,
1509        VP_FLAGS_CON_FABRIC = 3,
1510        VP_FLAGS_NAME_VALID = BIT_5,
1511};
1512
1513struct vp_rpt_id_entry_24xx {
1514        uint8_t entry_type;             /* Entry type. */
1515        uint8_t entry_count;            /* Entry count. */
1516        uint8_t sys_define;             /* System defined. */
1517        uint8_t entry_status;           /* Entry Status. */
1518        __le32 resv1;
1519        uint8_t vp_acquired;
1520        uint8_t vp_setup;
1521        uint8_t vp_idx;         /* Format 0=reserved */
1522        uint8_t vp_status;      /* Format 0=reserved */
1523
1524        uint8_t port_id[3];
1525        uint8_t format;
1526        union {
1527                struct _f0 {
1528                        /* format 0 loop */
1529                        uint8_t vp_idx_map[16];
1530                        uint8_t reserved_4[32];
1531                } f0;
1532                struct _f1 {
1533                        /* format 1 fabric */
1534                        uint8_t vpstat1_subcode; /* vp_status=1 subcode */
1535                        uint8_t flags;
1536#define TOPO_MASK  0xE
1537#define TOPO_FL    0x2
1538#define TOPO_N2N   0x4
1539#define TOPO_F     0x6
1540
1541                        uint16_t fip_flags;
1542                        uint8_t rsv2[12];
1543
1544                        uint8_t ls_rjt_vendor;
1545                        uint8_t ls_rjt_explanation;
1546                        uint8_t ls_rjt_reason;
1547                        uint8_t rsv3[5];
1548
1549                        uint8_t port_name[8];
1550                        uint8_t node_name[8];
1551                        uint16_t bbcr;
1552                        uint8_t reserved_5[6];
1553                } f1;
1554                struct _f2 { /* format 2: N2N direct connect */
1555                        uint8_t vpstat1_subcode;
1556                        uint8_t flags;
1557                        uint16_t fip_flags;
1558                        uint8_t rsv2[12];
1559
1560                        uint8_t ls_rjt_vendor;
1561                        uint8_t ls_rjt_explanation;
1562                        uint8_t ls_rjt_reason;
1563                        uint8_t rsv3[5];
1564
1565                        uint8_t port_name[8];
1566                        uint8_t node_name[8];
1567                        uint16_t bbcr;
1568                        uint8_t reserved_5[2];
1569                        uint8_t remote_nport_id[4];
1570                } f2;
1571        } u;
1572};
1573
1574#define VF_EVFP_IOCB_TYPE       0x26    /* Exchange Virtual Fabric Parameters entry. */
1575struct vf_evfp_entry_24xx {
1576        uint8_t entry_type;             /* Entry type. */
1577        uint8_t entry_count;            /* Entry count. */
1578        uint8_t sys_define;             /* System defined. */
1579        uint8_t entry_status;           /* Entry Status. */
1580
1581        uint32_t handle;                /* System handle. */
1582        __le16  comp_status;           /* Completion status. */
1583        __le16  timeout;               /* timeout */
1584        __le16  adim_tagging_mode;
1585
1586        __le16  vfport_id;
1587        uint32_t exch_addr;
1588
1589        __le16  nport_handle;          /* N_PORT handle. */
1590        __le16  control_flags;
1591        uint32_t io_parameter_0;
1592        uint32_t io_parameter_1;
1593        __le64   tx_address __packed;   /* Data segment 0 address. */
1594        uint32_t tx_len;                /* Data segment 0 length. */
1595        __le64   rx_address __packed;   /* Data segment 1 address. */
1596        uint32_t rx_len;                /* Data segment 1 length. */
1597};
1598
1599/* END MID Support ***********************************************************/
1600
1601/* Flash Description Table ***************************************************/
1602
1603struct qla_fdt_layout {
1604        uint8_t sig[4];
1605        __le16  version;
1606        __le16  len;
1607        __le16  checksum;
1608        uint8_t unused1[2];
1609        uint8_t model[16];
1610        __le16  man_id;
1611        __le16  id;
1612        uint8_t flags;
1613        uint8_t erase_cmd;
1614        uint8_t alt_erase_cmd;
1615        uint8_t wrt_enable_cmd;
1616        uint8_t wrt_enable_bits;
1617        uint8_t wrt_sts_reg_cmd;
1618        uint8_t unprotect_sec_cmd;
1619        uint8_t read_man_id_cmd;
1620        __le32 block_size;
1621        __le32 alt_block_size;
1622        __le32 flash_size;
1623        __le32 wrt_enable_data;
1624        uint8_t read_id_addr_len;
1625        uint8_t wrt_disable_bits;
1626        uint8_t read_dev_id_len;
1627        uint8_t chip_erase_cmd;
1628        __le16  read_timeout;
1629        uint8_t protect_sec_cmd;
1630        uint8_t unused2[65];
1631};
1632
1633/* Flash Layout Table ********************************************************/
1634
1635struct qla_flt_location {
1636        uint8_t sig[4];
1637        __le16  start_lo;
1638        __le16  start_hi;
1639        uint8_t version;
1640        uint8_t unused[5];
1641        __le16  checksum;
1642};
1643
1644#define FLT_REG_FW              0x01
1645#define FLT_REG_BOOT_CODE       0x07
1646#define FLT_REG_VPD_0           0x14
1647#define FLT_REG_NVRAM_0         0x15
1648#define FLT_REG_VPD_1           0x16
1649#define FLT_REG_NVRAM_1         0x17
1650#define FLT_REG_VPD_2           0xD4
1651#define FLT_REG_NVRAM_2         0xD5
1652#define FLT_REG_VPD_3           0xD6
1653#define FLT_REG_NVRAM_3         0xD7
1654#define FLT_REG_FDT             0x1a
1655#define FLT_REG_FLT             0x1c
1656#define FLT_REG_HW_EVENT_0      0x1d
1657#define FLT_REG_HW_EVENT_1      0x1f
1658#define FLT_REG_NPIV_CONF_0     0x29
1659#define FLT_REG_NPIV_CONF_1     0x2a
1660#define FLT_REG_GOLD_FW         0x2f
1661#define FLT_REG_FCP_PRIO_0      0x87
1662#define FLT_REG_FCP_PRIO_1      0x88
1663#define FLT_REG_CNA_FW          0x97
1664#define FLT_REG_BOOT_CODE_8044  0xA2
1665#define FLT_REG_FCOE_FW         0xA4
1666#define FLT_REG_FCOE_NVRAM_0    0xAA
1667#define FLT_REG_FCOE_NVRAM_1    0xAC
1668
1669/* 27xx */
1670#define FLT_REG_IMG_PRI_27XX    0x95
1671#define FLT_REG_IMG_SEC_27XX    0x96
1672#define FLT_REG_FW_SEC_27XX     0x02
1673#define FLT_REG_BOOTLOAD_SEC_27XX       0x9
1674#define FLT_REG_VPD_SEC_27XX_0  0x50
1675#define FLT_REG_VPD_SEC_27XX_1  0x52
1676#define FLT_REG_VPD_SEC_27XX_2  0xD8
1677#define FLT_REG_VPD_SEC_27XX_3  0xDA
1678
1679/* 28xx */
1680#define FLT_REG_AUX_IMG_PRI_28XX        0x125
1681#define FLT_REG_AUX_IMG_SEC_28XX        0x126
1682#define FLT_REG_VPD_SEC_28XX_0          0x10C
1683#define FLT_REG_VPD_SEC_28XX_1          0x10E
1684#define FLT_REG_VPD_SEC_28XX_2          0x110
1685#define FLT_REG_VPD_SEC_28XX_3          0x112
1686#define FLT_REG_NVRAM_SEC_28XX_0        0x10D
1687#define FLT_REG_NVRAM_SEC_28XX_1        0x10F
1688#define FLT_REG_NVRAM_SEC_28XX_2        0x111
1689#define FLT_REG_NVRAM_SEC_28XX_3        0x113
1690#define FLT_REG_MPI_PRI_28XX            0xD3
1691#define FLT_REG_MPI_SEC_28XX            0xF0
1692#define FLT_REG_PEP_PRI_28XX            0xD1
1693#define FLT_REG_PEP_SEC_28XX            0xF1
1694
1695struct qla_flt_region {
1696        __le16  code;
1697        uint8_t attribute;
1698        uint8_t reserved;
1699        __le32 size;
1700        __le32 start;
1701        __le32 end;
1702};
1703
1704struct qla_flt_header {
1705        __le16  version;
1706        __le16  length;
1707        __le16  checksum;
1708        __le16  unused;
1709        struct qla_flt_region region[0];
1710};
1711
1712#define FLT_REGION_SIZE         16
1713#define FLT_MAX_REGIONS         0xFF
1714#define FLT_REGIONS_SIZE        (FLT_REGION_SIZE * FLT_MAX_REGIONS)
1715
1716/* Flash NPIV Configuration Table ********************************************/
1717
1718struct qla_npiv_header {
1719        uint8_t sig[2];
1720        __le16  version;
1721        __le16  entries;
1722        __le16  unused[4];
1723        __le16  checksum;
1724};
1725
1726struct qla_npiv_entry {
1727        __le16  flags;
1728        __le16  vf_id;
1729        uint8_t q_qos;
1730        uint8_t f_qos;
1731        __le16  unused1;
1732        uint8_t port_name[WWN_SIZE];
1733        uint8_t node_name[WWN_SIZE];
1734};
1735
1736/* 84XX Support **************************************************************/
1737
1738#define MBA_ISP84XX_ALERT       0x800f  /* Alert Notification. */
1739#define A84_PANIC_RECOVERY      0x1
1740#define A84_OP_LOGIN_COMPLETE   0x2
1741#define A84_DIAG_LOGIN_COMPLETE 0x3
1742#define A84_GOLD_LOGIN_COMPLETE 0x4
1743
1744#define MBC_ISP84XX_RESET       0x3a    /* Reset. */
1745
1746#define FSTATE_REMOTE_FC_DOWN   BIT_0
1747#define FSTATE_NSL_LINK_DOWN    BIT_1
1748#define FSTATE_IS_DIAG_FW       BIT_2
1749#define FSTATE_LOGGED_IN        BIT_3
1750#define FSTATE_WAITING_FOR_VERIFY       BIT_4
1751
1752#define VERIFY_CHIP_IOCB_TYPE   0x1B
1753struct verify_chip_entry_84xx {
1754        uint8_t entry_type;
1755        uint8_t entry_count;
1756        uint8_t sys_defined;
1757        uint8_t entry_status;
1758
1759        uint32_t handle;
1760
1761        __le16  options;
1762#define VCO_DONT_UPDATE_FW      BIT_0
1763#define VCO_FORCE_UPDATE        BIT_1
1764#define VCO_DONT_RESET_UPDATE   BIT_2
1765#define VCO_DIAG_FW             BIT_3
1766#define VCO_END_OF_DATA         BIT_14
1767#define VCO_ENABLE_DSD          BIT_15
1768
1769        __le16  reserved_1;
1770
1771        __le16  data_seg_cnt;
1772        __le16  reserved_2[3];
1773
1774        __le32  fw_ver;
1775        __le32  exchange_address;
1776
1777        __le32 reserved_3[3];
1778        __le32  fw_size;
1779        __le32  fw_seq_size;
1780        __le32  relative_offset;
1781
1782        struct dsd64 dsd;
1783};
1784
1785struct verify_chip_rsp_84xx {
1786        uint8_t entry_type;
1787        uint8_t entry_count;
1788        uint8_t sys_defined;
1789        uint8_t entry_status;
1790
1791        uint32_t handle;
1792
1793        __le16  comp_status;
1794#define CS_VCS_CHIP_FAILURE     0x3
1795#define CS_VCS_BAD_EXCHANGE     0x8
1796#define CS_VCS_SEQ_COMPLETEi    0x40
1797
1798        __le16  failure_code;
1799#define VFC_CHECKSUM_ERROR      0x1
1800#define VFC_INVALID_LEN         0x2
1801#define VFC_ALREADY_IN_PROGRESS 0x8
1802
1803        __le16  reserved_1[4];
1804
1805        __le32  fw_ver;
1806        __le32  exchange_address;
1807
1808        __le32 reserved_2[6];
1809};
1810
1811#define ACCESS_CHIP_IOCB_TYPE   0x2B
1812struct access_chip_84xx {
1813        uint8_t entry_type;
1814        uint8_t entry_count;
1815        uint8_t sys_defined;
1816        uint8_t entry_status;
1817
1818        uint32_t handle;
1819
1820        __le16  options;
1821#define ACO_DUMP_MEMORY         0x0
1822#define ACO_LOAD_MEMORY         0x1
1823#define ACO_CHANGE_CONFIG_PARAM 0x2
1824#define ACO_REQUEST_INFO        0x3
1825
1826        __le16  reserved1;
1827
1828        __le16  dseg_count;
1829        __le16  reserved2[3];
1830
1831        __le32  parameter1;
1832        __le32  parameter2;
1833        __le32  parameter3;
1834
1835        __le32  reserved3[3];
1836        __le32  total_byte_cnt;
1837        __le32  reserved4;
1838
1839        struct dsd64 dsd;
1840};
1841
1842struct access_chip_rsp_84xx {
1843        uint8_t entry_type;
1844        uint8_t entry_count;
1845        uint8_t sys_defined;
1846        uint8_t entry_status;
1847
1848        uint32_t handle;
1849
1850        __le16  comp_status;
1851        __le16  failure_code;
1852        __le32  residual_count;
1853
1854        __le32  reserved[12];
1855};
1856
1857/* 81XX Support **************************************************************/
1858
1859#define MBA_DCBX_START          0x8016
1860#define MBA_DCBX_COMPLETE       0x8030
1861#define MBA_FCF_CONF_ERR        0x8031
1862#define MBA_DCBX_PARAM_UPDATE   0x8032
1863#define MBA_IDC_COMPLETE        0x8100
1864#define MBA_IDC_NOTIFY          0x8101
1865#define MBA_IDC_TIME_EXT        0x8102
1866
1867#define MBC_IDC_ACK             0x101
1868#define MBC_RESTART_MPI_FW      0x3d
1869#define MBC_FLASH_ACCESS_CTRL   0x3e    /* Control flash access. */
1870#define MBC_GET_XGMAC_STATS     0x7a
1871#define MBC_GET_DCBX_PARAMS     0x51
1872
1873/*
1874 * ISP83xx mailbox commands
1875 */
1876#define MBC_WRITE_REMOTE_REG            0x0001 /* Write remote register */
1877#define MBC_READ_REMOTE_REG             0x0009 /* Read remote register */
1878#define MBC_RESTART_NIC_FIRMWARE        0x003d /* Restart NIC firmware */
1879#define MBC_SET_ACCESS_CONTROL          0x003e /* Access control command */
1880
1881/* Flash access control option field bit definitions */
1882#define FAC_OPT_FORCE_SEMAPHORE         BIT_15
1883#define FAC_OPT_REQUESTOR_ID            BIT_14
1884#define FAC_OPT_CMD_SUBCODE             0xff
1885
1886/* Flash access control command subcodes */
1887#define FAC_OPT_CMD_WRITE_PROTECT       0x00
1888#define FAC_OPT_CMD_WRITE_ENABLE        0x01
1889#define FAC_OPT_CMD_ERASE_SECTOR        0x02
1890#define FAC_OPT_CMD_LOCK_SEMAPHORE      0x03
1891#define FAC_OPT_CMD_UNLOCK_SEMAPHORE    0x04
1892#define FAC_OPT_CMD_GET_SECTOR_SIZE     0x05
1893
1894/* enhanced features bit definitions */
1895#define NEF_LR_DIST_ENABLE      BIT_0
1896
1897/* LR Distance bit positions */
1898#define LR_DIST_NV_POS          2
1899#define LR_DIST_NV_MASK         0xf
1900#define LR_DIST_FW_POS          12
1901
1902/* FAC semaphore defines */
1903#define FAC_SEMAPHORE_UNLOCK    0
1904#define FAC_SEMAPHORE_LOCK      1
1905
1906struct nvram_81xx {
1907        /* NVRAM header. */
1908        uint8_t id[4];
1909        __le16  nvram_version;
1910        __le16  reserved_0;
1911
1912        /* Firmware Initialization Control Block. */
1913        __le16  version;
1914        __le16  reserved_1;
1915        __le16  frame_payload_size;
1916        __le16  execution_throttle;
1917        __le16  exchange_count;
1918        __le16  reserved_2;
1919
1920        uint8_t port_name[WWN_SIZE];
1921        uint8_t node_name[WWN_SIZE];
1922
1923        __le16  login_retry_count;
1924        __le16  reserved_3;
1925        __le16  interrupt_delay_timer;
1926        __le16  login_timeout;
1927
1928        __le32  firmware_options_1;
1929        __le32  firmware_options_2;
1930        __le32  firmware_options_3;
1931
1932        __le16  reserved_4[4];
1933
1934        /* Offset 64. */
1935        uint8_t enode_mac[6];
1936        __le16  reserved_5[5];
1937
1938        /* Offset 80. */
1939        __le16  reserved_6[24];
1940
1941        /* Offset 128. */
1942        __le16  ex_version;
1943        uint8_t prio_fcf_matching_flags;
1944        uint8_t reserved_6_1[3];
1945        __le16  pri_fcf_vlan_id;
1946        uint8_t pri_fcf_fabric_name[8];
1947        __le16  reserved_6_2[7];
1948        uint8_t spma_mac_addr[6];
1949        __le16  reserved_6_3[14];
1950
1951        /* Offset 192. */
1952        uint8_t min_supported_speed;
1953        uint8_t reserved_7_0;
1954        __le16  reserved_7[31];
1955
1956        /*
1957         * BIT 0  = Enable spinup delay
1958         * BIT 1  = Disable BIOS
1959         * BIT 2  = Enable Memory Map BIOS
1960         * BIT 3  = Enable Selectable Boot
1961         * BIT 4  = Disable RISC code load
1962         * BIT 5  = Disable Serdes
1963         * BIT 6  = Opt boot mode
1964         * BIT 7  = Interrupt enable
1965         *
1966         * BIT 8  = EV Control enable
1967         * BIT 9  = Enable lip reset
1968         * BIT 10 = Enable lip full login
1969         * BIT 11 = Enable target reset
1970         * BIT 12 = Stop firmware
1971         * BIT 13 = Enable nodename option
1972         * BIT 14 = Default WWPN valid
1973         * BIT 15 = Enable alternate WWN
1974         *
1975         * BIT 16 = CLP LUN string
1976         * BIT 17 = CLP Target string
1977         * BIT 18 = CLP BIOS enable string
1978         * BIT 19 = CLP Serdes string
1979         * BIT 20 = CLP WWPN string
1980         * BIT 21 = CLP WWNN string
1981         * BIT 22 =
1982         * BIT 23 =
1983         * BIT 24 = Keep WWPN
1984         * BIT 25 = Temp WWPN
1985         * BIT 26-31 =
1986         */
1987        __le32  host_p;
1988
1989        uint8_t alternate_port_name[WWN_SIZE];
1990        uint8_t alternate_node_name[WWN_SIZE];
1991
1992        uint8_t boot_port_name[WWN_SIZE];
1993        __le16  boot_lun_number;
1994        __le16  reserved_8;
1995
1996        uint8_t alt1_boot_port_name[WWN_SIZE];
1997        __le16  alt1_boot_lun_number;
1998        __le16  reserved_9;
1999
2000        uint8_t alt2_boot_port_name[WWN_SIZE];

2001        __le16  alt2_boot_lun_number;
2002        __le16  reserved_10;
2003
2004        uint8_t alt3_boot_port_name[WWN_SIZE];
2005        __le16  alt3_boot_lun_number;
2006        __le16  reserved_11;
2007
2008        /*
2009         * BIT 0 = Selective Login
2010         * BIT 1 = Alt-Boot Enable
2011         * BIT 2 = Reserved
2012         * BIT 3 = Boot Order List
2013         * BIT 4 = Reserved
2014         * BIT 5 = Selective LUN
2015         * BIT 6 = Reserved
2016         * BIT 7-31 =
2017         */
2018        __le32  efi_parameters;
2019
2020        uint8_t reset_delay;
2021        uint8_t reserved_12;
2022        __le16  reserved_13;
2023
2024        __le16  boot_id_number;
2025        __le16  reserved_14;
2026
2027        __le16  max_luns_per_target;
2028        __le16  reserved_15;
2029
2030        __le16  port_down_retry_count;
2031        __le16  link_down_timeout;
2032
2033        /* FCode parameters. */
2034        __le16  fcode_parameter;
2035
2036        __le16  reserved_16[3];
2037
2038        /* Offset 352. */
2039        uint8_t reserved_17[4];
2040        __le16  reserved_18[5];
2041        uint8_t reserved_19[2];
2042        __le16  reserved_20[8];
2043
2044        /* Offset 384. */
2045        uint8_t reserved_21[16];
2046        __le16  reserved_22[3];
2047
2048        /* Offset 406 (0x196) Enhanced Features
2049         * BIT 0    = Extended BB credits for LR
2050         * BIT 1    = Virtual Fabric Enable
2051         * BIT 2-5  = Distance Support if BIT 0 is on
2052         * BIT 6    = Prefer FCP
2053         * BIT 7    = SCM Disabled if BIT is set (1)
2054         * BIT 8-15 = Unused
2055         */
2056        uint16_t enhanced_features;
2057
2058        uint16_t reserved_24[4];
2059
2060        /* Offset 416. */
2061        __le16  reserved_25[32];
2062
2063        /* Offset 480. */
2064        uint8_t model_name[16];
2065
2066        /* Offset 496. */
2067        __le16  feature_mask_l;
2068        __le16  feature_mask_h;
2069        __le16  reserved_26[2];
2070
2071        __le16  subsystem_vendor_id;
2072        __le16  subsystem_device_id;
2073
2074        __le32  checksum;
2075};
2076
2077/*
2078 * ISP Initialization Control Block.
2079 * Little endian except where noted.
2080 */
2081#define ICB_VERSION 1
2082struct init_cb_81xx {
2083        __le16  version;
2084        __le16  reserved_1;
2085
2086        __le16  frame_payload_size;
2087        __le16  execution_throttle;
2088        __le16  exchange_count;
2089
2090        __le16  reserved_2;
2091
2092        uint8_t port_name[WWN_SIZE];            /* Big endian. */
2093        uint8_t node_name[WWN_SIZE];            /* Big endian. */
2094
2095        __le16  response_q_inpointer;
2096        __le16  request_q_outpointer;
2097
2098        __le16  login_retry_count;
2099
2100        __le16  prio_request_q_outpointer;
2101
2102        __le16  response_q_length;
2103        __le16  request_q_length;
2104
2105        __le16  reserved_3;
2106
2107        __le16  prio_request_q_length;
2108
2109        __le64   request_q_address __packed;
2110        __le64   response_q_address __packed;
2111        __le64   prio_request_q_address __packed;
2112
2113        uint8_t reserved_4[8];
2114
2115        __le16  atio_q_inpointer;
2116        __le16  atio_q_length;
2117        __le64   atio_q_address __packed;
2118
2119        __le16  interrupt_delay_timer;          /* 100us increments. */
2120        __le16  login_timeout;
2121
2122        /*
2123         * BIT 0-3 = Reserved
2124         * BIT 4  = Enable Target Mode
2125         * BIT 5  = Disable Initiator Mode
2126         * BIT 6  = Reserved
2127         * BIT 7  = Reserved
2128         *
2129         * BIT 8-13 = Reserved
2130         * BIT 14 = Node Name Option
2131         * BIT 15-31 = Reserved
2132         */
2133        __le32  firmware_options_1;
2134
2135        /*
2136         * BIT 0  = Operation Mode bit 0
2137         * BIT 1  = Operation Mode bit 1
2138         * BIT 2  = Operation Mode bit 2
2139         * BIT 3  = Operation Mode bit 3
2140         * BIT 4-7 = Reserved
2141         *
2142         * BIT 8  = Enable Class 2
2143         * BIT 9  = Enable ACK0
2144         * BIT 10 = Reserved
2145         * BIT 11 = Enable FC-SP Security
2146         * BIT 12 = FC Tape Enable
2147         * BIT 13 = Reserved
2148         * BIT 14 = Enable Target PRLI Control
2149         * BIT 15-31 = Reserved
2150         */
2151        __le32  firmware_options_2;
2152
2153        /*
2154         * BIT 0-3 = Reserved
2155         * BIT 4  = FCP RSP Payload bit 0
2156         * BIT 5  = FCP RSP Payload bit 1
2157         * BIT 6  = Enable Receive Out-of-Order data frame handling
2158         * BIT 7  = Reserved
2159         *
2160         * BIT 8  = Reserved
2161         * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
2162         * BIT 10-16 = Reserved
2163         * BIT 17 = Enable multiple FCFs
2164         * BIT 18-20 = MAC addressing mode
2165         * BIT 21-25 = Ethernet data rate
2166         * BIT 26 = Enable ethernet header rx IOCB for ATIO q
2167         * BIT 27 = Enable ethernet header rx IOCB for response q
2168         * BIT 28 = SPMA selection bit 0
2169         * BIT 28 = SPMA selection bit 1
2170         * BIT 30-31 = Reserved
2171         */
2172        __le32  firmware_options_3;
2173
2174        uint8_t  reserved_5[8];
2175
2176        uint8_t enode_mac[6];
2177
2178        uint8_t reserved_6[10];
2179};
2180
2181struct mid_init_cb_81xx {
2182        struct init_cb_81xx init_cb;
2183
2184        uint16_t count;
2185        uint16_t options;
2186
2187        struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
2188};
2189
2190struct ex_init_cb_81xx {
2191        uint16_t ex_version;
2192        uint8_t prio_fcf_matching_flags;
2193        uint8_t reserved_1[3];
2194        uint16_t pri_fcf_vlan_id;
2195        uint8_t pri_fcf_fabric_name[8];
2196        uint16_t reserved_2[7];
2197        uint8_t spma_mac_addr[6];
2198        uint16_t reserved_3[14];
2199};
2200
2201#define FARX_ACCESS_FLASH_CONF_81XX     0x7FFD0000
2202#define FARX_ACCESS_FLASH_DATA_81XX     0x7F800000
2203#define FARX_ACCESS_FLASH_CONF_28XX     0x7FFD0000
2204#define FARX_ACCESS_FLASH_DATA_28XX     0x7F7D0000
2205
2206/* FCP priority config defines *************************************/
2207/* operations */
2208#define QLFC_FCP_PRIO_DISABLE           0x0
2209#define QLFC_FCP_PRIO_ENABLE            0x1
2210#define QLFC_FCP_PRIO_GET_CONFIG        0x2
2211#define QLFC_FCP_PRIO_SET_CONFIG        0x3
2212
2213struct qla_fcp_prio_entry {
2214        uint16_t flags;         /* Describes parameter(s) in FCP        */
2215        /* priority entry that are valid        */
2216#define FCP_PRIO_ENTRY_VALID            0x1
2217#define FCP_PRIO_ENTRY_TAG_VALID        0x2
2218#define FCP_PRIO_ENTRY_SPID_VALID       0x4
2219#define FCP_PRIO_ENTRY_DPID_VALID       0x8
2220#define FCP_PRIO_ENTRY_LUNB_VALID       0x10
2221#define FCP_PRIO_ENTRY_LUNE_VALID       0x20
2222#define FCP_PRIO_ENTRY_SWWN_VALID       0x40
2223#define FCP_PRIO_ENTRY_DWWN_VALID       0x80
2224        uint8_t  tag;           /* Priority value                   */
2225        uint8_t  reserved;      /* Reserved for future use          */
2226        uint32_t src_pid;       /* Src port id. high order byte     */
2227                                /* unused; -1 (wild card)           */
2228        uint32_t dst_pid;       /* Src port id. high order byte     */
2229        /* unused; -1 (wild card)           */
2230        uint16_t lun_beg;       /* 1st lun num of lun range.        */
2231                                /* -1 (wild card)                   */
2232        uint16_t lun_end;       /* 2nd lun num of lun range.        */
2233                                /* -1 (wild card)                   */
2234        uint8_t  src_wwpn[8];   /* Source WWPN: -1 (wild card)      */
2235        uint8_t  dst_wwpn[8];   /* Destination WWPN: -1 (wild card) */
2236};
2237
2238struct qla_fcp_prio_cfg {
2239        uint8_t  signature[4];  /* "HQOS" signature of config data  */
2240        uint16_t version;       /* 1: Initial version               */
2241        uint16_t length;        /* config data size in num bytes    */
2242        uint16_t checksum;      /* config data bytes checksum       */
2243        uint16_t num_entries;   /* Number of entries                */
2244        uint16_t size_of_entry; /* Size of each entry in num bytes  */
2245        uint8_t  attributes;    /* enable/disable, persistence      */
2246#define FCP_PRIO_ATTR_DISABLE   0x0
2247#define FCP_PRIO_ATTR_ENABLE    0x1
2248#define FCP_PRIO_ATTR_PERSIST   0x2
2249        uint8_t  reserved;      /* Reserved for future use          */
2250#define FCP_PRIO_CFG_HDR_SIZE   offsetof(struct qla_fcp_prio_cfg, entry)
2251        struct qla_fcp_prio_entry entry[1023]; /* fcp priority entries  */
2252        uint8_t  reserved2[16];
2253};
2254
2255#define FCP_PRIO_CFG_SIZE       (32*1024) /* fcp prio data per port*/
2256
2257/* 25XX Support ****************************************************/
2258#define FA_FCP_PRIO0_ADDR_25    0x3C000
2259#define FA_FCP_PRIO1_ADDR_25    0x3E000
2260
2261/* 81XX Flash locations -- occupies second 2MB region. */
2262#define FA_BOOT_CODE_ADDR_81    0x80000
2263#define FA_RISC_CODE_ADDR_81    0xA0000
2264#define FA_FW_AREA_ADDR_81      0xC0000
2265#define FA_VPD_NVRAM_ADDR_81    0xD0000
2266#define FA_VPD0_ADDR_81         0xD0000
2267#define FA_VPD1_ADDR_81         0xD0400
2268#define FA_NVRAM0_ADDR_81       0xD0080
2269#define FA_NVRAM1_ADDR_81       0xD0180
2270#define FA_FEATURE_ADDR_81      0xD4000
2271#define FA_FLASH_DESCR_ADDR_81  0xD8000
2272#define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2273#define FA_HW_EVENT0_ADDR_81    0xDC000
2274#define FA_HW_EVENT1_ADDR_81    0xDC400
2275#define FA_NPIV_CONF0_ADDR_81   0xD1000
2276#define FA_NPIV_CONF1_ADDR_81   0xD2000
2277
2278/* 83XX Flash locations -- occupies second 8MB region. */
2279#define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
2280#define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
2281
2282#define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196
2283
2284#endif
2285