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11#ifndef _UFS_H
12#define _UFS_H
13
14#include <linux/mutex.h>
15#include <linux/types.h>
16#include <uapi/scsi/scsi_bsg_ufs.h>
17
18#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
19#define QUERY_DESC_MAX_SIZE 255
20#define QUERY_DESC_MIN_SIZE 2
21#define QUERY_DESC_HDR_SIZE 2
22#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
23 (sizeof(struct utp_upiu_header)))
24#define UFS_SENSE_SIZE 18
25
26#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
27 cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
28 (byte1 << 8) | (byte0))
29
30
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32
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35
36
37
38#define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
39#define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
40#define UFS_UPIU_WLUN_ID (1 << 7)
41#define UFS_RPMB_UNIT 0xC4
42
43
44#define UFS_UPIU_MAX_WB_LUN_ID 8
45
46
47enum {
48 UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
49 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
50 UFS_UPIU_BOOT_WLUN = 0xB0,
51 UFS_UPIU_RPMB_WLUN = 0xC4,
52};
53
54
55
56
57
58
59enum {
60 UFS_ABORT_TASK = 0x01,
61 UFS_ABORT_TASK_SET = 0x02,
62 UFS_CLEAR_TASK_SET = 0x04,
63 UFS_LOGICAL_RESET = 0x08,
64 UFS_QUERY_TASK = 0x80,
65 UFS_QUERY_TASK_SET = 0x81,
66};
67
68
69enum {
70 UPIU_TRANSACTION_NOP_OUT = 0x00,
71 UPIU_TRANSACTION_COMMAND = 0x01,
72 UPIU_TRANSACTION_DATA_OUT = 0x02,
73 UPIU_TRANSACTION_TASK_REQ = 0x04,
74 UPIU_TRANSACTION_QUERY_REQ = 0x16,
75};
76
77
78enum {
79 UPIU_TRANSACTION_NOP_IN = 0x20,
80 UPIU_TRANSACTION_RESPONSE = 0x21,
81 UPIU_TRANSACTION_DATA_IN = 0x22,
82 UPIU_TRANSACTION_TASK_RSP = 0x24,
83 UPIU_TRANSACTION_READY_XFER = 0x31,
84 UPIU_TRANSACTION_QUERY_RSP = 0x36,
85 UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
86};
87
88
89enum {
90 UPIU_CMD_FLAGS_NONE = 0x00,
91 UPIU_CMD_FLAGS_WRITE = 0x20,
92 UPIU_CMD_FLAGS_READ = 0x40,
93};
94
95
96enum {
97 UPIU_TASK_ATTR_SIMPLE = 0x00,
98 UPIU_TASK_ATTR_ORDERED = 0x01,
99 UPIU_TASK_ATTR_HEADQ = 0x02,
100 UPIU_TASK_ATTR_ACA = 0x03,
101};
102
103
104enum {
105 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
106 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
107};
108
109
110enum flag_idn {
111 QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
112 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
113 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
114 QUERY_FLAG_IDN_BKOPS_EN = 0x04,
115 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
116 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
117 QUERY_FLAG_IDN_RESERVED2 = 0x07,
118 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
119 QUERY_FLAG_IDN_BUSY_RTC = 0x09,
120 QUERY_FLAG_IDN_RESERVED3 = 0x0A,
121 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
122 QUERY_FLAG_IDN_WB_EN = 0x0E,
123 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
124 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
125 QUERY_FLAG_IDN_HPB_RESET = 0x11,
126 QUERY_FLAG_IDN_HPB_EN = 0x12,
127};
128
129
130enum attr_idn {
131 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
132 QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
133 QUERY_ATTR_IDN_POWER_MODE = 0x02,
134 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
135 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
136 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
137 QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
138 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
139 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
140 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
141 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
142 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
143 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
144 QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
145 QUERY_ATTR_IDN_EE_STATUS = 0x0E,
146 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
147 QUERY_ATTR_IDN_CNTX_CONF = 0x10,
148 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
149 QUERY_ATTR_IDN_RESERVED2 = 0x12,
150 QUERY_ATTR_IDN_RESERVED3 = 0x13,
151 QUERY_ATTR_IDN_FFU_STATUS = 0x14,
152 QUERY_ATTR_IDN_PSA_STATE = 0x15,
153 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
154 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
155 QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
156 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
157 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
158 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
159};
160
161
162enum desc_idn {
163 QUERY_DESC_IDN_DEVICE = 0x0,
164 QUERY_DESC_IDN_CONFIGURATION = 0x1,
165 QUERY_DESC_IDN_UNIT = 0x2,
166 QUERY_DESC_IDN_RFU_0 = 0x3,
167 QUERY_DESC_IDN_INTERCONNECT = 0x4,
168 QUERY_DESC_IDN_STRING = 0x5,
169 QUERY_DESC_IDN_RFU_1 = 0x6,
170 QUERY_DESC_IDN_GEOMETRY = 0x7,
171 QUERY_DESC_IDN_POWER = 0x8,
172 QUERY_DESC_IDN_HEALTH = 0x9,
173 QUERY_DESC_IDN_MAX,
174};
175
176enum desc_header_offset {
177 QUERY_DESC_LENGTH_OFFSET = 0x00,
178 QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
179};
180
181
182enum unit_desc_param {
183 UNIT_DESC_PARAM_LEN = 0x0,
184 UNIT_DESC_PARAM_TYPE = 0x1,
185 UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
186 UNIT_DESC_PARAM_LU_ENABLE = 0x3,
187 UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
188 UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
189 UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
190 UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
191 UNIT_DESC_PARAM_MEM_TYPE = 0x8,
192 UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
193 UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
194 UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
195 UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
196 UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
197 UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
198 UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
199 UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
200 UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
201 UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
202 UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
203 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
204};
205
206
207enum device_desc_param {
208 DEVICE_DESC_PARAM_LEN = 0x0,
209 DEVICE_DESC_PARAM_TYPE = 0x1,
210 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
211 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
212 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
213 DEVICE_DESC_PARAM_PRTCL = 0x5,
214 DEVICE_DESC_PARAM_NUM_LU = 0x6,
215 DEVICE_DESC_PARAM_NUM_WLU = 0x7,
216 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
217 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
218 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
219 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
220 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
221 DEVICE_DESC_PARAM_SEC_LU = 0xD,
222 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
223 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
224 DEVICE_DESC_PARAM_SPEC_VER = 0x10,
225 DEVICE_DESC_PARAM_MANF_DATE = 0x12,
226 DEVICE_DESC_PARAM_MANF_NAME = 0x14,
227 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
228 DEVICE_DESC_PARAM_SN = 0x16,
229 DEVICE_DESC_PARAM_OEM_ID = 0x17,
230 DEVICE_DESC_PARAM_MANF_ID = 0x18,
231 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
232 DEVICE_DESC_PARAM_UD_LEN = 0x1B,
233 DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
234 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
235 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
236 DEVICE_DESC_PARAM_FFU_TMT = 0x20,
237 DEVICE_DESC_PARAM_Q_DPTH = 0x21,
238 DEVICE_DESC_PARAM_DEV_VER = 0x22,
239 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
240 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
241 DEVICE_DESC_PARAM_PSA_TMT = 0x29,
242 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
243 DEVICE_DESC_PARAM_HPB_VER = 0x40,
244 DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
245 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
246 DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
247 DEVICE_DESC_PARAM_WB_TYPE = 0x54,
248 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
249};
250
251
252enum interconnect_desc_param {
253 INTERCONNECT_DESC_PARAM_LEN = 0x0,
254 INTERCONNECT_DESC_PARAM_TYPE = 0x1,
255 INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
256 INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
257};
258
259
260enum geometry_desc_param {
261 GEOMETRY_DESC_PARAM_LEN = 0x0,
262 GEOMETRY_DESC_PARAM_TYPE = 0x1,
263 GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
264 GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
265 GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
266 GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
267 GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
268 GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
269 GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
270 GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
271 GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
272 GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
273 GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
274 GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
275 GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
276 GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
277 GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
278 GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
279 GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
280 GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
281 GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
282 GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
283 GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
284 GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
285 GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
286 GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
287 GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
288 GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
289 GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
290 GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
291 GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
292 GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
293 GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
294 GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
295 GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
296 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
297 GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
298 GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
299 GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
300 GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
301 GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
302};
303
304
305enum health_desc_param {
306 HEALTH_DESC_PARAM_LEN = 0x0,
307 HEALTH_DESC_PARAM_TYPE = 0x1,
308 HEALTH_DESC_PARAM_EOL_INFO = 0x2,
309 HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
310 HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
311};
312
313
314enum {
315 WB_BUF_MODE_LU_DEDICATED = 0x0,
316 WB_BUF_MODE_SHARED = 0x1,
317};
318
319
320
321
322
323
324
325enum ufs_lu_wp_type {
326 UFS_LU_NO_WP = 0x00,
327 UFS_LU_POWER_ON_WP = 0x01,
328 UFS_LU_PERM_WP = 0x02,
329};
330
331
332enum {
333 UFSHCD_NANO_AMP = 0,
334 UFSHCD_MICRO_AMP = 1,
335 UFSHCD_MILI_AMP = 2,
336 UFSHCD_AMP = 3,
337};
338
339
340enum {
341 UFS_DEV_HPB_SUPPORT = BIT(7),
342 UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
343};
344#define UFS_DEV_HPB_SUPPORT_VERSION 0x310
345
346#define POWER_DESC_MAX_ACTV_ICC_LVLS 16
347
348
349#define ATTR_ICC_LVL_UNIT_OFFSET 14
350#define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
351#define ATTR_ICC_LVL_VALUE_MASK 0x3FF
352
353
354enum power_desc_param_offset {
355 PWR_DESC_LEN = 0x0,
356 PWR_DESC_TYPE = 0x1,
357 PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
358 PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
359 PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
360};
361
362
363enum {
364 MASK_EE_STATUS = 0xFFFF,
365 MASK_EE_DYNCAP_EVENT = BIT(0),
366 MASK_EE_SYSPOOL_EVENT = BIT(1),
367 MASK_EE_URGENT_BKOPS = BIT(2),
368 MASK_EE_TOO_HIGH_TEMP = BIT(3),
369 MASK_EE_TOO_LOW_TEMP = BIT(4),
370 MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
371 MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
372};
373
374
375enum bkops_status {
376 BKOPS_STATUS_NO_OP = 0x0,
377 BKOPS_STATUS_NON_CRITICAL = 0x1,
378 BKOPS_STATUS_PERF_IMPACT = 0x2,
379 BKOPS_STATUS_CRITICAL = 0x3,
380 BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
381};
382
383
384enum query_opcode {
385 UPIU_QUERY_OPCODE_NOP = 0x0,
386 UPIU_QUERY_OPCODE_READ_DESC = 0x1,
387 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
388 UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
389 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
390 UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
391 UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
392 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
393 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
394};
395
396
397enum ufs_ref_clk_freq {
398 REF_CLK_FREQ_19_2_MHZ = 0,
399 REF_CLK_FREQ_26_MHZ = 1,
400 REF_CLK_FREQ_38_4_MHZ = 2,
401 REF_CLK_FREQ_52_MHZ = 3,
402 REF_CLK_FREQ_INVAL = -1,
403};
404
405struct ufs_ref_clk {
406 unsigned long freq_hz;
407 enum ufs_ref_clk_freq val;
408};
409
410
411enum {
412 QUERY_RESULT_SUCCESS = 0x00,
413 QUERY_RESULT_NOT_READABLE = 0xF6,
414 QUERY_RESULT_NOT_WRITEABLE = 0xF7,
415 QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
416 QUERY_RESULT_INVALID_LENGTH = 0xF9,
417 QUERY_RESULT_INVALID_VALUE = 0xFA,
418 QUERY_RESULT_INVALID_SELECTOR = 0xFB,
419 QUERY_RESULT_INVALID_INDEX = 0xFC,
420 QUERY_RESULT_INVALID_IDN = 0xFD,
421 QUERY_RESULT_INVALID_OPCODE = 0xFE,
422 QUERY_RESULT_GENERAL_FAILURE = 0xFF,
423};
424
425
426enum {
427 UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
428 UPIU_COMMAND_SET_TYPE_UFS = 0x1,
429 UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
430};
431
432
433#define UPIU_COMMAND_TYPE_OFFSET 28
434
435
436#define UPIU_RSP_CODE_OFFSET 8
437
438enum {
439 MASK_SCSI_STATUS = 0xFF,
440 MASK_TASK_RESPONSE = 0xFF00,
441 MASK_RSP_UPIU_RESULT = 0xFFFF,
442 MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
443 MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
444 MASK_RSP_EXCEPTION_EVENT = 0x10000,
445 MASK_TM_SERVICE_RESP = 0xFF,
446 MASK_TM_FUNC = 0xFF,
447};
448
449
450enum {
451 UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
452 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
453 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
454 UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
455 UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
456};
457
458
459enum ufs_dev_pwr_mode {
460 UFS_ACTIVE_PWR_MODE = 1,
461 UFS_SLEEP_PWR_MODE = 2,
462 UFS_POWERDOWN_PWR_MODE = 3,
463 UFS_DEEPSLEEP_PWR_MODE = 4,
464};
465
466#define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
467
468
469
470
471
472
473
474
475struct utp_cmd_rsp {
476 __be32 residual_transfer_count;
477 __be32 reserved[4];
478 __be16 sense_data_len;
479 u8 sense_data[UFS_SENSE_SIZE];
480};
481
482struct ufshpb_active_field {
483 __be16 active_rgn;
484 __be16 active_srgn;
485};
486#define HPB_ACT_FIELD_SIZE 4
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502struct utp_hpb_rsp {
503 __be32 residual_transfer_count;
504 __be32 reserved1[4];
505 __be16 sense_data_len;
506 u8 desc_type;
507 u8 additional_len;
508 u8 hpb_op;
509 u8 lun;
510 u8 active_rgn_cnt;
511 u8 inactive_rgn_cnt;
512 struct ufshpb_active_field hpb_active_field[2];
513 __be16 hpb_inactive_field[2];
514};
515#define UTP_HPB_RSP_SIZE 40
516
517
518
519
520
521
522
523struct utp_upiu_rsp {
524 struct utp_upiu_header header;
525 union {
526 struct utp_cmd_rsp sr;
527 struct utp_hpb_rsp hr;
528 struct utp_upiu_query qr;
529 };
530};
531
532
533
534
535
536
537struct ufs_query_req {
538 u8 query_func;
539 struct utp_upiu_query upiu_req;
540};
541
542
543
544
545
546
547struct ufs_query_res {
548 u8 response;
549 struct utp_upiu_query upiu_res;
550};
551
552#define UFS_VREG_VCC_MIN_UV 2700000
553#define UFS_VREG_VCC_MAX_UV 3600000
554#define UFS_VREG_VCC_1P8_MIN_UV 1700000
555#define UFS_VREG_VCC_1P8_MAX_UV 1950000
556#define UFS_VREG_VCCQ_MIN_UV 1140000
557#define UFS_VREG_VCCQ_MAX_UV 1260000
558#define UFS_VREG_VCCQ2_MIN_UV 1700000
559#define UFS_VREG_VCCQ2_MAX_UV 1950000
560
561
562
563
564
565#define UFS_VREG_LPM_LOAD_UA 1000
566
567struct ufs_vreg {
568 struct regulator *reg;
569 const char *name;
570 bool always_on;
571 bool enabled;
572 int min_uV;
573 int max_uV;
574 int max_uA;
575};
576
577struct ufs_vreg_info {
578 struct ufs_vreg *vcc;
579 struct ufs_vreg *vccq;
580 struct ufs_vreg *vccq2;
581 struct ufs_vreg *vdd_hba;
582};
583
584struct ufs_dev_info {
585 bool f_power_on_wp_en;
586
587 bool is_lu_power_on_wp;
588
589 u8 max_lu_supported;
590 u16 wmanufacturerid;
591
592 u8 *model;
593 u16 wspecversion;
594 u32 clk_gating_wait_us;
595
596
597 bool hpb_enabled;
598
599
600 bool wb_enabled;
601 bool wb_buf_flush_enabled;
602 u8 wb_dedicated_lu;
603 u8 wb_buffer_type;
604
605 bool b_rpm_dev_flush_capable;
606 u8 b_presrv_uspc_en;
607};
608
609
610
611
612enum ufs_trace_str_t {
613 UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
614 UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
615 UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
616};
617
618
619
620
621
622enum ufs_trace_tsf_t {
623 UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
624};
625
626
627
628
629
630
631
632static inline bool ufs_is_valid_unit_desc_lun(struct ufs_dev_info *dev_info,
633 u8 lun, u8 param_offset)
634{
635 if (!dev_info || !dev_info->max_lu_supported) {
636 pr_err("Max General LU supported by UFS isn't initialized\n");
637 return false;
638 }
639
640 if (param_offset == UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS)
641 return lun < UFS_UPIU_MAX_WB_LUN_ID;
642 return lun == UFS_UPIU_RPMB_WLUN || (lun < dev_info->max_lu_supported);
643}
644
645#endif
646