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12#include <linux/async.h>
13#include <linux/devfreq.h>
14#include <linux/nls.h>
15#include <linux/of.h>
16#include <linux/bitfield.h>
17#include <linux/blk-pm.h>
18#include <linux/blkdev.h>
19#include <scsi/scsi_driver.h>
20#include "ufshcd.h"
21#include "ufs_quirks.h"
22#include "unipro.h"
23#include "ufs-sysfs.h"
24#include "ufs-debugfs.h"
25#include "ufs-fault-injection.h"
26#include "ufs_bsg.h"
27#include "ufshcd-crypto.h"
28#include "ufshpb.h"
29#include <asm/unaligned.h>
30
31#define CREATE_TRACE_POINTS
32#include <trace/events/ufs.h>
33
34#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
35 UTP_TASK_REQ_COMPL |\
36 UFSHCD_ERROR_MASK)
37
38#define UIC_CMD_TIMEOUT 500
39
40
41#define NOP_OUT_RETRIES 10
42
43#define NOP_OUT_TIMEOUT 50
44
45
46#define QUERY_REQ_RETRIES 3
47
48#define QUERY_REQ_TIMEOUT 1500
49
50
51#define TM_CMD_TIMEOUT 100
52
53
54#define UFS_UIC_COMMAND_RETRIES 3
55
56
57#define DME_LINKSTARTUP_RETRIES 3
58
59
60#define UIC_HIBERN8_ENTER_RETRIES 3
61
62
63#define MAX_HOST_RESET_RETRIES 5
64
65
66#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
67
68
69#define INT_AGGR_DEF_TO 0x02
70
71
72#define RPM_AUTOSUSPEND_DELAY_MS 2000
73
74
75#define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
76
77
78#define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF
79
80
81#define FDEVICEINIT_COMPL_TIMEOUT 1500
82
83#define wlun_dev_to_hba(dv) shost_priv(to_scsi_device(dv)->host)
84
85#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
86 ({ \
87 int _ret; \
88 if (_on) \
89 _ret = ufshcd_enable_vreg(_dev, _vreg); \
90 else \
91 _ret = ufshcd_disable_vreg(_dev, _vreg); \
92 _ret; \
93 })
94
95#define ufshcd_hex_dump(prefix_str, buf, len) do { \
96 size_t __len = (len); \
97 print_hex_dump(KERN_ERR, prefix_str, \
98 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
99 16, 4, buf, __len, false); \
100} while (0)
101
102int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
103 const char *prefix)
104{
105 u32 *regs;
106 size_t pos;
107
108 if (offset % 4 != 0 || len % 4 != 0)
109 return -EINVAL;
110
111 regs = kzalloc(len, GFP_ATOMIC);
112 if (!regs)
113 return -ENOMEM;
114
115 for (pos = 0; pos < len; pos += 4)
116 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
117
118 ufshcd_hex_dump(prefix, regs, len);
119 kfree(regs);
120
121 return 0;
122}
123EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
124
125enum {
126 UFSHCD_MAX_CHANNEL = 0,
127 UFSHCD_MAX_ID = 1,
128 UFSHCD_CMD_PER_LUN = 32,
129 UFSHCD_CAN_QUEUE = 32,
130};
131
132
133enum {
134 UFSHCD_EH_IN_PROGRESS = (1 << 0),
135};
136
137
138enum {
139 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0),
140 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1),
141 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2),
142 UFSHCD_UIC_NL_ERROR = (1 << 3),
143 UFSHCD_UIC_TL_ERROR = (1 << 4),
144 UFSHCD_UIC_DME_ERROR = (1 << 5),
145 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6),
146};
147
148#define ufshcd_set_eh_in_progress(h) \
149 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
150#define ufshcd_eh_in_progress(h) \
151 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
152#define ufshcd_clear_eh_in_progress(h) \
153 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
154
155struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
156 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
157 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
158 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
159 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
160 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
161 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
162
163
164
165
166 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
167};
168
169static inline enum ufs_dev_pwr_mode
170ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
171{
172 return ufs_pm_lvl_states[lvl].dev_state;
173}
174
175static inline enum uic_link_state
176ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
177{
178 return ufs_pm_lvl_states[lvl].link_state;
179}
180
181static inline enum ufs_pm_level
182ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
183 enum uic_link_state link_state)
184{
185 enum ufs_pm_level lvl;
186
187 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
188 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
189 (ufs_pm_lvl_states[lvl].link_state == link_state))
190 return lvl;
191 }
192
193
194 return UFS_PM_LVL_0;
195}
196
197static struct ufs_dev_fix ufs_fixups[] = {
198
199 UFS_FIX(UFS_VENDOR_MICRON, UFS_ANY_MODEL,
200 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
201 UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ),
202 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
203 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
204 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
205 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
206 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
207 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
208 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" ,
209 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
210 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
211 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
212 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
213 UFS_DEVICE_QUIRK_PA_TACTIVATE),
214 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
215 UFS_DEVICE_QUIRK_PA_TACTIVATE),
216 END_FIX
217};
218
219static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
220static void ufshcd_async_scan(void *data, async_cookie_t cookie);
221static int ufshcd_reset_and_restore(struct ufs_hba *hba);
222static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
223static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
224static void ufshcd_hba_exit(struct ufs_hba *hba);
225static int ufshcd_clear_ua_wluns(struct ufs_hba *hba);
226static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
227static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
228static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
229static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
230static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
231static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
232static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
233static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
234static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
235static irqreturn_t ufshcd_intr(int irq, void *__hba);
236static int ufshcd_change_power_mode(struct ufs_hba *hba,
237 struct ufs_pa_layer_attr *pwr_mode);
238static void ufshcd_schedule_eh_work(struct ufs_hba *hba);
239static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
240static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
241static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
242 struct ufs_vreg *vreg);
243static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
244static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
245static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
246static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
247static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
248
249static inline void ufshcd_enable_irq(struct ufs_hba *hba)
250{
251 if (!hba->is_irq_enabled) {
252 enable_irq(hba->irq);
253 hba->is_irq_enabled = true;
254 }
255}
256
257static inline void ufshcd_disable_irq(struct ufs_hba *hba)
258{
259 if (hba->is_irq_enabled) {
260 disable_irq(hba->irq);
261 hba->is_irq_enabled = false;
262 }
263}
264
265static inline void ufshcd_wb_config(struct ufs_hba *hba)
266{
267 if (!ufshcd_is_wb_allowed(hba))
268 return;
269
270 ufshcd_wb_toggle(hba, true);
271
272 ufshcd_wb_toggle_flush_during_h8(hba, true);
273 if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
274 ufshcd_wb_toggle_flush(hba, true);
275}
276
277static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
278{
279 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
280 scsi_unblock_requests(hba->host);
281}
282
283static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
284{
285 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
286 scsi_block_requests(hba->host);
287}
288
289static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
290 enum ufs_trace_str_t str_t)
291{
292 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
293 struct utp_upiu_header *header;
294
295 if (!trace_ufshcd_upiu_enabled())
296 return;
297
298 if (str_t == UFS_CMD_SEND)
299 header = &rq->header;
300 else
301 header = &hba->lrb[tag].ucd_rsp_ptr->header;
302
303 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
304 UFS_TSF_CDB);
305}
306
307static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
308 enum ufs_trace_str_t str_t,
309 struct utp_upiu_req *rq_rsp)
310{
311 if (!trace_ufshcd_upiu_enabled())
312 return;
313
314 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
315 &rq_rsp->qr, UFS_TSF_OSF);
316}
317
318static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
319 enum ufs_trace_str_t str_t)
320{
321 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
322
323 if (!trace_ufshcd_upiu_enabled())
324 return;
325
326 if (str_t == UFS_TM_SEND)
327 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
328 &descp->upiu_req.req_header,
329 &descp->upiu_req.input_param1,
330 UFS_TSF_TM_INPUT);
331 else
332 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
333 &descp->upiu_rsp.rsp_header,
334 &descp->upiu_rsp.output_param1,
335 UFS_TSF_TM_OUTPUT);
336}
337
338static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
339 struct uic_command *ucmd,
340 enum ufs_trace_str_t str_t)
341{
342 u32 cmd;
343
344 if (!trace_ufshcd_uic_command_enabled())
345 return;
346
347 if (str_t == UFS_CMD_SEND)
348 cmd = ucmd->command;
349 else
350 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
351
352 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
353 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
354 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
355 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
356}
357
358static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
359 enum ufs_trace_str_t str_t)
360{
361 u64 lba;
362 u8 opcode = 0, group_id = 0;
363 u32 intr, doorbell;
364 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
365 struct scsi_cmnd *cmd = lrbp->cmd;
366 struct request *rq = scsi_cmd_to_rq(cmd);
367 int transfer_len = -1;
368
369 if (!cmd)
370 return;
371
372
373 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
374 if (!trace_ufshcd_command_enabled())
375 return;
376
377 opcode = cmd->cmnd[0];
378 lba = scsi_get_lba(cmd);
379
380 if (opcode == READ_10 || opcode == WRITE_10) {
381
382
383
384 transfer_len =
385 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
386 if (opcode == WRITE_10)
387 group_id = lrbp->cmd->cmnd[6];
388 } else if (opcode == UNMAP) {
389
390
391
392 transfer_len = blk_rq_bytes(rq);
393 }
394
395 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
396 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
397 trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
398 doorbell, transfer_len, intr, lba, opcode, group_id);
399}
400
401static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
402{
403 struct ufs_clk_info *clki;
404 struct list_head *head = &hba->clk_list_head;
405
406 if (list_empty(head))
407 return;
408
409 list_for_each_entry(clki, head, list) {
410 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
411 clki->max_freq)
412 dev_err(hba->dev, "clk: %s, rate: %u\n",
413 clki->name, clki->curr_freq);
414 }
415}
416
417static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
418 char *err_name)
419{
420 int i;
421 bool found = false;
422 struct ufs_event_hist *e;
423
424 if (id >= UFS_EVT_CNT)
425 return;
426
427 e = &hba->ufs_stats.event[id];
428
429 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
430 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
431
432 if (e->tstamp[p] == 0)
433 continue;
434 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
435 e->val[p], ktime_to_us(e->tstamp[p]));
436 found = true;
437 }
438
439 if (!found)
440 dev_err(hba->dev, "No record of %s\n", err_name);
441 else
442 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
443}
444
445static void ufshcd_print_evt_hist(struct ufs_hba *hba)
446{
447 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
448
449 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
450 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
451 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
452 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
453 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
454 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
455 "auto_hibern8_err");
456 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
457 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
458 "link_startup_fail");
459 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
460 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
461 "suspend_fail");
462 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
463 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
464 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
465
466 ufshcd_vops_dbg_register_dump(hba);
467}
468
469static
470void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
471{
472 struct ufshcd_lrb *lrbp;
473 int prdt_length;
474 int tag;
475
476 for_each_set_bit(tag, &bitmap, hba->nutrs) {
477 lrbp = &hba->lrb[tag];
478
479 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
480 tag, ktime_to_us(lrbp->issue_time_stamp));
481 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
482 tag, ktime_to_us(lrbp->compl_time_stamp));
483 dev_err(hba->dev,
484 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
485 tag, (u64)lrbp->utrd_dma_addr);
486
487 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
488 sizeof(struct utp_transfer_req_desc));
489 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
490 (u64)lrbp->ucd_req_dma_addr);
491 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
492 sizeof(struct utp_upiu_req));
493 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
494 (u64)lrbp->ucd_rsp_dma_addr);
495 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
496 sizeof(struct utp_upiu_rsp));
497
498 prdt_length = le16_to_cpu(
499 lrbp->utr_descriptor_ptr->prd_table_length);
500 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
501 prdt_length /= sizeof(struct ufshcd_sg_entry);
502
503 dev_err(hba->dev,
504 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
505 tag, prdt_length,
506 (u64)lrbp->ucd_prdt_dma_addr);
507
508 if (pr_prdt)
509 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
510 sizeof(struct ufshcd_sg_entry) * prdt_length);
511 }
512}
513
514static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
515{
516 int tag;
517
518 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
519 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
520
521 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
522 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
523 }
524}
525
526static void ufshcd_print_host_state(struct ufs_hba *hba)
527{
528 struct scsi_device *sdev_ufs = hba->sdev_ufs_device;
529
530 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
531 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
532 hba->outstanding_reqs, hba->outstanding_tasks);
533 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
534 hba->saved_err, hba->saved_uic_err);
535 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
536 hba->curr_dev_pwr_mode, hba->uic_link_state);
537 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
538 hba->pm_op_in_progress, hba->is_sys_suspended);
539 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
540 hba->auto_bkops_enabled, hba->host->host_self_blocked);
541 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
542 dev_err(hba->dev,
543 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
544 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
545 hba->ufs_stats.hibern8_exit_cnt);
546 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
547 ktime_to_us(hba->ufs_stats.last_intr_ts),
548 hba->ufs_stats.last_intr_status);
549 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
550 hba->eh_flags, hba->req_abort_count);
551 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
552 hba->ufs_version, hba->capabilities, hba->caps);
553 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
554 hba->dev_quirks);
555 if (sdev_ufs)
556 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
557 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
558
559 ufshcd_print_clk_freqs(hba);
560}
561
562
563
564
565
566
567static void ufshcd_print_pwr_info(struct ufs_hba *hba)
568{
569 static const char * const names[] = {
570 "INVALID MODE",
571 "FAST MODE",
572 "SLOW_MODE",
573 "INVALID MODE",
574 "FASTAUTO_MODE",
575 "SLOWAUTO_MODE",
576 "INVALID MODE",
577 };
578
579 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
580 __func__,
581 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
582 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
583 names[hba->pwr_info.pwr_rx],
584 names[hba->pwr_info.pwr_tx],
585 hba->pwr_info.hs_rate);
586}
587
588static void ufshcd_device_reset(struct ufs_hba *hba)
589{
590 int err;
591
592 err = ufshcd_vops_device_reset(hba);
593
594 if (!err) {
595 ufshcd_set_ufs_dev_active(hba);
596 if (ufshcd_is_wb_allowed(hba)) {
597 hba->dev_info.wb_enabled = false;
598 hba->dev_info.wb_buf_flush_enabled = false;
599 }
600 }
601 if (err != -EOPNOTSUPP)
602 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
603}
604
605void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
606{
607 if (!us)
608 return;
609
610 if (us < 10)
611 udelay(us);
612 else
613 usleep_range(us, us + tolerance);
614}
615EXPORT_SYMBOL_GPL(ufshcd_delay_us);
616
617
618
619
620
621
622
623
624
625
626
627
628
629int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
630 u32 val, unsigned long interval_us,
631 unsigned long timeout_ms)
632{
633 int err = 0;
634 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
635
636
637 val = val & mask;
638
639 while ((ufshcd_readl(hba, reg) & mask) != val) {
640 usleep_range(interval_us, interval_us + 50);
641 if (time_after(jiffies, timeout)) {
642 if ((ufshcd_readl(hba, reg) & mask) != val)
643 err = -ETIMEDOUT;
644 break;
645 }
646 }
647
648 return err;
649}
650
651
652
653
654
655
656
657static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
658{
659 if (hba->ufs_version == ufshci_version(1, 0))
660 return INTERRUPT_MASK_ALL_VER_10;
661 if (hba->ufs_version <= ufshci_version(2, 0))
662 return INTERRUPT_MASK_ALL_VER_11;
663
664 return INTERRUPT_MASK_ALL_VER_21;
665}
666
667
668
669
670
671
672
673static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
674{
675 u32 ufshci_ver;
676
677 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
678 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
679 else
680 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
681
682
683
684
685
686
687 if (ufshci_ver & 0x00010000)
688 return ufshci_version(1, ufshci_ver & 0x00000100);
689
690 return ufshci_ver;
691}
692
693
694
695
696
697
698
699
700static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
701{
702 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
703 DEVICE_PRESENT) ? true : false;
704}
705
706
707
708
709
710
711
712
713static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
714{
715 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
716}
717
718
719
720
721
722
723static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
724{
725 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
726 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
727 else
728 ufshcd_writel(hba, ~(1 << pos),
729 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
730}
731
732
733
734
735
736
737static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
738{
739 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
740 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
741 else
742 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
743}
744
745
746
747
748
749
750
751static inline int ufshcd_get_lists_status(u32 reg)
752{
753 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
754}
755
756
757
758
759
760
761
762
763static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
764{
765 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
766 MASK_UIC_COMMAND_RESULT;
767}
768
769
770
771
772
773
774
775
776static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
777{
778 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
779}
780
781
782
783
784
785static inline int
786ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
787{
788 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
789}
790
791
792
793
794
795
796
797
798static inline int
799ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
800{
801 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
802}
803
804
805
806
807
808
809
810
811static inline unsigned int
812ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
813{
814 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
815 MASK_RSP_UPIU_DATA_SEG_LEN;
816}
817
818
819
820
821
822
823
824
825
826
827static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
828{
829 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
830 MASK_RSP_EXCEPTION_EVENT ? true : false;
831}
832
833
834
835
836
837static inline void
838ufshcd_reset_intr_aggr(struct ufs_hba *hba)
839{
840 ufshcd_writel(hba, INT_AGGR_ENABLE |
841 INT_AGGR_COUNTER_AND_TIMER_RESET,
842 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
843}
844
845
846
847
848
849
850
851static inline void
852ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
853{
854 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
855 INT_AGGR_COUNTER_THLD_VAL(cnt) |
856 INT_AGGR_TIMEOUT_VAL(tmout),
857 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
858}
859
860
861
862
863
864static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
865{
866 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
867}
868
869
870
871
872
873
874
875static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
876{
877 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
878 REG_UTP_TASK_REQ_LIST_RUN_STOP);
879 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
880 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
881}
882
883
884
885
886
887static inline void ufshcd_hba_start(struct ufs_hba *hba)
888{
889 u32 val = CONTROLLER_ENABLE;
890
891 if (ufshcd_crypto_enable(hba))
892 val |= CRYPTO_GENERAL_ENABLE;
893
894 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
895}
896
897
898
899
900
901
902
903static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
904{
905 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
906 ? false : true;
907}
908
909u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
910{
911
912 if (hba->ufs_version <= ufshci_version(1, 1))
913 return UFS_UNIPRO_VER_1_41;
914 else
915 return UFS_UNIPRO_VER_1_6;
916}
917EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
918
919static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
920{
921
922
923
924
925
926
927
928
929
930 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
931 return true;
932 else
933 return false;
934}
935
936
937
938
939
940
941
942
943
944static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
945{
946 int ret = 0;
947 struct ufs_clk_info *clki;
948 struct list_head *head = &hba->clk_list_head;
949
950 if (list_empty(head))
951 goto out;
952
953 list_for_each_entry(clki, head, list) {
954 if (!IS_ERR_OR_NULL(clki->clk)) {
955 if (scale_up && clki->max_freq) {
956 if (clki->curr_freq == clki->max_freq)
957 continue;
958
959 ret = clk_set_rate(clki->clk, clki->max_freq);
960 if (ret) {
961 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
962 __func__, clki->name,
963 clki->max_freq, ret);
964 break;
965 }
966 trace_ufshcd_clk_scaling(dev_name(hba->dev),
967 "scaled up", clki->name,
968 clki->curr_freq,
969 clki->max_freq);
970
971 clki->curr_freq = clki->max_freq;
972
973 } else if (!scale_up && clki->min_freq) {
974 if (clki->curr_freq == clki->min_freq)
975 continue;
976
977 ret = clk_set_rate(clki->clk, clki->min_freq);
978 if (ret) {
979 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
980 __func__, clki->name,
981 clki->min_freq, ret);
982 break;
983 }
984 trace_ufshcd_clk_scaling(dev_name(hba->dev),
985 "scaled down", clki->name,
986 clki->curr_freq,
987 clki->min_freq);
988 clki->curr_freq = clki->min_freq;
989 }
990 }
991 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
992 clki->name, clk_get_rate(clki->clk));
993 }
994
995out:
996 return ret;
997}
998
999
1000
1001
1002
1003
1004
1005
1006
1007static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1008{
1009 int ret = 0;
1010 ktime_t start = ktime_get();
1011
1012 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1013 if (ret)
1014 goto out;
1015
1016 ret = ufshcd_set_clk_freq(hba, scale_up);
1017 if (ret)
1018 goto out;
1019
1020 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1021 if (ret)
1022 ufshcd_set_clk_freq(hba, !scale_up);
1023
1024out:
1025 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1026 (scale_up ? "up" : "down"),
1027 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1028 return ret;
1029}
1030
1031
1032
1033
1034
1035
1036
1037
1038static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1039 bool scale_up)
1040{
1041 struct ufs_clk_info *clki;
1042 struct list_head *head = &hba->clk_list_head;
1043
1044 if (list_empty(head))
1045 return false;
1046
1047 list_for_each_entry(clki, head, list) {
1048 if (!IS_ERR_OR_NULL(clki->clk)) {
1049 if (scale_up && clki->max_freq) {
1050 if (clki->curr_freq == clki->max_freq)
1051 continue;
1052 return true;
1053 } else if (!scale_up && clki->min_freq) {
1054 if (clki->curr_freq == clki->min_freq)
1055 continue;
1056 return true;
1057 }
1058 }
1059 }
1060
1061 return false;
1062}
1063
1064static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1065 u64 wait_timeout_us)
1066{
1067 unsigned long flags;
1068 int ret = 0;
1069 u32 tm_doorbell;
1070 u32 tr_doorbell;
1071 bool timeout = false, do_last_check = false;
1072 ktime_t start;
1073
1074 ufshcd_hold(hba, false);
1075 spin_lock_irqsave(hba->host->host_lock, flags);
1076
1077
1078
1079
1080 start = ktime_get();
1081 do {
1082 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1083 ret = -EBUSY;
1084 goto out;
1085 }
1086
1087 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1088 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1089 if (!tm_doorbell && !tr_doorbell) {
1090 timeout = false;
1091 break;
1092 } else if (do_last_check) {
1093 break;
1094 }
1095
1096 spin_unlock_irqrestore(hba->host->host_lock, flags);
1097 schedule();
1098 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1099 wait_timeout_us) {
1100 timeout = true;
1101
1102
1103
1104
1105
1106 do_last_check = true;
1107 }
1108 spin_lock_irqsave(hba->host->host_lock, flags);
1109 } while (tm_doorbell || tr_doorbell);
1110
1111 if (timeout) {
1112 dev_err(hba->dev,
1113 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1114 __func__, tm_doorbell, tr_doorbell);
1115 ret = -EBUSY;
1116 }
1117out:
1118 spin_unlock_irqrestore(hba->host->host_lock, flags);
1119 ufshcd_release(hba);
1120 return ret;
1121}
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1133{
1134 int ret = 0;
1135 struct ufs_pa_layer_attr new_pwr_info;
1136
1137 if (scale_up) {
1138 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1139 sizeof(struct ufs_pa_layer_attr));
1140 } else {
1141 memcpy(&new_pwr_info, &hba->pwr_info,
1142 sizeof(struct ufs_pa_layer_attr));
1143
1144 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1145 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1146
1147 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1148 &hba->pwr_info,
1149 sizeof(struct ufs_pa_layer_attr));
1150
1151
1152 new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1153 new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1154 }
1155 }
1156
1157
1158 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1159 if (ret)
1160 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1161 __func__, ret,
1162 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1163 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1164
1165 return ret;
1166}
1167
1168static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1169{
1170 #define DOORBELL_CLR_TOUT_US (1000 * 1000)
1171 int ret = 0;
1172
1173
1174
1175
1176 ufshcd_scsi_block_requests(hba);
1177 down_write(&hba->clk_scaling_lock);
1178
1179 if (!hba->clk_scaling.is_allowed ||
1180 ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1181 ret = -EBUSY;
1182 up_write(&hba->clk_scaling_lock);
1183 ufshcd_scsi_unblock_requests(hba);
1184 goto out;
1185 }
1186
1187
1188 ufshcd_hold(hba, false);
1189
1190out:
1191 return ret;
1192}
1193
1194static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
1195{
1196 if (writelock)
1197 up_write(&hba->clk_scaling_lock);
1198 else
1199 up_read(&hba->clk_scaling_lock);
1200 ufshcd_scsi_unblock_requests(hba);
1201 ufshcd_release(hba);
1202}
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1214{
1215 int ret = 0;
1216 bool is_writelock = true;
1217
1218 ret = ufshcd_clock_scaling_prepare(hba);
1219 if (ret)
1220 return ret;
1221
1222
1223 if (!scale_up) {
1224 ret = ufshcd_scale_gear(hba, false);
1225 if (ret)
1226 goto out_unprepare;
1227 }
1228
1229 ret = ufshcd_scale_clks(hba, scale_up);
1230 if (ret) {
1231 if (!scale_up)
1232 ufshcd_scale_gear(hba, true);
1233 goto out_unprepare;
1234 }
1235
1236
1237 if (scale_up) {
1238 ret = ufshcd_scale_gear(hba, true);
1239 if (ret) {
1240 ufshcd_scale_clks(hba, false);
1241 goto out_unprepare;
1242 }
1243 }
1244
1245
1246 downgrade_write(&hba->clk_scaling_lock);
1247 is_writelock = false;
1248 ufshcd_wb_toggle(hba, scale_up);
1249
1250out_unprepare:
1251 ufshcd_clock_scaling_unprepare(hba, is_writelock);
1252 return ret;
1253}
1254
1255static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1256{
1257 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1258 clk_scaling.suspend_work);
1259 unsigned long irq_flags;
1260
1261 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1262 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1263 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1264 return;
1265 }
1266 hba->clk_scaling.is_suspended = true;
1267 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1268
1269 __ufshcd_suspend_clkscaling(hba);
1270}
1271
1272static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1273{
1274 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1275 clk_scaling.resume_work);
1276 unsigned long irq_flags;
1277
1278 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1279 if (!hba->clk_scaling.is_suspended) {
1280 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1281 return;
1282 }
1283 hba->clk_scaling.is_suspended = false;
1284 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1285
1286 devfreq_resume_device(hba->devfreq);
1287}
1288
1289static int ufshcd_devfreq_target(struct device *dev,
1290 unsigned long *freq, u32 flags)
1291{
1292 int ret = 0;
1293 struct ufs_hba *hba = dev_get_drvdata(dev);
1294 ktime_t start;
1295 bool scale_up, sched_clk_scaling_suspend_work = false;
1296 struct list_head *clk_list = &hba->clk_list_head;
1297 struct ufs_clk_info *clki;
1298 unsigned long irq_flags;
1299
1300 if (!ufshcd_is_clkscaling_supported(hba))
1301 return -EINVAL;
1302
1303 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1304
1305 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1306 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1307 if (ufshcd_eh_in_progress(hba)) {
1308 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1309 return 0;
1310 }
1311
1312 if (!hba->clk_scaling.active_reqs)
1313 sched_clk_scaling_suspend_work = true;
1314
1315 if (list_empty(clk_list)) {
1316 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1317 goto out;
1318 }
1319
1320
1321 scale_up = (*freq == clki->max_freq) ? true : false;
1322 if (!scale_up)
1323 *freq = clki->min_freq;
1324
1325 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1326 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1327 ret = 0;
1328 goto out;
1329 }
1330 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1331
1332 start = ktime_get();
1333 ret = ufshcd_devfreq_scale(hba, scale_up);
1334
1335 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1336 (scale_up ? "up" : "down"),
1337 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1338
1339out:
1340 if (sched_clk_scaling_suspend_work)
1341 queue_work(hba->clk_scaling.workq,
1342 &hba->clk_scaling.suspend_work);
1343
1344 return ret;
1345}
1346
1347static bool ufshcd_is_busy(struct request *req, void *priv, bool reserved)
1348{
1349 int *busy = priv;
1350
1351 WARN_ON_ONCE(reserved);
1352 (*busy)++;
1353 return false;
1354}
1355
1356
1357static bool ufshcd_any_tag_in_use(struct ufs_hba *hba)
1358{
1359 struct request_queue *q = hba->cmd_queue;
1360 int busy = 0;
1361
1362 blk_mq_tagset_busy_iter(q->tag_set, ufshcd_is_busy, &busy);
1363 return busy;
1364}
1365
1366static int ufshcd_devfreq_get_dev_status(struct device *dev,
1367 struct devfreq_dev_status *stat)
1368{
1369 struct ufs_hba *hba = dev_get_drvdata(dev);
1370 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1371 unsigned long flags;
1372 struct list_head *clk_list = &hba->clk_list_head;
1373 struct ufs_clk_info *clki;
1374 ktime_t curr_t;
1375
1376 if (!ufshcd_is_clkscaling_supported(hba))
1377 return -EINVAL;
1378
1379 memset(stat, 0, sizeof(*stat));
1380
1381 spin_lock_irqsave(hba->host->host_lock, flags);
1382 curr_t = ktime_get();
1383 if (!scaling->window_start_t)
1384 goto start_window;
1385
1386 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1387
1388
1389
1390
1391
1392 stat->current_frequency = clki->curr_freq;
1393 if (scaling->is_busy_started)
1394 scaling->tot_busy_t += ktime_us_delta(curr_t,
1395 scaling->busy_start_t);
1396
1397 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1398 stat->busy_time = scaling->tot_busy_t;
1399start_window:
1400 scaling->window_start_t = curr_t;
1401 scaling->tot_busy_t = 0;
1402
1403 if (hba->outstanding_reqs) {
1404 scaling->busy_start_t = curr_t;
1405 scaling->is_busy_started = true;
1406 } else {
1407 scaling->busy_start_t = 0;
1408 scaling->is_busy_started = false;
1409 }
1410 spin_unlock_irqrestore(hba->host->host_lock, flags);
1411 return 0;
1412}
1413
1414static int ufshcd_devfreq_init(struct ufs_hba *hba)
1415{
1416 struct list_head *clk_list = &hba->clk_list_head;
1417 struct ufs_clk_info *clki;
1418 struct devfreq *devfreq;
1419 int ret;
1420
1421
1422 if (list_empty(clk_list))
1423 return 0;
1424
1425 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1426 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1427 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1428
1429 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1430 &hba->vps->ondemand_data);
1431 devfreq = devfreq_add_device(hba->dev,
1432 &hba->vps->devfreq_profile,
1433 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1434 &hba->vps->ondemand_data);
1435 if (IS_ERR(devfreq)) {
1436 ret = PTR_ERR(devfreq);
1437 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1438
1439 dev_pm_opp_remove(hba->dev, clki->min_freq);
1440 dev_pm_opp_remove(hba->dev, clki->max_freq);
1441 return ret;
1442 }
1443
1444 hba->devfreq = devfreq;
1445
1446 return 0;
1447}
1448
1449static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1450{
1451 struct list_head *clk_list = &hba->clk_list_head;
1452 struct ufs_clk_info *clki;
1453
1454 if (!hba->devfreq)
1455 return;
1456
1457 devfreq_remove_device(hba->devfreq);
1458 hba->devfreq = NULL;
1459
1460 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1461 dev_pm_opp_remove(hba->dev, clki->min_freq);
1462 dev_pm_opp_remove(hba->dev, clki->max_freq);
1463}
1464
1465static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1466{
1467 unsigned long flags;
1468
1469 devfreq_suspend_device(hba->devfreq);
1470 spin_lock_irqsave(hba->host->host_lock, flags);
1471 hba->clk_scaling.window_start_t = 0;
1472 spin_unlock_irqrestore(hba->host->host_lock, flags);
1473}
1474
1475static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1476{
1477 unsigned long flags;
1478 bool suspend = false;
1479
1480 cancel_work_sync(&hba->clk_scaling.suspend_work);
1481 cancel_work_sync(&hba->clk_scaling.resume_work);
1482
1483 spin_lock_irqsave(hba->host->host_lock, flags);
1484 if (!hba->clk_scaling.is_suspended) {
1485 suspend = true;
1486 hba->clk_scaling.is_suspended = true;
1487 }
1488 spin_unlock_irqrestore(hba->host->host_lock, flags);
1489
1490 if (suspend)
1491 __ufshcd_suspend_clkscaling(hba);
1492}
1493
1494static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1495{
1496 unsigned long flags;
1497 bool resume = false;
1498
1499 spin_lock_irqsave(hba->host->host_lock, flags);
1500 if (hba->clk_scaling.is_suspended) {
1501 resume = true;
1502 hba->clk_scaling.is_suspended = false;
1503 }
1504 spin_unlock_irqrestore(hba->host->host_lock, flags);
1505
1506 if (resume)
1507 devfreq_resume_device(hba->devfreq);
1508}
1509
1510static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1511 struct device_attribute *attr, char *buf)
1512{
1513 struct ufs_hba *hba = dev_get_drvdata(dev);
1514
1515 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1516}
1517
1518static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1519 struct device_attribute *attr, const char *buf, size_t count)
1520{
1521 struct ufs_hba *hba = dev_get_drvdata(dev);
1522 u32 value;
1523 int err = 0;
1524
1525 if (kstrtou32(buf, 0, &value))
1526 return -EINVAL;
1527
1528 down(&hba->host_sem);
1529 if (!ufshcd_is_user_access_allowed(hba)) {
1530 err = -EBUSY;
1531 goto out;
1532 }
1533
1534 value = !!value;
1535 if (value == hba->clk_scaling.is_enabled)
1536 goto out;
1537
1538 ufshcd_rpm_get_sync(hba);
1539 ufshcd_hold(hba, false);
1540
1541 hba->clk_scaling.is_enabled = value;
1542
1543 if (value) {
1544 ufshcd_resume_clkscaling(hba);
1545 } else {
1546 ufshcd_suspend_clkscaling(hba);
1547 err = ufshcd_devfreq_scale(hba, true);
1548 if (err)
1549 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1550 __func__, err);
1551 }
1552
1553 ufshcd_release(hba);
1554 ufshcd_rpm_put_sync(hba);
1555out:
1556 up(&hba->host_sem);
1557 return err ? err : count;
1558}
1559
1560static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1561{
1562 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1563 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1564 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1565 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1566 hba->clk_scaling.enable_attr.attr.mode = 0644;
1567 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1568 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1569}
1570
1571static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1572{
1573 if (hba->clk_scaling.enable_attr.attr.name)
1574 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1575}
1576
1577static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1578{
1579 char wq_name[sizeof("ufs_clkscaling_00")];
1580
1581 if (!ufshcd_is_clkscaling_supported(hba))
1582 return;
1583
1584 if (!hba->clk_scaling.min_gear)
1585 hba->clk_scaling.min_gear = UFS_HS_G1;
1586
1587 INIT_WORK(&hba->clk_scaling.suspend_work,
1588 ufshcd_clk_scaling_suspend_work);
1589 INIT_WORK(&hba->clk_scaling.resume_work,
1590 ufshcd_clk_scaling_resume_work);
1591
1592 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1593 hba->host->host_no);
1594 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1595
1596 hba->clk_scaling.is_initialized = true;
1597}
1598
1599static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1600{
1601 if (!hba->clk_scaling.is_initialized)
1602 return;
1603
1604 ufshcd_remove_clk_scaling_sysfs(hba);
1605 destroy_workqueue(hba->clk_scaling.workq);
1606 ufshcd_devfreq_remove(hba);
1607 hba->clk_scaling.is_initialized = false;
1608}
1609
1610static void ufshcd_ungate_work(struct work_struct *work)
1611{
1612 int ret;
1613 unsigned long flags;
1614 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1615 clk_gating.ungate_work);
1616
1617 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1618
1619 spin_lock_irqsave(hba->host->host_lock, flags);
1620 if (hba->clk_gating.state == CLKS_ON) {
1621 spin_unlock_irqrestore(hba->host->host_lock, flags);
1622 goto unblock_reqs;
1623 }
1624
1625 spin_unlock_irqrestore(hba->host->host_lock, flags);
1626 ufshcd_hba_vreg_set_hpm(hba);
1627 ufshcd_setup_clocks(hba, true);
1628
1629 ufshcd_enable_irq(hba);
1630
1631
1632 if (ufshcd_can_hibern8_during_gating(hba)) {
1633
1634 hba->clk_gating.is_suspended = true;
1635 if (ufshcd_is_link_hibern8(hba)) {
1636 ret = ufshcd_uic_hibern8_exit(hba);
1637 if (ret)
1638 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1639 __func__, ret);
1640 else
1641 ufshcd_set_link_active(hba);
1642 }
1643 hba->clk_gating.is_suspended = false;
1644 }
1645unblock_reqs:
1646 ufshcd_scsi_unblock_requests(hba);
1647}
1648
1649
1650
1651
1652
1653
1654
1655int ufshcd_hold(struct ufs_hba *hba, bool async)
1656{
1657 int rc = 0;
1658 bool flush_result;
1659 unsigned long flags;
1660
1661 if (!ufshcd_is_clkgating_allowed(hba))
1662 goto out;
1663 spin_lock_irqsave(hba->host->host_lock, flags);
1664 hba->clk_gating.active_reqs++;
1665
1666start:
1667 switch (hba->clk_gating.state) {
1668 case CLKS_ON:
1669
1670
1671
1672
1673
1674
1675
1676
1677 if (ufshcd_can_hibern8_during_gating(hba) &&
1678 ufshcd_is_link_hibern8(hba)) {
1679 if (async) {
1680 rc = -EAGAIN;
1681 hba->clk_gating.active_reqs--;
1682 break;
1683 }
1684 spin_unlock_irqrestore(hba->host->host_lock, flags);
1685 flush_result = flush_work(&hba->clk_gating.ungate_work);
1686 if (hba->clk_gating.is_suspended && !flush_result)
1687 goto out;
1688 spin_lock_irqsave(hba->host->host_lock, flags);
1689 goto start;
1690 }
1691 break;
1692 case REQ_CLKS_OFF:
1693 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1694 hba->clk_gating.state = CLKS_ON;
1695 trace_ufshcd_clk_gating(dev_name(hba->dev),
1696 hba->clk_gating.state);
1697 break;
1698 }
1699
1700
1701
1702
1703
1704 fallthrough;
1705 case CLKS_OFF:
1706 hba->clk_gating.state = REQ_CLKS_ON;
1707 trace_ufshcd_clk_gating(dev_name(hba->dev),
1708 hba->clk_gating.state);
1709 if (queue_work(hba->clk_gating.clk_gating_workq,
1710 &hba->clk_gating.ungate_work))
1711 ufshcd_scsi_block_requests(hba);
1712
1713
1714
1715
1716 fallthrough;
1717 case REQ_CLKS_ON:
1718 if (async) {
1719 rc = -EAGAIN;
1720 hba->clk_gating.active_reqs--;
1721 break;
1722 }
1723
1724 spin_unlock_irqrestore(hba->host->host_lock, flags);
1725 flush_work(&hba->clk_gating.ungate_work);
1726
1727 spin_lock_irqsave(hba->host->host_lock, flags);
1728 goto start;
1729 default:
1730 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1731 __func__, hba->clk_gating.state);
1732 break;
1733 }
1734 spin_unlock_irqrestore(hba->host->host_lock, flags);
1735out:
1736 return rc;
1737}
1738EXPORT_SYMBOL_GPL(ufshcd_hold);
1739
1740static void ufshcd_gate_work(struct work_struct *work)
1741{
1742 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1743 clk_gating.gate_work.work);
1744 unsigned long flags;
1745 int ret;
1746
1747 spin_lock_irqsave(hba->host->host_lock, flags);
1748
1749
1750
1751
1752
1753
1754 if (hba->clk_gating.is_suspended ||
1755 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1756 hba->clk_gating.state = CLKS_ON;
1757 trace_ufshcd_clk_gating(dev_name(hba->dev),
1758 hba->clk_gating.state);
1759 goto rel_lock;
1760 }
1761
1762 if (hba->clk_gating.active_reqs
1763 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1764 || ufshcd_any_tag_in_use(hba) || hba->outstanding_tasks
1765 || hba->active_uic_cmd || hba->uic_async_done)
1766 goto rel_lock;
1767
1768 spin_unlock_irqrestore(hba->host->host_lock, flags);
1769
1770
1771 if (ufshcd_can_hibern8_during_gating(hba)) {
1772 ret = ufshcd_uic_hibern8_enter(hba);
1773 if (ret) {
1774 hba->clk_gating.state = CLKS_ON;
1775 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1776 __func__, ret);
1777 trace_ufshcd_clk_gating(dev_name(hba->dev),
1778 hba->clk_gating.state);
1779 goto out;
1780 }
1781 ufshcd_set_link_hibern8(hba);
1782 }
1783
1784 ufshcd_disable_irq(hba);
1785
1786 ufshcd_setup_clocks(hba, false);
1787
1788
1789 ufshcd_hba_vreg_set_lpm(hba);
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799 spin_lock_irqsave(hba->host->host_lock, flags);
1800 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1801 hba->clk_gating.state = CLKS_OFF;
1802 trace_ufshcd_clk_gating(dev_name(hba->dev),
1803 hba->clk_gating.state);
1804 }
1805rel_lock:
1806 spin_unlock_irqrestore(hba->host->host_lock, flags);
1807out:
1808 return;
1809}
1810
1811
1812static void __ufshcd_release(struct ufs_hba *hba)
1813{
1814 if (!ufshcd_is_clkgating_allowed(hba))
1815 return;
1816
1817 hba->clk_gating.active_reqs--;
1818
1819 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1820 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1821 hba->outstanding_tasks ||
1822 hba->active_uic_cmd || hba->uic_async_done ||
1823 hba->clk_gating.state == CLKS_OFF)
1824 return;
1825
1826 hba->clk_gating.state = REQ_CLKS_OFF;
1827 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1828 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1829 &hba->clk_gating.gate_work,
1830 msecs_to_jiffies(hba->clk_gating.delay_ms));
1831}
1832
1833void ufshcd_release(struct ufs_hba *hba)
1834{
1835 unsigned long flags;
1836
1837 spin_lock_irqsave(hba->host->host_lock, flags);
1838 __ufshcd_release(hba);
1839 spin_unlock_irqrestore(hba->host->host_lock, flags);
1840}
1841EXPORT_SYMBOL_GPL(ufshcd_release);
1842
1843static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1844 struct device_attribute *attr, char *buf)
1845{
1846 struct ufs_hba *hba = dev_get_drvdata(dev);
1847
1848 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1849}
1850
1851static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1852 struct device_attribute *attr, const char *buf, size_t count)
1853{
1854 struct ufs_hba *hba = dev_get_drvdata(dev);
1855 unsigned long flags, value;
1856
1857 if (kstrtoul(buf, 0, &value))
1858 return -EINVAL;
1859
1860 spin_lock_irqsave(hba->host->host_lock, flags);
1861 hba->clk_gating.delay_ms = value;
1862 spin_unlock_irqrestore(hba->host->host_lock, flags);
1863 return count;
1864}
1865
1866static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1867 struct device_attribute *attr, char *buf)
1868{
1869 struct ufs_hba *hba = dev_get_drvdata(dev);
1870
1871 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
1872}
1873
1874static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1875 struct device_attribute *attr, const char *buf, size_t count)
1876{
1877 struct ufs_hba *hba = dev_get_drvdata(dev);
1878 unsigned long flags;
1879 u32 value;
1880
1881 if (kstrtou32(buf, 0, &value))
1882 return -EINVAL;
1883
1884 value = !!value;
1885
1886 spin_lock_irqsave(hba->host->host_lock, flags);
1887 if (value == hba->clk_gating.is_enabled)
1888 goto out;
1889
1890 if (value)
1891 __ufshcd_release(hba);
1892 else
1893 hba->clk_gating.active_reqs++;
1894
1895 hba->clk_gating.is_enabled = value;
1896out:
1897 spin_unlock_irqrestore(hba->host->host_lock, flags);
1898 return count;
1899}
1900
1901static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
1902{
1903 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1904 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1905 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1906 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1907 hba->clk_gating.delay_attr.attr.mode = 0644;
1908 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1909 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1910
1911 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1912 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1913 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1914 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1915 hba->clk_gating.enable_attr.attr.mode = 0644;
1916 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1917 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1918}
1919
1920static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
1921{
1922 if (hba->clk_gating.delay_attr.attr.name)
1923 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1924 if (hba->clk_gating.enable_attr.attr.name)
1925 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1926}
1927
1928static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1929{
1930 char wq_name[sizeof("ufs_clk_gating_00")];
1931
1932 if (!ufshcd_is_clkgating_allowed(hba))
1933 return;
1934
1935 hba->clk_gating.state = CLKS_ON;
1936
1937 hba->clk_gating.delay_ms = 150;
1938 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1939 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1940
1941 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1942 hba->host->host_no);
1943 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1944 WQ_MEM_RECLAIM | WQ_HIGHPRI);
1945
1946 ufshcd_init_clk_gating_sysfs(hba);
1947
1948 hba->clk_gating.is_enabled = true;
1949 hba->clk_gating.is_initialized = true;
1950}
1951
1952static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1953{
1954 if (!hba->clk_gating.is_initialized)
1955 return;
1956 ufshcd_remove_clk_gating_sysfs(hba);
1957 cancel_work_sync(&hba->clk_gating.ungate_work);
1958 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1959 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1960 hba->clk_gating.is_initialized = false;
1961}
1962
1963
1964static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1965{
1966 bool queue_resume_work = false;
1967 ktime_t curr_t = ktime_get();
1968 unsigned long flags;
1969
1970 if (!ufshcd_is_clkscaling_supported(hba))
1971 return;
1972
1973 spin_lock_irqsave(hba->host->host_lock, flags);
1974 if (!hba->clk_scaling.active_reqs++)
1975 queue_resume_work = true;
1976
1977 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
1978 spin_unlock_irqrestore(hba->host->host_lock, flags);
1979 return;
1980 }
1981
1982 if (queue_resume_work)
1983 queue_work(hba->clk_scaling.workq,
1984 &hba->clk_scaling.resume_work);
1985
1986 if (!hba->clk_scaling.window_start_t) {
1987 hba->clk_scaling.window_start_t = curr_t;
1988 hba->clk_scaling.tot_busy_t = 0;
1989 hba->clk_scaling.is_busy_started = false;
1990 }
1991
1992 if (!hba->clk_scaling.is_busy_started) {
1993 hba->clk_scaling.busy_start_t = curr_t;
1994 hba->clk_scaling.is_busy_started = true;
1995 }
1996 spin_unlock_irqrestore(hba->host->host_lock, flags);
1997}
1998
1999static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2000{
2001 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2002 unsigned long flags;
2003
2004 if (!ufshcd_is_clkscaling_supported(hba))
2005 return;
2006
2007 spin_lock_irqsave(hba->host->host_lock, flags);
2008 hba->clk_scaling.active_reqs--;
2009 if (!hba->outstanding_reqs && scaling->is_busy_started) {
2010 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2011 scaling->busy_start_t));
2012 scaling->busy_start_t = 0;
2013 scaling->is_busy_started = false;
2014 }
2015 spin_unlock_irqrestore(hba->host->host_lock, flags);
2016}
2017
2018static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2019{
2020 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2021 return READ;
2022 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2023 return WRITE;
2024 else
2025 return -EINVAL;
2026}
2027
2028static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2029 struct ufshcd_lrb *lrbp)
2030{
2031 struct ufs_hba_monitor *m = &hba->monitor;
2032
2033 return (m->enabled && lrbp && lrbp->cmd &&
2034 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2035 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2036}
2037
2038static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2039{
2040 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2041 unsigned long flags;
2042
2043 spin_lock_irqsave(hba->host->host_lock, flags);
2044 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2045 hba->monitor.busy_start_ts[dir] = ktime_get();
2046 spin_unlock_irqrestore(hba->host->host_lock, flags);
2047}
2048
2049static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2050{
2051 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2052 unsigned long flags;
2053
2054 spin_lock_irqsave(hba->host->host_lock, flags);
2055 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2056 struct request *req = scsi_cmd_to_rq(lrbp->cmd);
2057 struct ufs_hba_monitor *m = &hba->monitor;
2058 ktime_t now, inc, lat;
2059
2060 now = lrbp->compl_time_stamp;
2061 inc = ktime_sub(now, m->busy_start_ts[dir]);
2062 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2063 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2064
2065
2066 m->nr_req[dir]++;
2067 lat = ktime_sub(now, lrbp->issue_time_stamp);
2068 m->lat_sum[dir] += lat;
2069 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2070 m->lat_max[dir] = lat;
2071 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2072 m->lat_min[dir] = lat;
2073
2074 m->nr_queued[dir]--;
2075
2076 m->busy_start_ts[dir] = now;
2077 }
2078 spin_unlock_irqrestore(hba->host->host_lock, flags);
2079}
2080
2081
2082
2083
2084
2085
2086static inline
2087void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2088{
2089 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2090 unsigned long flags;
2091
2092 lrbp->issue_time_stamp = ktime_get();
2093 lrbp->compl_time_stamp = ktime_set(0, 0);
2094 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2095 ufshcd_clk_scaling_start_busy(hba);
2096 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2097 ufshcd_start_monitor(hba, lrbp);
2098
2099 spin_lock_irqsave(&hba->outstanding_lock, flags);
2100 if (hba->vops && hba->vops->setup_xfer_req)
2101 hba->vops->setup_xfer_req(hba, task_tag, !!lrbp->cmd);
2102 __set_bit(task_tag, &hba->outstanding_reqs);
2103 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
2104 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2105
2106
2107 wmb();
2108}
2109
2110
2111
2112
2113
2114static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2115{
2116 int len;
2117 if (lrbp->sense_buffer &&
2118 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
2119 int len_to_copy;
2120
2121 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2122 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2123
2124 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2125 len_to_copy);
2126 }
2127}
2128
2129
2130
2131
2132
2133
2134
2135static
2136int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2137{
2138 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2139
2140 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2141
2142
2143 if (hba->dev_cmd.query.descriptor &&
2144 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2145 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2146 GENERAL_UPIU_REQUEST_SIZE;
2147 u16 resp_len;
2148 u16 buf_len;
2149
2150
2151 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
2152 MASK_QUERY_DATA_SEG_LEN;
2153 buf_len = be16_to_cpu(
2154 hba->dev_cmd.query.request.upiu_req.length);
2155 if (likely(buf_len >= resp_len)) {
2156 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2157 } else {
2158 dev_warn(hba->dev,
2159 "%s: rsp size %d is bigger than buffer size %d",
2160 __func__, resp_len, buf_len);
2161 return -EINVAL;
2162 }
2163 }
2164
2165 return 0;
2166}
2167
2168
2169
2170
2171
2172
2173
2174static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2175{
2176 int err;
2177
2178 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2179
2180
2181 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2182 hba->nutmrs =
2183 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2184
2185
2186 err = ufshcd_hba_init_crypto_capabilities(hba);
2187 if (err)
2188 dev_err(hba->dev, "crypto setup failed\n");
2189
2190 return err;
2191}
2192
2193
2194
2195
2196
2197
2198
2199static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2200{
2201 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
2202 return true;
2203 else
2204 return false;
2205}
2206
2207
2208
2209
2210
2211
2212
2213
2214static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2215{
2216 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2217}
2218
2219
2220
2221
2222
2223
2224static inline void
2225ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2226{
2227 lockdep_assert_held(&hba->uic_cmd_mutex);
2228
2229 WARN_ON(hba->active_uic_cmd);
2230
2231 hba->active_uic_cmd = uic_cmd;
2232
2233
2234 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2235 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2236 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2237
2238 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2239
2240
2241 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2242 REG_UIC_COMMAND);
2243}
2244
2245
2246
2247
2248
2249
2250
2251
2252static int
2253ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2254{
2255 int ret;
2256 unsigned long flags;
2257
2258 lockdep_assert_held(&hba->uic_cmd_mutex);
2259
2260 if (wait_for_completion_timeout(&uic_cmd->done,
2261 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2262 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2263 } else {
2264 ret = -ETIMEDOUT;
2265 dev_err(hba->dev,
2266 "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2267 uic_cmd->command, uic_cmd->argument3);
2268
2269 if (!uic_cmd->cmd_active) {
2270 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2271 __func__);
2272 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2273 }
2274 }
2275
2276 spin_lock_irqsave(hba->host->host_lock, flags);
2277 hba->active_uic_cmd = NULL;
2278 spin_unlock_irqrestore(hba->host->host_lock, flags);
2279
2280 return ret;
2281}
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291static int
2292__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2293 bool completion)
2294{
2295 lockdep_assert_held(&hba->uic_cmd_mutex);
2296 lockdep_assert_held(hba->host->host_lock);
2297
2298 if (!ufshcd_ready_for_uic_cmd(hba)) {
2299 dev_err(hba->dev,
2300 "Controller not ready to accept UIC commands\n");
2301 return -EIO;
2302 }
2303
2304 if (completion)
2305 init_completion(&uic_cmd->done);
2306
2307 uic_cmd->cmd_active = 1;
2308 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2309
2310 return 0;
2311}
2312
2313
2314
2315
2316
2317
2318
2319
2320int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2321{
2322 int ret;
2323 unsigned long flags;
2324
2325 ufshcd_hold(hba, false);
2326 mutex_lock(&hba->uic_cmd_mutex);
2327 ufshcd_add_delay_before_dme_cmd(hba);
2328
2329 spin_lock_irqsave(hba->host->host_lock, flags);
2330 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2331 spin_unlock_irqrestore(hba->host->host_lock, flags);
2332 if (!ret)
2333 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2334
2335 mutex_unlock(&hba->uic_cmd_mutex);
2336
2337 ufshcd_release(hba);
2338 return ret;
2339}
2340
2341
2342
2343
2344
2345
2346
2347
2348static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2349{
2350 struct ufshcd_sg_entry *prd_table;
2351 struct scatterlist *sg;
2352 struct scsi_cmnd *cmd;
2353 int sg_segments;
2354 int i;
2355
2356 cmd = lrbp->cmd;
2357 sg_segments = scsi_dma_map(cmd);
2358 if (sg_segments < 0)
2359 return sg_segments;
2360
2361 if (sg_segments) {
2362
2363 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2364 lrbp->utr_descriptor_ptr->prd_table_length =
2365 cpu_to_le16((sg_segments *
2366 sizeof(struct ufshcd_sg_entry)));
2367 else
2368 lrbp->utr_descriptor_ptr->prd_table_length =
2369 cpu_to_le16((u16) (sg_segments));
2370
2371 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2372
2373 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2374 prd_table[i].size =
2375 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2376 prd_table[i].base_addr =
2377 cpu_to_le32(lower_32_bits(sg->dma_address));
2378 prd_table[i].upper_addr =
2379 cpu_to_le32(upper_32_bits(sg->dma_address));
2380 prd_table[i].reserved = 0;
2381 }
2382 } else {
2383 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2384 }
2385
2386 return 0;
2387}
2388
2389
2390
2391
2392
2393
2394static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2395{
2396 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2397
2398 if (hba->ufs_version == ufshci_version(1, 0)) {
2399 u32 rw;
2400 rw = set & INTERRUPT_MASK_RW_VER_10;
2401 set = rw | ((set ^ intrs) & intrs);
2402 } else {
2403 set |= intrs;
2404 }
2405
2406 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2407}
2408
2409
2410
2411
2412
2413
2414static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2415{
2416 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2417
2418 if (hba->ufs_version == ufshci_version(1, 0)) {
2419 u32 rw;
2420 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2421 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2422 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2423
2424 } else {
2425 set &= ~intrs;
2426 }
2427
2428 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2429}
2430
2431
2432
2433
2434
2435
2436
2437
2438static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2439 u8 *upiu_flags, enum dma_data_direction cmd_dir)
2440{
2441 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2442 u32 data_direction;
2443 u32 dword_0;
2444 u32 dword_1 = 0;
2445 u32 dword_3 = 0;
2446
2447 if (cmd_dir == DMA_FROM_DEVICE) {
2448 data_direction = UTP_DEVICE_TO_HOST;
2449 *upiu_flags = UPIU_CMD_FLAGS_READ;
2450 } else if (cmd_dir == DMA_TO_DEVICE) {
2451 data_direction = UTP_HOST_TO_DEVICE;
2452 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2453 } else {
2454 data_direction = UTP_NO_DATA_TRANSFER;
2455 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2456 }
2457
2458 dword_0 = data_direction | (lrbp->command_type
2459 << UPIU_COMMAND_TYPE_OFFSET);
2460 if (lrbp->intr_cmd)
2461 dword_0 |= UTP_REQ_DESC_INT_CMD;
2462
2463
2464 ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2465
2466
2467 req_desc->header.dword_0 = cpu_to_le32(dword_0);
2468 req_desc->header.dword_1 = cpu_to_le32(dword_1);
2469
2470
2471
2472
2473
2474 req_desc->header.dword_2 =
2475 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2476 req_desc->header.dword_3 = cpu_to_le32(dword_3);
2477
2478 req_desc->prd_table_length = 0;
2479}
2480
2481
2482
2483
2484
2485
2486
2487static
2488void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2489{
2490 struct scsi_cmnd *cmd = lrbp->cmd;
2491 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2492 unsigned short cdb_len;
2493
2494
2495 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2496 UPIU_TRANSACTION_COMMAND, upiu_flags,
2497 lrbp->lun, lrbp->task_tag);
2498 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2499 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2500
2501
2502 ucd_req_ptr->header.dword_2 = 0;
2503
2504 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2505
2506 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2507 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2508 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2509
2510 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2511}
2512
2513
2514
2515
2516
2517
2518
2519
2520static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2521 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2522{
2523 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2524 struct ufs_query *query = &hba->dev_cmd.query;
2525 u16 len = be16_to_cpu(query->request.upiu_req.length);
2526
2527
2528 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2529 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2530 lrbp->lun, lrbp->task_tag);
2531 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2532 0, query->request.query_func, 0, 0);
2533
2534
2535 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2536 ucd_req_ptr->header.dword_2 =
2537 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2538 else
2539 ucd_req_ptr->header.dword_2 = 0;
2540
2541
2542 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2543 QUERY_OSF_SIZE);
2544
2545
2546 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2547 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2548
2549 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2550}
2551
2552static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2553{
2554 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2555
2556 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2557
2558
2559 ucd_req_ptr->header.dword_0 =
2560 UPIU_HEADER_DWORD(
2561 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2562
2563 ucd_req_ptr->header.dword_1 = 0;
2564 ucd_req_ptr->header.dword_2 = 0;
2565
2566 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2567}
2568
2569
2570
2571
2572
2573
2574
2575static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2576 struct ufshcd_lrb *lrbp)
2577{
2578 u8 upiu_flags;
2579 int ret = 0;
2580
2581 if (hba->ufs_version <= ufshci_version(1, 1))
2582 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2583 else
2584 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2585
2586 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2587 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2588 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2589 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2590 ufshcd_prepare_utp_nop_upiu(lrbp);
2591 else
2592 ret = -EINVAL;
2593
2594 return ret;
2595}
2596
2597
2598
2599
2600
2601
2602
2603static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2604{
2605 u8 upiu_flags;
2606 int ret = 0;
2607
2608 if (hba->ufs_version <= ufshci_version(1, 1))
2609 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2610 else
2611 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2612
2613 if (likely(lrbp->cmd)) {
2614 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2615 lrbp->cmd->sc_data_direction);
2616 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2617 } else {
2618 ret = -EINVAL;
2619 }
2620
2621 return ret;
2622}
2623
2624
2625
2626
2627
2628
2629
2630static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2631{
2632 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2633}
2634
2635static inline bool is_rpmb_wlun(struct scsi_device *sdev)
2636{
2637 return sdev->lun == ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN);
2638}
2639
2640static inline bool is_device_wlun(struct scsi_device *sdev)
2641{
2642 return sdev->lun ==
2643 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2644}
2645
2646static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2647{
2648 struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2649 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2650 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2651 i * sizeof(struct utp_transfer_cmd_desc);
2652 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2653 response_upiu);
2654 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2655
2656 lrb->utr_descriptor_ptr = utrdlp + i;
2657 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2658 i * sizeof(struct utp_transfer_req_desc);
2659 lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2660 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2661 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2662 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2663 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2664 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2665}
2666
2667
2668
2669
2670
2671
2672
2673
2674static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2675{
2676 struct ufs_hba *hba = shost_priv(host);
2677 int tag = scsi_cmd_to_rq(cmd)->tag;
2678 struct ufshcd_lrb *lrbp;
2679 int err = 0;
2680
2681 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
2682
2683 if (!down_read_trylock(&hba->clk_scaling_lock))
2684 return SCSI_MLQUEUE_HOST_BUSY;
2685
2686 switch (hba->ufshcd_state) {
2687 case UFSHCD_STATE_OPERATIONAL:
2688 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2689 break;
2690 case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701 if (hba->pm_op_in_progress) {
2702 hba->force_reset = true;
2703 set_host_byte(cmd, DID_BAD_TARGET);
2704 cmd->scsi_done(cmd);
2705 goto out;
2706 }
2707 fallthrough;
2708 case UFSHCD_STATE_RESET:
2709 err = SCSI_MLQUEUE_HOST_BUSY;
2710 goto out;
2711 case UFSHCD_STATE_ERROR:
2712 set_host_byte(cmd, DID_ERROR);
2713 cmd->scsi_done(cmd);
2714 goto out;
2715 }
2716
2717 hba->req_abort_count = 0;
2718
2719 err = ufshcd_hold(hba, true);
2720 if (err) {
2721 err = SCSI_MLQUEUE_HOST_BUSY;
2722 goto out;
2723 }
2724 WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2725 (hba->clk_gating.state != CLKS_ON));
2726
2727 lrbp = &hba->lrb[tag];
2728 WARN_ON(lrbp->cmd);
2729 lrbp->cmd = cmd;
2730 lrbp->sense_bufflen = UFS_SENSE_SIZE;
2731 lrbp->sense_buffer = cmd->sense_buffer;
2732 lrbp->task_tag = tag;
2733 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2734 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
2735
2736 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
2737
2738 lrbp->req_abort_skip = false;
2739
2740 ufshpb_prep(hba, lrbp);
2741
2742 ufshcd_comp_scsi_upiu(hba, lrbp);
2743
2744 err = ufshcd_map_sg(hba, lrbp);
2745 if (err) {
2746 lrbp->cmd = NULL;
2747 ufshcd_release(hba);
2748 goto out;
2749 }
2750
2751 ufshcd_send_command(hba, tag);
2752out:
2753 up_read(&hba->clk_scaling_lock);
2754
2755 if (ufs_trigger_eh()) {
2756 unsigned long flags;
2757
2758 spin_lock_irqsave(hba->host->host_lock, flags);
2759 ufshcd_schedule_eh_work(hba);
2760 spin_unlock_irqrestore(hba->host->host_lock, flags);
2761 }
2762
2763 return err;
2764}
2765
2766static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2767 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2768{
2769 lrbp->cmd = NULL;
2770 lrbp->sense_bufflen = 0;
2771 lrbp->sense_buffer = NULL;
2772 lrbp->task_tag = tag;
2773 lrbp->lun = 0;
2774 lrbp->intr_cmd = true;
2775 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2776 hba->dev_cmd.type = cmd_type;
2777
2778 return ufshcd_compose_devman_upiu(hba, lrbp);
2779}
2780
2781static int
2782ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2783{
2784 int err = 0;
2785 unsigned long flags;
2786 u32 mask = 1 << tag;
2787
2788
2789 spin_lock_irqsave(hba->host->host_lock, flags);
2790 ufshcd_utrl_clear(hba, tag);
2791 spin_unlock_irqrestore(hba->host->host_lock, flags);
2792
2793
2794
2795
2796
2797 err = ufshcd_wait_for_register(hba,
2798 REG_UTP_TRANSFER_REQ_DOOR_BELL,
2799 mask, ~mask, 1000, 1000);
2800
2801 return err;
2802}
2803
2804static int
2805ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2806{
2807 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2808
2809
2810 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2811 UPIU_RSP_CODE_OFFSET;
2812 return query_res->response;
2813}
2814
2815
2816
2817
2818
2819
2820static int
2821ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2822{
2823 int resp;
2824 int err = 0;
2825
2826 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2827 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2828
2829 switch (resp) {
2830 case UPIU_TRANSACTION_NOP_IN:
2831 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2832 err = -EINVAL;
2833 dev_err(hba->dev, "%s: unexpected response %x\n",
2834 __func__, resp);
2835 }
2836 break;
2837 case UPIU_TRANSACTION_QUERY_RSP:
2838 err = ufshcd_check_query_response(hba, lrbp);
2839 if (!err)
2840 err = ufshcd_copy_query_response(hba, lrbp);
2841 break;
2842 case UPIU_TRANSACTION_REJECT_UPIU:
2843
2844 err = -EPERM;
2845 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2846 __func__);
2847 break;
2848 default:
2849 err = -EINVAL;
2850 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2851 __func__, resp);
2852 break;
2853 }
2854
2855 return err;
2856}
2857
2858static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2859 struct ufshcd_lrb *lrbp, int max_timeout)
2860{
2861 int err = 0;
2862 unsigned long time_left;
2863 unsigned long flags;
2864
2865 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2866 msecs_to_jiffies(max_timeout));
2867
2868 spin_lock_irqsave(hba->host->host_lock, flags);
2869 hba->dev_cmd.complete = NULL;
2870 if (likely(time_left)) {
2871 err = ufshcd_get_tr_ocs(lrbp);
2872 if (!err)
2873 err = ufshcd_dev_cmd_completion(hba, lrbp);
2874 }
2875 spin_unlock_irqrestore(hba->host->host_lock, flags);
2876
2877 if (!time_left) {
2878 err = -ETIMEDOUT;
2879 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2880 __func__, lrbp->task_tag);
2881 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
2882
2883 err = -EAGAIN;
2884
2885
2886
2887
2888
2889 spin_lock_irqsave(&hba->outstanding_lock, flags);
2890 __clear_bit(lrbp->task_tag, &hba->outstanding_reqs);
2891 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2892 }
2893
2894 return err;
2895}
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2907 enum dev_cmd_type cmd_type, int timeout)
2908{
2909 struct request_queue *q = hba->cmd_queue;
2910 DECLARE_COMPLETION_ONSTACK(wait);
2911 struct request *req;
2912 struct ufshcd_lrb *lrbp;
2913 int err;
2914 int tag;
2915
2916 down_read(&hba->clk_scaling_lock);
2917
2918
2919
2920
2921
2922
2923 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
2924 if (IS_ERR(req)) {
2925 err = PTR_ERR(req);
2926 goto out_unlock;
2927 }
2928 tag = req->tag;
2929 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
2930
2931 req->timeout = msecs_to_jiffies(2 * timeout);
2932 blk_mq_start_request(req);
2933
2934 lrbp = &hba->lrb[tag];
2935 WARN_ON(lrbp->cmd);
2936 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2937 if (unlikely(err))
2938 goto out;
2939
2940 hba->dev_cmd.complete = &wait;
2941
2942 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
2943
2944 ufshcd_send_command(hba, tag);
2945 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2946 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
2947 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
2948
2949out:
2950 blk_put_request(req);
2951out_unlock:
2952 up_read(&hba->clk_scaling_lock);
2953 return err;
2954}
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966static inline void ufshcd_init_query(struct ufs_hba *hba,
2967 struct ufs_query_req **request, struct ufs_query_res **response,
2968 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2969{
2970 *request = &hba->dev_cmd.query.request;
2971 *response = &hba->dev_cmd.query.response;
2972 memset(*request, 0, sizeof(struct ufs_query_req));
2973 memset(*response, 0, sizeof(struct ufs_query_res));
2974 (*request)->upiu_req.opcode = opcode;
2975 (*request)->upiu_req.idn = idn;
2976 (*request)->upiu_req.index = index;
2977 (*request)->upiu_req.selector = selector;
2978}
2979
2980static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2981 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
2982{
2983 int ret;
2984 int retries;
2985
2986 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2987 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
2988 if (ret)
2989 dev_dbg(hba->dev,
2990 "%s: failed with error %d, retries %d\n",
2991 __func__, ret, retries);
2992 else
2993 break;
2994 }
2995
2996 if (ret)
2997 dev_err(hba->dev,
2998 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2999 __func__, opcode, idn, ret, retries);
3000 return ret;
3001}
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3014 enum flag_idn idn, u8 index, bool *flag_res)
3015{
3016 struct ufs_query_req *request = NULL;
3017 struct ufs_query_res *response = NULL;
3018 int err, selector = 0;
3019 int timeout = QUERY_REQ_TIMEOUT;
3020
3021 BUG_ON(!hba);
3022
3023 ufshcd_hold(hba, false);
3024 mutex_lock(&hba->dev_cmd.lock);
3025 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3026 selector);
3027
3028 switch (opcode) {
3029 case UPIU_QUERY_OPCODE_SET_FLAG:
3030 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3031 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3032 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3033 break;
3034 case UPIU_QUERY_OPCODE_READ_FLAG:
3035 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3036 if (!flag_res) {
3037
3038 dev_err(hba->dev, "%s: Invalid argument for read request\n",
3039 __func__);
3040 err = -EINVAL;
3041 goto out_unlock;
3042 }
3043 break;
3044 default:
3045 dev_err(hba->dev,
3046 "%s: Expected query flag opcode but got = %d\n",
3047 __func__, opcode);
3048 err = -EINVAL;
3049 goto out_unlock;
3050 }
3051
3052 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3053
3054 if (err) {
3055 dev_err(hba->dev,
3056 "%s: Sending flag query for idn %d failed, err = %d\n",
3057 __func__, idn, err);
3058 goto out_unlock;
3059 }
3060
3061 if (flag_res)
3062 *flag_res = (be32_to_cpu(response->upiu_res.value) &
3063 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3064
3065out_unlock:
3066 mutex_unlock(&hba->dev_cmd.lock);
3067 ufshcd_release(hba);
3068 return err;
3069}
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3083 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3084{
3085 struct ufs_query_req *request = NULL;
3086 struct ufs_query_res *response = NULL;
3087 int err;
3088
3089 BUG_ON(!hba);
3090
3091 if (!attr_val) {
3092 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3093 __func__, opcode);
3094 return -EINVAL;
3095 }
3096
3097 ufshcd_hold(hba, false);
3098
3099 mutex_lock(&hba->dev_cmd.lock);
3100 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3101 selector);
3102
3103 switch (opcode) {
3104 case UPIU_QUERY_OPCODE_WRITE_ATTR:
3105 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3106 request->upiu_req.value = cpu_to_be32(*attr_val);
3107 break;
3108 case UPIU_QUERY_OPCODE_READ_ATTR:
3109 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3110 break;
3111 default:
3112 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3113 __func__, opcode);
3114 err = -EINVAL;
3115 goto out_unlock;
3116 }
3117
3118 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3119
3120 if (err) {
3121 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3122 __func__, opcode, idn, index, err);
3123 goto out_unlock;
3124 }
3125
3126 *attr_val = be32_to_cpu(response->upiu_res.value);
3127
3128out_unlock:
3129 mutex_unlock(&hba->dev_cmd.lock);
3130 ufshcd_release(hba);
3131 return err;
3132}
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147int ufshcd_query_attr_retry(struct ufs_hba *hba,
3148 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3149 u32 *attr_val)
3150{
3151 int ret = 0;
3152 u32 retries;
3153
3154 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3155 ret = ufshcd_query_attr(hba, opcode, idn, index,
3156 selector, attr_val);
3157 if (ret)
3158 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3159 __func__, ret, retries);
3160 else
3161 break;
3162 }
3163
3164 if (ret)
3165 dev_err(hba->dev,
3166 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3167 __func__, idn, ret, QUERY_REQ_RETRIES);
3168 return ret;
3169}
3170
3171static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3172 enum query_opcode opcode, enum desc_idn idn, u8 index,
3173 u8 selector, u8 *desc_buf, int *buf_len)
3174{
3175 struct ufs_query_req *request = NULL;
3176 struct ufs_query_res *response = NULL;
3177 int err;
3178
3179 BUG_ON(!hba);
3180
3181 if (!desc_buf) {
3182 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3183 __func__, opcode);
3184 return -EINVAL;
3185 }
3186
3187 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3188 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3189 __func__, *buf_len);
3190 return -EINVAL;
3191 }
3192
3193 ufshcd_hold(hba, false);
3194
3195 mutex_lock(&hba->dev_cmd.lock);
3196 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3197 selector);
3198 hba->dev_cmd.query.descriptor = desc_buf;
3199 request->upiu_req.length = cpu_to_be16(*buf_len);
3200
3201 switch (opcode) {
3202 case UPIU_QUERY_OPCODE_WRITE_DESC:
3203 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3204 break;
3205 case UPIU_QUERY_OPCODE_READ_DESC:
3206 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3207 break;
3208 default:
3209 dev_err(hba->dev,
3210 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3211 __func__, opcode);
3212 err = -EINVAL;
3213 goto out_unlock;
3214 }
3215
3216 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3217
3218 if (err) {
3219 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3220 __func__, opcode, idn, index, err);
3221 goto out_unlock;
3222 }
3223
3224 *buf_len = be16_to_cpu(response->upiu_res.length);
3225
3226out_unlock:
3227 hba->dev_cmd.query.descriptor = NULL;
3228 mutex_unlock(&hba->dev_cmd.lock);
3229 ufshcd_release(hba);
3230 return err;
3231}
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3248 enum query_opcode opcode,
3249 enum desc_idn idn, u8 index,
3250 u8 selector,
3251 u8 *desc_buf, int *buf_len)
3252{
3253 int err;
3254 int retries;
3255
3256 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3257 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3258 selector, desc_buf, buf_len);
3259 if (!err || err == -EINVAL)
3260 break;
3261 }
3262
3263 return err;
3264}
3265
3266
3267
3268
3269
3270
3271
3272void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3273 int *desc_len)
3274{
3275 if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3276 desc_id == QUERY_DESC_IDN_RFU_1)
3277 *desc_len = 0;
3278 else
3279 *desc_len = hba->desc_size[desc_id];
3280}
3281EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3282
3283static void ufshcd_update_desc_length(struct ufs_hba *hba,
3284 enum desc_idn desc_id, int desc_index,
3285 unsigned char desc_len)
3286{
3287 if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
3288 desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3289
3290
3291
3292
3293
3294 hba->desc_size[desc_id] = desc_len;
3295}
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308int ufshcd_read_desc_param(struct ufs_hba *hba,
3309 enum desc_idn desc_id,
3310 int desc_index,
3311 u8 param_offset,
3312 u8 *param_read_buf,
3313 u8 param_size)
3314{
3315 int ret;
3316 u8 *desc_buf;
3317 int buff_len;
3318 bool is_kmalloc = true;
3319
3320
3321 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3322 return -EINVAL;
3323
3324
3325 ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3326 if (!buff_len) {
3327 dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
3328 return -EINVAL;
3329 }
3330
3331 if (param_offset >= buff_len) {
3332 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3333 __func__, param_offset, desc_id, buff_len);
3334 return -EINVAL;
3335 }
3336
3337
3338 if (param_offset != 0 || param_size < buff_len) {
3339 desc_buf = kzalloc(buff_len, GFP_KERNEL);
3340 if (!desc_buf)
3341 return -ENOMEM;
3342 } else {
3343 desc_buf = param_read_buf;
3344 is_kmalloc = false;
3345 }
3346
3347
3348 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3349 desc_id, desc_index, 0,
3350 desc_buf, &buff_len);
3351
3352 if (ret) {
3353 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3354 __func__, desc_id, desc_index, param_offset, ret);
3355 goto out;
3356 }
3357
3358
3359 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3360 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3361 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3362 ret = -EINVAL;
3363 goto out;
3364 }
3365
3366
3367 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3368 ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
3369
3370 if (is_kmalloc) {
3371
3372 if (param_offset >= buff_len)
3373 ret = -EINVAL;
3374 else
3375 memcpy(param_read_buf, &desc_buf[param_offset],
3376 min_t(u32, param_size, buff_len - param_offset));
3377 }
3378out:
3379 if (is_kmalloc)
3380 kfree(desc_buf);
3381 return ret;
3382}
3383
3384
3385
3386
3387
3388
3389
3390
3391struct uc_string_id {
3392 u8 len;
3393 u8 type;
3394 wchar_t uc[];
3395} __packed;
3396
3397
3398static inline char ufshcd_remove_non_printable(u8 ch)
3399{
3400 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3401}
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3418 u8 **buf, bool ascii)
3419{
3420 struct uc_string_id *uc_str;
3421 u8 *str;
3422 int ret;
3423
3424 if (!buf)
3425 return -EINVAL;
3426
3427 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3428 if (!uc_str)
3429 return -ENOMEM;
3430
3431 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3432 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3433 if (ret < 0) {
3434 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3435 QUERY_REQ_RETRIES, ret);
3436 str = NULL;
3437 goto out;
3438 }
3439
3440 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3441 dev_dbg(hba->dev, "String Desc is of zero length\n");
3442 str = NULL;
3443 ret = 0;
3444 goto out;
3445 }
3446
3447 if (ascii) {
3448 ssize_t ascii_len;
3449 int i;
3450
3451 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3452 str = kzalloc(ascii_len, GFP_KERNEL);
3453 if (!str) {
3454 ret = -ENOMEM;
3455 goto out;
3456 }
3457
3458
3459
3460
3461
3462 ret = utf16s_to_utf8s(uc_str->uc,
3463 uc_str->len - QUERY_DESC_HDR_SIZE,
3464 UTF16_BIG_ENDIAN, str, ascii_len);
3465
3466
3467 for (i = 0; i < ret; i++)
3468 str[i] = ufshcd_remove_non_printable(str[i]);
3469
3470 str[ret++] = '\0';
3471
3472 } else {
3473 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3474 if (!str) {
3475 ret = -ENOMEM;
3476 goto out;
3477 }
3478 ret = uc_str->len;
3479 }
3480out:
3481 *buf = str;
3482 kfree(uc_str);
3483 return ret;
3484}
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3497 int lun,
3498 enum unit_desc_param param_offset,
3499 u8 *param_read_buf,
3500 u32 param_size)
3501{
3502
3503
3504
3505
3506 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
3507 return -EOPNOTSUPP;
3508
3509 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3510 param_offset, param_read_buf, param_size);
3511}
3512
3513static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3514{
3515 int err = 0;
3516 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3517
3518 if (hba->dev_info.wspecversion >= 0x300) {
3519 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3520 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3521 &gating_wait);
3522 if (err)
3523 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3524 err, gating_wait);
3525
3526 if (gating_wait == 0) {
3527 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3528 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3529 gating_wait);
3530 }
3531
3532 hba->dev_info.clk_gating_wait_us = gating_wait;
3533 }
3534
3535 return err;
3536}
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551static int ufshcd_memory_alloc(struct ufs_hba *hba)
3552{
3553 size_t utmrdl_size, utrdl_size, ucdl_size;
3554
3555
3556 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3557 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3558 ucdl_size,
3559 &hba->ucdl_dma_addr,
3560 GFP_KERNEL);
3561
3562
3563
3564
3565
3566
3567
3568 if (!hba->ucdl_base_addr ||
3569 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3570 dev_err(hba->dev,
3571 "Command Descriptor Memory allocation failed\n");
3572 goto out;
3573 }
3574
3575
3576
3577
3578
3579 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3580 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3581 utrdl_size,
3582 &hba->utrdl_dma_addr,
3583 GFP_KERNEL);
3584 if (!hba->utrdl_base_addr ||
3585 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3586 dev_err(hba->dev,
3587 "Transfer Descriptor Memory allocation failed\n");
3588 goto out;
3589 }
3590
3591
3592
3593
3594
3595 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3596 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3597 utmrdl_size,
3598 &hba->utmrdl_dma_addr,
3599 GFP_KERNEL);
3600 if (!hba->utmrdl_base_addr ||
3601 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3602 dev_err(hba->dev,
3603 "Task Management Descriptor Memory allocation failed\n");
3604 goto out;
3605 }
3606
3607
3608 hba->lrb = devm_kcalloc(hba->dev,
3609 hba->nutrs, sizeof(struct ufshcd_lrb),
3610 GFP_KERNEL);
3611 if (!hba->lrb) {
3612 dev_err(hba->dev, "LRB Memory allocation failed\n");
3613 goto out;
3614 }
3615 return 0;
3616out:
3617 return -ENOMEM;
3618}
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3634{
3635 struct utp_transfer_req_desc *utrdlp;
3636 dma_addr_t cmd_desc_dma_addr;
3637 dma_addr_t cmd_desc_element_addr;
3638 u16 response_offset;
3639 u16 prdt_offset;
3640 int cmd_desc_size;
3641 int i;
3642
3643 utrdlp = hba->utrdl_base_addr;
3644
3645 response_offset =
3646 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3647 prdt_offset =
3648 offsetof(struct utp_transfer_cmd_desc, prd_table);
3649
3650 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3651 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3652
3653 for (i = 0; i < hba->nutrs; i++) {
3654
3655 cmd_desc_element_addr =
3656 (cmd_desc_dma_addr + (cmd_desc_size * i));
3657 utrdlp[i].command_desc_base_addr_lo =
3658 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3659 utrdlp[i].command_desc_base_addr_hi =
3660 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3661
3662
3663 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3664 utrdlp[i].response_upiu_offset =
3665 cpu_to_le16(response_offset);
3666 utrdlp[i].prd_table_offset =
3667 cpu_to_le16(prdt_offset);
3668 utrdlp[i].response_upiu_length =
3669 cpu_to_le16(ALIGNED_UPIU_SIZE);
3670 } else {
3671 utrdlp[i].response_upiu_offset =
3672 cpu_to_le16(response_offset >> 2);
3673 utrdlp[i].prd_table_offset =
3674 cpu_to_le16(prdt_offset >> 2);
3675 utrdlp[i].response_upiu_length =
3676 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3677 }
3678
3679 ufshcd_init_lrb(hba, &hba->lrb[i], i);
3680 }
3681}
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3695{
3696 struct uic_command uic_cmd = {0};
3697 int ret;
3698
3699 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3700
3701 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3702 if (ret)
3703 dev_dbg(hba->dev,
3704 "dme-link-startup: error code %d\n", ret);
3705 return ret;
3706}
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716static int ufshcd_dme_reset(struct ufs_hba *hba)
3717{
3718 struct uic_command uic_cmd = {0};
3719 int ret;
3720
3721 uic_cmd.command = UIC_CMD_DME_RESET;
3722
3723 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3724 if (ret)
3725 dev_err(hba->dev,
3726 "dme-reset: error code %d\n", ret);
3727
3728 return ret;
3729}
3730
3731int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3732 int agreed_gear,
3733 int adapt_val)
3734{
3735 int ret;
3736
3737 if (agreed_gear != UFS_HS_G4)
3738 adapt_val = PA_NO_ADAPT;
3739
3740 ret = ufshcd_dme_set(hba,
3741 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3742 adapt_val);
3743 return ret;
3744}
3745EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755static int ufshcd_dme_enable(struct ufs_hba *hba)
3756{
3757 struct uic_command uic_cmd = {0};
3758 int ret;
3759
3760 uic_cmd.command = UIC_CMD_DME_ENABLE;
3761
3762 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3763 if (ret)
3764 dev_err(hba->dev,
3765 "dme-enable: error code %d\n", ret);
3766
3767 return ret;
3768}
3769
3770static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3771{
3772 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3773 unsigned long min_sleep_time_us;
3774
3775 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3776 return;
3777
3778
3779
3780
3781
3782 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3783 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3784 } else {
3785 unsigned long delta =
3786 (unsigned long) ktime_to_us(
3787 ktime_sub(ktime_get(),
3788 hba->last_dme_cmd_tstamp));
3789
3790 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3791 min_sleep_time_us =
3792 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3793 else
3794 return;
3795 }
3796
3797
3798 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3799}
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3812 u8 attr_set, u32 mib_val, u8 peer)
3813{
3814 struct uic_command uic_cmd = {0};
3815 static const char *const action[] = {
3816 "dme-set",
3817 "dme-peer-set"
3818 };
3819 const char *set = action[!!peer];
3820 int ret;
3821 int retries = UFS_UIC_COMMAND_RETRIES;
3822
3823 uic_cmd.command = peer ?
3824 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3825 uic_cmd.argument1 = attr_sel;
3826 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3827 uic_cmd.argument3 = mib_val;
3828
3829 do {
3830
3831 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3832 if (ret)
3833 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3834 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3835 } while (ret && peer && --retries);
3836
3837 if (ret)
3838 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3839 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3840 UFS_UIC_COMMAND_RETRIES - retries);
3841
3842 return ret;
3843}
3844EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3856 u32 *mib_val, u8 peer)
3857{
3858 struct uic_command uic_cmd = {0};
3859 static const char *const action[] = {
3860 "dme-get",
3861 "dme-peer-get"
3862 };
3863 const char *get = action[!!peer];
3864 int ret;
3865 int retries = UFS_UIC_COMMAND_RETRIES;
3866 struct ufs_pa_layer_attr orig_pwr_info;
3867 struct ufs_pa_layer_attr temp_pwr_info;
3868 bool pwr_mode_change = false;
3869
3870 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3871 orig_pwr_info = hba->pwr_info;
3872 temp_pwr_info = orig_pwr_info;
3873
3874 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3875 orig_pwr_info.pwr_rx == FAST_MODE) {
3876 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3877 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3878 pwr_mode_change = true;
3879 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3880 orig_pwr_info.pwr_rx == SLOW_MODE) {
3881 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3882 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3883 pwr_mode_change = true;
3884 }
3885 if (pwr_mode_change) {
3886 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3887 if (ret)
3888 goto out;
3889 }
3890 }
3891
3892 uic_cmd.command = peer ?
3893 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3894 uic_cmd.argument1 = attr_sel;
3895
3896 do {
3897
3898 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3899 if (ret)
3900 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3901 get, UIC_GET_ATTR_ID(attr_sel), ret);
3902 } while (ret && peer && --retries);
3903
3904 if (ret)
3905 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
3906 get, UIC_GET_ATTR_ID(attr_sel),
3907 UFS_UIC_COMMAND_RETRIES - retries);
3908
3909 if (mib_val && !ret)
3910 *mib_val = uic_cmd.argument3;
3911
3912 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3913 && pwr_mode_change)
3914 ufshcd_change_power_mode(hba, &orig_pwr_info);
3915out:
3916 return ret;
3917}
3918EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
3937{
3938 DECLARE_COMPLETION_ONSTACK(uic_async_done);
3939 unsigned long flags;
3940 u8 status;
3941 int ret;
3942 bool reenable_intr = false;
3943
3944 mutex_lock(&hba->uic_cmd_mutex);
3945 ufshcd_add_delay_before_dme_cmd(hba);
3946
3947 spin_lock_irqsave(hba->host->host_lock, flags);
3948 if (ufshcd_is_link_broken(hba)) {
3949 ret = -ENOLINK;
3950 goto out_unlock;
3951 }
3952 hba->uic_async_done = &uic_async_done;
3953 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3954 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3955
3956
3957
3958
3959 wmb();
3960 reenable_intr = true;
3961 }
3962 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3963 spin_unlock_irqrestore(hba->host->host_lock, flags);
3964 if (ret) {
3965 dev_err(hba->dev,
3966 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3967 cmd->command, cmd->argument3, ret);
3968 goto out;
3969 }
3970
3971 if (!wait_for_completion_timeout(hba->uic_async_done,
3972 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3973 dev_err(hba->dev,
3974 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3975 cmd->command, cmd->argument3);
3976
3977 if (!cmd->cmd_active) {
3978 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
3979 __func__);
3980 goto check_upmcrs;
3981 }
3982
3983 ret = -ETIMEDOUT;
3984 goto out;
3985 }
3986
3987check_upmcrs:
3988 status = ufshcd_get_upmcrs(hba);
3989 if (status != PWR_LOCAL) {
3990 dev_err(hba->dev,
3991 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
3992 cmd->command, status);
3993 ret = (status != PWR_OK) ? status : -1;
3994 }
3995out:
3996 if (ret) {
3997 ufshcd_print_host_state(hba);
3998 ufshcd_print_pwr_info(hba);
3999 ufshcd_print_evt_hist(hba);
4000 }
4001
4002 spin_lock_irqsave(hba->host->host_lock, flags);
4003 hba->active_uic_cmd = NULL;
4004 hba->uic_async_done = NULL;
4005 if (reenable_intr)
4006 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4007 if (ret) {
4008 ufshcd_set_link_broken(hba);
4009 ufshcd_schedule_eh_work(hba);
4010 }
4011out_unlock:
4012 spin_unlock_irqrestore(hba->host->host_lock, flags);
4013 mutex_unlock(&hba->uic_cmd_mutex);
4014
4015 return ret;
4016}
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4027{
4028 struct uic_command uic_cmd = {0};
4029 int ret;
4030
4031 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4032 ret = ufshcd_dme_set(hba,
4033 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4034 if (ret) {
4035 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4036 __func__, ret);
4037 goto out;
4038 }
4039 }
4040
4041 uic_cmd.command = UIC_CMD_DME_SET;
4042 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4043 uic_cmd.argument3 = mode;
4044 ufshcd_hold(hba, false);
4045 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4046 ufshcd_release(hba);
4047
4048out:
4049 return ret;
4050}
4051
4052int ufshcd_link_recovery(struct ufs_hba *hba)
4053{
4054 int ret;
4055 unsigned long flags;
4056
4057 spin_lock_irqsave(hba->host->host_lock, flags);
4058 hba->ufshcd_state = UFSHCD_STATE_RESET;
4059 ufshcd_set_eh_in_progress(hba);
4060 spin_unlock_irqrestore(hba->host->host_lock, flags);
4061
4062
4063 ufshcd_device_reset(hba);
4064
4065 ret = ufshcd_host_reset_and_restore(hba);
4066
4067 spin_lock_irqsave(hba->host->host_lock, flags);
4068 if (ret)
4069 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4070 ufshcd_clear_eh_in_progress(hba);
4071 spin_unlock_irqrestore(hba->host->host_lock, flags);
4072
4073 if (ret)
4074 dev_err(hba->dev, "%s: link recovery failed, err %d",
4075 __func__, ret);
4076 else
4077 ufshcd_clear_ua_wluns(hba);
4078
4079 return ret;
4080}
4081EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4082
4083static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4084{
4085 int ret;
4086 struct uic_command uic_cmd = {0};
4087 ktime_t start = ktime_get();
4088
4089 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4090
4091 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4092 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4093 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4094 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4095
4096 if (ret)
4097 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4098 __func__, ret);
4099 else
4100 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4101 POST_CHANGE);
4102
4103 return ret;
4104}
4105
4106int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4107{
4108 struct uic_command uic_cmd = {0};
4109 int ret;
4110 ktime_t start = ktime_get();
4111
4112 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4113
4114 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4115 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4116 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4117 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4118
4119 if (ret) {
4120 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4121 __func__, ret);
4122 } else {
4123 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4124 POST_CHANGE);
4125 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
4126 hba->ufs_stats.hibern8_exit_cnt++;
4127 }
4128
4129 return ret;
4130}
4131EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4132
4133void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4134{
4135 unsigned long flags;
4136 bool update = false;
4137
4138 if (!ufshcd_is_auto_hibern8_supported(hba))
4139 return;
4140
4141 spin_lock_irqsave(hba->host->host_lock, flags);
4142 if (hba->ahit != ahit) {
4143 hba->ahit = ahit;
4144 update = true;
4145 }
4146 spin_unlock_irqrestore(hba->host->host_lock, flags);
4147
4148 if (update &&
4149 !pm_runtime_suspended(&hba->sdev_ufs_device->sdev_gendev)) {
4150 ufshcd_rpm_get_sync(hba);
4151 ufshcd_hold(hba, false);
4152 ufshcd_auto_hibern8_enable(hba);
4153 ufshcd_release(hba);
4154 ufshcd_rpm_put_sync(hba);
4155 }
4156}
4157EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4158
4159void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
4160{
4161 unsigned long flags;
4162
4163 if (!ufshcd_is_auto_hibern8_supported(hba))
4164 return;
4165
4166 spin_lock_irqsave(hba->host->host_lock, flags);
4167 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4168 spin_unlock_irqrestore(hba->host->host_lock, flags);
4169}
4170
4171
4172
4173
4174
4175
4176static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4177{
4178 hba->pwr_info.gear_rx = UFS_PWM_G1;
4179 hba->pwr_info.gear_tx = UFS_PWM_G1;
4180 hba->pwr_info.lane_rx = 1;
4181 hba->pwr_info.lane_tx = 1;
4182 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4183 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4184 hba->pwr_info.hs_rate = 0;
4185}
4186
4187
4188
4189
4190
4191static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4192{
4193 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4194
4195 if (hba->max_pwr_info.is_valid)
4196 return 0;
4197
4198 pwr_info->pwr_tx = FAST_MODE;
4199 pwr_info->pwr_rx = FAST_MODE;
4200 pwr_info->hs_rate = PA_HS_MODE_B;
4201
4202
4203 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4204 &pwr_info->lane_rx);
4205 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4206 &pwr_info->lane_tx);
4207
4208 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4209 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4210 __func__,
4211 pwr_info->lane_rx,
4212 pwr_info->lane_tx);
4213 return -EINVAL;
4214 }
4215
4216
4217
4218
4219
4220
4221 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4222 if (!pwr_info->gear_rx) {
4223 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4224 &pwr_info->gear_rx);
4225 if (!pwr_info->gear_rx) {
4226 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4227 __func__, pwr_info->gear_rx);
4228 return -EINVAL;
4229 }
4230 pwr_info->pwr_rx = SLOW_MODE;
4231 }
4232
4233 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4234 &pwr_info->gear_tx);
4235 if (!pwr_info->gear_tx) {
4236 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4237 &pwr_info->gear_tx);
4238 if (!pwr_info->gear_tx) {
4239 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4240 __func__, pwr_info->gear_tx);
4241 return -EINVAL;
4242 }
4243 pwr_info->pwr_tx = SLOW_MODE;
4244 }
4245
4246 hba->max_pwr_info.is_valid = true;
4247 return 0;
4248}
4249
4250static int ufshcd_change_power_mode(struct ufs_hba *hba,
4251 struct ufs_pa_layer_attr *pwr_mode)
4252{
4253 int ret;
4254
4255
4256 if (!hba->force_pmc &&
4257 pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4258 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4259 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4260 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4261 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4262 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4263 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4264 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4265 return 0;
4266 }
4267
4268
4269
4270
4271
4272
4273
4274 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4275 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4276 pwr_mode->lane_rx);
4277 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4278 pwr_mode->pwr_rx == FAST_MODE)
4279 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
4280 else
4281 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
4282
4283 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4284 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4285 pwr_mode->lane_tx);
4286 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4287 pwr_mode->pwr_tx == FAST_MODE)
4288 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
4289 else
4290 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
4291
4292 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4293 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4294 pwr_mode->pwr_rx == FAST_MODE ||
4295 pwr_mode->pwr_tx == FAST_MODE)
4296 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4297 pwr_mode->hs_rate);
4298
4299 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4300 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4301 DL_FC0ProtectionTimeOutVal_Default);
4302 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4303 DL_TC0ReplayTimeOutVal_Default);
4304 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4305 DL_AFC0ReqTimeOutVal_Default);
4306 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4307 DL_FC1ProtectionTimeOutVal_Default);
4308 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4309 DL_TC1ReplayTimeOutVal_Default);
4310 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4311 DL_AFC1ReqTimeOutVal_Default);
4312
4313 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4314 DL_FC0ProtectionTimeOutVal_Default);
4315 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4316 DL_TC0ReplayTimeOutVal_Default);
4317 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4318 DL_AFC0ReqTimeOutVal_Default);
4319 }
4320
4321 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4322 | pwr_mode->pwr_tx);
4323
4324 if (ret) {
4325 dev_err(hba->dev,
4326 "%s: power mode change failed %d\n", __func__, ret);
4327 } else {
4328 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4329 pwr_mode);
4330
4331 memcpy(&hba->pwr_info, pwr_mode,
4332 sizeof(struct ufs_pa_layer_attr));
4333 }
4334
4335 return ret;
4336}
4337
4338
4339
4340
4341
4342
4343int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4344 struct ufs_pa_layer_attr *desired_pwr_mode)
4345{
4346 struct ufs_pa_layer_attr final_params = { 0 };
4347 int ret;
4348
4349 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4350 desired_pwr_mode, &final_params);
4351
4352 if (ret)
4353 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4354
4355 ret = ufshcd_change_power_mode(hba, &final_params);
4356
4357 return ret;
4358}
4359EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4360
4361
4362
4363
4364
4365
4366
4367static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4368{
4369 int err;
4370 bool flag_res = true;
4371 ktime_t timeout;
4372
4373 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4374 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4375 if (err) {
4376 dev_err(hba->dev,
4377 "%s setting fDeviceInit flag failed with error %d\n",
4378 __func__, err);
4379 goto out;
4380 }
4381
4382
4383 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4384 do {
4385 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4386 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4387 if (!flag_res)
4388 break;
4389 usleep_range(5000, 10000);
4390 } while (ktime_before(ktime_get(), timeout));
4391
4392 if (err) {
4393 dev_err(hba->dev,
4394 "%s reading fDeviceInit flag failed with error %d\n",
4395 __func__, err);
4396 } else if (flag_res) {
4397 dev_err(hba->dev,
4398 "%s fDeviceInit was not cleared by the device\n",
4399 __func__);
4400 err = -EBUSY;
4401 }
4402out:
4403 return err;
4404}
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418int ufshcd_make_hba_operational(struct ufs_hba *hba)
4419{
4420 int err = 0;
4421 u32 reg;
4422
4423
4424 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4425
4426
4427 if (ufshcd_is_intr_aggr_allowed(hba))
4428 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4429 else
4430 ufshcd_disable_intr_aggr(hba);
4431
4432
4433 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4434 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4435 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4436 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4437 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4438 REG_UTP_TASK_REQ_LIST_BASE_L);
4439 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4440 REG_UTP_TASK_REQ_LIST_BASE_H);
4441
4442
4443
4444
4445
4446 wmb();
4447
4448
4449
4450
4451 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4452 if (!(ufshcd_get_lists_status(reg))) {
4453 ufshcd_enable_run_stop_reg(hba);
4454 } else {
4455 dev_err(hba->dev,
4456 "Host controller not ready to process requests");
4457 err = -EIO;
4458 }
4459
4460 return err;
4461}
4462EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4463
4464
4465
4466
4467
4468void ufshcd_hba_stop(struct ufs_hba *hba)
4469{
4470 unsigned long flags;
4471 int err;
4472
4473
4474
4475
4476
4477 spin_lock_irqsave(hba->host->host_lock, flags);
4478 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4479 spin_unlock_irqrestore(hba->host->host_lock, flags);
4480
4481 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4482 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4483 10, 1);
4484 if (err)
4485 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4486}
4487EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4500{
4501 int retry_outer = 3;
4502 int retry_inner;
4503
4504start:
4505 if (!ufshcd_is_hba_active(hba))
4506
4507 ufshcd_hba_stop(hba);
4508
4509
4510 ufshcd_set_link_off(hba);
4511
4512 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4513
4514
4515 ufshcd_hba_start(hba);
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4528
4529
4530 retry_inner = 50;
4531 while (ufshcd_is_hba_active(hba)) {
4532 if (retry_inner) {
4533 retry_inner--;
4534 } else {
4535 dev_err(hba->dev,
4536 "Controller enable failed\n");
4537 if (retry_outer) {
4538 retry_outer--;
4539 goto start;
4540 }
4541 return -EIO;
4542 }
4543 usleep_range(1000, 1100);
4544 }
4545
4546
4547 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4548
4549 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4550
4551 return 0;
4552}
4553
4554int ufshcd_hba_enable(struct ufs_hba *hba)
4555{
4556 int ret;
4557
4558 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4559 ufshcd_set_link_off(hba);
4560 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4561
4562
4563 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4564 ret = ufshcd_dme_reset(hba);
4565 if (!ret) {
4566 ret = ufshcd_dme_enable(hba);
4567 if (!ret)
4568 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4569 if (ret)
4570 dev_err(hba->dev,
4571 "Host controller enable failed with non-hce\n");
4572 }
4573 } else {
4574 ret = ufshcd_hba_execute_hce(hba);
4575 }
4576
4577 return ret;
4578}
4579EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4580
4581static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4582{
4583 int tx_lanes = 0, i, err = 0;
4584
4585 if (!peer)
4586 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4587 &tx_lanes);
4588 else
4589 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4590 &tx_lanes);
4591 for (i = 0; i < tx_lanes; i++) {
4592 if (!peer)
4593 err = ufshcd_dme_set(hba,
4594 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4595 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4596 0);
4597 else
4598 err = ufshcd_dme_peer_set(hba,
4599 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4600 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4601 0);
4602 if (err) {
4603 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4604 __func__, peer, i, err);
4605 break;
4606 }
4607 }
4608
4609 return err;
4610}
4611
4612static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4613{
4614 return ufshcd_disable_tx_lcc(hba, true);
4615}
4616
4617void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4618{
4619 struct ufs_event_hist *e;
4620
4621 if (id >= UFS_EVT_CNT)
4622 return;
4623
4624 e = &hba->ufs_stats.event[id];
4625 e->val[e->pos] = val;
4626 e->tstamp[e->pos] = ktime_get();
4627 e->cnt += 1;
4628 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4629
4630 ufshcd_vops_event_notify(hba, id, &val);
4631}
4632EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4633
4634
4635
4636
4637
4638
4639
4640static int ufshcd_link_startup(struct ufs_hba *hba)
4641{
4642 int ret;
4643 int retries = DME_LINKSTARTUP_RETRIES;
4644 bool link_startup_again = false;
4645
4646
4647
4648
4649
4650 if (!ufshcd_is_ufs_dev_active(hba))
4651 link_startup_again = true;
4652
4653link_startup:
4654 do {
4655 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4656
4657 ret = ufshcd_dme_link_startup(hba);
4658
4659
4660 if (!ret && !ufshcd_is_device_present(hba)) {
4661 ufshcd_update_evt_hist(hba,
4662 UFS_EVT_LINK_STARTUP_FAIL,
4663 0);
4664 dev_err(hba->dev, "%s: Device not present\n", __func__);
4665 ret = -ENXIO;
4666 goto out;
4667 }
4668
4669
4670
4671
4672
4673
4674 if (ret && ufshcd_hba_enable(hba)) {
4675 ufshcd_update_evt_hist(hba,
4676 UFS_EVT_LINK_STARTUP_FAIL,
4677 (u32)ret);
4678 goto out;
4679 }
4680 } while (ret && retries--);
4681
4682 if (ret) {
4683
4684 ufshcd_update_evt_hist(hba,
4685 UFS_EVT_LINK_STARTUP_FAIL,
4686 (u32)ret);
4687 goto out;
4688 }
4689
4690 if (link_startup_again) {
4691 link_startup_again = false;
4692 retries = DME_LINKSTARTUP_RETRIES;
4693 goto link_startup;
4694 }
4695
4696
4697 ufshcd_init_pwr_info(hba);
4698 ufshcd_print_pwr_info(hba);
4699
4700 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4701 ret = ufshcd_disable_device_tx_lcc(hba);
4702 if (ret)
4703 goto out;
4704 }
4705
4706
4707 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4708 if (ret)
4709 goto out;
4710
4711
4712 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4713 ret = ufshcd_make_hba_operational(hba);
4714out:
4715 if (ret) {
4716 dev_err(hba->dev, "link startup failed %d\n", ret);
4717 ufshcd_print_host_state(hba);
4718 ufshcd_print_pwr_info(hba);
4719 ufshcd_print_evt_hist(hba);
4720 }
4721 return ret;
4722}
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4735{
4736 int err = 0;
4737 int retries;
4738
4739 ufshcd_hold(hba, false);
4740 mutex_lock(&hba->dev_cmd.lock);
4741 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4742 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4743 hba->nop_out_timeout);
4744
4745 if (!err || err == -ETIMEDOUT)
4746 break;
4747
4748 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4749 }
4750 mutex_unlock(&hba->dev_cmd.lock);
4751 ufshcd_release(hba);
4752
4753 if (err)
4754 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4755 return err;
4756}
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4768{
4769 int ret = 0;
4770 u8 lun_qdepth;
4771 struct ufs_hba *hba;
4772
4773 hba = shost_priv(sdev->host);
4774
4775 lun_qdepth = hba->nutrs;
4776 ret = ufshcd_read_unit_desc_param(hba,
4777 ufshcd_scsi_to_upiu_lun(sdev->lun),
4778 UNIT_DESC_PARAM_LU_Q_DEPTH,
4779 &lun_qdepth,
4780 sizeof(lun_qdepth));
4781
4782
4783 if (ret == -EOPNOTSUPP)
4784 lun_qdepth = 1;
4785 else if (!lun_qdepth)
4786
4787 lun_qdepth = hba->nutrs;
4788 else
4789 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4790
4791 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4792 __func__, lun_qdepth);
4793 scsi_change_queue_depth(sdev, lun_qdepth);
4794}
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4808 u8 lun,
4809 u8 *b_lu_write_protect)
4810{
4811 int ret;
4812
4813 if (!b_lu_write_protect)
4814 ret = -EINVAL;
4815
4816
4817
4818
4819
4820 else if (lun >= hba->dev_info.max_lu_supported)
4821 ret = -ENOTSUPP;
4822 else
4823 ret = ufshcd_read_unit_desc_param(hba,
4824 lun,
4825 UNIT_DESC_PARAM_LU_WR_PROTECT,
4826 b_lu_write_protect,
4827 sizeof(*b_lu_write_protect));
4828 return ret;
4829}
4830
4831
4832
4833
4834
4835
4836
4837
4838static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4839 struct scsi_device *sdev)
4840{
4841 if (hba->dev_info.f_power_on_wp_en &&
4842 !hba->dev_info.is_lu_power_on_wp) {
4843 u8 b_lu_write_protect;
4844
4845 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4846 &b_lu_write_protect) &&
4847 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4848 hba->dev_info.is_lu_power_on_wp = true;
4849 }
4850}
4851
4852
4853
4854
4855
4856
4857static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4858{
4859 struct device_link *link;
4860
4861
4862
4863
4864
4865 if (hba->sdev_ufs_device) {
4866 link = device_link_add(&sdev->sdev_gendev,
4867 &hba->sdev_ufs_device->sdev_gendev,
4868 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4869 if (!link) {
4870 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4871 dev_name(&hba->sdev_ufs_device->sdev_gendev));
4872 return;
4873 }
4874 hba->luns_avail--;
4875
4876 if (hba->luns_avail == 1) {
4877 ufshcd_rpm_put(hba);
4878 return;
4879 }
4880 } else {
4881
4882
4883
4884
4885 hba->luns_avail--;
4886 }
4887}
4888
4889
4890
4891
4892
4893
4894
4895static int ufshcd_slave_alloc(struct scsi_device *sdev)
4896{
4897 struct ufs_hba *hba;
4898
4899 hba = shost_priv(sdev->host);
4900
4901
4902 sdev->use_10_for_ms = 1;
4903
4904
4905 sdev->set_dbd_for_ms = 1;
4906
4907
4908 sdev->allow_restart = 1;
4909
4910
4911 sdev->no_report_opcodes = 1;
4912
4913
4914 sdev->no_write_same = 1;
4915
4916 ufshcd_set_queue_depth(sdev);
4917
4918 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4919
4920 ufshcd_setup_links(hba, sdev);
4921
4922 return 0;
4923}
4924
4925
4926
4927
4928
4929
4930
4931
4932static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4933{
4934 struct ufs_hba *hba = shost_priv(sdev->host);
4935
4936 if (depth > hba->nutrs)
4937 depth = hba->nutrs;
4938 return scsi_change_queue_depth(sdev, depth);
4939}
4940
4941static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
4942{
4943
4944 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4945 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
4946 return;
4947
4948 ufshpb_destroy_lu(hba, sdev);
4949}
4950
4951static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
4952{
4953
4954 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
4955 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
4956 return;
4957
4958 ufshpb_init_hpb_lu(hba, sdev);
4959}
4960
4961
4962
4963
4964
4965static int ufshcd_slave_configure(struct scsi_device *sdev)
4966{
4967 struct ufs_hba *hba = shost_priv(sdev->host);
4968 struct request_queue *q = sdev->request_queue;
4969
4970 ufshcd_hpb_configure(hba, sdev);
4971
4972 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4973 if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
4974 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
4975
4976
4977
4978
4979 if (is_device_wlun(sdev))
4980 pm_runtime_get_noresume(&sdev->sdev_gendev);
4981 else if (ufshcd_is_rpm_autosuspend_allowed(hba))
4982 sdev->rpm_autosuspend = 1;
4983
4984 ufshcd_crypto_setup_rq_keyslot_manager(hba, q);
4985
4986 return 0;
4987}
4988
4989
4990
4991
4992
4993static void ufshcd_slave_destroy(struct scsi_device *sdev)
4994{
4995 struct ufs_hba *hba;
4996 unsigned long flags;
4997
4998 hba = shost_priv(sdev->host);
4999
5000 ufshcd_hpb_destroy(hba, sdev);
5001
5002
5003 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5004 spin_lock_irqsave(hba->host->host_lock, flags);
5005 hba->sdev_ufs_device = NULL;
5006 spin_unlock_irqrestore(hba->host->host_lock, flags);
5007 } else if (hba->sdev_ufs_device) {
5008 struct device *supplier = NULL;
5009
5010
5011 spin_lock_irqsave(hba->host->host_lock, flags);
5012 if (hba->sdev_ufs_device) {
5013 supplier = &hba->sdev_ufs_device->sdev_gendev;
5014 get_device(supplier);
5015 }
5016 spin_unlock_irqrestore(hba->host->host_lock, flags);
5017
5018 if (supplier) {
5019
5020
5021
5022
5023
5024 device_link_remove(&sdev->sdev_gendev, supplier);
5025 put_device(supplier);
5026 }
5027 }
5028}
5029
5030
5031
5032
5033
5034
5035
5036
5037static inline int
5038ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5039{
5040 int result = 0;
5041
5042 switch (scsi_status) {
5043 case SAM_STAT_CHECK_CONDITION:
5044 ufshcd_copy_sense_data(lrbp);
5045 fallthrough;
5046 case SAM_STAT_GOOD:
5047 result |= DID_OK << 16 | scsi_status;
5048 break;
5049 case SAM_STAT_TASK_SET_FULL:
5050 case SAM_STAT_BUSY:
5051 case SAM_STAT_TASK_ABORTED:
5052 ufshcd_copy_sense_data(lrbp);
5053 result |= scsi_status;
5054 break;
5055 default:
5056 result |= DID_ERROR << 16;
5057 break;
5058 }
5059
5060 return result;
5061}
5062
5063
5064
5065
5066
5067
5068
5069
5070static inline int
5071ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5072{
5073 int result = 0;
5074 int scsi_status;
5075 int ocs;
5076
5077
5078 ocs = ufshcd_get_tr_ocs(lrbp);
5079
5080 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5081 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5082 MASK_RSP_UPIU_RESULT)
5083 ocs = OCS_SUCCESS;
5084 }
5085
5086 switch (ocs) {
5087 case OCS_SUCCESS:
5088 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
5089 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5090 switch (result) {
5091 case UPIU_TRANSACTION_RESPONSE:
5092
5093
5094
5095
5096 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5097
5098
5099
5100
5101
5102 scsi_status = result & MASK_SCSI_STATUS;
5103 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5104
5105
5106
5107
5108
5109
5110
5111
5112
5113
5114
5115
5116
5117 if (!hba->pm_op_in_progress &&
5118 !ufshcd_eh_in_progress(hba) &&
5119 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5120
5121 schedule_work(&hba->eeh_work);
5122
5123 if (scsi_status == SAM_STAT_GOOD)
5124 ufshpb_rsp_upiu(hba, lrbp);
5125 break;
5126 case UPIU_TRANSACTION_REJECT_UPIU:
5127
5128 result = DID_ERROR << 16;
5129 dev_err(hba->dev,
5130 "Reject UPIU not fully implemented\n");
5131 break;
5132 default:
5133 dev_err(hba->dev,
5134 "Unexpected request response code = %x\n",
5135 result);
5136 result = DID_ERROR << 16;
5137 break;
5138 }
5139 break;
5140 case OCS_ABORTED:
5141 result |= DID_ABORT << 16;
5142 break;
5143 case OCS_INVALID_COMMAND_STATUS:
5144 result |= DID_REQUEUE << 16;
5145 break;
5146 case OCS_INVALID_CMD_TABLE_ATTR:
5147 case OCS_INVALID_PRDT_ATTR:
5148 case OCS_MISMATCH_DATA_BUF_SIZE:
5149 case OCS_MISMATCH_RESP_UPIU_SIZE:
5150 case OCS_PEER_COMM_FAILURE:
5151 case OCS_FATAL_ERROR:
5152 case OCS_DEVICE_FATAL_ERROR:
5153 case OCS_INVALID_CRYPTO_CONFIG:
5154 case OCS_GENERAL_CRYPTO_ERROR:
5155 default:
5156 result |= DID_ERROR << 16;
5157 dev_err(hba->dev,
5158 "OCS error from controller = %x for tag %d\n",
5159 ocs, lrbp->task_tag);
5160 ufshcd_print_evt_hist(hba);
5161 ufshcd_print_host_state(hba);
5162 break;
5163 }
5164
5165 if ((host_byte(result) != DID_OK) &&
5166 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5167 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
5168 return result;
5169}
5170
5171static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5172 u32 intr_mask)
5173{
5174 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5175 !ufshcd_is_auto_hibern8_enabled(hba))
5176 return false;
5177
5178 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5179 return false;
5180
5181 if (hba->active_uic_cmd &&
5182 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5183 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5184 return false;
5185
5186 return true;
5187}
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197
5198static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5199{
5200 irqreturn_t retval = IRQ_NONE;
5201
5202 spin_lock(hba->host->host_lock);
5203 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5204 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5205
5206 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5207 hba->active_uic_cmd->argument2 |=
5208 ufshcd_get_uic_cmd_result(hba);
5209 hba->active_uic_cmd->argument3 =
5210 ufshcd_get_dme_attr_val(hba);
5211 if (!hba->uic_async_done)
5212 hba->active_uic_cmd->cmd_active = 0;
5213 complete(&hba->active_uic_cmd->done);
5214 retval = IRQ_HANDLED;
5215 }
5216
5217 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5218 hba->active_uic_cmd->cmd_active = 0;
5219 complete(hba->uic_async_done);
5220 retval = IRQ_HANDLED;
5221 }
5222
5223 if (retval == IRQ_HANDLED)
5224 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5225 UFS_CMD_COMP);
5226 spin_unlock(hba->host->host_lock);
5227 return retval;
5228}
5229
5230
5231
5232
5233
5234
5235
5236static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5237 unsigned long completed_reqs,
5238 bool retry_requests)
5239{
5240 struct ufshcd_lrb *lrbp;
5241 struct scsi_cmnd *cmd;
5242 int result;
5243 int index;
5244 bool update_scaling = false;
5245
5246 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5247 lrbp = &hba->lrb[index];
5248 lrbp->compl_time_stamp = ktime_get();
5249 cmd = lrbp->cmd;
5250 if (cmd) {
5251 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5252 ufshcd_update_monitor(hba, lrbp);
5253 ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
5254 result = retry_requests ? DID_BUS_BUSY << 16 :
5255 ufshcd_transfer_rsp_status(hba, lrbp);
5256 scsi_dma_unmap(cmd);
5257 cmd->result = result;
5258
5259 lrbp->cmd = NULL;
5260
5261 cmd->scsi_done(cmd);
5262 ufshcd_release(hba);
5263 update_scaling = true;
5264 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5265 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5266 if (hba->dev_cmd.complete) {
5267 ufshcd_add_command_trace(hba, index,
5268 UFS_DEV_COMP);
5269 complete(hba->dev_cmd.complete);
5270 update_scaling = true;
5271 }
5272 }
5273 if (update_scaling)
5274 ufshcd_clk_scaling_update_busy(hba);
5275 }
5276}
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba,
5288 bool retry_requests)
5289{
5290 unsigned long completed_reqs, flags;
5291 u32 tr_doorbell;
5292
5293
5294
5295
5296
5297
5298
5299
5300 if (ufshcd_is_intr_aggr_allowed(hba) &&
5301 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5302 ufshcd_reset_intr_aggr(hba);
5303
5304 if (ufs_fail_completion())
5305 return IRQ_HANDLED;
5306
5307 spin_lock_irqsave(&hba->outstanding_lock, flags);
5308 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5309 completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5310 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5311 "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5312 hba->outstanding_reqs);
5313 hba->outstanding_reqs &= ~completed_reqs;
5314 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5315
5316 if (completed_reqs) {
5317 __ufshcd_transfer_req_compl(hba, completed_reqs,
5318 retry_requests);
5319 return IRQ_HANDLED;
5320 } else {
5321 return IRQ_NONE;
5322 }
5323}
5324
5325int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5326{
5327 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5328 QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5329 &ee_ctrl_mask);
5330}
5331
5332int ufshcd_write_ee_control(struct ufs_hba *hba)
5333{
5334 int err;
5335
5336 mutex_lock(&hba->ee_ctrl_mutex);
5337 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5338 mutex_unlock(&hba->ee_ctrl_mutex);
5339 if (err)
5340 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5341 __func__, err);
5342 return err;
5343}
5344
5345int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask,
5346 u16 set, u16 clr)
5347{
5348 u16 new_mask, ee_ctrl_mask;
5349 int err = 0;
5350
5351 mutex_lock(&hba->ee_ctrl_mutex);
5352 new_mask = (*mask & ~clr) | set;
5353 ee_ctrl_mask = new_mask | *other_mask;
5354 if (ee_ctrl_mask != hba->ee_ctrl_mask)
5355 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5356
5357 if (!err) {
5358 hba->ee_ctrl_mask = ee_ctrl_mask;
5359 *mask = new_mask;
5360 }
5361 mutex_unlock(&hba->ee_ctrl_mutex);
5362 return err;
5363}
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5376{
5377 return ufshcd_update_ee_drv_mask(hba, 0, mask);
5378}
5379
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5391{
5392 return ufshcd_update_ee_drv_mask(hba, mask, 0);
5393}
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405
5406static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5407{
5408 int err = 0;
5409
5410 if (hba->auto_bkops_enabled)
5411 goto out;
5412
5413 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5414 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5415 if (err) {
5416 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5417 __func__, err);
5418 goto out;
5419 }
5420
5421 hba->auto_bkops_enabled = true;
5422 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5423
5424
5425 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5426 if (err)
5427 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5428 __func__, err);
5429out:
5430 return err;
5431}
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5446{
5447 int err = 0;
5448
5449 if (!hba->auto_bkops_enabled)
5450 goto out;
5451
5452
5453
5454
5455
5456 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5457 if (err) {
5458 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5459 __func__, err);
5460 goto out;
5461 }
5462
5463 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5464 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5465 if (err) {
5466 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5467 __func__, err);
5468 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5469 goto out;
5470 }
5471
5472 hba->auto_bkops_enabled = false;
5473 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5474 hba->is_urgent_bkops_lvl_checked = false;
5475out:
5476 return err;
5477}
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487
5488static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5489{
5490 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5491 hba->auto_bkops_enabled = false;
5492 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5493 ufshcd_enable_auto_bkops(hba);
5494 } else {
5495 hba->auto_bkops_enabled = true;
5496 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5497 ufshcd_disable_auto_bkops(hba);
5498 }
5499 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5500 hba->is_urgent_bkops_lvl_checked = false;
5501}
5502
5503static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5504{
5505 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5506 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5507}
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523
5524
5525static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5526 enum bkops_status status)
5527{
5528 int err;
5529 u32 curr_status = 0;
5530
5531 err = ufshcd_get_bkops_status(hba, &curr_status);
5532 if (err) {
5533 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5534 __func__, err);
5535 goto out;
5536 } else if (curr_status > BKOPS_STATUS_MAX) {
5537 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5538 __func__, curr_status);
5539 err = -EINVAL;
5540 goto out;
5541 }
5542
5543 if (curr_status >= status)
5544 err = ufshcd_enable_auto_bkops(hba);
5545 else
5546 err = ufshcd_disable_auto_bkops(hba);
5547out:
5548 return err;
5549}
5550
5551
5552
5553
5554
5555
5556
5557
5558
5559
5560
5561static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5562{
5563 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5564}
5565
5566static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5567{
5568 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5569 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5570}
5571
5572static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5573{
5574 int err;
5575 u32 curr_status = 0;
5576
5577 if (hba->is_urgent_bkops_lvl_checked)
5578 goto enable_auto_bkops;
5579
5580 err = ufshcd_get_bkops_status(hba, &curr_status);
5581 if (err) {
5582 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5583 __func__, err);
5584 goto out;
5585 }
5586
5587
5588
5589
5590
5591
5592
5593 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5594 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5595 __func__, curr_status);
5596
5597 hba->urgent_bkops_lvl = curr_status;
5598 hba->is_urgent_bkops_lvl_checked = true;
5599 }
5600
5601enable_auto_bkops:
5602 err = ufshcd_enable_auto_bkops(hba);
5603out:
5604 if (err < 0)
5605 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5606 __func__, err);
5607}
5608
5609static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5610{
5611 u8 index;
5612 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5613 UPIU_QUERY_OPCODE_CLEAR_FLAG;
5614
5615 index = ufshcd_wb_get_query_index(hba);
5616 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5617}
5618
5619int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5620{
5621 int ret;
5622
5623 if (!ufshcd_is_wb_allowed(hba))
5624 return 0;
5625
5626 if (!(enable ^ hba->dev_info.wb_enabled))
5627 return 0;
5628
5629 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
5630 if (ret) {
5631 dev_err(hba->dev, "%s Write Booster %s failed %d\n",
5632 __func__, enable ? "enable" : "disable", ret);
5633 return ret;
5634 }
5635
5636 hba->dev_info.wb_enabled = enable;
5637 dev_info(hba->dev, "%s Write Booster %s\n",
5638 __func__, enable ? "enabled" : "disabled");
5639
5640 return ret;
5641}
5642
5643static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5644{
5645 int ret;
5646
5647 ret = __ufshcd_wb_toggle(hba, set,
5648 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5649 if (ret) {
5650 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed: %d\n",
5651 __func__, set ? "enable" : "disable", ret);
5652 return;
5653 }
5654 dev_dbg(hba->dev, "%s WB-Buf Flush during H8 %s\n",
5655 __func__, set ? "enabled" : "disabled");
5656}
5657
5658static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5659{
5660 int ret;
5661
5662 if (!ufshcd_is_wb_allowed(hba) ||
5663 hba->dev_info.wb_buf_flush_enabled == enable)
5664 return;
5665
5666 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
5667 if (ret) {
5668 dev_err(hba->dev, "%s WB-Buf Flush %s failed %d\n", __func__,
5669 enable ? "enable" : "disable", ret);
5670 return;
5671 }
5672
5673 hba->dev_info.wb_buf_flush_enabled = enable;
5674
5675 dev_dbg(hba->dev, "%s WB-Buf Flush %s\n",
5676 __func__, enable ? "enabled" : "disabled");
5677}
5678
5679static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5680 u32 avail_buf)
5681{
5682 u32 cur_buf;
5683 int ret;
5684 u8 index;
5685
5686 index = ufshcd_wb_get_query_index(hba);
5687 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5688 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5689 index, 0, &cur_buf);
5690 if (ret) {
5691 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5692 __func__, ret);
5693 return false;
5694 }
5695
5696 if (!cur_buf) {
5697 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5698 cur_buf);
5699 return false;
5700 }
5701
5702 if (avail_buf < hba->vps->wb_flush_threshold)
5703 return true;
5704
5705 return false;
5706}
5707
5708static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
5709{
5710 int ret;
5711 u32 avail_buf;
5712 u8 index;
5713
5714 if (!ufshcd_is_wb_allowed(hba))
5715 return false;
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725
5726
5727 index = ufshcd_wb_get_query_index(hba);
5728 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5729 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
5730 index, 0, &avail_buf);
5731 if (ret) {
5732 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5733 __func__, ret);
5734 return false;
5735 }
5736
5737 if (!hba->dev_info.b_presrv_uspc_en) {
5738 if (avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10))
5739 return true;
5740 return false;
5741 }
5742
5743 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5744}
5745
5746static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5747{
5748 struct ufs_hba *hba = container_of(to_delayed_work(work),
5749 struct ufs_hba,
5750 rpm_dev_flush_recheck_work);
5751
5752
5753
5754
5755
5756
5757 ufshcd_rpm_get_sync(hba);
5758 ufshcd_rpm_put_sync(hba);
5759}
5760
5761
5762
5763
5764
5765
5766
5767
5768static void ufshcd_exception_event_handler(struct work_struct *work)
5769{
5770 struct ufs_hba *hba;
5771 int err;
5772 u32 status = 0;
5773 hba = container_of(work, struct ufs_hba, eeh_work);
5774
5775 ufshcd_scsi_block_requests(hba);
5776 err = ufshcd_get_ee_status(hba, &status);
5777 if (err) {
5778 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5779 __func__, err);
5780 goto out;
5781 }
5782
5783 trace_ufshcd_exception_event(dev_name(hba->dev), status);
5784
5785 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
5786 ufshcd_bkops_exception_event_handler(hba);
5787
5788 ufs_debugfs_exception_event(hba, status);
5789out:
5790 ufshcd_scsi_unblock_requests(hba);
5791 return;
5792}
5793
5794
5795static void ufshcd_complete_requests(struct ufs_hba *hba)
5796{
5797 ufshcd_transfer_req_compl(hba, false);
5798 ufshcd_tmc_handler(hba);
5799}
5800
5801static void ufshcd_retry_aborted_requests(struct ufs_hba *hba)
5802{
5803 ufshcd_transfer_req_compl(hba, true);
5804 ufshcd_tmc_handler(hba);
5805}
5806
5807
5808
5809
5810
5811
5812
5813
5814static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5815{
5816 unsigned long flags;
5817 bool err_handling = true;
5818
5819 spin_lock_irqsave(hba->host->host_lock, flags);
5820
5821
5822
5823
5824 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5825 goto out;
5826
5827 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5828 ((hba->saved_err & UIC_ERROR) &&
5829 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5830 goto out;
5831
5832 if ((hba->saved_err & UIC_ERROR) &&
5833 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5834 int err;
5835
5836
5837
5838 spin_unlock_irqrestore(hba->host->host_lock, flags);
5839 msleep(50);
5840 spin_lock_irqsave(hba->host->host_lock, flags);
5841
5842
5843
5844
5845
5846 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5847 ((hba->saved_err & UIC_ERROR) &&
5848 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5849 goto out;
5850
5851
5852
5853
5854
5855
5856
5857
5858 spin_unlock_irqrestore(hba->host->host_lock, flags);
5859 err = ufshcd_verify_dev_init(hba);
5860 spin_lock_irqsave(hba->host->host_lock, flags);
5861
5862 if (err)
5863 goto out;
5864
5865
5866 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5867 hba->saved_err &= ~UIC_ERROR;
5868
5869 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5870 if (!hba->saved_uic_err)
5871 err_handling = false;
5872 }
5873out:
5874 spin_unlock_irqrestore(hba->host->host_lock, flags);
5875 return err_handling;
5876}
5877
5878
5879static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
5880{
5881 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
5882 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
5883}
5884
5885
5886static inline void ufshcd_schedule_eh_work(struct ufs_hba *hba)
5887{
5888
5889 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
5890 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
5891 ufshcd_is_saved_err_fatal(hba))
5892 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
5893 else
5894 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
5895 queue_work(hba->eh_wq, &hba->eh_work);
5896 }
5897}
5898
5899static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
5900{
5901 down_write(&hba->clk_scaling_lock);
5902 hba->clk_scaling.is_allowed = allow;
5903 up_write(&hba->clk_scaling_lock);
5904}
5905
5906static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
5907{
5908 if (suspend) {
5909 if (hba->clk_scaling.is_enabled)
5910 ufshcd_suspend_clkscaling(hba);
5911 ufshcd_clk_scaling_allow(hba, false);
5912 } else {
5913 ufshcd_clk_scaling_allow(hba, true);
5914 if (hba->clk_scaling.is_enabled)
5915 ufshcd_resume_clkscaling(hba);
5916 }
5917}
5918
5919static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
5920{
5921 ufshcd_rpm_get_sync(hba);
5922 if (pm_runtime_status_suspended(&hba->sdev_ufs_device->sdev_gendev) ||
5923 hba->is_sys_suspended) {
5924 enum ufs_pm_op pm_op;
5925
5926
5927
5928
5929
5930
5931 ufshcd_setup_hba_vreg(hba, true);
5932 ufshcd_enable_irq(hba);
5933 ufshcd_setup_vreg(hba, true);
5934 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5935 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5936 ufshcd_hold(hba, false);
5937 if (!ufshcd_is_clkgating_allowed(hba))
5938 ufshcd_setup_clocks(hba, true);
5939 ufshcd_release(hba);
5940 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
5941 ufshcd_vops_resume(hba, pm_op);
5942 } else {
5943 ufshcd_hold(hba, false);
5944 if (ufshcd_is_clkscaling_supported(hba) &&
5945 hba->clk_scaling.is_enabled)
5946 ufshcd_suspend_clkscaling(hba);
5947 ufshcd_clk_scaling_allow(hba, false);
5948 }
5949 ufshcd_scsi_block_requests(hba);
5950
5951 down_write(&hba->clk_scaling_lock);
5952 up_write(&hba->clk_scaling_lock);
5953 cancel_work_sync(&hba->eeh_work);
5954}
5955
5956static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
5957{
5958 ufshcd_scsi_unblock_requests(hba);
5959 ufshcd_release(hba);
5960 if (ufshcd_is_clkscaling_supported(hba))
5961 ufshcd_clk_scaling_suspend(hba, false);
5962 ufshcd_clear_ua_wluns(hba);
5963 ufshcd_rpm_put(hba);
5964}
5965
5966static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
5967{
5968 return (!hba->is_powered || hba->shutting_down ||
5969 !hba->sdev_ufs_device ||
5970 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
5971 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
5972 ufshcd_is_link_broken(hba))));
5973}
5974
5975#ifdef CONFIG_PM
5976static void ufshcd_recover_pm_error(struct ufs_hba *hba)
5977{
5978 struct Scsi_Host *shost = hba->host;
5979 struct scsi_device *sdev;
5980 struct request_queue *q;
5981 int ret;
5982
5983 hba->is_sys_suspended = false;
5984
5985
5986
5987
5988 ret = pm_runtime_set_active(&hba->sdev_ufs_device->sdev_gendev);
5989
5990
5991 if (ret)
5992 ret = pm_runtime_set_active(hba->dev);
5993
5994
5995
5996
5997
5998
5999 if (!ret) {
6000 shost_for_each_device(sdev, shost) {
6001 q = sdev->request_queue;
6002 if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6003 q->rpm_status == RPM_SUSPENDING))
6004 pm_request_resume(q->dev);
6005 }
6006 }
6007}
6008#else
6009static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6010{
6011}
6012#endif
6013
6014static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6015{
6016 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6017 u32 mode;
6018
6019 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6020
6021 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6022 return true;
6023
6024 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6025 return true;
6026
6027 return false;
6028}
6029
6030
6031
6032
6033
6034static void ufshcd_err_handler(struct work_struct *work)
6035{
6036 struct ufs_hba *hba;
6037 unsigned long flags;
6038 bool err_xfer = false;
6039 bool err_tm = false;
6040 int err = 0, pmc_err;
6041 int tag;
6042 bool needs_reset = false, needs_restore = false;
6043
6044 hba = container_of(work, struct ufs_hba, eh_work);
6045
6046 down(&hba->host_sem);
6047 spin_lock_irqsave(hba->host->host_lock, flags);
6048 if (ufshcd_err_handling_should_stop(hba)) {
6049 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6050 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6051 spin_unlock_irqrestore(hba->host->host_lock, flags);
6052 up(&hba->host_sem);
6053 return;
6054 }
6055 ufshcd_set_eh_in_progress(hba);
6056 spin_unlock_irqrestore(hba->host->host_lock, flags);
6057 ufshcd_err_handling_prepare(hba);
6058
6059 ufshcd_complete_requests(hba);
6060 spin_lock_irqsave(hba->host->host_lock, flags);
6061 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6062 hba->ufshcd_state = UFSHCD_STATE_RESET;
6063
6064
6065
6066
6067 if (ufshcd_err_handling_should_stop(hba))
6068 goto skip_err_handling;
6069
6070 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6071 bool ret;
6072
6073 spin_unlock_irqrestore(hba->host->host_lock, flags);
6074
6075 ret = ufshcd_quirk_dl_nac_errors(hba);
6076 spin_lock_irqsave(hba->host->host_lock, flags);
6077 if (!ret && ufshcd_err_handling_should_stop(hba))
6078 goto skip_err_handling;
6079 }
6080
6081 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6082 (hba->saved_uic_err &&
6083 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6084 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6085
6086 spin_unlock_irqrestore(hba->host->host_lock, flags);
6087 ufshcd_print_host_state(hba);
6088 ufshcd_print_pwr_info(hba);
6089 ufshcd_print_evt_hist(hba);
6090 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6091 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6092 spin_lock_irqsave(hba->host->host_lock, flags);
6093 }
6094
6095
6096
6097
6098
6099
6100 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6101 ufshcd_is_saved_err_fatal(hba) ||
6102 ((hba->saved_err & UIC_ERROR) &&
6103 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6104 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6105 needs_reset = true;
6106 goto do_reset;
6107 }
6108
6109
6110
6111
6112
6113 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6114 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6115 if (!hba->saved_uic_err)
6116 hba->saved_err &= ~UIC_ERROR;
6117 spin_unlock_irqrestore(hba->host->host_lock, flags);
6118 if (ufshcd_is_pwr_mode_restore_needed(hba))
6119 needs_restore = true;
6120 spin_lock_irqsave(hba->host->host_lock, flags);
6121 if (!hba->saved_err && !needs_restore)
6122 goto skip_err_handling;
6123 }
6124
6125 hba->silence_err_logs = true;
6126
6127 spin_unlock_irqrestore(hba->host->host_lock, flags);
6128
6129 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
6130 if (ufshcd_try_to_abort_task(hba, tag)) {
6131 err_xfer = true;
6132 goto lock_skip_pending_xfer_clear;
6133 }
6134 }
6135
6136
6137 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6138 if (ufshcd_clear_tm_cmd(hba, tag)) {
6139 err_tm = true;
6140 goto lock_skip_pending_xfer_clear;
6141 }
6142 }
6143
6144lock_skip_pending_xfer_clear:
6145 ufshcd_retry_aborted_requests(hba);
6146
6147 spin_lock_irqsave(hba->host->host_lock, flags);
6148 hba->silence_err_logs = false;
6149 if (err_xfer || err_tm) {
6150 needs_reset = true;
6151 goto do_reset;
6152 }
6153
6154
6155
6156
6157
6158 if (needs_restore) {
6159 spin_unlock_irqrestore(hba->host->host_lock, flags);
6160
6161
6162
6163
6164 down_write(&hba->clk_scaling_lock);
6165 hba->force_pmc = true;
6166 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6167 if (pmc_err) {
6168 needs_reset = true;
6169 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6170 __func__, pmc_err);
6171 }
6172 hba->force_pmc = false;
6173 ufshcd_print_pwr_info(hba);
6174 up_write(&hba->clk_scaling_lock);
6175 spin_lock_irqsave(hba->host->host_lock, flags);
6176 }
6177
6178do_reset:
6179
6180 if (needs_reset) {
6181 hba->force_reset = false;
6182 spin_unlock_irqrestore(hba->host->host_lock, flags);
6183 err = ufshcd_reset_and_restore(hba);
6184 if (err)
6185 dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6186 __func__, err);
6187 else
6188 ufshcd_recover_pm_error(hba);
6189 spin_lock_irqsave(hba->host->host_lock, flags);
6190 }
6191
6192skip_err_handling:
6193 if (!needs_reset) {
6194 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6195 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6196 if (hba->saved_err || hba->saved_uic_err)
6197 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6198 __func__, hba->saved_err, hba->saved_uic_err);
6199 }
6200 ufshcd_clear_eh_in_progress(hba);
6201 spin_unlock_irqrestore(hba->host->host_lock, flags);
6202 ufshcd_err_handling_unprepare(hba);
6203 up(&hba->host_sem);
6204}
6205
6206
6207
6208
6209
6210
6211
6212
6213
6214static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6215{
6216 u32 reg;
6217 irqreturn_t retval = IRQ_NONE;
6218
6219
6220 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6221 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6222 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6223 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6224
6225
6226
6227
6228 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6229 dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6230 __func__);
6231
6232
6233 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6234 struct uic_command *cmd = NULL;
6235
6236 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6237 if (hba->uic_async_done && hba->active_uic_cmd)
6238 cmd = hba->active_uic_cmd;
6239
6240
6241
6242
6243 if (cmd && (cmd->command == UIC_CMD_DME_SET))
6244 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6245 }
6246 retval |= IRQ_HANDLED;
6247 }
6248
6249
6250 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6251 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6252 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6253 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6254
6255 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6256 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6257 else if (hba->dev_quirks &
6258 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6259 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6260 hba->uic_error |=
6261 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6262 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6263 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6264 }
6265 retval |= IRQ_HANDLED;
6266 }
6267
6268
6269 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6270 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6271 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6272 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6273 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6274 retval |= IRQ_HANDLED;
6275 }
6276
6277 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6278 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6279 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6280 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6281 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6282 retval |= IRQ_HANDLED;
6283 }
6284
6285 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6286 if ((reg & UIC_DME_ERROR) &&
6287 (reg & UIC_DME_ERROR_CODE_MASK)) {
6288 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6289 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6290 retval |= IRQ_HANDLED;
6291 }
6292
6293 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6294 __func__, hba->uic_error);
6295 return retval;
6296}
6297
6298
6299
6300
6301
6302
6303
6304
6305
6306
6307static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6308{
6309 bool queue_eh_work = false;
6310 irqreturn_t retval = IRQ_NONE;
6311
6312 spin_lock(hba->host->host_lock);
6313 hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6314
6315 if (hba->errors & INT_FATAL_ERRORS) {
6316 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6317 hba->errors);
6318 queue_eh_work = true;
6319 }
6320
6321 if (hba->errors & UIC_ERROR) {
6322 hba->uic_error = 0;
6323 retval = ufshcd_update_uic_error(hba);
6324 if (hba->uic_error)
6325 queue_eh_work = true;
6326 }
6327
6328 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6329 dev_err(hba->dev,
6330 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6331 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6332 "Enter" : "Exit",
6333 hba->errors, ufshcd_get_upmcrs(hba));
6334 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6335 hba->errors);
6336 ufshcd_set_link_broken(hba);
6337 queue_eh_work = true;
6338 }
6339
6340 if (queue_eh_work) {
6341
6342
6343
6344
6345 hba->saved_err |= hba->errors;
6346 hba->saved_uic_err |= hba->uic_error;
6347
6348
6349 if ((hba->saved_err &
6350 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6351 (hba->saved_uic_err &&
6352 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6353 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6354 __func__, hba->saved_err,
6355 hba->saved_uic_err);
6356 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6357 "host_regs: ");
6358 ufshcd_print_pwr_info(hba);
6359 }
6360 ufshcd_schedule_eh_work(hba);
6361 retval |= IRQ_HANDLED;
6362 }
6363
6364
6365
6366
6367
6368
6369 hba->errors = 0;
6370 hba->uic_error = 0;
6371 spin_unlock(hba->host->host_lock);
6372 return retval;
6373}
6374
6375
6376
6377
6378
6379
6380
6381
6382
6383static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6384{
6385 unsigned long flags, pending, issued;
6386 irqreturn_t ret = IRQ_NONE;
6387 int tag;
6388
6389 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6390
6391 spin_lock_irqsave(hba->host->host_lock, flags);
6392 issued = hba->outstanding_tasks & ~pending;
6393 for_each_set_bit(tag, &issued, hba->nutmrs) {
6394 struct request *req = hba->tmf_rqs[tag];
6395 struct completion *c = req->end_io_data;
6396
6397 complete(c);
6398 ret = IRQ_HANDLED;
6399 }
6400 spin_unlock_irqrestore(hba->host->host_lock, flags);
6401
6402 return ret;
6403}
6404
6405
6406
6407
6408
6409
6410
6411
6412
6413
6414static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6415{
6416 irqreturn_t retval = IRQ_NONE;
6417
6418 if (intr_status & UFSHCD_UIC_MASK)
6419 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6420
6421 if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6422 retval |= ufshcd_check_errors(hba, intr_status);
6423
6424 if (intr_status & UTP_TASK_REQ_COMPL)
6425 retval |= ufshcd_tmc_handler(hba);
6426
6427 if (intr_status & UTP_TRANSFER_REQ_COMPL)
6428 retval |= ufshcd_transfer_req_compl(hba, false);
6429
6430 return retval;
6431}
6432
6433
6434
6435
6436
6437
6438
6439
6440
6441
6442static irqreturn_t ufshcd_intr(int irq, void *__hba)
6443{
6444 u32 intr_status, enabled_intr_status = 0;
6445 irqreturn_t retval = IRQ_NONE;
6446 struct ufs_hba *hba = __hba;
6447 int retries = hba->nutrs;
6448
6449 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6450 hba->ufs_stats.last_intr_status = intr_status;
6451 hba->ufs_stats.last_intr_ts = ktime_get();
6452
6453
6454
6455
6456
6457
6458
6459 while (intr_status && retries--) {
6460 enabled_intr_status =
6461 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6462 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6463 if (enabled_intr_status)
6464 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6465
6466 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6467 }
6468
6469 if (enabled_intr_status && retval == IRQ_NONE &&
6470 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6471 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6472 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6473 __func__,
6474 intr_status,
6475 hba->ufs_stats.last_intr_status,
6476 enabled_intr_status);
6477 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6478 }
6479
6480 return retval;
6481}
6482
6483static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6484{
6485 int err = 0;
6486 u32 mask = 1 << tag;
6487 unsigned long flags;
6488
6489 if (!test_bit(tag, &hba->outstanding_tasks))
6490 goto out;
6491
6492 spin_lock_irqsave(hba->host->host_lock, flags);
6493 ufshcd_utmrl_clear(hba, tag);
6494 spin_unlock_irqrestore(hba->host->host_lock, flags);
6495
6496
6497 err = ufshcd_wait_for_register(hba,
6498 REG_UTP_TASK_REQ_DOOR_BELL,
6499 mask, 0, 1000, 1000);
6500out:
6501 return err;
6502}
6503
6504static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6505 struct utp_task_req_desc *treq, u8 tm_function)
6506{
6507 struct request_queue *q = hba->tmf_queue;
6508 struct Scsi_Host *host = hba->host;
6509 DECLARE_COMPLETION_ONSTACK(wait);
6510 struct request *req;
6511 unsigned long flags;
6512 int task_tag, err;
6513
6514
6515
6516
6517 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6518 if (IS_ERR(req))
6519 return PTR_ERR(req);
6520
6521 req->end_io_data = &wait;
6522 ufshcd_hold(hba, false);
6523
6524 spin_lock_irqsave(host->host_lock, flags);
6525
6526 task_tag = req->tag;
6527 hba->tmf_rqs[req->tag] = req;
6528 treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
6529
6530 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6531 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
6532
6533
6534 __set_bit(task_tag, &hba->outstanding_tasks);
6535
6536 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
6537
6538 wmb();
6539
6540 spin_unlock_irqrestore(host->host_lock, flags);
6541
6542 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6543
6544
6545 err = wait_for_completion_io_timeout(&wait,
6546 msecs_to_jiffies(TM_CMD_TIMEOUT));
6547 if (!err) {
6548
6549
6550
6551
6552 req->end_io_data = NULL;
6553 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
6554 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6555 __func__, tm_function);
6556 if (ufshcd_clear_tm_cmd(hba, task_tag))
6557 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6558 __func__, task_tag);
6559 err = -ETIMEDOUT;
6560 } else {
6561 err = 0;
6562 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
6563
6564 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
6565 }
6566
6567 spin_lock_irqsave(hba->host->host_lock, flags);
6568 hba->tmf_rqs[req->tag] = NULL;
6569 __clear_bit(task_tag, &hba->outstanding_tasks);
6570 spin_unlock_irqrestore(hba->host->host_lock, flags);
6571
6572 ufshcd_release(hba);
6573 blk_put_request(req);
6574
6575 return err;
6576}
6577
6578
6579
6580
6581
6582
6583
6584
6585
6586
6587
6588static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6589 u8 tm_function, u8 *tm_response)
6590{
6591 struct utp_task_req_desc treq = { { 0 }, };
6592 int ocs_value, err;
6593
6594
6595 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6596 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6597
6598
6599 treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6600 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6601 treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6602
6603
6604
6605
6606
6607 treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6608 treq.upiu_req.input_param2 = cpu_to_be32(task_id);
6609
6610 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6611 if (err == -ETIMEDOUT)
6612 return err;
6613
6614 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6615 if (ocs_value != OCS_SUCCESS)
6616 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6617 __func__, ocs_value);
6618 else if (tm_response)
6619 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
6620 MASK_TM_SERVICE_RESP;
6621 return err;
6622}
6623
6624
6625
6626
6627
6628
6629
6630
6631
6632
6633
6634
6635
6636
6637
6638
6639
6640
6641static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6642 struct utp_upiu_req *req_upiu,
6643 struct utp_upiu_req *rsp_upiu,
6644 u8 *desc_buff, int *buff_len,
6645 enum dev_cmd_type cmd_type,
6646 enum query_opcode desc_op)
6647{
6648 struct request_queue *q = hba->cmd_queue;
6649 DECLARE_COMPLETION_ONSTACK(wait);
6650 struct request *req;
6651 struct ufshcd_lrb *lrbp;
6652 int err = 0;
6653 int tag;
6654 u8 upiu_flags;
6655
6656 down_read(&hba->clk_scaling_lock);
6657
6658 req = blk_get_request(q, REQ_OP_DRV_OUT, 0);
6659 if (IS_ERR(req)) {
6660 err = PTR_ERR(req);
6661 goto out_unlock;
6662 }
6663 tag = req->tag;
6664 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
6665
6666 if (unlikely(test_bit(tag, &hba->outstanding_reqs))) {
6667 err = -EBUSY;
6668 goto out;
6669 }
6670
6671 lrbp = &hba->lrb[tag];
6672 WARN_ON(lrbp->cmd);
6673 lrbp->cmd = NULL;
6674 lrbp->sense_bufflen = 0;
6675 lrbp->sense_buffer = NULL;
6676 lrbp->task_tag = tag;
6677 lrbp->lun = 0;
6678 lrbp->intr_cmd = true;
6679 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
6680 hba->dev_cmd.type = cmd_type;
6681
6682 if (hba->ufs_version <= ufshci_version(1, 1))
6683 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
6684 else
6685 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
6686
6687
6688 req_upiu->header.dword_0 |= cpu_to_be32(tag);
6689
6690 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6691
6692
6693 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6694 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6695
6696
6697
6698
6699 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6700 *buff_len = 0;
6701 }
6702
6703 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6704
6705 hba->dev_cmd.complete = &wait;
6706
6707 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
6708
6709 ufshcd_send_command(hba, tag);
6710
6711
6712
6713
6714
6715 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6716
6717
6718 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
6719 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6720 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6721 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6722 MASK_QUERY_DATA_SEG_LEN;
6723
6724 if (*buff_len >= resp_len) {
6725 memcpy(desc_buff, descp, resp_len);
6726 *buff_len = resp_len;
6727 } else {
6728 dev_warn(hba->dev,
6729 "%s: rsp size %d is bigger than buffer size %d",
6730 __func__, resp_len, *buff_len);
6731 *buff_len = 0;
6732 err = -EINVAL;
6733 }
6734 }
6735 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6736 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6737
6738out:
6739 blk_put_request(req);
6740out_unlock:
6741 up_read(&hba->clk_scaling_lock);
6742 return err;
6743}
6744
6745
6746
6747
6748
6749
6750
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6761 struct utp_upiu_req *req_upiu,
6762 struct utp_upiu_req *rsp_upiu,
6763 int msgcode,
6764 u8 *desc_buff, int *buff_len,
6765 enum query_opcode desc_op)
6766{
6767 int err;
6768 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
6769 struct utp_task_req_desc treq = { { 0 }, };
6770 int ocs_value;
6771 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6772
6773 switch (msgcode) {
6774 case UPIU_TRANSACTION_NOP_OUT:
6775 cmd_type = DEV_CMD_TYPE_NOP;
6776 fallthrough;
6777 case UPIU_TRANSACTION_QUERY_REQ:
6778 ufshcd_hold(hba, false);
6779 mutex_lock(&hba->dev_cmd.lock);
6780 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6781 desc_buff, buff_len,
6782 cmd_type, desc_op);
6783 mutex_unlock(&hba->dev_cmd.lock);
6784 ufshcd_release(hba);
6785
6786 break;
6787 case UPIU_TRANSACTION_TASK_REQ:
6788 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6789 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6790
6791 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
6792
6793 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6794 if (err == -ETIMEDOUT)
6795 break;
6796
6797 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6798 if (ocs_value != OCS_SUCCESS) {
6799 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6800 ocs_value);
6801 break;
6802 }
6803
6804 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
6805
6806 break;
6807 default:
6808 err = -EINVAL;
6809
6810 break;
6811 }
6812
6813 return err;
6814}
6815
6816
6817
6818
6819
6820
6821
6822
6823static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
6824{
6825 struct Scsi_Host *host;
6826 struct ufs_hba *hba;
6827 u32 pos;
6828 int err;
6829 u8 resp = 0xF, lun;
6830
6831 host = cmd->device->host;
6832 hba = shost_priv(host);
6833
6834 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
6835 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
6836 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6837 if (!err)
6838 err = resp;
6839 goto out;
6840 }
6841
6842
6843 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6844 if (hba->lrb[pos].lun == lun) {
6845 err = ufshcd_clear_cmd(hba, pos);
6846 if (err)
6847 break;
6848 __ufshcd_transfer_req_compl(hba, 1U << pos, false);
6849 }
6850 }
6851
6852out:
6853 hba->req_abort_count = 0;
6854 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
6855 if (!err) {
6856 err = SUCCESS;
6857 } else {
6858 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6859 err = FAILED;
6860 }
6861 return err;
6862}
6863
6864static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
6865{
6866 struct ufshcd_lrb *lrbp;
6867 int tag;
6868
6869 for_each_set_bit(tag, &bitmap, hba->nutrs) {
6870 lrbp = &hba->lrb[tag];
6871 lrbp->req_abort_skip = true;
6872 }
6873}
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884
6885
6886
6887
6888static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
6889{
6890 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6891 int err = 0;
6892 int poll_cnt;
6893 u8 resp = 0xF;
6894 u32 reg;
6895
6896 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6897 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6898 UFS_QUERY_TASK, &resp);
6899 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6900
6901 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6902 __func__, tag);
6903 break;
6904 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6905
6906
6907
6908
6909 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6910 __func__, tag);
6911 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6912 if (reg & (1 << tag)) {
6913
6914 usleep_range(100, 200);
6915 continue;
6916 }
6917
6918 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6919 __func__, tag);
6920 goto out;
6921 } else {
6922 dev_err(hba->dev,
6923 "%s: no response from device. tag = %d, err %d\n",
6924 __func__, tag, err);
6925 if (!err)
6926 err = resp;
6927 goto out;
6928 }
6929 }
6930
6931 if (!poll_cnt) {
6932 err = -EBUSY;
6933 goto out;
6934 }
6935
6936 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6937 UFS_ABORT_TASK, &resp);
6938 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6939 if (!err) {
6940 err = resp;
6941 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6942 __func__, tag, err);
6943 }
6944 goto out;
6945 }
6946
6947 err = ufshcd_clear_cmd(hba, tag);
6948 if (err)
6949 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6950 __func__, tag, err);
6951
6952out:
6953 return err;
6954}
6955
6956
6957
6958
6959
6960
6961
6962static int ufshcd_abort(struct scsi_cmnd *cmd)
6963{
6964 struct Scsi_Host *host = cmd->device->host;
6965 struct ufs_hba *hba = shost_priv(host);
6966 int tag = scsi_cmd_to_rq(cmd)->tag;
6967 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6968 unsigned long flags;
6969 int err = FAILED;
6970 u32 reg;
6971
6972 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
6973
6974 ufshcd_hold(hba, false);
6975 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6976
6977 if (!(test_bit(tag, &hba->outstanding_reqs))) {
6978 dev_err(hba->dev,
6979 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6980 __func__, tag, hba->outstanding_reqs, reg);
6981 goto release;
6982 }
6983
6984
6985 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
6986
6987
6988
6989
6990
6991
6992
6993
6994 scsi_print_command(cmd);
6995 if (!hba->req_abort_count) {
6996 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
6997 ufshcd_print_evt_hist(hba);
6998 ufshcd_print_host_state(hba);
6999 ufshcd_print_pwr_info(hba);
7000 ufshcd_print_trs(hba, 1 << tag, true);
7001 } else {
7002 ufshcd_print_trs(hba, 1 << tag, false);
7003 }
7004 hba->req_abort_count++;
7005
7006 if (!(reg & (1 << tag))) {
7007 dev_err(hba->dev,
7008 "%s: cmd was completed, but without a notifying intr, tag = %d",
7009 __func__, tag);
7010 __ufshcd_transfer_req_compl(hba, 1UL << tag, false);
7011 goto release;
7012 }
7013
7014
7015
7016
7017
7018
7019
7020
7021
7022 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7023 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7024
7025 spin_lock_irqsave(host->host_lock, flags);
7026 hba->force_reset = true;
7027 ufshcd_schedule_eh_work(hba);
7028 spin_unlock_irqrestore(host->host_lock, flags);
7029 goto release;
7030 }
7031
7032
7033 if (lrbp->req_abort_skip) {
7034 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7035 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7036 goto release;
7037 }
7038
7039 err = ufshcd_try_to_abort_task(hba, tag);
7040 if (err) {
7041 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7042 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7043 err = FAILED;
7044 goto release;
7045 }
7046
7047 err = SUCCESS;
7048
7049release:
7050
7051 ufshcd_release(hba);
7052 return err;
7053}
7054
7055
7056
7057
7058
7059
7060
7061
7062
7063
7064
7065static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7066{
7067 int err;
7068
7069
7070
7071
7072
7073 ufshpb_reset_host(hba);
7074 ufshcd_hba_stop(hba);
7075 hba->silence_err_logs = true;
7076 ufshcd_retry_aborted_requests(hba);
7077 hba->silence_err_logs = false;
7078
7079
7080 ufshcd_set_clk_freq(hba, true);
7081
7082 err = ufshcd_hba_enable(hba);
7083
7084
7085 if (!err)
7086 err = ufshcd_probe_hba(hba, false);
7087
7088 if (err)
7089 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7090 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7091 return err;
7092}
7093
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7104{
7105 u32 saved_err;
7106 u32 saved_uic_err;
7107 int err = 0;
7108 unsigned long flags;
7109 int retries = MAX_HOST_RESET_RETRIES;
7110
7111
7112
7113
7114
7115 spin_lock_irqsave(hba->host->host_lock, flags);
7116 saved_err = hba->saved_err;
7117 saved_uic_err = hba->saved_uic_err;
7118 hba->saved_err = 0;
7119 hba->saved_uic_err = 0;
7120 spin_unlock_irqrestore(hba->host->host_lock, flags);
7121
7122 do {
7123
7124 ufshcd_device_reset(hba);
7125
7126 err = ufshcd_host_reset_and_restore(hba);
7127 } while (err && --retries);
7128
7129 spin_lock_irqsave(hba->host->host_lock, flags);
7130
7131
7132
7133
7134 scsi_report_bus_reset(hba->host, 0);
7135 if (err) {
7136 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7137 hba->saved_err |= saved_err;
7138 hba->saved_uic_err |= saved_uic_err;
7139 }
7140 spin_unlock_irqrestore(hba->host->host_lock, flags);
7141
7142 return err;
7143}
7144
7145
7146
7147
7148
7149
7150
7151static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7152{
7153 int err = SUCCESS;
7154 unsigned long flags;
7155 struct ufs_hba *hba;
7156
7157 hba = shost_priv(cmd->device->host);
7158
7159 spin_lock_irqsave(hba->host->host_lock, flags);
7160 hba->force_reset = true;
7161 ufshcd_schedule_eh_work(hba);
7162 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7163 spin_unlock_irqrestore(hba->host->host_lock, flags);
7164
7165 flush_work(&hba->eh_work);
7166
7167 spin_lock_irqsave(hba->host->host_lock, flags);
7168 if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7169 err = FAILED;
7170 spin_unlock_irqrestore(hba->host->host_lock, flags);
7171
7172 return err;
7173}
7174
7175
7176
7177
7178
7179
7180
7181
7182
7183static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
7184{
7185 int i;
7186 int curr_uA;
7187 u16 data;
7188 u16 unit;
7189
7190 for (i = start_scan; i >= 0; i--) {
7191 data = be16_to_cpup((__be16 *)&buff[2 * i]);
7192 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7193 ATTR_ICC_LVL_UNIT_OFFSET;
7194 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7195 switch (unit) {
7196 case UFSHCD_NANO_AMP:
7197 curr_uA = curr_uA / 1000;
7198 break;
7199 case UFSHCD_MILI_AMP:
7200 curr_uA = curr_uA * 1000;
7201 break;
7202 case UFSHCD_AMP:
7203 curr_uA = curr_uA * 1000 * 1000;
7204 break;
7205 case UFSHCD_MICRO_AMP:
7206 default:
7207 break;
7208 }
7209 if (sup_curr_uA >= curr_uA)
7210 break;
7211 }
7212 if (i < 0) {
7213 i = 0;
7214 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7215 }
7216
7217 return (u32)i;
7218}
7219
7220
7221
7222
7223
7224
7225
7226
7227
7228
7229static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7230 u8 *desc_buf, int len)
7231{
7232 u32 icc_level = 0;
7233
7234 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7235 !hba->vreg_info.vccq2) {
7236 dev_err(hba->dev,
7237 "%s: Regulator capability was not set, actvIccLevel=%d",
7238 __func__, icc_level);
7239 goto out;
7240 }
7241
7242 if (hba->vreg_info.vcc->max_uA)
7243 icc_level = ufshcd_get_max_icc_level(
7244 hba->vreg_info.vcc->max_uA,
7245 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7246 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7247
7248 if (hba->vreg_info.vccq->max_uA)
7249 icc_level = ufshcd_get_max_icc_level(
7250 hba->vreg_info.vccq->max_uA,
7251 icc_level,
7252 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7253
7254 if (hba->vreg_info.vccq2->max_uA)
7255 icc_level = ufshcd_get_max_icc_level(
7256 hba->vreg_info.vccq2->max_uA,
7257 icc_level,
7258 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7259out:
7260 return icc_level;
7261}
7262
7263static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7264{
7265 int ret;
7266 int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
7267 u8 *desc_buf;
7268 u32 icc_level;
7269
7270 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7271 if (!desc_buf)
7272 return;
7273
7274 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7275 desc_buf, buff_len);
7276 if (ret) {
7277 dev_err(hba->dev,
7278 "%s: Failed reading power descriptor.len = %d ret = %d",
7279 __func__, buff_len, ret);
7280 goto out;
7281 }
7282
7283 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7284 buff_len);
7285 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7286
7287 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7288 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7289
7290 if (ret)
7291 dev_err(hba->dev,
7292 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
7293 __func__, icc_level, ret);
7294
7295out:
7296 kfree(desc_buf);
7297}
7298
7299static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7300{
7301 scsi_autopm_get_device(sdev);
7302 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7303 if (sdev->rpm_autosuspend)
7304 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7305 RPM_AUTOSUSPEND_DELAY_MS);
7306 scsi_autopm_put_device(sdev);
7307}
7308
7309
7310
7311
7312
7313
7314
7315
7316
7317
7318
7319
7320
7321
7322
7323
7324
7325
7326
7327
7328
7329
7330
7331
7332
7333
7334
7335static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7336{
7337 int ret = 0;
7338 struct scsi_device *sdev_boot;
7339
7340 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
7341 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7342 if (IS_ERR(hba->sdev_ufs_device)) {
7343 ret = PTR_ERR(hba->sdev_ufs_device);
7344 hba->sdev_ufs_device = NULL;
7345 goto out;
7346 }
7347 scsi_device_put(hba->sdev_ufs_device);
7348
7349 hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7350 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7351 if (IS_ERR(hba->sdev_rpmb)) {
7352 ret = PTR_ERR(hba->sdev_rpmb);
7353 goto remove_sdev_ufs_device;
7354 }
7355 ufshcd_blk_pm_runtime_init(hba->sdev_rpmb);
7356 scsi_device_put(hba->sdev_rpmb);
7357
7358 sdev_boot = __scsi_add_device(hba->host, 0, 0,
7359 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7360 if (IS_ERR(sdev_boot)) {
7361 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7362 } else {
7363 ufshcd_blk_pm_runtime_init(sdev_boot);
7364 scsi_device_put(sdev_boot);
7365 }
7366 goto out;
7367
7368remove_sdev_ufs_device:
7369 scsi_remove_device(hba->sdev_ufs_device);
7370out:
7371 return ret;
7372}
7373
7374static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7375{
7376 struct ufs_dev_info *dev_info = &hba->dev_info;
7377 u8 lun;
7378 u32 d_lu_wb_buf_alloc;
7379 u32 ext_ufs_feature;
7380
7381 if (!ufshcd_is_wb_allowed(hba))
7382 return;
7383
7384
7385
7386
7387
7388 if (!(dev_info->wspecversion >= 0x310 ||
7389 dev_info->wspecversion == 0x220 ||
7390 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7391 goto wb_disabled;
7392
7393 if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7394 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
7395 goto wb_disabled;
7396
7397 ext_ufs_feature = get_unaligned_be32(desc_buf +
7398 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7399
7400 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
7401 goto wb_disabled;
7402
7403
7404
7405
7406
7407
7408 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
7409
7410 dev_info->b_presrv_uspc_en =
7411 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7412
7413 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
7414 if (!get_unaligned_be32(desc_buf +
7415 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
7416 goto wb_disabled;
7417 } else {
7418 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7419 d_lu_wb_buf_alloc = 0;
7420 ufshcd_read_unit_desc_param(hba,
7421 lun,
7422 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7423 (u8 *)&d_lu_wb_buf_alloc,
7424 sizeof(d_lu_wb_buf_alloc));
7425 if (d_lu_wb_buf_alloc) {
7426 dev_info->wb_dedicated_lu = lun;
7427 break;
7428 }
7429 }
7430
7431 if (!d_lu_wb_buf_alloc)
7432 goto wb_disabled;
7433 }
7434 return;
7435
7436wb_disabled:
7437 hba->caps &= ~UFSHCD_CAP_WB_EN;
7438}
7439
7440void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, struct ufs_dev_fix *fixups)
7441{
7442 struct ufs_dev_fix *f;
7443 struct ufs_dev_info *dev_info = &hba->dev_info;
7444
7445 if (!fixups)
7446 return;
7447
7448 for (f = fixups; f->quirk; f++) {
7449 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7450 f->wmanufacturerid == UFS_ANY_VENDOR) &&
7451 ((dev_info->model &&
7452 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7453 !strcmp(f->model, UFS_ANY_MODEL)))
7454 hba->dev_quirks |= f->quirk;
7455 }
7456}
7457EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
7458
7459static void ufs_fixup_device_setup(struct ufs_hba *hba)
7460{
7461
7462 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
7463
7464
7465 ufshcd_vops_fixup_dev_quirks(hba);
7466}
7467
7468static int ufs_get_device_desc(struct ufs_hba *hba)
7469{
7470 int err;
7471 u8 model_index;
7472 u8 b_ufs_feature_sup;
7473 u8 *desc_buf;
7474 struct ufs_dev_info *dev_info = &hba->dev_info;
7475
7476 desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7477 if (!desc_buf) {
7478 err = -ENOMEM;
7479 goto out;
7480 }
7481
7482 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7483 hba->desc_size[QUERY_DESC_IDN_DEVICE]);
7484 if (err) {
7485 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7486 __func__, err);
7487 goto out;
7488 }
7489
7490
7491
7492
7493
7494 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
7495 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7496
7497
7498 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7499 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
7500 b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
7501
7502 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
7503
7504 if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
7505 (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
7506 bool hpb_en = false;
7507
7508 ufshpb_get_dev_info(hba, desc_buf);
7509
7510 if (!ufshpb_is_legacy(hba))
7511 err = ufshcd_query_flag_retry(hba,
7512 UPIU_QUERY_OPCODE_READ_FLAG,
7513 QUERY_FLAG_IDN_HPB_EN, 0,
7514 &hpb_en);
7515
7516 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
7517 dev_info->hpb_enabled = true;
7518 }
7519
7520 err = ufshcd_read_string_desc(hba, model_index,
7521 &dev_info->model, SD_ASCII_STD);
7522 if (err < 0) {
7523 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7524 __func__, err);
7525 goto out;
7526 }
7527
7528 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7529 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7530
7531 ufs_fixup_device_setup(hba);
7532
7533 ufshcd_wb_probe(hba, desc_buf);
7534
7535
7536
7537
7538
7539 err = 0;
7540
7541out:
7542 kfree(desc_buf);
7543 return err;
7544}
7545
7546static void ufs_put_device_desc(struct ufs_hba *hba)
7547{
7548 struct ufs_dev_info *dev_info = &hba->dev_info;
7549
7550 kfree(dev_info->model);
7551 dev_info->model = NULL;
7552}
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562
7563
7564
7565static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7566{
7567 int ret = 0;
7568 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7569
7570 ret = ufshcd_dme_peer_get(hba,
7571 UIC_ARG_MIB_SEL(
7572 RX_MIN_ACTIVATETIME_CAPABILITY,
7573 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7574 &peer_rx_min_activatetime);
7575 if (ret)
7576 goto out;
7577
7578
7579 tuned_pa_tactivate =
7580 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7581 / PA_TACTIVATE_TIME_UNIT_US);
7582 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7583 tuned_pa_tactivate);
7584
7585out:
7586 return ret;
7587}
7588
7589
7590
7591
7592
7593
7594
7595
7596
7597
7598
7599
7600static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7601{
7602 int ret = 0;
7603 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7604 u32 max_hibern8_time, tuned_pa_hibern8time;
7605
7606 ret = ufshcd_dme_get(hba,
7607 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7608 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7609 &local_tx_hibern8_time_cap);
7610 if (ret)
7611 goto out;
7612
7613 ret = ufshcd_dme_peer_get(hba,
7614 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7615 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7616 &peer_rx_hibern8_time_cap);
7617 if (ret)
7618 goto out;
7619
7620 max_hibern8_time = max(local_tx_hibern8_time_cap,
7621 peer_rx_hibern8_time_cap);
7622
7623 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7624 / PA_HIBERN8_TIME_UNIT_US);
7625 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7626 tuned_pa_hibern8time);
7627out:
7628 return ret;
7629}
7630
7631
7632
7633
7634
7635
7636
7637
7638
7639
7640
7641
7642static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7643{
7644 int ret = 0;
7645 u32 granularity, peer_granularity;
7646 u32 pa_tactivate, peer_pa_tactivate;
7647 u32 pa_tactivate_us, peer_pa_tactivate_us;
7648 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7649
7650 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7651 &granularity);
7652 if (ret)
7653 goto out;
7654
7655 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7656 &peer_granularity);
7657 if (ret)
7658 goto out;
7659
7660 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7661 (granularity > PA_GRANULARITY_MAX_VAL)) {
7662 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7663 __func__, granularity);
7664 return -EINVAL;
7665 }
7666
7667 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7668 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7669 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7670 __func__, peer_granularity);
7671 return -EINVAL;
7672 }
7673
7674 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7675 if (ret)
7676 goto out;
7677
7678 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7679 &peer_pa_tactivate);
7680 if (ret)
7681 goto out;
7682
7683 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7684 peer_pa_tactivate_us = peer_pa_tactivate *
7685 gran_to_us_table[peer_granularity - 1];
7686
7687 if (pa_tactivate_us > peer_pa_tactivate_us) {
7688 u32 new_peer_pa_tactivate;
7689
7690 new_peer_pa_tactivate = pa_tactivate_us /
7691 gran_to_us_table[peer_granularity - 1];
7692 new_peer_pa_tactivate++;
7693 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7694 new_peer_pa_tactivate);
7695 }
7696
7697out:
7698 return ret;
7699}
7700
7701static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
7702{
7703 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7704 ufshcd_tune_pa_tactivate(hba);
7705 ufshcd_tune_pa_hibern8time(hba);
7706 }
7707
7708 ufshcd_vops_apply_dev_quirks(hba);
7709
7710 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7711
7712 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
7713
7714 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7715 ufshcd_quirk_tune_host_pa_tactivate(hba);
7716}
7717
7718static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7719{
7720 hba->ufs_stats.hibern8_exit_cnt = 0;
7721 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7722 hba->req_abort_count = 0;
7723}
7724
7725static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7726{
7727 int err;
7728 size_t buff_len;
7729 u8 *desc_buf;
7730
7731 buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
7732 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7733 if (!desc_buf) {
7734 err = -ENOMEM;
7735 goto out;
7736 }
7737
7738 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7739 desc_buf, buff_len);
7740 if (err) {
7741 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7742 __func__, err);
7743 goto out;
7744 }
7745
7746 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7747 hba->dev_info.max_lu_supported = 32;
7748 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7749 hba->dev_info.max_lu_supported = 8;
7750
7751 if (hba->desc_size[QUERY_DESC_IDN_GEOMETRY] >=
7752 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
7753 ufshpb_get_geo_info(hba, desc_buf);
7754
7755out:
7756 kfree(desc_buf);
7757 return err;
7758}
7759
7760static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
7761 {19200000, REF_CLK_FREQ_19_2_MHZ},
7762 {26000000, REF_CLK_FREQ_26_MHZ},
7763 {38400000, REF_CLK_FREQ_38_4_MHZ},
7764 {52000000, REF_CLK_FREQ_52_MHZ},
7765 {0, REF_CLK_FREQ_INVAL},
7766};
7767
7768static enum ufs_ref_clk_freq
7769ufs_get_bref_clk_from_hz(unsigned long freq)
7770{
7771 int i;
7772
7773 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
7774 if (ufs_ref_clk_freqs[i].freq_hz == freq)
7775 return ufs_ref_clk_freqs[i].val;
7776
7777 return REF_CLK_FREQ_INVAL;
7778}
7779
7780void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
7781{
7782 unsigned long freq;
7783
7784 freq = clk_get_rate(refclk);
7785
7786 hba->dev_ref_clk_freq =
7787 ufs_get_bref_clk_from_hz(freq);
7788
7789 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
7790 dev_err(hba->dev,
7791 "invalid ref_clk setting = %ld\n", freq);
7792}
7793
7794static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
7795{
7796 int err;
7797 u32 ref_clk;
7798 u32 freq = hba->dev_ref_clk_freq;
7799
7800 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
7801 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
7802
7803 if (err) {
7804 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
7805 err);
7806 goto out;
7807 }
7808
7809 if (ref_clk == freq)
7810 goto out;
7811
7812 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7813 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
7814
7815 if (err) {
7816 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
7817 ufs_ref_clk_freqs[freq].freq_hz);
7818 goto out;
7819 }
7820
7821 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
7822 ufs_ref_clk_freqs[freq].freq_hz);
7823
7824out:
7825 return err;
7826}
7827
7828static int ufshcd_device_params_init(struct ufs_hba *hba)
7829{
7830 bool flag;
7831 int ret, i;
7832
7833
7834 for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
7835 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
7836
7837
7838 ret = ufshcd_device_geo_params_init(hba);
7839 if (ret)
7840 goto out;
7841
7842
7843 ret = ufs_get_device_desc(hba);
7844 if (ret) {
7845 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
7846 __func__, ret);
7847 goto out;
7848 }
7849
7850 ufshcd_get_ref_clk_gating_wait(hba);
7851
7852 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
7853 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
7854 hba->dev_info.f_power_on_wp_en = flag;
7855
7856
7857 if (ufshcd_get_max_pwr_mode(hba))
7858 dev_err(hba->dev,
7859 "%s: Failed getting max supported power mode\n",
7860 __func__);
7861out:
7862 return ret;
7863}
7864
7865
7866
7867
7868
7869static int ufshcd_add_lus(struct ufs_hba *hba)
7870{
7871 int ret;
7872
7873
7874 ret = ufshcd_scsi_add_wlus(hba);
7875 if (ret)
7876 goto out;
7877
7878 ufshcd_clear_ua_wluns(hba);
7879
7880
7881 if (ufshcd_is_clkscaling_supported(hba)) {
7882 memcpy(&hba->clk_scaling.saved_pwr_info.info,
7883 &hba->pwr_info,
7884 sizeof(struct ufs_pa_layer_attr));
7885 hba->clk_scaling.saved_pwr_info.is_valid = true;
7886 hba->clk_scaling.is_allowed = true;
7887
7888 ret = ufshcd_devfreq_init(hba);
7889 if (ret)
7890 goto out;
7891
7892 hba->clk_scaling.is_enabled = true;
7893 ufshcd_init_clk_scaling_sysfs(hba);
7894 }
7895
7896 ufs_bsg_probe(hba);
7897 ufshpb_init(hba);
7898 scsi_scan_host(hba->host);
7899 pm_runtime_put_sync(hba->dev);
7900
7901out:
7902 return ret;
7903}
7904
7905static void ufshcd_request_sense_done(struct request *rq, blk_status_t error)
7906{
7907 if (error != BLK_STS_OK)
7908 pr_err("%s: REQUEST SENSE failed (%d)\n", __func__, error);
7909 kfree(rq->end_io_data);
7910 blk_put_request(rq);
7911}
7912
7913static int
7914ufshcd_request_sense_async(struct ufs_hba *hba, struct scsi_device *sdev)
7915{
7916
7917
7918
7919
7920 static const u8 cmd[6] = {REQUEST_SENSE, 0, 0, 0, UFS_SENSE_SIZE, 0};
7921 struct scsi_request *rq;
7922 struct request *req;
7923 char *buffer;
7924 int ret;
7925
7926 buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
7927 if (!buffer)
7928 return -ENOMEM;
7929
7930 req = blk_get_request(sdev->request_queue, REQ_OP_DRV_IN,
7931 BLK_MQ_REQ_PM);
7932 if (IS_ERR(req)) {
7933 ret = PTR_ERR(req);
7934 goto out_free;
7935 }
7936
7937 ret = blk_rq_map_kern(sdev->request_queue, req,
7938 buffer, UFS_SENSE_SIZE, GFP_NOIO);
7939 if (ret)
7940 goto out_put;
7941
7942 rq = scsi_req(req);
7943 rq->cmd_len = ARRAY_SIZE(cmd);
7944 memcpy(rq->cmd, cmd, rq->cmd_len);
7945 rq->retries = 3;
7946 req->timeout = 1 * HZ;
7947 req->rq_flags |= RQF_PM | RQF_QUIET;
7948 req->end_io_data = buffer;
7949
7950 blk_execute_rq_nowait(NULL, req, true,
7951 ufshcd_request_sense_done);
7952 return 0;
7953
7954out_put:
7955 blk_put_request(req);
7956out_free:
7957 kfree(buffer);
7958 return ret;
7959}
7960
7961static int ufshcd_clear_ua_wlun(struct ufs_hba *hba, u8 wlun)
7962{
7963 struct scsi_device *sdp;
7964 unsigned long flags;
7965 int ret = 0;
7966
7967 spin_lock_irqsave(hba->host->host_lock, flags);
7968 if (wlun == UFS_UPIU_UFS_DEVICE_WLUN)
7969 sdp = hba->sdev_ufs_device;
7970 else if (wlun == UFS_UPIU_RPMB_WLUN)
7971 sdp = hba->sdev_rpmb;
7972 else
7973 BUG();
7974 if (sdp) {
7975 ret = scsi_device_get(sdp);
7976 if (!ret && !scsi_device_online(sdp)) {
7977 ret = -ENODEV;
7978 scsi_device_put(sdp);
7979 }
7980 } else {
7981 ret = -ENODEV;
7982 }
7983 spin_unlock_irqrestore(hba->host->host_lock, flags);
7984 if (ret)
7985 goto out_err;
7986
7987 ret = ufshcd_request_sense_async(hba, sdp);
7988 scsi_device_put(sdp);
7989out_err:
7990 if (ret)
7991 dev_err(hba->dev, "%s: UAC clear LU=%x ret = %d\n",
7992 __func__, wlun, ret);
7993 return ret;
7994}
7995
7996static int ufshcd_clear_ua_wluns(struct ufs_hba *hba)
7997{
7998 int ret = 0;
7999
8000 if (!hba->wlun_dev_clr_ua)
8001 goto out;
8002
8003 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
8004 if (!ret)
8005 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
8006 if (!ret)
8007 hba->wlun_dev_clr_ua = false;
8008out:
8009 if (ret)
8010 dev_err(hba->dev, "%s: Failed to clear UAC WLUNS ret = %d\n",
8011 __func__, ret);
8012 return ret;
8013}
8014
8015
8016
8017
8018
8019
8020
8021
8022static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8023{
8024 int ret;
8025 unsigned long flags;
8026 ktime_t start = ktime_get();
8027
8028 hba->ufshcd_state = UFSHCD_STATE_RESET;
8029
8030 ret = ufshcd_link_startup(hba);
8031 if (ret)
8032 goto out;
8033
8034
8035 ufshcd_clear_dbg_ufs_stats(hba);
8036
8037
8038 ufshcd_set_link_active(hba);
8039
8040
8041 ret = ufshcd_verify_dev_init(hba);
8042 if (ret)
8043 goto out;
8044
8045
8046 ret = ufshcd_complete_dev_init(hba);
8047 if (ret)
8048 goto out;
8049
8050
8051
8052
8053
8054 if (init_dev_params) {
8055 ret = ufshcd_device_params_init(hba);
8056 if (ret)
8057 goto out;
8058 }
8059
8060 ufshcd_tune_unipro_params(hba);
8061
8062
8063 ufshcd_set_ufs_dev_active(hba);
8064 ufshcd_force_reset_auto_bkops(hba);
8065 hba->wlun_dev_clr_ua = true;
8066 hba->wlun_rpmb_clr_ua = true;
8067
8068
8069 if (hba->max_pwr_info.is_valid) {
8070
8071
8072
8073
8074 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8075 ufshcd_set_dev_ref_clk(hba);
8076 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8077 if (ret) {
8078 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8079 __func__, ret);
8080 goto out;
8081 }
8082 ufshcd_print_pwr_info(hba);
8083 }
8084
8085
8086
8087
8088
8089
8090
8091 ufshcd_set_active_icc_lvl(hba);
8092
8093 ufshcd_wb_config(hba);
8094 if (hba->ee_usr_mask)
8095 ufshcd_write_ee_control(hba);
8096
8097 ufshcd_auto_hibern8_enable(hba);
8098
8099 ufshpb_reset(hba);
8100out:
8101 spin_lock_irqsave(hba->host->host_lock, flags);
8102 if (ret)
8103 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8104 else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8105 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8106 spin_unlock_irqrestore(hba->host->host_lock, flags);
8107
8108 trace_ufshcd_init(dev_name(hba->dev), ret,
8109 ktime_to_us(ktime_sub(ktime_get(), start)),
8110 hba->curr_dev_pwr_mode, hba->uic_link_state);
8111 return ret;
8112}
8113
8114
8115
8116
8117
8118
8119static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8120{
8121 struct ufs_hba *hba = (struct ufs_hba *)data;
8122 int ret;
8123
8124 down(&hba->host_sem);
8125
8126 ret = ufshcd_probe_hba(hba, true);
8127 up(&hba->host_sem);
8128 if (ret)
8129 goto out;
8130
8131
8132 ret = ufshcd_add_lus(hba);
8133out:
8134
8135
8136
8137
8138 if (ret) {
8139 pm_runtime_put_sync(hba->dev);
8140 ufshcd_hba_exit(hba);
8141 }
8142}
8143
8144static const struct attribute_group *ufshcd_driver_groups[] = {
8145 &ufs_sysfs_unit_descriptor_group,
8146 &ufs_sysfs_lun_attributes_group,
8147#ifdef CONFIG_SCSI_UFS_HPB
8148 &ufs_sysfs_hpb_stat_group,
8149 &ufs_sysfs_hpb_param_group,
8150#endif
8151 NULL,
8152};
8153
8154static struct ufs_hba_variant_params ufs_hba_vps = {
8155 .hba_enable_delay_us = 1000,
8156 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
8157 .devfreq_profile.polling_ms = 100,
8158 .devfreq_profile.target = ufshcd_devfreq_target,
8159 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8160 .ondemand_data.upthreshold = 70,
8161 .ondemand_data.downdifferential = 5,
8162};
8163
8164static struct scsi_host_template ufshcd_driver_template = {
8165 .module = THIS_MODULE,
8166 .name = UFSHCD,
8167 .proc_name = UFSHCD,
8168 .queuecommand = ufshcd_queuecommand,
8169 .slave_alloc = ufshcd_slave_alloc,
8170 .slave_configure = ufshcd_slave_configure,
8171 .slave_destroy = ufshcd_slave_destroy,
8172 .change_queue_depth = ufshcd_change_queue_depth,
8173 .eh_abort_handler = ufshcd_abort,
8174 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8175 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
8176 .this_id = -1,
8177 .sg_tablesize = SG_ALL,
8178 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
8179 .can_queue = UFSHCD_CAN_QUEUE,
8180 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
8181 .max_host_blocked = 1,
8182 .track_queue_depth = 1,
8183 .sdev_groups = ufshcd_driver_groups,
8184 .dma_boundary = PAGE_SIZE - 1,
8185 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
8186};
8187
8188static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8189 int ua)
8190{
8191 int ret;
8192
8193 if (!vreg)
8194 return 0;
8195
8196
8197
8198
8199
8200
8201
8202 if (!vreg->max_uA)
8203 return 0;
8204
8205 ret = regulator_set_load(vreg->reg, ua);
8206 if (ret < 0) {
8207 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8208 __func__, vreg->name, ua, ret);
8209 }
8210
8211 return ret;
8212}
8213
8214static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8215 struct ufs_vreg *vreg)
8216{
8217 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8218}
8219
8220static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8221 struct ufs_vreg *vreg)
8222{
8223 if (!vreg)
8224 return 0;
8225
8226 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8227}
8228
8229static int ufshcd_config_vreg(struct device *dev,
8230 struct ufs_vreg *vreg, bool on)
8231{
8232 int ret = 0;
8233 struct regulator *reg;
8234 const char *name;
8235 int min_uV, uA_load;
8236
8237 BUG_ON(!vreg);
8238
8239 reg = vreg->reg;
8240 name = vreg->name;
8241
8242 if (regulator_count_voltages(reg) > 0) {
8243 uA_load = on ? vreg->max_uA : 0;
8244 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
8245 if (ret)
8246 goto out;
8247
8248 if (vreg->min_uV && vreg->max_uV) {
8249 min_uV = on ? vreg->min_uV : 0;
8250 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
8251 if (ret)
8252 dev_err(dev,
8253 "%s: %s set voltage failed, err=%d\n",
8254 __func__, name, ret);
8255 }
8256 }
8257out:
8258 return ret;
8259}
8260
8261static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8262{
8263 int ret = 0;
8264
8265 if (!vreg || vreg->enabled)
8266 goto out;
8267
8268 ret = ufshcd_config_vreg(dev, vreg, true);
8269 if (!ret)
8270 ret = regulator_enable(vreg->reg);
8271
8272 if (!ret)
8273 vreg->enabled = true;
8274 else
8275 dev_err(dev, "%s: %s enable failed, err=%d\n",
8276 __func__, vreg->name, ret);
8277out:
8278 return ret;
8279}
8280
8281static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8282{
8283 int ret = 0;
8284
8285 if (!vreg || !vreg->enabled || vreg->always_on)
8286 goto out;
8287
8288 ret = regulator_disable(vreg->reg);
8289
8290 if (!ret) {
8291
8292 ufshcd_config_vreg(dev, vreg, false);
8293 vreg->enabled = false;
8294 } else {
8295 dev_err(dev, "%s: %s disable failed, err=%d\n",
8296 __func__, vreg->name, ret);
8297 }
8298out:
8299 return ret;
8300}
8301
8302static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8303{
8304 int ret = 0;
8305 struct device *dev = hba->dev;
8306 struct ufs_vreg_info *info = &hba->vreg_info;
8307
8308 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8309 if (ret)
8310 goto out;
8311
8312 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8313 if (ret)
8314 goto out;
8315
8316 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
8317
8318out:
8319 if (ret) {
8320 ufshcd_toggle_vreg(dev, info->vccq2, false);
8321 ufshcd_toggle_vreg(dev, info->vccq, false);
8322 ufshcd_toggle_vreg(dev, info->vcc, false);
8323 }
8324 return ret;
8325}
8326
8327static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8328{
8329 struct ufs_vreg_info *info = &hba->vreg_info;
8330
8331 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
8332}
8333
8334static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8335{
8336 int ret = 0;
8337
8338 if (!vreg)
8339 goto out;
8340
8341 vreg->reg = devm_regulator_get(dev, vreg->name);
8342 if (IS_ERR(vreg->reg)) {
8343 ret = PTR_ERR(vreg->reg);
8344 dev_err(dev, "%s: %s get failed, err=%d\n",
8345 __func__, vreg->name, ret);
8346 }
8347out:
8348 return ret;
8349}
8350
8351static int ufshcd_init_vreg(struct ufs_hba *hba)
8352{
8353 int ret = 0;
8354 struct device *dev = hba->dev;
8355 struct ufs_vreg_info *info = &hba->vreg_info;
8356
8357 ret = ufshcd_get_vreg(dev, info->vcc);
8358 if (ret)
8359 goto out;
8360
8361 ret = ufshcd_get_vreg(dev, info->vccq);
8362 if (!ret)
8363 ret = ufshcd_get_vreg(dev, info->vccq2);
8364out:
8365 return ret;
8366}
8367
8368static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8369{
8370 struct ufs_vreg_info *info = &hba->vreg_info;
8371
8372 if (info)
8373 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8374
8375 return 0;
8376}
8377
8378static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
8379{
8380 int ret = 0;
8381 struct ufs_clk_info *clki;
8382 struct list_head *head = &hba->clk_list_head;
8383 unsigned long flags;
8384 ktime_t start = ktime_get();
8385 bool clk_state_changed = false;
8386
8387 if (list_empty(head))
8388 goto out;
8389
8390 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8391 if (ret)
8392 return ret;
8393
8394 list_for_each_entry(clki, head, list) {
8395 if (!IS_ERR_OR_NULL(clki->clk)) {
8396
8397
8398
8399
8400 if (ufshcd_is_link_active(hba) &&
8401 clki->keep_link_active)
8402 continue;
8403
8404 clk_state_changed = on ^ clki->enabled;
8405 if (on && !clki->enabled) {
8406 ret = clk_prepare_enable(clki->clk);
8407 if (ret) {
8408 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8409 __func__, clki->name, ret);
8410 goto out;
8411 }
8412 } else if (!on && clki->enabled) {
8413 clk_disable_unprepare(clki->clk);
8414 }
8415 clki->enabled = on;
8416 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8417 clki->name, on ? "en" : "dis");
8418 }
8419 }
8420
8421 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8422 if (ret)
8423 return ret;
8424
8425out:
8426 if (ret) {
8427 list_for_each_entry(clki, head, list) {
8428 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8429 clk_disable_unprepare(clki->clk);
8430 }
8431 } else if (!ret && on) {
8432 spin_lock_irqsave(hba->host->host_lock, flags);
8433 hba->clk_gating.state = CLKS_ON;
8434 trace_ufshcd_clk_gating(dev_name(hba->dev),
8435 hba->clk_gating.state);
8436 spin_unlock_irqrestore(hba->host->host_lock, flags);
8437 }
8438
8439 if (clk_state_changed)
8440 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8441 (on ? "on" : "off"),
8442 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
8443 return ret;
8444}
8445
8446static int ufshcd_init_clocks(struct ufs_hba *hba)
8447{
8448 int ret = 0;
8449 struct ufs_clk_info *clki;
8450 struct device *dev = hba->dev;
8451 struct list_head *head = &hba->clk_list_head;
8452
8453 if (list_empty(head))
8454 goto out;
8455
8456 list_for_each_entry(clki, head, list) {
8457 if (!clki->name)
8458 continue;
8459
8460 clki->clk = devm_clk_get(dev, clki->name);
8461 if (IS_ERR(clki->clk)) {
8462 ret = PTR_ERR(clki->clk);
8463 dev_err(dev, "%s: %s clk get failed, %d\n",
8464 __func__, clki->name, ret);
8465 goto out;
8466 }
8467
8468
8469
8470
8471
8472
8473 if (!strcmp(clki->name, "ref_clk"))
8474 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8475
8476 if (clki->max_freq) {
8477 ret = clk_set_rate(clki->clk, clki->max_freq);
8478 if (ret) {
8479 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8480 __func__, clki->name,
8481 clki->max_freq, ret);
8482 goto out;
8483 }
8484 clki->curr_freq = clki->max_freq;
8485 }
8486 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8487 clki->name, clk_get_rate(clki->clk));
8488 }
8489out:
8490 return ret;
8491}
8492
8493static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8494{
8495 int err = 0;
8496
8497 if (!hba->vops)
8498 goto out;
8499
8500 err = ufshcd_vops_init(hba);
8501 if (err)
8502 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
8503 __func__, ufshcd_get_var_name(hba), err);
8504out:
8505 return err;
8506}
8507
8508static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8509{
8510 if (!hba->vops)
8511 return;
8512
8513 ufshcd_vops_exit(hba);
8514}
8515
8516static int ufshcd_hba_init(struct ufs_hba *hba)
8517{
8518 int err;
8519
8520
8521
8522
8523
8524
8525
8526
8527 err = ufshcd_init_hba_vreg(hba);
8528 if (err)
8529 goto out;
8530
8531 err = ufshcd_setup_hba_vreg(hba, true);
8532 if (err)
8533 goto out;
8534
8535 err = ufshcd_init_clocks(hba);
8536 if (err)
8537 goto out_disable_hba_vreg;
8538
8539 err = ufshcd_setup_clocks(hba, true);
8540 if (err)
8541 goto out_disable_hba_vreg;
8542
8543 err = ufshcd_init_vreg(hba);
8544 if (err)
8545 goto out_disable_clks;
8546
8547 err = ufshcd_setup_vreg(hba, true);
8548 if (err)
8549 goto out_disable_clks;
8550
8551 err = ufshcd_variant_hba_init(hba);
8552 if (err)
8553 goto out_disable_vreg;
8554
8555 ufs_debugfs_hba_init(hba);
8556
8557 hba->is_powered = true;
8558 goto out;
8559
8560out_disable_vreg:
8561 ufshcd_setup_vreg(hba, false);
8562out_disable_clks:
8563 ufshcd_setup_clocks(hba, false);
8564out_disable_hba_vreg:
8565 ufshcd_setup_hba_vreg(hba, false);
8566out:
8567 return err;
8568}
8569
8570static void ufshcd_hba_exit(struct ufs_hba *hba)
8571{
8572 if (hba->is_powered) {
8573 ufshcd_exit_clk_scaling(hba);
8574 ufshcd_exit_clk_gating(hba);
8575 if (hba->eh_wq)
8576 destroy_workqueue(hba->eh_wq);
8577 ufs_debugfs_hba_exit(hba);
8578 ufshcd_variant_hba_exit(hba);
8579 ufshcd_setup_vreg(hba, false);
8580 ufshcd_setup_clocks(hba, false);
8581 ufshcd_setup_hba_vreg(hba, false);
8582 hba->is_powered = false;
8583 ufs_put_device_desc(hba);
8584 }
8585}
8586
8587
8588
8589
8590
8591
8592
8593
8594
8595
8596static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8597 enum ufs_dev_pwr_mode pwr_mode)
8598{
8599 unsigned char cmd[6] = { START_STOP };
8600 struct scsi_sense_hdr sshdr;
8601 struct scsi_device *sdp;
8602 unsigned long flags;
8603 int ret;
8604
8605 spin_lock_irqsave(hba->host->host_lock, flags);
8606 sdp = hba->sdev_ufs_device;
8607 if (sdp) {
8608 ret = scsi_device_get(sdp);
8609 if (!ret && !scsi_device_online(sdp)) {
8610 ret = -ENODEV;
8611 scsi_device_put(sdp);
8612 }
8613 } else {
8614 ret = -ENODEV;
8615 }
8616 spin_unlock_irqrestore(hba->host->host_lock, flags);
8617
8618 if (ret)
8619 return ret;
8620
8621
8622
8623
8624
8625
8626
8627 hba->host->eh_noresume = 1;
8628 if (hba->wlun_dev_clr_ua)
8629 ufshcd_clear_ua_wlun(hba, UFS_UPIU_UFS_DEVICE_WLUN);
8630
8631 cmd[4] = pwr_mode << 4;
8632
8633
8634
8635
8636
8637
8638 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8639 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
8640 if (ret) {
8641 sdev_printk(KERN_WARNING, sdp,
8642 "START_STOP failed for power mode: %d, result %x\n",
8643 pwr_mode, ret);
8644 if (ret > 0 && scsi_sense_valid(&sshdr))
8645 scsi_print_sense_hdr(sdp, NULL, &sshdr);
8646 }
8647
8648 if (!ret)
8649 hba->curr_dev_pwr_mode = pwr_mode;
8650
8651 scsi_device_put(sdp);
8652 hba->host->eh_noresume = 0;
8653 return ret;
8654}
8655
8656static int ufshcd_link_state_transition(struct ufs_hba *hba,
8657 enum uic_link_state req_link_state,
8658 int check_for_bkops)
8659{
8660 int ret = 0;
8661
8662 if (req_link_state == hba->uic_link_state)
8663 return 0;
8664
8665 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8666 ret = ufshcd_uic_hibern8_enter(hba);
8667 if (!ret) {
8668 ufshcd_set_link_hibern8(hba);
8669 } else {
8670 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8671 __func__, ret);
8672 goto out;
8673 }
8674 }
8675
8676
8677
8678
8679
8680 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
8681 (!check_for_bkops || !hba->auto_bkops_enabled)) {
8682
8683
8684
8685
8686
8687
8688
8689
8690
8691
8692 ret = ufshcd_uic_hibern8_enter(hba);
8693 if (ret) {
8694 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8695 __func__, ret);
8696 goto out;
8697 }
8698
8699
8700
8701
8702 ufshcd_hba_stop(hba);
8703
8704
8705
8706
8707 ufshcd_set_link_off(hba);
8708 }
8709
8710out:
8711 return ret;
8712}
8713
8714static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8715{
8716 bool vcc_off = false;
8717
8718
8719
8720
8721
8722
8723
8724 if (!ufshcd_is_link_active(hba) &&
8725 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8726 usleep_range(2000, 2100);
8727
8728
8729
8730
8731
8732
8733
8734
8735
8736
8737
8738
8739
8740
8741
8742
8743 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8744 !hba->dev_info.is_lu_power_on_wp) {
8745 ufshcd_setup_vreg(hba, false);
8746 vcc_off = true;
8747 } else if (!ufshcd_is_ufs_dev_active(hba)) {
8748 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8749 vcc_off = true;
8750 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
8751 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8752 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8753 }
8754 }
8755
8756
8757
8758
8759 if (vcc_off && hba->vreg_info.vcc &&
8760 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8761 usleep_range(5000, 5100);
8762}
8763
8764#ifdef CONFIG_PM
8765static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8766{
8767 int ret = 0;
8768
8769 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8770 !hba->dev_info.is_lu_power_on_wp) {
8771 ret = ufshcd_setup_vreg(hba, true);
8772 } else if (!ufshcd_is_ufs_dev_active(hba)) {
8773 if (!ufshcd_is_link_active(hba)) {
8774 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8775 if (ret)
8776 goto vcc_disable;
8777 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8778 if (ret)
8779 goto vccq_lpm;
8780 }
8781 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
8782 }
8783 goto out;
8784
8785vccq_lpm:
8786 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8787vcc_disable:
8788 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8789out:
8790 return ret;
8791}
8792#endif
8793
8794static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8795{
8796 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8797 ufshcd_setup_hba_vreg(hba, false);
8798}
8799
8800static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8801{
8802 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8803 ufshcd_setup_hba_vreg(hba, true);
8804}
8805
8806static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8807{
8808 int ret = 0;
8809 int check_for_bkops;
8810 enum ufs_pm_level pm_lvl;
8811 enum ufs_dev_pwr_mode req_dev_pwr_mode;
8812 enum uic_link_state req_link_state;
8813
8814 hba->pm_op_in_progress = true;
8815 if (pm_op != UFS_SHUTDOWN_PM) {
8816 pm_lvl = pm_op == UFS_RUNTIME_PM ?
8817 hba->rpm_lvl : hba->spm_lvl;
8818 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8819 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8820 } else {
8821 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8822 req_link_state = UIC_LINK_OFF_STATE;
8823 }
8824
8825 ufshpb_suspend(hba);
8826
8827
8828
8829
8830
8831 ufshcd_hold(hba, false);
8832 hba->clk_gating.is_suspended = true;
8833
8834 if (ufshcd_is_clkscaling_supported(hba))
8835 ufshcd_clk_scaling_suspend(hba, true);
8836
8837 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8838 req_link_state == UIC_LINK_ACTIVE_STATE) {
8839 goto vops_suspend;
8840 }
8841
8842 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8843 (req_link_state == hba->uic_link_state))
8844 goto enable_scaling;
8845
8846
8847 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8848 ret = -EINVAL;
8849 goto enable_scaling;
8850 }
8851
8852 if (pm_op == UFS_RUNTIME_PM) {
8853 if (ufshcd_can_autobkops_during_suspend(hba)) {
8854
8855
8856
8857
8858
8859 ret = ufshcd_urgent_bkops(hba);
8860 if (ret)
8861 goto enable_scaling;
8862 } else {
8863
8864 ufshcd_disable_auto_bkops(hba);
8865 }
8866
8867
8868
8869
8870
8871 hba->dev_info.b_rpm_dev_flush_capable =
8872 hba->auto_bkops_enabled ||
8873 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8874 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8875 ufshcd_is_auto_hibern8_enabled(hba))) &&
8876 ufshcd_wb_need_flush(hba));
8877 }
8878
8879 flush_work(&hba->eeh_work);
8880
8881 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
8882 if (pm_op != UFS_RUNTIME_PM)
8883
8884 ufshcd_disable_auto_bkops(hba);
8885
8886 if (!hba->dev_info.b_rpm_dev_flush_capable) {
8887 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8888 if (ret)
8889 goto enable_scaling;
8890 }
8891 }
8892
8893
8894
8895
8896
8897 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
8898 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
8899 if (ret)
8900 goto set_dev_active;
8901
8902vops_suspend:
8903
8904
8905
8906
8907
8908 ret = ufshcd_vops_suspend(hba, pm_op);
8909 if (ret)
8910 goto set_link_active;
8911 goto out;
8912
8913set_link_active:
8914
8915
8916
8917
8918
8919 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8920 ufshcd_device_reset(hba);
8921 WARN_ON(!ufshcd_is_link_off(hba));
8922 }
8923 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
8924 ufshcd_set_link_active(hba);
8925 else if (ufshcd_is_link_off(hba))
8926 ufshcd_host_reset_and_restore(hba);
8927set_dev_active:
8928
8929 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8930 ufshcd_device_reset(hba);
8931 ufshcd_host_reset_and_restore(hba);
8932 }
8933 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8934 ufshcd_disable_auto_bkops(hba);
8935enable_scaling:
8936 if (ufshcd_is_clkscaling_supported(hba))
8937 ufshcd_clk_scaling_suspend(hba, false);
8938
8939 hba->dev_info.b_rpm_dev_flush_capable = false;
8940out:
8941 if (hba->dev_info.b_rpm_dev_flush_capable) {
8942 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
8943 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
8944 }
8945
8946 if (ret) {
8947 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
8948 hba->clk_gating.is_suspended = false;
8949 ufshcd_release(hba);
8950 ufshpb_resume(hba);
8951 }
8952 hba->pm_op_in_progress = false;
8953 return ret;
8954}
8955
8956#ifdef CONFIG_PM
8957static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8958{
8959 int ret;
8960 enum uic_link_state old_link_state = hba->uic_link_state;
8961
8962 hba->pm_op_in_progress = true;
8963
8964
8965
8966
8967
8968
8969 ret = ufshcd_vops_resume(hba, pm_op);
8970 if (ret)
8971 goto out;
8972
8973
8974 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
8975
8976 if (ufshcd_is_link_hibern8(hba)) {
8977 ret = ufshcd_uic_hibern8_exit(hba);
8978 if (!ret) {
8979 ufshcd_set_link_active(hba);
8980 } else {
8981 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
8982 __func__, ret);
8983 goto vendor_suspend;
8984 }
8985 } else if (ufshcd_is_link_off(hba)) {
8986
8987
8988
8989
8990
8991
8992 ret = ufshcd_reset_and_restore(hba);
8993
8994
8995
8996
8997 if (ret || !ufshcd_is_link_active(hba))
8998 goto vendor_suspend;
8999 }
9000
9001 if (!ufshcd_is_ufs_dev_active(hba)) {
9002 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9003 if (ret)
9004 goto set_old_link_state;
9005 }
9006
9007 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9008 ufshcd_enable_auto_bkops(hba);
9009 else
9010
9011
9012
9013
9014 ufshcd_urgent_bkops(hba);
9015
9016 if (hba->ee_usr_mask)
9017 ufshcd_write_ee_control(hba);
9018
9019 if (ufshcd_is_clkscaling_supported(hba))
9020 ufshcd_clk_scaling_suspend(hba, false);
9021
9022 if (hba->dev_info.b_rpm_dev_flush_capable) {
9023 hba->dev_info.b_rpm_dev_flush_capable = false;
9024 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9025 }
9026
9027
9028 ufshcd_auto_hibern8_enable(hba);
9029
9030 ufshpb_resume(hba);
9031 goto out;
9032
9033set_old_link_state:
9034 ufshcd_link_state_transition(hba, old_link_state, 0);
9035vendor_suspend:
9036 ufshcd_vops_suspend(hba, pm_op);
9037out:
9038 if (ret)
9039 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9040 hba->clk_gating.is_suspended = false;
9041 ufshcd_release(hba);
9042 hba->pm_op_in_progress = false;
9043 return ret;
9044}
9045
9046static int ufshcd_wl_runtime_suspend(struct device *dev)
9047{
9048 struct scsi_device *sdev = to_scsi_device(dev);
9049 struct ufs_hba *hba;
9050 int ret;
9051 ktime_t start = ktime_get();
9052
9053 hba = shost_priv(sdev->host);
9054
9055 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9056 if (ret)
9057 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9058
9059 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9060 ktime_to_us(ktime_sub(ktime_get(), start)),
9061 hba->curr_dev_pwr_mode, hba->uic_link_state);
9062
9063 return ret;
9064}
9065
9066static int ufshcd_wl_runtime_resume(struct device *dev)
9067{
9068 struct scsi_device *sdev = to_scsi_device(dev);
9069 struct ufs_hba *hba;
9070 int ret = 0;
9071 ktime_t start = ktime_get();
9072
9073 hba = shost_priv(sdev->host);
9074
9075 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9076 if (ret)
9077 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9078
9079 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9080 ktime_to_us(ktime_sub(ktime_get(), start)),
9081 hba->curr_dev_pwr_mode, hba->uic_link_state);
9082
9083 return ret;
9084}
9085#endif
9086
9087#ifdef CONFIG_PM_SLEEP
9088static int ufshcd_wl_suspend(struct device *dev)
9089{
9090 struct scsi_device *sdev = to_scsi_device(dev);
9091 struct ufs_hba *hba;
9092 int ret = 0;
9093 ktime_t start = ktime_get();
9094
9095 hba = shost_priv(sdev->host);
9096 down(&hba->host_sem);
9097
9098 if (pm_runtime_suspended(dev))
9099 goto out;
9100
9101 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9102 if (ret) {
9103 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9104 up(&hba->host_sem);
9105 }
9106
9107out:
9108 if (!ret)
9109 hba->is_sys_suspended = true;
9110 trace_ufshcd_wl_suspend(dev_name(dev), ret,
9111 ktime_to_us(ktime_sub(ktime_get(), start)),
9112 hba->curr_dev_pwr_mode, hba->uic_link_state);
9113
9114 return ret;
9115}
9116
9117static int ufshcd_wl_resume(struct device *dev)
9118{
9119 struct scsi_device *sdev = to_scsi_device(dev);
9120 struct ufs_hba *hba;
9121 int ret = 0;
9122 ktime_t start = ktime_get();
9123
9124 hba = shost_priv(sdev->host);
9125
9126 if (pm_runtime_suspended(dev))
9127 goto out;
9128
9129 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9130 if (ret)
9131 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9132out:
9133 trace_ufshcd_wl_resume(dev_name(dev), ret,
9134 ktime_to_us(ktime_sub(ktime_get(), start)),
9135 hba->curr_dev_pwr_mode, hba->uic_link_state);
9136 if (!ret)
9137 hba->is_sys_suspended = false;
9138 up(&hba->host_sem);
9139 return ret;
9140}
9141#endif
9142
9143static void ufshcd_wl_shutdown(struct device *dev)
9144{
9145 struct scsi_device *sdev = to_scsi_device(dev);
9146 struct ufs_hba *hba;
9147
9148 hba = shost_priv(sdev->host);
9149
9150 down(&hba->host_sem);
9151 hba->shutting_down = true;
9152 up(&hba->host_sem);
9153
9154
9155 ufshcd_rpm_get_sync(hba);
9156 scsi_device_quiesce(sdev);
9157 shost_for_each_device(sdev, hba->host) {
9158 if (sdev == hba->sdev_ufs_device)
9159 continue;
9160 scsi_device_quiesce(sdev);
9161 }
9162 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9163}
9164
9165
9166
9167
9168
9169
9170
9171
9172static int ufshcd_suspend(struct ufs_hba *hba)
9173{
9174 int ret;
9175
9176 if (!hba->is_powered)
9177 return 0;
9178
9179
9180
9181
9182 ufshcd_disable_irq(hba);
9183 ret = ufshcd_setup_clocks(hba, false);
9184 if (ret) {
9185 ufshcd_enable_irq(hba);
9186 return ret;
9187 }
9188 if (ufshcd_is_clkgating_allowed(hba)) {
9189 hba->clk_gating.state = CLKS_OFF;
9190 trace_ufshcd_clk_gating(dev_name(hba->dev),
9191 hba->clk_gating.state);
9192 }
9193
9194 ufshcd_vreg_set_lpm(hba);
9195
9196 ufshcd_hba_vreg_set_lpm(hba);
9197 return ret;
9198}
9199
9200#ifdef CONFIG_PM
9201
9202
9203
9204
9205
9206
9207
9208
9209
9210static int ufshcd_resume(struct ufs_hba *hba)
9211{
9212 int ret;
9213
9214 if (!hba->is_powered)
9215 return 0;
9216
9217 ufshcd_hba_vreg_set_hpm(hba);
9218 ret = ufshcd_vreg_set_hpm(hba);
9219 if (ret)
9220 goto out;
9221
9222
9223 ret = ufshcd_setup_clocks(hba, true);
9224 if (ret)
9225 goto disable_vreg;
9226
9227
9228 ufshcd_enable_irq(hba);
9229 goto out;
9230
9231disable_vreg:
9232 ufshcd_vreg_set_lpm(hba);
9233out:
9234 if (ret)
9235 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
9236 return ret;
9237}
9238#endif
9239
9240#ifdef CONFIG_PM_SLEEP
9241
9242
9243
9244
9245
9246
9247
9248
9249
9250int ufshcd_system_suspend(struct device *dev)
9251{
9252 struct ufs_hba *hba = dev_get_drvdata(dev);
9253 int ret = 0;
9254 ktime_t start = ktime_get();
9255
9256 if (pm_runtime_suspended(hba->dev))
9257 goto out;
9258
9259 ret = ufshcd_suspend(hba);
9260out:
9261 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9262 ktime_to_us(ktime_sub(ktime_get(), start)),
9263 hba->curr_dev_pwr_mode, hba->uic_link_state);
9264 return ret;
9265}
9266EXPORT_SYMBOL(ufshcd_system_suspend);
9267
9268
9269
9270
9271
9272
9273
9274
9275
9276
9277int ufshcd_system_resume(struct device *dev)
9278{
9279 struct ufs_hba *hba = dev_get_drvdata(dev);
9280 ktime_t start = ktime_get();
9281 int ret = 0;
9282
9283 if (pm_runtime_suspended(hba->dev))
9284 goto out;
9285
9286 ret = ufshcd_resume(hba);
9287
9288out:
9289 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9290 ktime_to_us(ktime_sub(ktime_get(), start)),
9291 hba->curr_dev_pwr_mode, hba->uic_link_state);
9292
9293 return ret;
9294}
9295EXPORT_SYMBOL(ufshcd_system_resume);
9296#endif
9297
9298#ifdef CONFIG_PM
9299
9300
9301
9302
9303
9304
9305
9306
9307int ufshcd_runtime_suspend(struct device *dev)
9308{
9309 struct ufs_hba *hba = dev_get_drvdata(dev);
9310 int ret;
9311 ktime_t start = ktime_get();
9312
9313 ret = ufshcd_suspend(hba);
9314
9315 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9316 ktime_to_us(ktime_sub(ktime_get(), start)),
9317 hba->curr_dev_pwr_mode, hba->uic_link_state);
9318 return ret;
9319}
9320EXPORT_SYMBOL(ufshcd_runtime_suspend);
9321
9322
9323
9324
9325
9326
9327
9328
9329
9330
9331
9332int ufshcd_runtime_resume(struct device *dev)
9333{
9334 struct ufs_hba *hba = dev_get_drvdata(dev);
9335 int ret;
9336 ktime_t start = ktime_get();
9337
9338 ret = ufshcd_resume(hba);
9339
9340 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9341 ktime_to_us(ktime_sub(ktime_get(), start)),
9342 hba->curr_dev_pwr_mode, hba->uic_link_state);
9343 return ret;
9344}
9345EXPORT_SYMBOL(ufshcd_runtime_resume);
9346#endif
9347
9348
9349
9350
9351
9352
9353
9354
9355
9356
9357int ufshcd_shutdown(struct ufs_hba *hba)
9358{
9359 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9360 goto out;
9361
9362 pm_runtime_get_sync(hba->dev);
9363
9364 ufshcd_suspend(hba);
9365out:
9366 hba->is_powered = false;
9367
9368 return 0;
9369}
9370EXPORT_SYMBOL(ufshcd_shutdown);
9371
9372
9373
9374
9375
9376
9377void ufshcd_remove(struct ufs_hba *hba)
9378{
9379 if (hba->sdev_ufs_device)
9380 ufshcd_rpm_get_sync(hba);
9381 ufs_bsg_remove(hba);
9382 ufshpb_remove(hba);
9383 ufs_sysfs_remove_nodes(hba->dev);
9384 blk_cleanup_queue(hba->tmf_queue);
9385 blk_mq_free_tag_set(&hba->tmf_tag_set);
9386 blk_cleanup_queue(hba->cmd_queue);
9387 scsi_remove_host(hba->host);
9388
9389 ufshcd_disable_intr(hba, hba->intr_mask);
9390 ufshcd_hba_stop(hba);
9391 ufshcd_hba_exit(hba);
9392}
9393EXPORT_SYMBOL_GPL(ufshcd_remove);
9394
9395
9396
9397
9398
9399void ufshcd_dealloc_host(struct ufs_hba *hba)
9400{
9401 scsi_host_put(hba->host);
9402}
9403EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9404
9405
9406
9407
9408
9409
9410
9411
9412static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9413{
9414 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9415 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9416 return 0;
9417 }
9418 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9419}
9420
9421
9422
9423
9424
9425
9426
9427int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
9428{
9429 struct Scsi_Host *host;
9430 struct ufs_hba *hba;
9431 int err = 0;
9432
9433 if (!dev) {
9434 dev_err(dev,
9435 "Invalid memory reference for dev is NULL\n");
9436 err = -ENODEV;
9437 goto out_error;
9438 }
9439
9440 host = scsi_host_alloc(&ufshcd_driver_template,
9441 sizeof(struct ufs_hba));
9442 if (!host) {
9443 dev_err(dev, "scsi_host_alloc failed\n");
9444 err = -ENOMEM;
9445 goto out_error;
9446 }
9447 hba = shost_priv(host);
9448 hba->host = host;
9449 hba->dev = dev;
9450 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
9451 hba->nop_out_timeout = NOP_OUT_TIMEOUT;
9452 INIT_LIST_HEAD(&hba->clk_list_head);
9453 spin_lock_init(&hba->outstanding_lock);
9454
9455 *hba_handle = hba;
9456
9457out_error:
9458 return err;
9459}
9460EXPORT_SYMBOL(ufshcd_alloc_host);
9461
9462
9463static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9464 const struct blk_mq_queue_data *qd)
9465{
9466 WARN_ON_ONCE(true);
9467 return BLK_STS_NOTSUPP;
9468}
9469
9470static const struct blk_mq_ops ufshcd_tmf_ops = {
9471 .queue_rq = ufshcd_queue_tmf,
9472};
9473
9474
9475
9476
9477
9478
9479
9480
9481int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9482{
9483 int err;
9484 struct Scsi_Host *host = hba->host;
9485 struct device *dev = hba->dev;
9486 char eh_wq_name[sizeof("ufs_eh_wq_00")];
9487
9488 if (!mmio_base) {
9489 dev_err(hba->dev,
9490 "Invalid memory reference for mmio_base is NULL\n");
9491 err = -ENODEV;
9492 goto out_error;
9493 }
9494
9495 hba->mmio_base = mmio_base;
9496 hba->irq = irq;
9497 hba->vps = &ufs_hba_vps;
9498
9499 err = ufshcd_hba_init(hba);
9500 if (err)
9501 goto out_error;
9502
9503
9504 err = ufshcd_hba_capabilities(hba);
9505 if (err)
9506 goto out_disable;
9507
9508
9509 hba->ufs_version = ufshcd_get_ufs_version(hba);
9510
9511
9512 hba->intr_mask = ufshcd_get_intr_mask(hba);
9513
9514 err = ufshcd_set_dma_mask(hba);
9515 if (err) {
9516 dev_err(hba->dev, "set dma mask failed\n");
9517 goto out_disable;
9518 }
9519
9520
9521 err = ufshcd_memory_alloc(hba);
9522 if (err) {
9523 dev_err(hba->dev, "Memory allocation failed\n");
9524 goto out_disable;
9525 }
9526
9527
9528 ufshcd_host_memory_configure(hba);
9529
9530 host->can_queue = hba->nutrs;
9531 host->cmd_per_lun = hba->nutrs;
9532 host->max_id = UFSHCD_MAX_ID;
9533 host->max_lun = UFS_MAX_LUNS;
9534 host->max_channel = UFSHCD_MAX_CHANNEL;
9535 host->unique_id = host->host_no;
9536 host->max_cmd_len = UFS_CDB_SIZE;
9537
9538 hba->max_pwr_info.is_valid = false;
9539
9540
9541 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
9542 hba->host->host_no);
9543 hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
9544 if (!hba->eh_wq) {
9545 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
9546 __func__);
9547 err = -ENOMEM;
9548 goto out_disable;
9549 }
9550 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
9551 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
9552
9553 sema_init(&hba->host_sem, 1);
9554
9555
9556 mutex_init(&hba->uic_cmd_mutex);
9557
9558
9559 mutex_init(&hba->dev_cmd.lock);
9560
9561
9562 mutex_init(&hba->ee_ctrl_mutex);
9563
9564 init_rwsem(&hba->clk_scaling_lock);
9565
9566 ufshcd_init_clk_gating(hba);
9567
9568 ufshcd_init_clk_scaling(hba);
9569
9570
9571
9572
9573
9574
9575 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9576 REG_INTERRUPT_STATUS);
9577 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9578
9579
9580
9581
9582 mb();
9583
9584
9585 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
9586 if (err) {
9587 dev_err(hba->dev, "request irq failed\n");
9588 goto out_disable;
9589 } else {
9590 hba->is_irq_enabled = true;
9591 }
9592
9593 err = scsi_add_host(host, hba->dev);
9594 if (err) {
9595 dev_err(hba->dev, "scsi_add_host failed\n");
9596 goto out_disable;
9597 }
9598
9599 hba->cmd_queue = blk_mq_init_queue(&hba->host->tag_set);
9600 if (IS_ERR(hba->cmd_queue)) {
9601 err = PTR_ERR(hba->cmd_queue);
9602 goto out_remove_scsi_host;
9603 }
9604
9605 hba->tmf_tag_set = (struct blk_mq_tag_set) {
9606 .nr_hw_queues = 1,
9607 .queue_depth = hba->nutmrs,
9608 .ops = &ufshcd_tmf_ops,
9609 .flags = BLK_MQ_F_NO_SCHED,
9610 };
9611 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9612 if (err < 0)
9613 goto free_cmd_queue;
9614 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9615 if (IS_ERR(hba->tmf_queue)) {
9616 err = PTR_ERR(hba->tmf_queue);
9617 goto free_tmf_tag_set;
9618 }
9619 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
9620 sizeof(*hba->tmf_rqs), GFP_KERNEL);
9621 if (!hba->tmf_rqs) {
9622 err = -ENOMEM;
9623 goto free_tmf_queue;
9624 }
9625
9626
9627 ufshcd_device_reset(hba);
9628
9629 ufshcd_init_crypto(hba);
9630
9631
9632 err = ufshcd_hba_enable(hba);
9633 if (err) {
9634 dev_err(hba->dev, "Host controller enable failed\n");
9635 ufshcd_print_evt_hist(hba);
9636 ufshcd_print_host_state(hba);
9637 goto free_tmf_queue;
9638 }
9639
9640
9641
9642
9643
9644
9645 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9646 UFS_SLEEP_PWR_MODE,
9647 UIC_LINK_HIBERN8_STATE);
9648 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9649 UFS_SLEEP_PWR_MODE,
9650 UIC_LINK_HIBERN8_STATE);
9651
9652 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9653 ufshcd_rpm_dev_flush_recheck_work);
9654
9655
9656 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
9657 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9658 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9659 }
9660
9661
9662 pm_runtime_get_sync(dev);
9663 atomic_set(&hba->scsi_block_reqs_cnt, 0);
9664
9665
9666
9667
9668
9669
9670 ufshcd_set_ufs_dev_active(hba);
9671
9672 async_schedule(ufshcd_async_scan, hba);
9673 ufs_sysfs_add_nodes(hba->dev);
9674
9675 device_enable_async_suspend(dev);
9676 return 0;
9677
9678free_tmf_queue:
9679 blk_cleanup_queue(hba->tmf_queue);
9680free_tmf_tag_set:
9681 blk_mq_free_tag_set(&hba->tmf_tag_set);
9682free_cmd_queue:
9683 blk_cleanup_queue(hba->cmd_queue);
9684out_remove_scsi_host:
9685 scsi_remove_host(hba->host);
9686out_disable:
9687 hba->is_irq_enabled = false;
9688 ufshcd_hba_exit(hba);
9689out_error:
9690 return err;
9691}
9692EXPORT_SYMBOL_GPL(ufshcd_init);
9693
9694void ufshcd_resume_complete(struct device *dev)
9695{
9696 struct ufs_hba *hba = dev_get_drvdata(dev);
9697
9698 if (hba->complete_put) {
9699 ufshcd_rpm_put(hba);
9700 hba->complete_put = false;
9701 }
9702 if (hba->rpmb_complete_put) {
9703 ufshcd_rpmb_rpm_put(hba);
9704 hba->rpmb_complete_put = false;
9705 }
9706}
9707EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9708
9709int ufshcd_suspend_prepare(struct device *dev)
9710{
9711 struct ufs_hba *hba = dev_get_drvdata(dev);
9712 int ret;
9713
9714
9715
9716
9717
9718
9719
9720 if (hba->sdev_ufs_device) {
9721 ret = ufshcd_rpm_get_sync(hba);
9722 if (ret < 0 && ret != -EACCES) {
9723 ufshcd_rpm_put(hba);
9724 return ret;
9725 }
9726 hba->complete_put = true;
9727 }
9728 if (hba->sdev_rpmb) {
9729 ufshcd_rpmb_rpm_get_sync(hba);
9730 hba->rpmb_complete_put = true;
9731 }
9732 return 0;
9733}
9734EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9735
9736#ifdef CONFIG_PM_SLEEP
9737static int ufshcd_wl_poweroff(struct device *dev)
9738{
9739 struct scsi_device *sdev = to_scsi_device(dev);
9740 struct ufs_hba *hba = shost_priv(sdev->host);
9741
9742 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9743 return 0;
9744}
9745#endif
9746
9747static int ufshcd_wl_probe(struct device *dev)
9748{
9749 struct scsi_device *sdev = to_scsi_device(dev);
9750
9751 if (!is_device_wlun(sdev))
9752 return -ENODEV;
9753
9754 blk_pm_runtime_init(sdev->request_queue, dev);
9755 pm_runtime_set_autosuspend_delay(dev, 0);
9756 pm_runtime_allow(dev);
9757
9758 return 0;
9759}
9760
9761static int ufshcd_wl_remove(struct device *dev)
9762{
9763 pm_runtime_forbid(dev);
9764 return 0;
9765}
9766
9767static const struct dev_pm_ops ufshcd_wl_pm_ops = {
9768#ifdef CONFIG_PM_SLEEP
9769 .suspend = ufshcd_wl_suspend,
9770 .resume = ufshcd_wl_resume,
9771 .freeze = ufshcd_wl_suspend,
9772 .thaw = ufshcd_wl_resume,
9773 .poweroff = ufshcd_wl_poweroff,
9774 .restore = ufshcd_wl_resume,
9775#endif
9776 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
9777};
9778
9779
9780
9781
9782
9783
9784
9785
9786
9787
9788
9789static struct scsi_driver ufs_dev_wlun_template = {
9790 .gendrv = {
9791 .name = "ufs_device_wlun",
9792 .owner = THIS_MODULE,
9793 .probe = ufshcd_wl_probe,
9794 .remove = ufshcd_wl_remove,
9795 .pm = &ufshcd_wl_pm_ops,
9796 .shutdown = ufshcd_wl_shutdown,
9797 },
9798};
9799
9800static int ufshcd_rpmb_probe(struct device *dev)
9801{
9802 return is_rpmb_wlun(to_scsi_device(dev)) ? 0 : -ENODEV;
9803}
9804
9805static inline int ufshcd_clear_rpmb_uac(struct ufs_hba *hba)
9806{
9807 int ret = 0;
9808
9809 if (!hba->wlun_rpmb_clr_ua)
9810 return 0;
9811 ret = ufshcd_clear_ua_wlun(hba, UFS_UPIU_RPMB_WLUN);
9812 if (!ret)
9813 hba->wlun_rpmb_clr_ua = 0;
9814 return ret;
9815}
9816
9817#ifdef CONFIG_PM
9818static int ufshcd_rpmb_resume(struct device *dev)
9819{
9820 struct ufs_hba *hba = wlun_dev_to_hba(dev);
9821
9822 if (hba->sdev_rpmb)
9823 ufshcd_clear_rpmb_uac(hba);
9824 return 0;
9825}
9826#endif
9827
9828static const struct dev_pm_ops ufs_rpmb_pm_ops = {
9829 SET_RUNTIME_PM_OPS(NULL, ufshcd_rpmb_resume, NULL)
9830 SET_SYSTEM_SLEEP_PM_OPS(NULL, ufshcd_rpmb_resume)
9831};
9832
9833
9834static struct scsi_driver ufs_rpmb_wlun_template = {
9835 .gendrv = {
9836 .name = "ufs_rpmb_wlun",
9837 .owner = THIS_MODULE,
9838 .probe = ufshcd_rpmb_probe,
9839 .pm = &ufs_rpmb_pm_ops,
9840 },
9841};
9842
9843static int __init ufshcd_core_init(void)
9844{
9845 int ret;
9846
9847 ufs_debugfs_init();
9848
9849 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
9850 if (ret)
9851 goto debugfs_exit;
9852
9853 ret = scsi_register_driver(&ufs_rpmb_wlun_template.gendrv);
9854 if (ret)
9855 goto unregister;
9856
9857 return ret;
9858unregister:
9859 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9860debugfs_exit:
9861 ufs_debugfs_exit();
9862 return ret;
9863}
9864
9865static void __exit ufshcd_core_exit(void)
9866{
9867 ufs_debugfs_exit();
9868 scsi_unregister_driver(&ufs_rpmb_wlun_template.gendrv);
9869 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9870}
9871
9872module_init(ufshcd_core_init);
9873module_exit(ufshcd_core_exit);
9874
9875MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
9876MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
9877MODULE_DESCRIPTION("Generic UFS host controller driver Core");
9878MODULE_LICENSE("GPL");
9879MODULE_VERSION(UFSHCD_DRIVER_VERSION);
9880