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31#include "dpaa_sys.h"
32
33#include <soc/fsl/qman.h>
34#include <linux/dma-mapping.h>
35#include <linux/iommu.h>
36
37#if defined(CONFIG_FSL_PAMU)
38#include <asm/fsl_pamu_stash.h>
39#endif
40
41struct qm_mcr_querywq {
42 u8 verb;
43 u8 result;
44 u16 channel_wq;
45 u8 __reserved[28];
46 u32 wq_len[8];
47} __packed;
48
49static inline u16 qm_mcr_querywq_get_chan(const struct qm_mcr_querywq *wq)
50{
51 return wq->channel_wq >> 3;
52}
53
54struct __qm_mcr_querycongestion {
55 u32 state[8];
56};
57
58
59struct qm_mcr_querycongestion {
60 u8 verb;
61 u8 result;
62 u8 __reserved[30];
63
64 struct __qm_mcr_querycongestion state;
65} __packed;
66
67
68struct qm_mcr_querycgr {
69 u8 verb;
70 u8 result;
71 u16 __reserved1;
72 struct __qm_mc_cgr cgr;
73 u8 __reserved2[6];
74 u8 i_bcnt_hi;
75 __be32 i_bcnt_lo;
76 u8 __reserved3[3];
77 u8 a_bcnt_hi;
78 __be32 a_bcnt_lo;
79 __be32 cscn_targ_swp[4];
80} __packed;
81
82static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q)
83{
84 return ((u64)q->i_bcnt_hi << 32) | be32_to_cpu(q->i_bcnt_lo);
85}
86static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q)
87{
88 return ((u64)q->a_bcnt_hi << 32) | be32_to_cpu(q->a_bcnt_lo);
89}
90
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96
97
98
99#define CGR_BITS_PER_WORD 5
100#define CGR_WORD(x) ((x) >> CGR_BITS_PER_WORD)
101#define CGR_BIT(x) (BIT(31) >> ((x) & 0x1f))
102#define CGR_NUM (sizeof(struct __qm_mcr_querycongestion) << 3)
103
104struct qman_cgrs {
105 struct __qm_mcr_querycongestion q;
106};
107
108static inline void qman_cgrs_init(struct qman_cgrs *c)
109{
110 memset(c, 0, sizeof(*c));
111}
112
113static inline void qman_cgrs_fill(struct qman_cgrs *c)
114{
115 memset(c, 0xff, sizeof(*c));
116}
117
118static inline int qman_cgrs_get(struct qman_cgrs *c, u8 cgr)
119{
120 return c->q.state[CGR_WORD(cgr)] & CGR_BIT(cgr);
121}
122
123static inline void qman_cgrs_cp(struct qman_cgrs *dest,
124 const struct qman_cgrs *src)
125{
126 *dest = *src;
127}
128
129static inline void qman_cgrs_and(struct qman_cgrs *dest,
130 const struct qman_cgrs *a, const struct qman_cgrs *b)
131{
132 int ret;
133 u32 *_d = dest->q.state;
134 const u32 *_a = a->q.state;
135 const u32 *_b = b->q.state;
136
137 for (ret = 0; ret < 8; ret++)
138 *_d++ = *_a++ & *_b++;
139}
140
141static inline void qman_cgrs_xor(struct qman_cgrs *dest,
142 const struct qman_cgrs *a, const struct qman_cgrs *b)
143{
144 int ret;
145 u32 *_d = dest->q.state;
146 const u32 *_a = a->q.state;
147 const u32 *_b = b->q.state;
148
149 for (ret = 0; ret < 8; ret++)
150 *_d++ = *_a++ ^ *_b++;
151}
152
153void qman_init_cgr_all(void);
154
155struct qm_portal_config {
156
157 void *addr_virt_ce;
158 void __iomem *addr_virt_ci;
159 struct device *dev;
160 struct iommu_domain *iommu_domain;
161
162 struct list_head list;
163
164
165 int cpu;
166
167 int irq;
168
169
170
171
172 u16 channel;
173
174
175
176
177 u32 pools;
178};
179
180
181#define QMAN_REV11 0x0101
182#define QMAN_REV12 0x0102
183#define QMAN_REV20 0x0200
184#define QMAN_REV30 0x0300
185#define QMAN_REV31 0x0301
186#define QMAN_REV32 0x0302
187extern u16 qman_ip_rev;
188
189#define QM_FQID_RANGE_START 1
190extern struct gen_pool *qm_fqalloc;
191extern struct gen_pool *qm_qpalloc;
192extern struct gen_pool *qm_cgralloc;
193u32 qm_get_pools_sdqcr(void);
194
195int qman_wq_alloc(void);
196#ifdef CONFIG_FSL_PAMU
197#define qman_liodn_fixup __qman_liodn_fixup
198#else
199static inline void qman_liodn_fixup(u16 channel)
200{
201}
202#endif
203void __qman_liodn_fixup(u16 channel);
204void qman_set_sdest(u16 channel, unsigned int cpu_idx);
205
206struct qman_portal *qman_create_affine_portal(
207 const struct qm_portal_config *config,
208 const struct qman_cgrs *cgrs);
209const struct qm_portal_config *qman_destroy_affine_portal(void);
210
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214
215
216int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd);
217
218int qman_alloc_fq_table(u32 num_fqids);
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234
235#define QM_SDQCR_SOURCE_CHANNELS 0x0
236#define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000
237#define QM_SDQCR_COUNT_EXACT1 0x0
238#define QM_SDQCR_COUNT_UPTO3 0x20000000
239#define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000
240#define QM_SDQCR_TYPE_MASK 0x03000000
241#define QM_SDQCR_TYPE_NULL 0x0
242#define QM_SDQCR_TYPE_PRIO_QOS 0x01000000
243#define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000
244#define QM_SDQCR_TYPE_ACTIVE 0x03000000
245#define QM_SDQCR_TOKEN_MASK 0x00ff0000
246#define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16)
247#define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff)
248#define QM_SDQCR_CHANNELS_DEDICATED 0x00008000
249#define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7
250#define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000
251#define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
252#define QM_SDQCR_SPECIFICWQ_WQ(n) (n)
253
254
255#define QM_VDQCR_FQID_MASK 0x00ffffff
256#define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK)
257
258
259
260
261
262#define QM_PIRQ_DQAVAIL 0x0000ffff
263
264
265#define QM_DQAVAIL_PORTAL 0x8000
266#define QM_DQAVAIL_POOL(n) (0x8000 >> (n))
267#define QM_DQAVAIL_MASK 0xffff
268
269#define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI)
270
271extern struct qman_portal *affine_portals[NR_CPUS];
272extern struct qman_portal *qman_dma_portal;
273const struct qm_portal_config *qman_get_qm_portal_config(
274 struct qman_portal *portal);
275
276unsigned int qm_get_fqid_maxcnt(void);
277
278int qman_shutdown_fq(u32 fqid);
279
280int qman_requires_cleanup(void);
281void qman_done_cleanup(void);
282void qman_enable_irqs(void);
283