1
2
3
4
5
6
7
8
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/spi/spi.h>
21
22
23#define CDNS_SPI_NAME "cdns-spi"
24
25
26#define CDNS_SPI_CR 0x00
27#define CDNS_SPI_ISR 0x04
28#define CDNS_SPI_IER 0x08
29#define CDNS_SPI_IDR 0x0c
30#define CDNS_SPI_IMR 0x10
31#define CDNS_SPI_ER 0x14
32#define CDNS_SPI_DR 0x18
33#define CDNS_SPI_TXD 0x1C
34#define CDNS_SPI_RXD 0x20
35#define CDNS_SPI_SICR 0x24
36#define CDNS_SPI_THLD 0x28
37
38#define SPI_AUTOSUSPEND_TIMEOUT 3000
39
40
41
42
43
44
45#define CDNS_SPI_CR_MANSTRT 0x00010000
46#define CDNS_SPI_CR_CPHA 0x00000004
47#define CDNS_SPI_CR_CPOL 0x00000002
48#define CDNS_SPI_CR_SSCTRL 0x00003C00
49#define CDNS_SPI_CR_PERI_SEL 0x00000200
50#define CDNS_SPI_CR_BAUD_DIV 0x00000038
51#define CDNS_SPI_CR_MSTREN 0x00000001
52#define CDNS_SPI_CR_MANSTRTEN 0x00008000
53#define CDNS_SPI_CR_SSFORCE 0x00004000
54#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008
55#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
56 CDNS_SPI_CR_SSCTRL | \
57 CDNS_SPI_CR_SSFORCE | \
58 CDNS_SPI_CR_BAUD_DIV_4)
59
60
61
62
63
64
65
66
67#define CDNS_SPI_BAUD_DIV_MAX 7
68#define CDNS_SPI_BAUD_DIV_MIN 1
69#define CDNS_SPI_BAUD_DIV_SHIFT 3
70#define CDNS_SPI_SS_SHIFT 10
71#define CDNS_SPI_SS0 0x1
72
73
74
75
76
77
78
79#define CDNS_SPI_IXR_TXOW 0x00000004
80#define CDNS_SPI_IXR_MODF 0x00000002
81#define CDNS_SPI_IXR_RXNEMTY 0x00000010
82#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
83 CDNS_SPI_IXR_MODF)
84#define CDNS_SPI_IXR_TXFULL 0x00000008
85#define CDNS_SPI_IXR_ALL 0x0000007F
86
87
88
89
90
91
92#define CDNS_SPI_ER_ENABLE 0x00000001
93#define CDNS_SPI_ER_DISABLE 0x0
94
95
96#define CDNS_SPI_FIFO_DEPTH 128
97
98
99#define CDNS_SPI_DEFAULT_NUM_CS 4
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114struct cdns_spi {
115 void __iomem *regs;
116 struct clk *ref_clk;
117 struct clk *pclk;
118 unsigned int clk_rate;
119 u32 speed_hz;
120 const u8 *txbuf;
121 u8 *rxbuf;
122 int tx_bytes;
123 int rx_bytes;
124 u8 dev_busy;
125 u32 is_decoded_cs;
126};
127
128
129static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
130{
131 return readl_relaxed(xspi->regs + offset);
132}
133
134static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
135{
136 writel_relaxed(val, xspi->regs + offset);
137}
138
139
140
141
142
143
144
145
146
147
148
149
150static void cdns_spi_init_hw(struct cdns_spi *xspi)
151{
152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
153
154 if (xspi->is_decoded_cs)
155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
156
157 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
158 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
159
160
161 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
162 cdns_spi_read(xspi, CDNS_SPI_RXD);
163
164 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
165 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
166 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
167}
168
169
170
171
172
173
174static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
175{
176 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
177 u32 ctrl_reg;
178
179 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
180
181 if (is_high) {
182
183 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
184 } else {
185
186 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
187 if (!(xspi->is_decoded_cs))
188 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
189 CDNS_SPI_SS_SHIFT) &
190 CDNS_SPI_CR_SSCTRL;
191 else
192 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
193 CDNS_SPI_CR_SSCTRL;
194 }
195
196 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
197}
198
199
200
201
202
203
204
205static void cdns_spi_config_clock_mode(struct spi_device *spi)
206{
207 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
208 u32 ctrl_reg, new_ctrl_reg;
209
210 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
211 ctrl_reg = new_ctrl_reg;
212
213
214 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
215 if (spi->mode & SPI_CPHA)
216 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
217 if (spi->mode & SPI_CPOL)
218 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
219
220 if (new_ctrl_reg != ctrl_reg) {
221
222
223
224
225
226
227 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
228 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
229 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
230 }
231}
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247static void cdns_spi_config_clock_freq(struct spi_device *spi,
248 struct spi_transfer *transfer)
249{
250 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
251 u32 ctrl_reg, baud_rate_val;
252 unsigned long frequency;
253
254 frequency = xspi->clk_rate;
255
256 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
257
258
259 if (xspi->speed_hz != transfer->speed_hz) {
260
261 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
262 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
263 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
264 baud_rate_val++;
265
266 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
267 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
268
269 xspi->speed_hz = frequency / (2 << baud_rate_val);
270 }
271 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
272}
273
274
275
276
277
278
279
280
281
282
283
284
285static int cdns_spi_setup_transfer(struct spi_device *spi,
286 struct spi_transfer *transfer)
287{
288 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
289
290 cdns_spi_config_clock_freq(spi, transfer);
291
292 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
293 __func__, spi->mode, spi->bits_per_word,
294 xspi->speed_hz);
295
296 return 0;
297}
298
299
300
301
302
303static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
304{
305 unsigned long trans_cnt = 0;
306
307 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
308 (xspi->tx_bytes > 0)) {
309
310
311
312
313 if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
314 CDNS_SPI_IXR_TXFULL)
315 udelay(10);
316
317 if (xspi->txbuf)
318 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
319 else
320 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
321
322 xspi->tx_bytes--;
323 trans_cnt++;
324 }
325}
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
342{
343 struct spi_master *master = dev_id;
344 struct cdns_spi *xspi = spi_master_get_devdata(master);
345 u32 intr_status, status;
346
347 status = IRQ_NONE;
348 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
349 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
350
351 if (intr_status & CDNS_SPI_IXR_MODF) {
352
353
354
355
356 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
357 spi_finalize_current_transfer(master);
358 status = IRQ_HANDLED;
359 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
360 unsigned long trans_cnt;
361
362 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
363
364
365 while (trans_cnt) {
366 u8 data;
367
368 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
369 if (xspi->rxbuf)
370 *xspi->rxbuf++ = data;
371
372 xspi->rx_bytes--;
373 trans_cnt--;
374 }
375
376 if (xspi->tx_bytes) {
377
378 cdns_spi_fill_tx_fifo(xspi);
379 } else {
380
381 cdns_spi_write(xspi, CDNS_SPI_IDR,
382 CDNS_SPI_IXR_DEFAULT);
383 spi_finalize_current_transfer(master);
384 }
385 status = IRQ_HANDLED;
386 }
387
388 return status;
389}
390
391static int cdns_prepare_message(struct spi_master *master,
392 struct spi_message *msg)
393{
394 cdns_spi_config_clock_mode(msg->spi);
395 return 0;
396}
397
398
399
400
401
402
403
404
405
406
407
408
409
410static int cdns_transfer_one(struct spi_master *master,
411 struct spi_device *spi,
412 struct spi_transfer *transfer)
413{
414 struct cdns_spi *xspi = spi_master_get_devdata(master);
415
416 xspi->txbuf = transfer->tx_buf;
417 xspi->rxbuf = transfer->rx_buf;
418 xspi->tx_bytes = transfer->len;
419 xspi->rx_bytes = transfer->len;
420
421 cdns_spi_setup_transfer(spi, transfer);
422 cdns_spi_fill_tx_fifo(xspi);
423 spi_transfer_delay_exec(transfer);
424
425 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
426 return transfer->len;
427}
428
429
430
431
432
433
434
435
436
437
438static int cdns_prepare_transfer_hardware(struct spi_master *master)
439{
440 struct cdns_spi *xspi = spi_master_get_devdata(master);
441
442 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
443
444 return 0;
445}
446
447
448
449
450
451
452
453
454
455
456static int cdns_unprepare_transfer_hardware(struct spi_master *master)
457{
458 struct cdns_spi *xspi = spi_master_get_devdata(master);
459
460 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
461
462 return 0;
463}
464
465
466
467
468
469
470
471
472
473static int cdns_spi_probe(struct platform_device *pdev)
474{
475 int ret = 0, irq;
476 struct spi_master *master;
477 struct cdns_spi *xspi;
478 u32 num_cs;
479
480 master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
481 if (!master)
482 return -ENOMEM;
483
484 xspi = spi_master_get_devdata(master);
485 master->dev.of_node = pdev->dev.of_node;
486 platform_set_drvdata(pdev, master);
487
488 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
489 if (IS_ERR(xspi->regs)) {
490 ret = PTR_ERR(xspi->regs);
491 goto remove_master;
492 }
493
494 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
495 if (IS_ERR(xspi->pclk)) {
496 dev_err(&pdev->dev, "pclk clock not found.\n");
497 ret = PTR_ERR(xspi->pclk);
498 goto remove_master;
499 }
500
501 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
502 if (IS_ERR(xspi->ref_clk)) {
503 dev_err(&pdev->dev, "ref_clk clock not found.\n");
504 ret = PTR_ERR(xspi->ref_clk);
505 goto remove_master;
506 }
507
508 ret = clk_prepare_enable(xspi->pclk);
509 if (ret) {
510 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
511 goto remove_master;
512 }
513
514 ret = clk_prepare_enable(xspi->ref_clk);
515 if (ret) {
516 dev_err(&pdev->dev, "Unable to enable device clock.\n");
517 goto clk_dis_apb;
518 }
519
520 pm_runtime_use_autosuspend(&pdev->dev);
521 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
522 pm_runtime_get_noresume(&pdev->dev);
523 pm_runtime_set_active(&pdev->dev);
524 pm_runtime_enable(&pdev->dev);
525
526 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
527 if (ret < 0)
528 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
529 else
530 master->num_chipselect = num_cs;
531
532 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
533 &xspi->is_decoded_cs);
534 if (ret < 0)
535 xspi->is_decoded_cs = 0;
536
537
538 cdns_spi_init_hw(xspi);
539
540 irq = platform_get_irq(pdev, 0);
541 if (irq <= 0) {
542 ret = -ENXIO;
543 goto clk_dis_all;
544 }
545
546 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
547 0, pdev->name, master);
548 if (ret != 0) {
549 ret = -ENXIO;
550 dev_err(&pdev->dev, "request_irq failed\n");
551 goto clk_dis_all;
552 }
553
554 master->use_gpio_descriptors = true;
555 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
556 master->prepare_message = cdns_prepare_message;
557 master->transfer_one = cdns_transfer_one;
558 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
559 master->set_cs = cdns_spi_chipselect;
560 master->auto_runtime_pm = true;
561 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
562
563 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
564
565 master->max_speed_hz = xspi->clk_rate / 4;
566 xspi->speed_hz = master->max_speed_hz;
567
568 master->bits_per_word_mask = SPI_BPW_MASK(8);
569
570 pm_runtime_mark_last_busy(&pdev->dev);
571 pm_runtime_put_autosuspend(&pdev->dev);
572
573 ret = spi_register_master(master);
574 if (ret) {
575 dev_err(&pdev->dev, "spi_register_master failed\n");
576 goto clk_dis_all;
577 }
578
579 return ret;
580
581clk_dis_all:
582 pm_runtime_set_suspended(&pdev->dev);
583 pm_runtime_disable(&pdev->dev);
584 clk_disable_unprepare(xspi->ref_clk);
585clk_dis_apb:
586 clk_disable_unprepare(xspi->pclk);
587remove_master:
588 spi_master_put(master);
589 return ret;
590}
591
592
593
594
595
596
597
598
599
600
601
602static int cdns_spi_remove(struct platform_device *pdev)
603{
604 struct spi_master *master = platform_get_drvdata(pdev);
605 struct cdns_spi *xspi = spi_master_get_devdata(master);
606
607 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
608
609 clk_disable_unprepare(xspi->ref_clk);
610 clk_disable_unprepare(xspi->pclk);
611 pm_runtime_set_suspended(&pdev->dev);
612 pm_runtime_disable(&pdev->dev);
613
614 spi_unregister_master(master);
615
616 return 0;
617}
618
619
620
621
622
623
624
625
626
627
628static int __maybe_unused cdns_spi_suspend(struct device *dev)
629{
630 struct spi_master *master = dev_get_drvdata(dev);
631
632 return spi_master_suspend(master);
633}
634
635
636
637
638
639
640
641
642
643static int __maybe_unused cdns_spi_resume(struct device *dev)
644{
645 struct spi_master *master = dev_get_drvdata(dev);
646 struct cdns_spi *xspi = spi_master_get_devdata(master);
647
648 cdns_spi_init_hw(xspi);
649 return spi_master_resume(master);
650}
651
652
653
654
655
656
657
658
659
660static int __maybe_unused cnds_runtime_resume(struct device *dev)
661{
662 struct spi_master *master = dev_get_drvdata(dev);
663 struct cdns_spi *xspi = spi_master_get_devdata(master);
664 int ret;
665
666 ret = clk_prepare_enable(xspi->pclk);
667 if (ret) {
668 dev_err(dev, "Cannot enable APB clock.\n");
669 return ret;
670 }
671
672 ret = clk_prepare_enable(xspi->ref_clk);
673 if (ret) {
674 dev_err(dev, "Cannot enable device clock.\n");
675 clk_disable_unprepare(xspi->pclk);
676 return ret;
677 }
678 return 0;
679}
680
681
682
683
684
685
686
687
688
689static int __maybe_unused cnds_runtime_suspend(struct device *dev)
690{
691 struct spi_master *master = dev_get_drvdata(dev);
692 struct cdns_spi *xspi = spi_master_get_devdata(master);
693
694 clk_disable_unprepare(xspi->ref_clk);
695 clk_disable_unprepare(xspi->pclk);
696
697 return 0;
698}
699
700static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
701 SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
702 cnds_runtime_resume, NULL)
703 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
704};
705
706static const struct of_device_id cdns_spi_of_match[] = {
707 { .compatible = "xlnx,zynq-spi-r1p6" },
708 { .compatible = "cdns,spi-r1p6" },
709 { }
710};
711MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
712
713
714static struct platform_driver cdns_spi_driver = {
715 .probe = cdns_spi_probe,
716 .remove = cdns_spi_remove,
717 .driver = {
718 .name = CDNS_SPI_NAME,
719 .of_match_table = cdns_spi_of_match,
720 .pm = &cdns_spi_dev_pm_ops,
721 },
722};
723
724module_platform_driver(cdns_spi_driver);
725
726MODULE_AUTHOR("Xilinx, Inc.");
727MODULE_DESCRIPTION("Cadence SPI driver");
728MODULE_LICENSE("GPL");
729