1
2
3
4#include <linux/bitfield.h>
5#include <linux/bits.h>
6#include <linux/fsi.h>
7#include <linux/jiffies.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/spi/spi.h>
12
13#define FSI_ENGID_SPI 0x23
14#define FSI_MBOX_ROOT_CTRL_8 0x2860
15#define FSI_MBOX_ROOT_CTRL_8_SPI_MUX 0xf0000000
16
17#define FSI2SPI_DATA0 0x00
18#define FSI2SPI_DATA1 0x04
19#define FSI2SPI_CMD 0x08
20#define FSI2SPI_CMD_WRITE BIT(31)
21#define FSI2SPI_RESET 0x18
22#define FSI2SPI_STATUS 0x1c
23#define FSI2SPI_STATUS_ANY_ERROR BIT(31)
24#define FSI2SPI_IRQ 0x20
25
26#define SPI_FSI_BASE 0x70000
27#define SPI_FSI_INIT_TIMEOUT_MS 1000
28#define SPI_FSI_MAX_RX_SIZE 8
29#define SPI_FSI_MAX_TX_SIZE 40
30
31#define SPI_FSI_ERROR 0x0
32#define SPI_FSI_COUNTER_CFG 0x1
33#define SPI_FSI_CFG1 0x2
34#define SPI_FSI_CLOCK_CFG 0x3
35#define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32)
36#define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33))
37#define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38))
38#define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39))
39#define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42))
40#define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44)
41#define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51)
42#define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52)
43#define SPI_FSI_MMAP 0x4
44#define SPI_FSI_DATA_TX 0x5
45#define SPI_FSI_DATA_RX 0x6
46#define SPI_FSI_SEQUENCE 0x7
47#define SPI_FSI_SEQUENCE_STOP 0x00
48#define SPI_FSI_SEQUENCE_SEL_SLAVE(x) (0x10 | ((x) & 0xf))
49#define SPI_FSI_SEQUENCE_SHIFT_OUT(x) (0x30 | ((x) & 0xf))
50#define SPI_FSI_SEQUENCE_SHIFT_IN(x) (0x40 | ((x) & 0xf))
51#define SPI_FSI_SEQUENCE_COPY_DATA_TX 0xc0
52#define SPI_FSI_SEQUENCE_BRANCH(x) (0xe0 | ((x) & 0xf))
53#define SPI_FSI_STATUS 0x8
54#define SPI_FSI_STATUS_ERROR \
55 (GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12))
56#define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48)
57#define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48)
58#define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57)
59#define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58)
60#define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59)
61#define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61)
62#define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62)
63#define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63)
64#define SPI_FSI_STATUS_ANY_ERROR \
65 (SPI_FSI_STATUS_ERROR | \
66 SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \
67 SPI_FSI_STATUS_RDR_OVERRUN)
68#define SPI_FSI_PORT_CTRL 0x9
69
70struct fsi_spi {
71 struct device *dev;
72 struct fsi_device *fsi;
73 u32 base;
74};
75
76struct fsi_spi_sequence {
77 int bit;
78 u64 data;
79};
80
81static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev)
82{
83 int rc;
84 u32 root_ctrl_8;
85 __be32 root_ctrl_8_be;
86
87 rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be,
88 sizeof(root_ctrl_8_be));
89 if (rc)
90 return rc;
91
92 root_ctrl_8 = be32_to_cpu(root_ctrl_8_be);
93 dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8);
94 if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) ==
95 FSI_MBOX_ROOT_CTRL_8_SPI_MUX)
96 return 0;
97
98 return -ENOLINK;
99}
100
101static int fsi_spi_check_status(struct fsi_spi *ctx)
102{
103 int rc;
104 u32 sts;
105 __be32 sts_be;
106
107 rc = fsi_device_read(ctx->fsi, FSI2SPI_STATUS, &sts_be,
108 sizeof(sts_be));
109 if (rc)
110 return rc;
111
112 sts = be32_to_cpu(sts_be);
113 if (sts & FSI2SPI_STATUS_ANY_ERROR) {
114 dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts);
115 return -EIO;
116 }
117
118 return 0;
119}
120
121static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value)
122{
123 int rc;
124 __be32 cmd_be;
125 __be32 data_be;
126 u32 cmd = offset + ctx->base;
127
128 *value = 0ULL;
129
130 if (cmd & FSI2SPI_CMD_WRITE)
131 return -EINVAL;
132
133 cmd_be = cpu_to_be32(cmd);
134 rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be));
135 if (rc)
136 return rc;
137
138 rc = fsi_spi_check_status(ctx);
139 if (rc)
140 return rc;
141
142 rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA0, &data_be,
143 sizeof(data_be));
144 if (rc)
145 return rc;
146
147 *value |= (u64)be32_to_cpu(data_be) << 32;
148
149 rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA1, &data_be,
150 sizeof(data_be));
151 if (rc)
152 return rc;
153
154 *value |= (u64)be32_to_cpu(data_be);
155 dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value);
156
157 return 0;
158}
159
160static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value)
161{
162 int rc;
163 __be32 cmd_be;
164 __be32 data_be;
165 u32 cmd = offset + ctx->base;
166
167 if (cmd & FSI2SPI_CMD_WRITE)
168 return -EINVAL;
169
170 dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value);
171
172 data_be = cpu_to_be32(upper_32_bits(value));
173 rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA0, &data_be,
174 sizeof(data_be));
175 if (rc)
176 return rc;
177
178 data_be = cpu_to_be32(lower_32_bits(value));
179 rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA1, &data_be,
180 sizeof(data_be));
181 if (rc)
182 return rc;
183
184 cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE);
185 rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be));
186 if (rc)
187 return rc;
188
189 return fsi_spi_check_status(ctx);
190}
191
192static int fsi_spi_data_in(u64 in, u8 *rx, int len)
193{
194 int i;
195 int num_bytes = min(len, 8);
196
197 for (i = 0; i < num_bytes; ++i)
198 rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i)));
199
200 return num_bytes;
201}
202
203static int fsi_spi_data_out(u64 *out, const u8 *tx, int len)
204{
205 int i;
206 int num_bytes = min(len, 8);
207 u8 *out_bytes = (u8 *)out;
208
209
210 *out = 0ULL;
211
212 for (i = 0; i < num_bytes; ++i)
213 out_bytes[8 - (i + 1)] = tx[i];
214
215 return num_bytes;
216}
217
218static int fsi_spi_reset(struct fsi_spi *ctx)
219{
220 int rc;
221
222 dev_dbg(ctx->dev, "Resetting SPI controller.\n");
223
224 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
225 SPI_FSI_CLOCK_CFG_RESET1);
226 if (rc)
227 return rc;
228
229 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
230 SPI_FSI_CLOCK_CFG_RESET2);
231 if (rc)
232 return rc;
233
234 return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);
235}
236
237static void fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
238{
239
240
241
242
243
244
245 seq->data |= (u64)val << seq->bit;
246 seq->bit -= 8;
247}
248
249static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq)
250{
251 seq->bit = 56;
252 seq->data = 0ULL;
253}
254
255static int fsi_spi_transfer_data(struct fsi_spi *ctx,
256 struct spi_transfer *transfer)
257{
258 int rc = 0;
259 u64 status = 0ULL;
260
261 if (transfer->tx_buf) {
262 int nb;
263 int sent = 0;
264 u64 out = 0ULL;
265 const u8 *tx = transfer->tx_buf;
266
267 while (transfer->len > sent) {
268 nb = fsi_spi_data_out(&out, &tx[sent],
269 (int)transfer->len - sent);
270
271 rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out);
272 if (rc)
273 return rc;
274
275 do {
276 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
277 &status);
278 if (rc)
279 return rc;
280
281 if (status & SPI_FSI_STATUS_ANY_ERROR) {
282 rc = fsi_spi_reset(ctx);
283 if (rc)
284 return rc;
285
286 return -EREMOTEIO;
287 }
288 } while (status & SPI_FSI_STATUS_TDR_FULL);
289
290 sent += nb;
291 }
292 } else if (transfer->rx_buf) {
293 int recv = 0;
294 u64 in = 0ULL;
295 u8 *rx = transfer->rx_buf;
296
297 while (transfer->len > recv) {
298 do {
299 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
300 &status);
301 if (rc)
302 return rc;
303
304 if (status & SPI_FSI_STATUS_ANY_ERROR) {
305 rc = fsi_spi_reset(ctx);
306 if (rc)
307 return rc;
308
309 return -EREMOTEIO;
310 }
311 } while (!(status & SPI_FSI_STATUS_RDR_FULL));
312
313 rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in);
314 if (rc)
315 return rc;
316
317 recv += fsi_spi_data_in(in, &rx[recv],
318 (int)transfer->len - recv);
319 }
320 }
321
322 return 0;
323}
324
325static int fsi_spi_transfer_init(struct fsi_spi *ctx)
326{
327 int rc;
328 bool reset = false;
329 unsigned long end;
330 u64 seq_state;
331 u64 clock_cfg = 0ULL;
332 u64 status = 0ULL;
333 u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |
334 SPI_FSI_CLOCK_CFG_SCK_NO_DEL |
335 FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);
336
337 end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);
338 do {
339 if (time_after(jiffies, end))
340 return -ETIMEDOUT;
341
342 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);
343 if (rc)
344 return rc;
345
346 seq_state = status & SPI_FSI_STATUS_SEQ_STATE;
347
348 if (status & (SPI_FSI_STATUS_ANY_ERROR |
349 SPI_FSI_STATUS_TDR_FULL |
350 SPI_FSI_STATUS_RDR_FULL)) {
351 if (reset)
352 return -EIO;
353
354 rc = fsi_spi_reset(ctx);
355 if (rc)
356 return rc;
357
358 reset = true;
359 continue;
360 }
361 } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE));
362
363 rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);
364 if (rc)
365 return rc;
366
367 rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
368 if (rc)
369 return rc;
370
371 if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |
372 SPI_FSI_CLOCK_CFG_ECC_DISABLE |
373 SPI_FSI_CLOCK_CFG_MODE |
374 SPI_FSI_CLOCK_CFG_SCK_RECV_DEL |
375 SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg)
376 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
377 wanted_clock_cfg);
378
379 return rc;
380}
381
382static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,
383 struct spi_message *mesg)
384{
385 int rc;
386 u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1);
387 unsigned int len;
388 struct spi_transfer *transfer;
389 struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
390
391 rc = fsi_spi_check_mux(ctx->fsi, ctx->dev);
392 if (rc)
393 goto error;
394
395 list_for_each_entry(transfer, &mesg->transfers, transfer_list) {
396 struct fsi_spi_sequence seq;
397 struct spi_transfer *next = NULL;
398
399
400 if (!transfer->tx_buf || transfer->len > SPI_FSI_MAX_TX_SIZE) {
401 rc = -EINVAL;
402 goto error;
403 }
404
405 dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len);
406
407 rc = fsi_spi_transfer_init(ctx);
408 if (rc < 0)
409 goto error;
410
411 fsi_spi_sequence_init(&seq);
412 fsi_spi_sequence_add(&seq, seq_slave);
413
414 len = transfer->len;
415 while (len > 8) {
416 fsi_spi_sequence_add(&seq,
417 SPI_FSI_SEQUENCE_SHIFT_OUT(8));
418 len -= 8;
419 }
420 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SHIFT_OUT(len));
421
422 if (!list_is_last(&transfer->transfer_list,
423 &mesg->transfers)) {
424 next = list_next_entry(transfer, transfer_list);
425
426
427 if (next->rx_buf) {
428 u8 shift;
429
430 if (next->len > SPI_FSI_MAX_RX_SIZE) {
431 rc = -EINVAL;
432 goto error;
433 }
434
435 dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n",
436 next->len);
437
438 shift = SPI_FSI_SEQUENCE_SHIFT_IN(next->len);
439 fsi_spi_sequence_add(&seq, shift);
440 } else {
441 next = NULL;
442 }
443 }
444
445 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0));
446
447 rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data);
448 if (rc)
449 goto error;
450
451 rc = fsi_spi_transfer_data(ctx, transfer);
452 if (rc)
453 goto error;
454
455 if (next) {
456 rc = fsi_spi_transfer_data(ctx, next);
457 if (rc)
458 goto error;
459
460 transfer = next;
461 }
462 }
463
464error:
465 mesg->status = rc;
466 spi_finalize_current_message(ctlr);
467
468 return rc;
469}
470
471static size_t fsi_spi_max_transfer_size(struct spi_device *spi)
472{
473 return SPI_FSI_MAX_RX_SIZE;
474}
475
476static int fsi_spi_probe(struct device *dev)
477{
478 int rc;
479 struct device_node *np;
480 int num_controllers_registered = 0;
481 struct fsi_device *fsi = to_fsi_dev(dev);
482
483 rc = fsi_spi_check_mux(fsi, dev);
484 if (rc)
485 return -ENODEV;
486
487 for_each_available_child_of_node(dev->of_node, np) {
488 u32 base;
489 struct fsi_spi *ctx;
490 struct spi_controller *ctlr;
491
492 if (of_property_read_u32(np, "reg", &base))
493 continue;
494
495 ctlr = spi_alloc_master(dev, sizeof(*ctx));
496 if (!ctlr) {
497 of_node_put(np);
498 break;
499 }
500
501 ctlr->dev.of_node = np;
502 ctlr->num_chipselect = of_get_available_child_count(np) ?: 1;
503 ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
504 ctlr->max_transfer_size = fsi_spi_max_transfer_size;
505 ctlr->transfer_one_message = fsi_spi_transfer_one_message;
506
507 ctx = spi_controller_get_devdata(ctlr);
508 ctx->dev = &ctlr->dev;
509 ctx->fsi = fsi;
510 ctx->base = base + SPI_FSI_BASE;
511
512 rc = devm_spi_register_controller(dev, ctlr);
513 if (rc)
514 spi_controller_put(ctlr);
515 else
516 num_controllers_registered++;
517 }
518
519 if (!num_controllers_registered)
520 return -ENODEV;
521
522 return 0;
523}
524
525static const struct fsi_device_id fsi_spi_ids[] = {
526 { FSI_ENGID_SPI, FSI_VERSION_ANY },
527 { }
528};
529MODULE_DEVICE_TABLE(fsi, fsi_spi_ids);
530
531static struct fsi_driver fsi_spi_driver = {
532 .id_table = fsi_spi_ids,
533 .drv = {
534 .name = "spi-fsi",
535 .bus = &fsi_bus_type,
536 .probe = fsi_spi_probe,
537 },
538};
539module_fsi_driver(fsi_spi_driver);
540
541MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>");
542MODULE_DESCRIPTION("FSI attached SPI controller");
543MODULE_LICENSE("GPL");
544
