LXR linux/drivers/spi/spi-pxa2xx.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   4 * Copyright (C) 2013, 2021 Intel Corporation
   5 */
   6
   7#ifndef SPI_PXA2XX_H
   8#define SPI_PXA2XX_H
   9
  10#include <linux/interrupt.h>
  11#include <linux/io.h>
  12#include <linux/types.h>
  13#include <linux/sizes.h>
  14
  15#include <linux/pxa2xx_ssp.h>
  16
  17struct gpio_desc;
  18struct pxa2xx_spi_controller;
  19struct spi_controller;
  20struct spi_device;
  21struct spi_transfer;
  22
  23struct driver_data {
  24        /* SSP Info */
  25        struct ssp_device *ssp;
  26
  27        /* SPI framework hookup */
  28        enum pxa_ssp_type ssp_type;
  29        struct spi_controller *controller;
  30
  31        /* PXA hookup */
  32        struct pxa2xx_spi_controller *controller_info;
  33
  34        /* SSP masks*/
  35        u32 dma_cr1;
  36        u32 int_cr1;
  37        u32 clear_sr;
  38        u32 mask_sr;
  39
  40        /* DMA engine support */
  41        atomic_t dma_running;
  42
  43        /* Current transfer state info */
  44        void *tx;
  45        void *tx_end;
  46        void *rx;
  47        void *rx_end;
  48        u8 n_bytes;
  49        int (*write)(struct driver_data *drv_data);
  50        int (*read)(struct driver_data *drv_data);
  51        irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
  52        void (*cs_control)(u32 command);
  53
  54        void __iomem *lpss_base;
  55
  56        /* Optional slave FIFO ready signal */
  57        struct gpio_desc *gpiod_ready;
  58};
  59
  60struct chip_data {
  61        u32 cr1;
  62        u32 dds_rate;
  63        u32 timeout;
  64        u8 n_bytes;
  65        u8 enable_dma;
  66        u32 dma_burst_size;
  67        u32 dma_threshold;
  68        u32 threshold;
  69        u16 lpss_rx_threshold;
  70        u16 lpss_tx_threshold;
  71
  72        int (*write)(struct driver_data *drv_data);
  73        int (*read)(struct driver_data *drv_data);
  74
  75        void (*cs_control)(u32 command);
  76};
  77
  78static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
  79{
  80        return pxa_ssp_read_reg(drv_data->ssp, reg);
  81}
  82
  83static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
  84{
  85        pxa_ssp_write_reg(drv_data->ssp, reg, val);
  86}
  87
  88#define DMA_ALIGNMENT           8
  89
  90static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
  91{
  92        switch (drv_data->ssp_type) {
  93        case PXA25x_SSP:
  94        case CE4100_SSP:
  95        case QUARK_X1000_SSP:
  96                return 1;
  97        default:
  98                return 0;
  99        }
 100}
 101
 102static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
 103{
 104        pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
 105}
 106
 107static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
 108{
 109        return pxa2xx_spi_read(drv_data, SSSR) & bits;
 110}
 111
 112static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
 113{
 114        if (drv_data->ssp_type == CE4100_SSP ||
 115            drv_data->ssp_type == QUARK_X1000_SSP)
 116                val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
 117
 118        pxa2xx_spi_write(drv_data, SSSR, val);
 119}
 120
 121extern int pxa2xx_spi_flush(struct driver_data *drv_data);
 122
 123#define MAX_DMA_LEN             SZ_64K
 124#define DEFAULT_DMA_CR1         (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
 125
 126extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
 127extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
 128                                  struct spi_transfer *xfer);
 129extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
 130extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
 131extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
 132extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
 133extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
 134                                                  struct spi_device *spi,
 135                                                  u8 bits_per_word,
 136                                                  u32 *burst_code,
 137                                                  u32 *threshold);
 138
 139#endif /* SPI_PXA2XX_H */
 140