1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * EMXX FCD (Function Controller Driver) for USB. 4 * 5 * Copyright (C) 2010 Renesas Electronics Corporation 6 */ 7 8#ifndef _LINUX_EMXX_H 9#define _LINUX_EMXX_H 10 11/*---------------------------------------------------------------------------*/ 12 13/*----------------- Default define */ 14#define USE_DMA 1 15#define USE_SUSPEND_WAIT 1 16 17/*------------ Board dependence(Resource) */ 18#define VBUS_VALUE GPIO_VBUS 19 20/* below hacked up for staging integration */ 21#define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */ 22#define INT_VBUS 0 /* IRQ for GPIO_P153 */ 23 24/*------------ Board dependence(Wait) */ 25 26/* CHATTERING wait time ms */ 27#define VBUS_CHATTERING_MDELAY 1 28/* DMA Abort wait time ms */ 29#define DMA_DISABLE_TIME 10 30 31/*------------ Controller dependence */ 32#define NUM_ENDPOINTS 14 /* Endpoint */ 33#define REG_EP_NUM 15 /* Endpoint Register */ 34#define DMA_MAX_COUNT 256 /* DMA Block */ 35 36#define EPC_RST_DISABLE_TIME 1 /* 1 usec */ 37#define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */ 38#define EPC_PLL_LOCK_COUNT 1000 /* 1000 */ 39#define IN_DATA_EMPTY_COUNT 1000 /* 1000 */ 40 41#define CHATGER_TIME 700 /* 700msec */ 42#define USB_SUSPEND_TIME 2000 /* 2 sec */ 43 44/* U2F FLAG */ 45#define U2F_ENABLE 1 46#define U2F_DISABLE 0 47 48#define TEST_FORCE_ENABLE (BIT(18) | BIT(16)) 49 50#define INT_SEL BIT(10) 51#define CONSTFS BIT(9) 52#define SOF_RCV BIT(8) 53#define RSUM_IN BIT(7) 54#define SUSPEND BIT(6) 55#define CONF BIT(5) 56#define DEFAULT BIT(4) 57#define CONNECTB BIT(3) 58#define PUE2 BIT(2) 59 60#define MAX_TEST_MODE_NUM 0x05 61#define TEST_MODE_SHIFT 16 62 63/*------- (0x0004) USB Status Register */ 64#define SPEED_MODE BIT(6) 65#define HIGH_SPEED BIT(6) 66 67#define CONF BIT(5) 68#define DEFAULT BIT(4) 69#define USB_RST BIT(3) 70#define SPND_OUT BIT(2) 71#define RSUM_OUT BIT(1) 72 73/*------- (0x0008) USB Address Register */ 74#define USB_ADDR 0x007F0000 75#define SOF_STATUS BIT(15) 76#define UFRAME (BIT(14) | BIT(13) | BIT(12)) 77#define FRAME 0x000007FF 78 79#define USB_ADRS_SHIFT 16 80 81/*------- (0x000C) UTMI Characteristic 1 Register */ 82#define SQUSET (BIT(7) | BIT(6) | BIT(5) | BIT(4)) 83 84#define USB_SQUSET (BIT(6) | BIT(5) | BIT(4)) 85 86/*------- (0x0010) TEST Control Register */ 87#define FORCEHS BIT(2) 88#define CS_TESTMODEEN BIT(1) 89#define LOOPBACK BIT(0) 90 91/*------- (0x0018) Setup Data 0 Register */ 92/*------- (0x001C) Setup Data 1 Register */ 93 94/*------- (0x0020) USB Interrupt Status Register */ 95#define EPN_INT 0x00FFFF00 96#define EP15_INT BIT(23) 97#define EP14_INT BIT(22) 98#define EP13_INT BIT(21) 99#define EP12_INT BIT(20) 100#define EP11_INT BIT(19) 101#define EP10_INT BIT(18) 102#define EP9_INT BIT(17) 103#define EP8_INT BIT(16) 104#define EP7_INT BIT(15) 105#define EP6_INT BIT(14) 106#define EP5_INT BIT(13) 107#define EP4_INT BIT(12) 108#define EP3_INT BIT(11) 109#define EP2_INT BIT(10) 110#define EP1_INT BIT(9) 111#define EP0_INT BIT(8) 112#define SPEED_MODE_INT BIT(6) 113#define SOF_ERROR_INT BIT(5) 114#define SOF_INT BIT(4) 115#define USB_RST_INT BIT(3) 116#define SPND_INT BIT(2) 117#define RSUM_INT BIT(1) 118 119#define USB_INT_STA_RW 0x7E 120 121/*------- (0x0024) USB Interrupt Enable Register */ 122#define EP15_0_EN 0x00FFFF00 123#define EP15_EN BIT(23) 124#define EP14_EN BIT(22) 125#define EP13_EN BIT(21) 126#define EP12_EN BIT(20) 127#define EP11_EN BIT(19) 128#define EP10_EN BIT(18) 129#define EP9_EN BIT(17) 130#define EP8_EN BIT(16) 131#define EP7_EN BIT(15) 132#define EP6_EN BIT(14) 133#define EP5_EN BIT(13) 134#define EP4_EN BIT(12) 135#define EP3_EN BIT(11) 136#define EP2_EN BIT(10) 137#define EP1_EN BIT(9) 138#define EP0_EN BIT(8) 139#define SPEED_MODE_EN BIT(6) 140#define SOF_ERROR_EN BIT(5) 141#define SOF_EN BIT(4) 142#define USB_RST_EN BIT(3) 143#define SPND_EN BIT(2) 144#define RSUM_EN BIT(1) 145 146#define USB_INT_EN_BIT \ 147 (EP0_EN | SPEED_MODE_EN | USB_RST_EN | SPND_EN | RSUM_EN) 148 149/*------- (0x0028) EP0 Control Register */ 150#define EP0_STGSEL BIT(18) 151#define EP0_OVERSEL BIT(17) 152#define EP0_AUTO BIT(16) 153#define EP0_PIDCLR BIT(9) 154#define EP0_BCLR BIT(8) 155#define EP0_DEND BIT(7) 156#define EP0_DW (BIT(6) | BIT(5)) 157#define EP0_DW4 0 158#define EP0_DW3 (BIT(6) | BIT(5)) 159#define EP0_DW2 BIT(6) 160#define EP0_DW1 BIT(5) 161 162#define EP0_INAK_EN BIT(4) 163#define EP0_PERR_NAK_CLR BIT(3) 164#define EP0_STL BIT(2) 165#define EP0_INAK BIT(1) 166#define EP0_ONAK BIT(0) 167 168/*------- (0x002C) EP0 Status Register */ 169#define EP0_PID BIT(18) 170#define EP0_PERR_NAK BIT(17) 171#define EP0_PERR_NAK_INT BIT(16) 172#define EP0_OUT_NAK_INT BIT(15) 173#define EP0_OUT_NULL BIT(14) 174#define EP0_OUT_FULL BIT(13) 175#define EP0_OUT_EMPTY BIT(12) 176#define EP0_IN_NAK_INT BIT(11) 177#define EP0_IN_DATA BIT(10) 178#define EP0_IN_FULL BIT(9) 179#define EP0_IN_EMPTY BIT(8) 180#define EP0_OUT_NULL_INT BIT(7) 181#define EP0_OUT_OR_INT BIT(6) 182#define EP0_OUT_INT BIT(5) 183#define EP0_IN_INT BIT(4) 184#define EP0_STALL_INT BIT(3) 185#define STG_END_INT BIT(2) 186#define STG_START_INT BIT(1) 187#define SETUP_INT BIT(0) 188 189#define EP0_STATUS_RW_BIT (BIT(16) | BIT(15) | BIT(11) | 0xFF) 190 191/*------- (0x0030) EP0 Interrupt Enable Register */ 192#define EP0_PERR_NAK_EN BIT(16) 193#define EP0_OUT_NAK_EN BIT(15) 194 195#define EP0_IN_NAK_EN BIT(11) 196 197#define EP0_OUT_NULL_EN BIT(7) 198#define EP0_OUT_OR_EN BIT(6) 199#define EP0_OUT_EN BIT(5) 200#define EP0_IN_EN BIT(4) 201#define EP0_STALL_EN BIT(3) 202#define STG_END_EN BIT(2) 203#define STG_START_EN BIT(1) 204#define SETUP_EN BIT(0) 205 206#define EP0_INT_EN_BIT \ 207 (EP0_OUT_OR_EN | EP0_OUT_EN | EP0_IN_EN | STG_END_EN | SETUP_EN) 208 209/*------- (0x0034) EP0 Length Register */ 210#define EP0_LDATA 0x0000007F 211 212/*------- (0x0038) EP0 Read Register */ 213/*------- (0x003C) EP0 Write Register */ 214 215/*------- (0x0040:) EPN Control Register */ 216#define EPN_EN BIT(31) 217#define EPN_BUF_TYPE BIT(30) 218#define EPN_BUF_SINGLE BIT(30) 219 220#define EPN_DIR0 BIT(26) 221#define EPN_MODE (BIT(25) | BIT(24)) 222#define EPN_BULK 0 223#define EPN_INTERRUPT BIT(24) 224#define EPN_ISO BIT(25) 225 226#define EPN_OVERSEL BIT(17) 227#define EPN_AUTO BIT(16) 228 229#define EPN_IPIDCLR BIT(11) 230#define EPN_OPIDCLR BIT(10) 231#define EPN_BCLR BIT(9) 232#define EPN_CBCLR BIT(8) 233#define EPN_DEND BIT(7) 234#define EPN_DW (BIT(6) | BIT(5)) 235#define EPN_DW4 0 236#define EPN_DW3 (BIT(6) | BIT(5)) 237#define EPN_DW2 BIT(6) 238#define EPN_DW1 BIT(5) 239 240#define EPN_OSTL_EN BIT(4) 241#define EPN_ISTL BIT(3) 242#define EPN_OSTL BIT(2) 243 244#define EPN_ONAK BIT(0) 245 246/*------- (0x0044:) EPN Status Register */ 247#define EPN_ISO_PIDERR BIT(29) /* R */ 248#define EPN_OPID BIT(28) /* R */ 249#define EPN_OUT_NOTKN BIT(27) /* R */ 250#define EPN_ISO_OR BIT(26) /* R */ 251 252#define EPN_ISO_CRC BIT(24) /* R */ 253#define EPN_OUT_END_INT BIT(23) /* RW */ 254#define EPN_OUT_OR_INT BIT(22) /* RW */ 255#define EPN_OUT_NAK_ERR_INT BIT(21) /* RW */ 256#define EPN_OUT_STALL_INT BIT(20) /* RW */ 257#define EPN_OUT_INT BIT(19) /* RW */ 258#define EPN_OUT_NULL_INT BIT(18) /* RW */ 259#define EPN_OUT_FULL BIT(17) /* R */ 260#define EPN_OUT_EMPTY BIT(16) /* R */ 261 262#define EPN_IPID BIT(10) /* R */ 263#define EPN_IN_NOTKN BIT(9) /* R */ 264#define EPN_ISO_UR BIT(8) /* R */ 265#define EPN_IN_END_INT BIT(7) /* RW */ 266 267#define EPN_IN_NAK_ERR_INT BIT(5) /* RW */ 268#define EPN_IN_STALL_INT BIT(4) /* RW */ 269#define EPN_IN_INT BIT(3) /* RW */ 270#define EPN_IN_DATA BIT(2) /* R */ 271#define EPN_IN_FULL BIT(1) /* R */ 272#define EPN_IN_EMPTY BIT(0) /* R */ 273 274#define EPN_INT_EN \ 275 (EPN_OUT_END_INT | EPN_OUT_INT | EPN_IN_END_INT | EPN_IN_INT) 276 277/*------- (0x0048:) EPN Interrupt Enable Register */ 278#define EPN_OUT_END_EN BIT(23) /* RW */ 279#define EPN_OUT_OR_EN BIT(22) /* RW */ 280#define EPN_OUT_NAK_ERR_EN BIT(21) /* RW */ 281#define EPN_OUT_STALL_EN BIT(20) /* RW */ 282#define EPN_OUT_EN BIT(19) /* RW */ 283#define EPN_OUT_NULL_EN BIT(18) /* RW */ 284 285#define EPN_IN_END_EN BIT(7) /* RW */ 286 287#define EPN_IN_NAK_ERR_EN BIT(5) /* RW */ 288#define EPN_IN_STALL_EN BIT(4) /* RW */ 289#define EPN_IN_EN BIT(3) /* RW */ 290 291/*------- (0x004C:) EPN Interrupt Enable Register */ 292#define EPN_STOP_MODE BIT(11) 293#define EPN_DEND_SET BIT(10) 294#define EPN_BURST_SET BIT(9) 295#define EPN_STOP_SET BIT(8) 296 297#define EPN_DMA_EN BIT(4) 298 299#define EPN_DMAMODE0 BIT(0) 300 301/*------- (0x0050:) EPN MaxPacket & BaseAddress Register */ 302#define EPN_BASEAD 0x1FFF0000 303#define EPN_MPKT 0x000007FF 304 305/*------- (0x0054:) EPN Length & DMA Count Register */ 306#define EPN_DMACNT 0x01FF0000 307#define EPN_LDATA 0x000007FF 308 309/*------- (0x0058:) EPN Read Register */ 310/*------- (0x005C:) EPN Write Register */ 311 312/*------- (0x1000) AHBSCTR Register */ 313#define WAIT_MODE BIT(0) 314 315/*------- (0x1004) AHBMCTR Register */ 316#define ARBITER_CTR BIT(31) /* RW */ 317#define MCYCLE_RST BIT(12) /* RW */ 318 319#define ENDIAN_CTR (BIT(9) | BIT(8)) /* RW */ 320#define ENDIAN_BYTE_SWAP BIT(9) 321#define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR 322 323#define HBUSREQ_MODE BIT(5) /* RW */ 324#define HTRANS_MODE BIT(4) /* RW */ 325 326#define WBURST_TYPE BIT(2) /* RW */ 327#define BURST_TYPE (BIT(1) | BIT(0)) /* RW */ 328#define BURST_MAX_16 0 329#define BURST_MAX_8 BIT(0) 330#define BURST_MAX_4 BIT(1) 331#define BURST_SINGLE BURST_TYPE 332 333/*------- (0x1008) AHBBINT Register */ 334#define DMA_ENDINT 0xFFFE0000 /* RW */ 335 336#define AHB_VBUS_INT BIT(13) /* RW */ 337 338#define MBUS_ERRINT BIT(6) /* RW */ 339 340#define SBUS_ERRINT0 BIT(4) /* RW */ 341#define ERR_MASTER 0x0000000F /* R */ 342 343/*------- (0x100C) AHBBINTEN Register */ 344#define DMA_ENDINTEN 0xFFFE0000 /* RW */ 345 346#define VBUS_INTEN BIT(13) /* RW */ 347 348#define MBUS_ERRINTEN BIT(6) /* RW */ 349 350#define SBUS_ERRINT0EN BIT(4) /* RW */ 351 352/*------- (0x1010) EPCTR Register */ 353#define DIRPD BIT(12) /* RW */ 354 355#define VBUS_LEVEL BIT(8) /* R */ 356 357#define PLL_RESUME BIT(5) /* RW */ 358#define PLL_LOCK BIT(4) /* R */ 359 360#define EPC_RST BIT(0) /* RW */ 361 362/*------- (0x1014) USBF_EPTEST Register */ 363#define LINESTATE (BIT(9) | BIT(8)) /* R */ 364#define DM_LEVEL BIT(9) /* R */ 365#define DP_LEVEL BIT(8) /* R */ 366 367#define PHY_TST BIT(1) /* RW */ 368#define PHY_TSTCLK BIT(0) /* RW */ 369 370/*------- (0x1020) USBSSVER Register */ 371#define AHBB_VER 0x00FF0000 /* R */ 372#define EPC_VER 0x0000FF00 /* R */ 373#define SS_VER 0x000000FF /* R */ 374 375/*------- (0x1024) USBSSCONF Register */ 376#define EP_AVAILABLE 0xFFFF0000 /* R */ 377#define DMA_AVAILABLE 0x0000FFFF /* R */ 378 379/*------- (0x1110:) EPNDCR1 Register */ 380#define DCR1_EPN_DMACNT 0x00FF0000 /* RW */ 381 382#define DCR1_EPN_DIR0 BIT(1) /* RW */ 383#define DCR1_EPN_REQEN BIT(0) /* RW */ 384 385/*------- (0x1114:) EPNDCR2 Register */ 386#define DCR2_EPN_LMPKT 0x07FF0000 /* RW */ 387 388#define DCR2_EPN_MPKT 0x000007FF /* RW */ 389 390/*------- (0x1118:) EPNTADR Register */ 391#define EPN_TADR 0xFFFFFFFF /* RW */ 392 393/*===========================================================================*/ 394/* Struct */ 395/*------- ep_regs */ 396struct ep_regs { 397 u32 EP_CONTROL; /* EP Control */ 398 u32 EP_STATUS; /* EP Status */ 399 u32 EP_INT_ENA; /* EP Interrupt Enable */ 400 u32 EP_DMA_CTRL; /* EP DMA Control */ 401 u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */ 402 u32 EP_LEN_DCNT; /* EP Length & DMA count */ 403 u32 EP_READ; /* EP Read */ 404 u32 EP_WRITE; /* EP Write */ 405}; 406 407/*------- ep_dcr */ 408struct ep_dcr { 409 u32 EP_DCR1; /* EP_DCR1 */ 410 u32 EP_DCR2; /* EP_DCR2 */ 411 u32 EP_TADR; /* EP_TADR */ 412 u32 Reserved; /* Reserved */ 413}; 414 415/*------- Function Registers */ 416struct fc_regs { 417 u32 USB_CONTROL; /* (0x0000) USB Control */ 418 u32 USB_STATUS; /* (0x0004) USB Status */ 419 u32 USB_ADDRESS; /* (0x0008) USB Address */ 420 u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */ 421 u32 TEST_CONTROL; /* (0x0010) TEST Control */ 422 u32 reserved_14; /* (0x0014) Reserved */ 423 u32 SETUP_DATA0; /* (0x0018) Setup Data0 */ 424 u32 SETUP_DATA1; /* (0x001C) Setup Data1 */ 425 u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */ 426 u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */ 427 u32 EP0_CONTROL; /* (0x0028) EP0 Control */ 428 u32 EP0_STATUS; /* (0x002C) EP0 Status */ 429 u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */ 430 u32 EP0_LENGTH; /* (0x0034) EP0 Length */ 431 u32 EP0_READ; /* (0x0038) EP0 Read */ 432 u32 EP0_WRITE; /* (0x003C) EP0 Write */ 433 434 struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */ 435 436 u8 reserved_220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */ 437 438 u32 AHBSCTR; /* (0x1000) AHBSCTR */ 439 u32 AHBMCTR; /* (0x1004) AHBMCTR */ 440 u32 AHBBINT; /* (0x1008) AHBBINT */ 441 u32 AHBBINTEN; /* (0x100C) AHBBINTEN */ 442 u32 EPCTR; /* (0x1010) EPCTR */ 443 u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */ 444 445 u8 reserved_1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */ 446 447 u32 USBSSVER; /* (0x1020) USBSSVER */ 448 u32 USBSSCONF; /* (0x1024) USBSSCONF */ 449 450 u8 reserved_1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */ 451 452 struct ep_dcr EP_DCR[REG_EP_NUM]; /* */ 453 454 u8 reserved_1200[0x1000 - 0x200]; /* Reserved */ 455} __aligned(32); 456 457#define EP0_PACKETSIZE 64 458#define EP_PACKETSIZE 1024 459 460/* EPN RAM SIZE */ 461#define D_RAM_SIZE_CTRL 64 462 463/* EPN Bulk Endpoint Max Packet Size */ 464#define D_FS_RAM_SIZE_BULK 64 465#define D_HS_RAM_SIZE_BULK 512 466 467struct nbu2ss_udc; 468 469enum ep0_state { 470 EP0_IDLE, 471 EP0_IN_DATA_PHASE, 472 EP0_OUT_DATA_PHASE, 473 EP0_IN_STATUS_PHASE, 474 EP0_OUT_STATUS_PAHSE, 475 EP0_END_XFER, 476 EP0_SUSPEND, 477 EP0_STALL, 478}; 479 480struct nbu2ss_req { 481 struct usb_request req; 482 struct list_head queue; 483 484 u32 div_len; 485 bool dma_flag; 486 bool zero; 487 488 bool unaligned; 489 490 unsigned mapped:1; 491}; 492 493struct nbu2ss_ep { 494 struct usb_ep ep; 495 struct list_head queue; 496 497 struct nbu2ss_udc *udc; 498 499 const struct usb_endpoint_descriptor *desc; 500 501 u8 epnum; 502 u8 direct; 503 u8 ep_type; 504 505 unsigned wedged:1; 506 unsigned halted:1; 507 unsigned stalled:1; 508 509 u8 *virt_buf; 510 dma_addr_t phys_buf; 511}; 512 513struct nbu2ss_udc { 514 struct usb_gadget gadget; 515 struct usb_gadget_driver *driver; 516 struct platform_device *pdev; 517 struct device *dev; 518 spinlock_t lock; /* Protects nbu2ss_udc structure fields */ 519 struct completion *pdone; 520 521 enum ep0_state ep0state; 522 enum usb_device_state devstate; 523 struct usb_ctrlrequest ctrl; 524 struct nbu2ss_req ep0_req; 525 u8 ep0_buf[EP0_PACKETSIZE]; 526 527 struct nbu2ss_ep ep[NUM_ENDPOINTS]; 528 529 unsigned softconnect:1; 530 unsigned vbus_active:1; 531 unsigned linux_suspended:1; 532 unsigned linux_resume:1; 533 unsigned usb_suspended:1; 534 unsigned remote_wakeup:1; 535 unsigned udc_enabled:1; 536 537 unsigned int mA; 538 539 u32 curr_config; /* Current Configuration Number */ 540 541 struct fc_regs __iomem *p_regs; 542}; 543 544/* USB register access structure */ 545union usb_reg_access { 546 struct { 547 unsigned char DATA[4]; 548 } byte; 549 unsigned int dw; 550}; 551 552/*-------------------------------------------------------------------------*/ 553 554#endif /* _LINUX_EMXX_H */ 555