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7
8#include <linux/delay.h>
9#include <linux/device.h>
10#include <linux/i2c.h>
11#include <linux/interrupt.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/stat.h>
16#include <linux/sysfs.h>
17
18#include <linux/iio/iio.h>
19#include <linux/iio/sysfs.h>
20
21
22
23
24
25#define AD7746_REG_STATUS 0
26#define AD7746_REG_CAP_DATA_HIGH 1
27#define AD7746_REG_VT_DATA_HIGH 4
28#define AD7746_REG_CAP_SETUP 7
29#define AD7746_REG_VT_SETUP 8
30#define AD7746_REG_EXC_SETUP 9
31#define AD7746_REG_CFG 10
32#define AD7746_REG_CAPDACA 11
33#define AD7746_REG_CAPDACB 12
34#define AD7746_REG_CAP_OFFH 13
35#define AD7746_REG_CAP_GAINH 15
36#define AD7746_REG_VOLT_GAINH 17
37
38
39#define AD7746_STATUS_EXCERR BIT(3)
40#define AD7746_STATUS_RDY BIT(2)
41#define AD7746_STATUS_RDYVT BIT(1)
42#define AD7746_STATUS_RDYCAP BIT(0)
43
44
45#define AD7746_CAPSETUP_CAPEN BIT(7)
46#define AD7746_CAPSETUP_CIN2 BIT(6)
47#define AD7746_CAPSETUP_CAPDIFF BIT(5)
48#define AD7746_CAPSETUP_CACHOP BIT(0)
49
50
51#define AD7746_VTSETUP_VTEN (1 << 7)
52#define AD7746_VTSETUP_VTMD_INT_TEMP (0 << 5)
53#define AD7746_VTSETUP_VTMD_EXT_TEMP (1 << 5)
54#define AD7746_VTSETUP_VTMD_VDD_MON (2 << 5)
55#define AD7746_VTSETUP_VTMD_EXT_VIN (3 << 5)
56#define AD7746_VTSETUP_EXTREF BIT(4)
57#define AD7746_VTSETUP_VTSHORT BIT(1)
58#define AD7746_VTSETUP_VTCHOP BIT(0)
59
60
61#define AD7746_EXCSETUP_CLKCTRL BIT(7)
62#define AD7746_EXCSETUP_EXCON BIT(6)
63#define AD7746_EXCSETUP_EXCB BIT(5)
64#define AD7746_EXCSETUP_NEXCB BIT(4)
65#define AD7746_EXCSETUP_EXCA BIT(3)
66#define AD7746_EXCSETUP_NEXCA BIT(2)
67#define AD7746_EXCSETUP_EXCLVL(x) (((x) & 0x3) << 0)
68
69
70#define AD7746_CONF_VTFS_SHIFT 6
71#define AD7746_CONF_CAPFS_SHIFT 3
72#define AD7746_CONF_VTFS_MASK GENMASK(7, 6)
73#define AD7746_CONF_CAPFS_MASK GENMASK(5, 3)
74#define AD7746_CONF_MODE_IDLE (0 << 0)
75#define AD7746_CONF_MODE_CONT_CONV (1 << 0)
76#define AD7746_CONF_MODE_SINGLE_CONV (2 << 0)
77#define AD7746_CONF_MODE_PWRDN (3 << 0)
78#define AD7746_CONF_MODE_OFFS_CAL (5 << 0)
79#define AD7746_CONF_MODE_GAIN_CAL (6 << 0)
80
81
82#define AD7746_CAPDAC_DACEN BIT(7)
83#define AD7746_CAPDAC_DACP(x) ((x) & 0x7F)
84
85struct ad7746_chip_info {
86 struct i2c_client *client;
87 struct mutex lock;
88
89
90
91
92 u8 config;
93 u8 cap_setup;
94 u8 vt_setup;
95 u8 capdac[2][2];
96 s8 capdac_set;
97
98 union {
99 __be32 d32;
100 u8 d8[4];
101 } data ____cacheline_aligned;
102};
103
104enum ad7746_chan {
105 VIN,
106 VIN_VDD,
107 TEMP_INT,
108 TEMP_EXT,
109 CIN1,
110 CIN1_DIFF,
111 CIN2,
112 CIN2_DIFF,
113};
114
115static const struct iio_chan_spec ad7746_channels[] = {
116 [VIN] = {
117 .type = IIO_VOLTAGE,
118 .indexed = 1,
119 .channel = 0,
120 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
121 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
122 BIT(IIO_CHAN_INFO_SAMP_FREQ),
123 .address = AD7746_REG_VT_DATA_HIGH << 8 |
124 AD7746_VTSETUP_VTMD_EXT_VIN,
125 },
126 [VIN_VDD] = {
127 .type = IIO_VOLTAGE,
128 .indexed = 1,
129 .channel = 1,
130 .extend_name = "supply",
131 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
132 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
133 BIT(IIO_CHAN_INFO_SAMP_FREQ),
134 .address = AD7746_REG_VT_DATA_HIGH << 8 |
135 AD7746_VTSETUP_VTMD_VDD_MON,
136 },
137 [TEMP_INT] = {
138 .type = IIO_TEMP,
139 .indexed = 1,
140 .channel = 0,
141 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
142 .address = AD7746_REG_VT_DATA_HIGH << 8 |
143 AD7746_VTSETUP_VTMD_INT_TEMP,
144 },
145 [TEMP_EXT] = {
146 .type = IIO_TEMP,
147 .indexed = 1,
148 .channel = 1,
149 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
150 .address = AD7746_REG_VT_DATA_HIGH << 8 |
151 AD7746_VTSETUP_VTMD_EXT_TEMP,
152 },
153 [CIN1] = {
154 .type = IIO_CAPACITANCE,
155 .indexed = 1,
156 .channel = 0,
157 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
158 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
159 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
160 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
161 .address = AD7746_REG_CAP_DATA_HIGH << 8,
162 },
163 [CIN1_DIFF] = {
164 .type = IIO_CAPACITANCE,
165 .differential = 1,
166 .indexed = 1,
167 .channel = 0,
168 .channel2 = 2,
169 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
170 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
171 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
172 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
173 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
174 AD7746_CAPSETUP_CAPDIFF
175 },
176 [CIN2] = {
177 .type = IIO_CAPACITANCE,
178 .indexed = 1,
179 .channel = 1,
180 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
181 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
182 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
183 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
184 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
185 AD7746_CAPSETUP_CIN2,
186 },
187 [CIN2_DIFF] = {
188 .type = IIO_CAPACITANCE,
189 .differential = 1,
190 .indexed = 1,
191 .channel = 1,
192 .channel2 = 3,
193 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
194 BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET),
195 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBBIAS) |
196 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
197 .address = AD7746_REG_CAP_DATA_HIGH << 8 |
198 AD7746_CAPSETUP_CAPDIFF | AD7746_CAPSETUP_CIN2,
199 }
200};
201
202
203static const unsigned char ad7746_vt_filter_rate_table[][2] = {
204 {50, 20 + 1}, {31, 32 + 1}, {16, 62 + 1}, {8, 122 + 1},
205};
206
207static const unsigned char ad7746_cap_filter_rate_table[][2] = {
208 {91, 11 + 1}, {84, 12 + 1}, {50, 20 + 1}, {26, 38 + 1},
209 {16, 62 + 1}, {13, 77 + 1}, {11, 92 + 1}, {9, 110 + 1},
210};
211
212static int ad7746_set_capdac(struct ad7746_chip_info *chip, int channel)
213{
214 int ret = i2c_smbus_write_byte_data(chip->client,
215 AD7746_REG_CAPDACA,
216 chip->capdac[channel][0]);
217 if (ret < 0)
218 return ret;
219
220 return i2c_smbus_write_byte_data(chip->client,
221 AD7746_REG_CAPDACB,
222 chip->capdac[channel][1]);
223}
224
225static int ad7746_select_channel(struct iio_dev *indio_dev,
226 struct iio_chan_spec const *chan)
227{
228 struct ad7746_chip_info *chip = iio_priv(indio_dev);
229 u8 vt_setup, cap_setup;
230 int ret, delay, idx;
231
232 switch (chan->type) {
233 case IIO_CAPACITANCE:
234 cap_setup = (chan->address & 0xFF) | AD7746_CAPSETUP_CAPEN;
235 vt_setup = chip->vt_setup & ~AD7746_VTSETUP_VTEN;
236 idx = (chip->config & AD7746_CONF_CAPFS_MASK) >>
237 AD7746_CONF_CAPFS_SHIFT;
238 delay = ad7746_cap_filter_rate_table[idx][1];
239
240 ret = ad7746_set_capdac(chip, chan->channel);
241 if (ret < 0)
242 return ret;
243
244 if (chip->capdac_set != chan->channel) {
245
246 chip->capdac_set = chan->channel;
247 }
248 break;
249 case IIO_VOLTAGE:
250 case IIO_TEMP:
251 vt_setup = (chan->address & 0xFF) | AD7746_VTSETUP_VTEN;
252 cap_setup = chip->cap_setup & ~AD7746_CAPSETUP_CAPEN;
253 idx = (chip->config & AD7746_CONF_VTFS_MASK) >>
254 AD7746_CONF_VTFS_SHIFT;
255 delay = ad7746_cap_filter_rate_table[idx][1];
256 break;
257 default:
258 return -EINVAL;
259 }
260
261 if (chip->cap_setup != cap_setup) {
262 ret = i2c_smbus_write_byte_data(chip->client,
263 AD7746_REG_CAP_SETUP,
264 cap_setup);
265 if (ret < 0)
266 return ret;
267
268 chip->cap_setup = cap_setup;
269 }
270
271 if (chip->vt_setup != vt_setup) {
272 ret = i2c_smbus_write_byte_data(chip->client,
273 AD7746_REG_VT_SETUP,
274 vt_setup);
275 if (ret < 0)
276 return ret;
277
278 chip->vt_setup = vt_setup;
279 }
280
281 return delay;
282}
283
284static inline ssize_t ad7746_start_calib(struct device *dev,
285 struct device_attribute *attr,
286 const char *buf,
287 size_t len,
288 u8 regval)
289{
290 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
291 struct ad7746_chip_info *chip = iio_priv(indio_dev);
292 int ret, timeout = 10;
293 bool doit;
294
295 ret = strtobool(buf, &doit);
296 if (ret < 0)
297 return ret;
298
299 if (!doit)
300 return 0;
301
302 mutex_lock(&chip->lock);
303 regval |= chip->config;
304 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG, regval);
305 if (ret < 0)
306 goto unlock;
307
308 do {
309 msleep(20);
310 ret = i2c_smbus_read_byte_data(chip->client, AD7746_REG_CFG);
311 if (ret < 0)
312 goto unlock;
313
314 } while ((ret == regval) && timeout--);
315
316 mutex_unlock(&chip->lock);
317
318 return len;
319
320unlock:
321 mutex_unlock(&chip->lock);
322 return ret;
323}
324
325static ssize_t ad7746_start_offset_calib(struct device *dev,
326 struct device_attribute *attr,
327 const char *buf,
328 size_t len)
329{
330 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
331 int ret = ad7746_select_channel(indio_dev,
332 &ad7746_channels[to_iio_dev_attr(attr)->address]);
333 if (ret < 0)
334 return ret;
335
336 return ad7746_start_calib(dev, attr, buf, len,
337 AD7746_CONF_MODE_OFFS_CAL);
338}
339
340static ssize_t ad7746_start_gain_calib(struct device *dev,
341 struct device_attribute *attr,
342 const char *buf,
343 size_t len)
344{
345 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
346 int ret = ad7746_select_channel(indio_dev,
347 &ad7746_channels[to_iio_dev_attr(attr)->address]);
348 if (ret < 0)
349 return ret;
350
351 return ad7746_start_calib(dev, attr, buf, len,
352 AD7746_CONF_MODE_GAIN_CAL);
353}
354
355static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration,
356 0200, NULL, ad7746_start_offset_calib, CIN1);
357static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration,
358 0200, NULL, ad7746_start_offset_calib, CIN2);
359static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration,
360 0200, NULL, ad7746_start_gain_calib, CIN1);
361static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration,
362 0200, NULL, ad7746_start_gain_calib, CIN2);
363static IIO_DEVICE_ATTR(in_voltage0_calibscale_calibration,
364 0200, NULL, ad7746_start_gain_calib, VIN);
365
366static int ad7746_store_cap_filter_rate_setup(struct ad7746_chip_info *chip,
367 int val)
368{
369 int i;
370
371 for (i = 0; i < ARRAY_SIZE(ad7746_cap_filter_rate_table); i++)
372 if (val >= ad7746_cap_filter_rate_table[i][0])
373 break;
374
375 if (i >= ARRAY_SIZE(ad7746_cap_filter_rate_table))
376 i = ARRAY_SIZE(ad7746_cap_filter_rate_table) - 1;
377
378 chip->config &= ~AD7746_CONF_CAPFS_MASK;
379 chip->config |= i << AD7746_CONF_CAPFS_SHIFT;
380
381 return 0;
382}
383
384static int ad7746_store_vt_filter_rate_setup(struct ad7746_chip_info *chip,
385 int val)
386{
387 int i;
388
389 for (i = 0; i < ARRAY_SIZE(ad7746_vt_filter_rate_table); i++)
390 if (val >= ad7746_vt_filter_rate_table[i][0])
391 break;
392
393 if (i >= ARRAY_SIZE(ad7746_vt_filter_rate_table))
394 i = ARRAY_SIZE(ad7746_vt_filter_rate_table) - 1;
395
396 chip->config &= ~AD7746_CONF_VTFS_MASK;
397 chip->config |= i << AD7746_CONF_VTFS_SHIFT;
398
399 return 0;
400}
401
402static IIO_CONST_ATTR(in_voltage_sampling_frequency_available, "50 31 16 8");
403static IIO_CONST_ATTR(in_capacitance_sampling_frequency_available,
404 "91 84 50 26 16 13 11 9");
405
406static struct attribute *ad7746_attributes[] = {
407 &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr,
408 &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr,
409 &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr,
410 &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr,
411 &iio_dev_attr_in_voltage0_calibscale_calibration.dev_attr.attr,
412 &iio_const_attr_in_voltage_sampling_frequency_available.dev_attr.attr,
413 &iio_const_attr_in_capacitance_sampling_frequency_available.dev_attr.attr,
414 NULL,
415};
416
417static const struct attribute_group ad7746_attribute_group = {
418 .attrs = ad7746_attributes,
419};
420
421static int ad7746_write_raw(struct iio_dev *indio_dev,
422 struct iio_chan_spec const *chan,
423 int val,
424 int val2,
425 long mask)
426{
427 struct ad7746_chip_info *chip = iio_priv(indio_dev);
428 int ret, reg;
429
430 mutex_lock(&chip->lock);
431
432 switch (mask) {
433 case IIO_CHAN_INFO_CALIBSCALE:
434 if (val != 1) {
435 ret = -EINVAL;
436 goto out;
437 }
438
439 val = (val2 * 1024) / 15625;
440
441 switch (chan->type) {
442 case IIO_CAPACITANCE:
443 reg = AD7746_REG_CAP_GAINH;
444 break;
445 case IIO_VOLTAGE:
446 reg = AD7746_REG_VOLT_GAINH;
447 break;
448 default:
449 ret = -EINVAL;
450 goto out;
451 }
452
453 ret = i2c_smbus_write_word_swapped(chip->client, reg, val);
454 if (ret < 0)
455 goto out;
456
457 ret = 0;
458 break;
459 case IIO_CHAN_INFO_CALIBBIAS:
460 if (val < 0 || val > 0xFFFF) {
461 ret = -EINVAL;
462 goto out;
463 }
464 ret = i2c_smbus_write_word_swapped(chip->client,
465 AD7746_REG_CAP_OFFH, val);
466 if (ret < 0)
467 goto out;
468
469 ret = 0;
470 break;
471 case IIO_CHAN_INFO_OFFSET:
472 if (val < 0 || val > 43008000) {
473 ret = -EINVAL;
474 goto out;
475 }
476
477
478
479
480
481
482
483 val /= 338646;
484
485 chip->capdac[chan->channel][chan->differential] = val > 0 ?
486 AD7746_CAPDAC_DACP(val) | AD7746_CAPDAC_DACEN : 0;
487
488 ret = ad7746_set_capdac(chip, chan->channel);
489 if (ret < 0)
490 goto out;
491
492 chip->capdac_set = chan->channel;
493
494 ret = 0;
495 break;
496 case IIO_CHAN_INFO_SAMP_FREQ:
497 if (val2) {
498 ret = -EINVAL;
499 goto out;
500 }
501
502 switch (chan->type) {
503 case IIO_CAPACITANCE:
504 ret = ad7746_store_cap_filter_rate_setup(chip, val);
505 break;
506 case IIO_VOLTAGE:
507 ret = ad7746_store_vt_filter_rate_setup(chip, val);
508 break;
509 default:
510 ret = -EINVAL;
511 }
512 break;
513 default:
514 ret = -EINVAL;
515 }
516
517out:
518 mutex_unlock(&chip->lock);
519 return ret;
520}
521
522static int ad7746_read_raw(struct iio_dev *indio_dev,
523 struct iio_chan_spec const *chan,
524 int *val, int *val2,
525 long mask)
526{
527 struct ad7746_chip_info *chip = iio_priv(indio_dev);
528 int ret, delay, idx;
529 u8 regval, reg;
530
531 mutex_lock(&chip->lock);
532
533 switch (mask) {
534 case IIO_CHAN_INFO_RAW:
535 case IIO_CHAN_INFO_PROCESSED:
536 ret = ad7746_select_channel(indio_dev, chan);
537 if (ret < 0)
538 goto out;
539 delay = ret;
540
541 regval = chip->config | AD7746_CONF_MODE_SINGLE_CONV;
542 ret = i2c_smbus_write_byte_data(chip->client, AD7746_REG_CFG,
543 regval);
544 if (ret < 0)
545 goto out;
546
547 msleep(delay);
548
549
550 ret = i2c_smbus_read_i2c_block_data(chip->client,
551 chan->address >> 8, 3,
552 &chip->data.d8[1]);
553
554 if (ret < 0)
555 goto out;
556
557 *val = (be32_to_cpu(chip->data.d32) & 0xFFFFFF) - 0x800000;
558
559 switch (chan->type) {
560 case IIO_TEMP:
561
562
563
564
565 *val = (*val * 125) / 256;
566 break;
567 case IIO_VOLTAGE:
568 if (chan->channel == 1)
569 *val = *val * 6;
570 break;
571 default:
572 break;
573 }
574
575 ret = IIO_VAL_INT;
576 break;
577 case IIO_CHAN_INFO_CALIBSCALE:
578 switch (chan->type) {
579 case IIO_CAPACITANCE:
580 reg = AD7746_REG_CAP_GAINH;
581 break;
582 case IIO_VOLTAGE:
583 reg = AD7746_REG_VOLT_GAINH;
584 break;
585 default:
586 ret = -EINVAL;
587 goto out;
588 }
589
590 ret = i2c_smbus_read_word_swapped(chip->client, reg);
591 if (ret < 0)
592 goto out;
593
594 *val = 1;
595 *val2 = (15625 * ret) / 1024;
596
597 ret = IIO_VAL_INT_PLUS_MICRO;
598 break;
599 case IIO_CHAN_INFO_CALIBBIAS:
600 ret = i2c_smbus_read_word_swapped(chip->client,
601 AD7746_REG_CAP_OFFH);
602 if (ret < 0)
603 goto out;
604 *val = ret;
605
606 ret = IIO_VAL_INT;
607 break;
608 case IIO_CHAN_INFO_OFFSET:
609 *val = AD7746_CAPDAC_DACP(chip->capdac[chan->channel]
610 [chan->differential]) * 338646;
611
612 ret = IIO_VAL_INT;
613 break;
614 case IIO_CHAN_INFO_SCALE:
615 switch (chan->type) {
616 case IIO_CAPACITANCE:
617
618 *val = 0;
619 *val2 = 488;
620 ret = IIO_VAL_INT_PLUS_NANO;
621 break;
622 case IIO_VOLTAGE:
623
624 *val = 1170;
625 *val2 = 23;
626 ret = IIO_VAL_FRACTIONAL_LOG2;
627 break;
628 default:
629 ret = -EINVAL;
630 break;
631 }
632
633 break;
634 case IIO_CHAN_INFO_SAMP_FREQ:
635 switch (chan->type) {
636 case IIO_CAPACITANCE:
637 idx = (chip->config & AD7746_CONF_CAPFS_MASK) >>
638 AD7746_CONF_CAPFS_SHIFT;
639 *val = ad7746_cap_filter_rate_table[idx][0];
640 ret = IIO_VAL_INT;
641 break;
642 case IIO_VOLTAGE:
643 idx = (chip->config & AD7746_CONF_VTFS_MASK) >>
644 AD7746_CONF_VTFS_SHIFT;
645 *val = ad7746_vt_filter_rate_table[idx][0];
646 ret = IIO_VAL_INT;
647 break;
648 default:
649 ret = -EINVAL;
650 }
651 break;
652 default:
653 ret = -EINVAL;
654 }
655out:
656 mutex_unlock(&chip->lock);
657 return ret;
658}
659
660static const struct iio_info ad7746_info = {
661 .attrs = &ad7746_attribute_group,
662 .read_raw = ad7746_read_raw,
663 .write_raw = ad7746_write_raw,
664};
665
666static int ad7746_probe(struct i2c_client *client,
667 const struct i2c_device_id *id)
668{
669 struct device *dev = &client->dev;
670 struct ad7746_chip_info *chip;
671 struct iio_dev *indio_dev;
672 unsigned char regval = 0;
673 unsigned int vdd_permille;
674 int ret;
675
676 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
677 if (!indio_dev)
678 return -ENOMEM;
679 chip = iio_priv(indio_dev);
680 mutex_init(&chip->lock);
681
682 i2c_set_clientdata(client, indio_dev);
683
684 chip->client = client;
685 chip->capdac_set = -1;
686
687 indio_dev->name = id->name;
688 indio_dev->info = &ad7746_info;
689 indio_dev->channels = ad7746_channels;
690 if (id->driver_data == 7746)
691 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels);
692 else
693 indio_dev->num_channels = ARRAY_SIZE(ad7746_channels) - 2;
694 indio_dev->modes = INDIO_DIRECT_MODE;
695
696 if (device_property_read_bool(dev, "adi,exca-output-en")) {
697 if (device_property_read_bool(dev, "adi,exca-output-invert"))
698 regval |= AD7746_EXCSETUP_NEXCA;
699 else
700 regval |= AD7746_EXCSETUP_EXCA;
701 }
702
703 if (device_property_read_bool(dev, "adi,excb-output-en")) {
704 if (device_property_read_bool(dev, "adi,excb-output-invert"))
705 regval |= AD7746_EXCSETUP_NEXCB;
706 else
707 regval |= AD7746_EXCSETUP_EXCB;
708 }
709
710 ret = device_property_read_u32(dev, "adi,excitation-vdd-permille",
711 &vdd_permille);
712 if (!ret) {
713 switch (vdd_permille) {
714 case 125:
715 regval |= AD7746_EXCSETUP_EXCLVL(0);
716 break;
717 case 250:
718 regval |= AD7746_EXCSETUP_EXCLVL(1);
719 break;
720 case 375:
721 regval |= AD7746_EXCSETUP_EXCLVL(2);
722 break;
723 case 500:
724 regval |= AD7746_EXCSETUP_EXCLVL(3);
725 break;
726 default:
727 break;
728 }
729 }
730
731 ret = i2c_smbus_write_byte_data(chip->client,
732 AD7746_REG_EXC_SETUP, regval);
733 if (ret < 0)
734 return ret;
735
736 return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
737}
738
739static const struct i2c_device_id ad7746_id[] = {
740 { "ad7745", 7745 },
741 { "ad7746", 7746 },
742 { "ad7747", 7747 },
743 {}
744};
745
746MODULE_DEVICE_TABLE(i2c, ad7746_id);
747
748static const struct of_device_id ad7746_of_match[] = {
749 { .compatible = "adi,ad7745" },
750 { .compatible = "adi,ad7746" },
751 { .compatible = "adi,ad7747" },
752 { },
753};
754
755MODULE_DEVICE_TABLE(of, ad7746_of_match);
756
757static struct i2c_driver ad7746_driver = {
758 .driver = {
759 .name = KBUILD_MODNAME,
760 .of_match_table = ad7746_of_match,
761 },
762 .probe = ad7746_probe,
763 .id_table = ad7746_id,
764};
765module_i2c_driver(ad7746_driver);
766
767MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
768MODULE_DESCRIPTION("Analog Devices AD7746/5/7 capacitive sensor driver");
769MODULE_LICENSE("GPL v2");
770
