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20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/pm_runtime.h>
23#include <linux/pm_qos.h>
24#include <linux/timer.h>
25#include <linux/delay.h>
26#include <linux/dmi.h>
27#include <linux/interrupt.h>
28
29#include <asm/iosf_mbi.h>
30
31#include "../../include/linux/atomisp_gmin_platform.h"
32
33#include "atomisp_cmd.h"
34#include "atomisp_common.h"
35#include "atomisp_fops.h"
36#include "atomisp_file.h"
37#include "atomisp_ioctl.h"
38#include "atomisp_internal.h"
39#include "atomisp_acc.h"
40#include "atomisp-regs.h"
41#include "atomisp_dfs_tables.h"
42#include "atomisp_drvfs.h"
43#include "hmm/hmm.h"
44#include "atomisp_trace_event.h"
45
46#include "sh_css_firmware.h"
47
48#include "device_access.h"
49
50
51#define SUBDEV_WAIT_TIMEOUT 50
52#define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40
53
54
55#define CSTATE_EXIT_LATENCY_C1 1
56
57static uint skip_fwload;
58module_param(skip_fwload, uint, 0644);
59MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load");
60
61
62static unsigned int repool_pgnr = 32768;
63module_param(repool_pgnr, uint, 0644);
64MODULE_PARM_DESC(repool_pgnr,
65 "Set the reserved memory pool size in page (default:32768)");
66
67
68unsigned int dypool_pgnr = UINT_MAX;
69module_param(dypool_pgnr, uint, 0644);
70MODULE_PARM_DESC(dypool_pgnr,
71 "Set the dynamic memory pool size in page (default: unlimited)");
72
73bool dypool_enable = true;
74module_param(dypool_enable, bool, 0644);
75MODULE_PARM_DESC(dypool_enable,
76 "dynamic memory pool enable/disable (default:enabled)");
77
78
79bool defer_fw_load;
80module_param(defer_fw_load, bool, 0644);
81MODULE_PARM_DESC(defer_fw_load,
82 "Defer FW loading until device is opened (default:disable)");
83
84
85int dbg_level;
86module_param(dbg_level, int, 0644);
87MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
88
89
90int dbg_func = 2;
91module_param(dbg_func, int, 0644);
92MODULE_PARM_DESC(dbg_func,
93 "log function switch non/trace_printk/printk (default:printk)");
94
95int mipicsi_flag;
96module_param(mipicsi_flag, int, 0644);
97MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm");
98
99static char firmware_name[256];
100module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
101MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name.");
102
103
104
105
106
107
108
109
110int pad_w = 16;
111module_param(pad_w, int, 0644);
112MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
113
114int pad_h = 16;
115module_param(pad_h, int, 0644);
116MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
117
118
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125
126
127
128struct device *atomisp_dev;
129
130static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
131 {
132 .width = ISP_FREQ_RULE_ANY,
133 .height = ISP_FREQ_RULE_ANY,
134 .fps = ISP_FREQ_RULE_ANY,
135 .isp_freq = ISP_FREQ_400MHZ,
136 .run_mode = ATOMISP_RUN_MODE_VIDEO,
137 },
138 {
139 .width = ISP_FREQ_RULE_ANY,
140 .height = ISP_FREQ_RULE_ANY,
141 .fps = ISP_FREQ_RULE_ANY,
142 .isp_freq = ISP_FREQ_400MHZ,
143 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
144 },
145 {
146 .width = ISP_FREQ_RULE_ANY,
147 .height = ISP_FREQ_RULE_ANY,
148 .fps = ISP_FREQ_RULE_ANY,
149 .isp_freq = ISP_FREQ_400MHZ,
150 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
151 },
152 {
153 .width = ISP_FREQ_RULE_ANY,
154 .height = ISP_FREQ_RULE_ANY,
155 .fps = ISP_FREQ_RULE_ANY,
156 .isp_freq = ISP_FREQ_400MHZ,
157 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
158 },
159 {
160 .width = ISP_FREQ_RULE_ANY,
161 .height = ISP_FREQ_RULE_ANY,
162 .fps = ISP_FREQ_RULE_ANY,
163 .isp_freq = ISP_FREQ_457MHZ,
164 .run_mode = ATOMISP_RUN_MODE_SDV,
165 },
166};
167
168
169static const struct atomisp_dfs_config dfs_config_merr = {
170 .lowest_freq = ISP_FREQ_200MHZ,
171 .max_freq_at_vmin = ISP_FREQ_400MHZ,
172 .highest_freq = ISP_FREQ_457MHZ,
173 .dfs_table = dfs_rules_merr,
174 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
175};
176
177static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
178 {
179 .width = ISP_FREQ_RULE_ANY,
180 .height = ISP_FREQ_RULE_ANY,
181 .fps = ISP_FREQ_RULE_ANY,
182 .isp_freq = ISP_FREQ_400MHZ,
183 .run_mode = ATOMISP_RUN_MODE_VIDEO,
184 },
185 {
186 .width = ISP_FREQ_RULE_ANY,
187 .height = ISP_FREQ_RULE_ANY,
188 .fps = ISP_FREQ_RULE_ANY,
189 .isp_freq = ISP_FREQ_400MHZ,
190 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
191 },
192 {
193 .width = ISP_FREQ_RULE_ANY,
194 .height = ISP_FREQ_RULE_ANY,
195 .fps = ISP_FREQ_RULE_ANY,
196 .isp_freq = ISP_FREQ_400MHZ,
197 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
198 },
199 {
200 .width = ISP_FREQ_RULE_ANY,
201 .height = ISP_FREQ_RULE_ANY,
202 .fps = ISP_FREQ_RULE_ANY,
203 .isp_freq = ISP_FREQ_400MHZ,
204 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
205 },
206 {
207 .width = ISP_FREQ_RULE_ANY,
208 .height = ISP_FREQ_RULE_ANY,
209 .fps = ISP_FREQ_RULE_ANY,
210 .isp_freq = ISP_FREQ_400MHZ,
211 .run_mode = ATOMISP_RUN_MODE_SDV,
212 },
213};
214
215static const struct atomisp_dfs_config dfs_config_merr_1179 = {
216 .lowest_freq = ISP_FREQ_200MHZ,
217 .max_freq_at_vmin = ISP_FREQ_400MHZ,
218 .highest_freq = ISP_FREQ_400MHZ,
219 .dfs_table = dfs_rules_merr_1179,
220 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
221};
222
223static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
224 {
225 .width = 1920,
226 .height = 1080,
227 .fps = 30,
228 .isp_freq = ISP_FREQ_266MHZ,
229 .run_mode = ATOMISP_RUN_MODE_VIDEO,
230 },
231 {
232 .width = 1080,
233 .height = 1920,
234 .fps = 30,
235 .isp_freq = ISP_FREQ_266MHZ,
236 .run_mode = ATOMISP_RUN_MODE_VIDEO,
237 },
238 {
239 .width = 1920,
240 .height = 1080,
241 .fps = 45,
242 .isp_freq = ISP_FREQ_320MHZ,
243 .run_mode = ATOMISP_RUN_MODE_VIDEO,
244 },
245 {
246 .width = 1080,
247 .height = 1920,
248 .fps = 45,
249 .isp_freq = ISP_FREQ_320MHZ,
250 .run_mode = ATOMISP_RUN_MODE_VIDEO,
251 },
252 {
253 .width = ISP_FREQ_RULE_ANY,
254 .height = ISP_FREQ_RULE_ANY,
255 .fps = 60,
256 .isp_freq = ISP_FREQ_356MHZ,
257 .run_mode = ATOMISP_RUN_MODE_VIDEO,
258 },
259 {
260 .width = ISP_FREQ_RULE_ANY,
261 .height = ISP_FREQ_RULE_ANY,
262 .fps = ISP_FREQ_RULE_ANY,
263 .isp_freq = ISP_FREQ_200MHZ,
264 .run_mode = ATOMISP_RUN_MODE_VIDEO,
265 },
266 {
267 .width = ISP_FREQ_RULE_ANY,
268 .height = ISP_FREQ_RULE_ANY,
269 .fps = ISP_FREQ_RULE_ANY,
270 .isp_freq = ISP_FREQ_400MHZ,
271 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
272 },
273 {
274 .width = ISP_FREQ_RULE_ANY,
275 .height = ISP_FREQ_RULE_ANY,
276 .fps = ISP_FREQ_RULE_ANY,
277 .isp_freq = ISP_FREQ_400MHZ,
278 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
279 },
280 {
281 .width = ISP_FREQ_RULE_ANY,
282 .height = ISP_FREQ_RULE_ANY,
283 .fps = ISP_FREQ_RULE_ANY,
284 .isp_freq = ISP_FREQ_200MHZ,
285 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
286 },
287 {
288 .width = ISP_FREQ_RULE_ANY,
289 .height = ISP_FREQ_RULE_ANY,
290 .fps = ISP_FREQ_RULE_ANY,
291 .isp_freq = ISP_FREQ_400MHZ,
292 .run_mode = ATOMISP_RUN_MODE_SDV,
293 },
294};
295
296static struct atomisp_dfs_config dfs_config_merr_117a = {
297 .lowest_freq = ISP_FREQ_200MHZ,
298 .max_freq_at_vmin = ISP_FREQ_200MHZ,
299 .highest_freq = ISP_FREQ_400MHZ,
300 .dfs_table = dfs_rules_merr_117a,
301 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
302};
303
304static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
305 {
306 .width = ISP_FREQ_RULE_ANY,
307 .height = ISP_FREQ_RULE_ANY,
308 .fps = ISP_FREQ_RULE_ANY,
309 .isp_freq = ISP_FREQ_400MHZ,
310 .run_mode = ATOMISP_RUN_MODE_VIDEO,
311 },
312 {
313 .width = ISP_FREQ_RULE_ANY,
314 .height = ISP_FREQ_RULE_ANY,
315 .fps = ISP_FREQ_RULE_ANY,
316 .isp_freq = ISP_FREQ_400MHZ,
317 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
318 },
319 {
320 .width = ISP_FREQ_RULE_ANY,
321 .height = ISP_FREQ_RULE_ANY,
322 .fps = ISP_FREQ_RULE_ANY,
323 .isp_freq = ISP_FREQ_400MHZ,
324 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
325 },
326 {
327 .width = ISP_FREQ_RULE_ANY,
328 .height = ISP_FREQ_RULE_ANY,
329 .fps = ISP_FREQ_RULE_ANY,
330 .isp_freq = ISP_FREQ_400MHZ,
331 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
332 },
333 {
334 .width = ISP_FREQ_RULE_ANY,
335 .height = ISP_FREQ_RULE_ANY,
336 .fps = ISP_FREQ_RULE_ANY,
337 .isp_freq = ISP_FREQ_400MHZ,
338 .run_mode = ATOMISP_RUN_MODE_SDV,
339 },
340};
341
342static const struct atomisp_dfs_config dfs_config_byt = {
343 .lowest_freq = ISP_FREQ_200MHZ,
344 .max_freq_at_vmin = ISP_FREQ_400MHZ,
345 .highest_freq = ISP_FREQ_400MHZ,
346 .dfs_table = dfs_rules_byt,
347 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
348};
349
350static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
351 {
352 .width = ISP_FREQ_RULE_ANY,
353 .height = ISP_FREQ_RULE_ANY,
354 .fps = ISP_FREQ_RULE_ANY,
355 .isp_freq = ISP_FREQ_320MHZ,
356 .run_mode = ATOMISP_RUN_MODE_VIDEO,
357 },
358 {
359 .width = ISP_FREQ_RULE_ANY,
360 .height = ISP_FREQ_RULE_ANY,
361 .fps = ISP_FREQ_RULE_ANY,
362 .isp_freq = ISP_FREQ_356MHZ,
363 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
364 },
365 {
366 .width = ISP_FREQ_RULE_ANY,
367 .height = ISP_FREQ_RULE_ANY,
368 .fps = ISP_FREQ_RULE_ANY,
369 .isp_freq = ISP_FREQ_320MHZ,
370 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
371 },
372 {
373 .width = ISP_FREQ_RULE_ANY,
374 .height = ISP_FREQ_RULE_ANY,
375 .fps = ISP_FREQ_RULE_ANY,
376 .isp_freq = ISP_FREQ_320MHZ,
377 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
378 },
379 {
380 .width = 1280,
381 .height = 720,
382 .fps = ISP_FREQ_RULE_ANY,
383 .isp_freq = ISP_FREQ_320MHZ,
384 .run_mode = ATOMISP_RUN_MODE_SDV,
385 },
386 {
387 .width = ISP_FREQ_RULE_ANY,
388 .height = ISP_FREQ_RULE_ANY,
389 .fps = ISP_FREQ_RULE_ANY,
390 .isp_freq = ISP_FREQ_356MHZ,
391 .run_mode = ATOMISP_RUN_MODE_SDV,
392 },
393};
394
395static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
396 {
397 .width = ISP_FREQ_RULE_ANY,
398 .height = ISP_FREQ_RULE_ANY,
399 .fps = ISP_FREQ_RULE_ANY,
400 .isp_freq = ISP_FREQ_356MHZ,
401 .run_mode = ATOMISP_RUN_MODE_VIDEO,
402 },
403 {
404 .width = ISP_FREQ_RULE_ANY,
405 .height = ISP_FREQ_RULE_ANY,
406 .fps = ISP_FREQ_RULE_ANY,
407 .isp_freq = ISP_FREQ_356MHZ,
408 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
409 },
410 {
411 .width = ISP_FREQ_RULE_ANY,
412 .height = ISP_FREQ_RULE_ANY,
413 .fps = ISP_FREQ_RULE_ANY,
414 .isp_freq = ISP_FREQ_320MHZ,
415 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
416 },
417 {
418 .width = ISP_FREQ_RULE_ANY,
419 .height = ISP_FREQ_RULE_ANY,
420 .fps = ISP_FREQ_RULE_ANY,
421 .isp_freq = ISP_FREQ_320MHZ,
422 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
423 },
424 {
425 .width = ISP_FREQ_RULE_ANY,
426 .height = ISP_FREQ_RULE_ANY,
427 .fps = ISP_FREQ_RULE_ANY,
428 .isp_freq = ISP_FREQ_356MHZ,
429 .run_mode = ATOMISP_RUN_MODE_SDV,
430 },
431};
432
433static const struct atomisp_dfs_config dfs_config_cht = {
434 .lowest_freq = ISP_FREQ_100MHZ,
435 .max_freq_at_vmin = ISP_FREQ_356MHZ,
436 .highest_freq = ISP_FREQ_356MHZ,
437 .dfs_table = dfs_rules_cht,
438 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
439};
440
441
442const struct atomisp_dfs_config dfs_config_cht_soc = {
443 .lowest_freq = ISP_FREQ_100MHZ,
444 .max_freq_at_vmin = ISP_FREQ_356MHZ,
445 .highest_freq = ISP_FREQ_356MHZ,
446 .dfs_table = dfs_rules_cht_soc,
447 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
448};
449
450int atomisp_video_init(struct atomisp_video_pipe *video, const char *name)
451{
452 int ret;
453 const char *direction;
454
455 switch (video->type) {
456 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
457 direction = "output";
458 video->pad.flags = MEDIA_PAD_FL_SINK;
459 video->vdev.fops = &atomisp_fops;
460 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
461 break;
462 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
463 direction = "input";
464 video->pad.flags = MEDIA_PAD_FL_SOURCE;
465 video->vdev.fops = &atomisp_file_fops;
466 video->vdev.ioctl_ops = &atomisp_file_ioctl_ops;
467 break;
468 default:
469 return -EINVAL;
470 }
471
472 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
473 if (ret < 0)
474 return ret;
475
476
477 snprintf(video->vdev.name, sizeof(video->vdev.name),
478 "ATOMISP ISP %s %s", name, direction);
479 video->vdev.release = video_device_release_empty;
480 video_set_drvdata(&video->vdev, video->isp);
481
482 return 0;
483}
484
485void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name)
486{
487 video->vdev.fops = &atomisp_fops;
488 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
489
490
491 snprintf(video->vdev.name, sizeof(video->vdev.name),
492 "ATOMISP ISP %s", name);
493 video->vdev.release = video_device_release_empty;
494 video_set_drvdata(&video->vdev, video->isp);
495}
496
497void atomisp_video_unregister(struct atomisp_video_pipe *video)
498{
499 if (video_is_registered(&video->vdev)) {
500 media_entity_cleanup(&video->vdev.entity);
501 video_unregister_device(&video->vdev);
502 }
503}
504
505void atomisp_acc_unregister(struct atomisp_acc_pipe *video)
506{
507 if (video_is_registered(&video->vdev))
508 video_unregister_device(&video->vdev);
509}
510
511static int atomisp_save_iunit_reg(struct atomisp_device *isp)
512{
513 struct pci_dev *pdev = to_pci_dev(isp->dev);
514
515 dev_dbg(isp->dev, "%s\n", __func__);
516
517 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
518
519 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
520 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
521 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
522 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
523 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
524
525 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
526
527 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
528 isp->saved_regs.i_control |=
529 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
530 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
531 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
532 &isp->saved_regs.csi_access_viol);
533 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
534 &isp->saved_regs.csi_rcomp_config);
535
536
537
538
539
540
541
542
543 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
544 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
545 &isp->saved_regs.csi_afe_dly);
546 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
547 &isp->saved_regs.csi_control);
548 if (isp->media_dev.hw_revision >=
549 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
550 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
551
552
553
554 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
555 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
556 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
557 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
558 &isp->saved_regs.csi_afe_rcomp_config);
559 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
560 &isp->saved_regs.csi_afe_hs_control);
561 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
562 &isp->saved_regs.csi_deadline_control);
563 return 0;
564}
565
566static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp)
567{
568 struct pci_dev *pdev = to_pci_dev(isp->dev);
569
570 dev_dbg(isp->dev, "%s\n", __func__);
571
572 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
573 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
574 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
575 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
576 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
577 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
578 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
579 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
580
581 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
582 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
583 isp->saved_regs.csi_access_viol);
584 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
585 isp->saved_regs.csi_rcomp_config);
586 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
587 isp->saved_regs.csi_afe_dly);
588 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
589 isp->saved_regs.csi_control);
590 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
591 isp->saved_regs.csi_afe_rcomp_config);
592 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
593 isp->saved_regs.csi_afe_hs_control);
594 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
595 isp->saved_regs.csi_deadline_control);
596
597
598
599
600
601
602
603
604 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
605 return 0;
606}
607
608static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
609{
610 struct pci_dev *pdev = to_pci_dev(isp->dev);
611 u32 irq;
612 unsigned long flags;
613
614 spin_lock_irqsave(&isp->lock, flags);
615 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) {
616 spin_unlock_irqrestore(&isp->lock, flags);
617 dev_dbg(isp->dev, "<%s %d.\n", __func__, __LINE__);
618 return 0;
619 }
620
621
622
623
624
625
626 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
627 irq = irq & 1 << INTR_IIR;
628 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
629
630 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
631 if (!(irq & (1 << INTR_IIR)))
632 goto done;
633
634 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
635 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
636 if (irq != 0) {
637 dev_err(isp->dev,
638 "%s: fail to clear isp interrupt status reg=0x%x\n",
639 __func__, irq);
640 spin_unlock_irqrestore(&isp->lock, flags);
641 return -EAGAIN;
642 } else {
643 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
644 irq = irq & 1 << INTR_IIR;
645 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
646
647 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
648 if (!(irq & (1 << INTR_IIR))) {
649 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
650 goto done;
651 }
652 dev_err(isp->dev,
653 "%s: error in iunit interrupt. status reg=0x%x\n",
654 __func__, irq);
655 spin_unlock_irqrestore(&isp->lock, flags);
656 return -EAGAIN;
657 }
658done:
659
660
661
662
663
664
665
666 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
667 irq &= ~(1 << INTR_IER);
668 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
669
670 atomisp_msi_irq_uninit(isp);
671 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
672 spin_unlock_irqrestore(&isp->lock, flags);
673
674 return 0;
675}
676
677
678
679
680
681static void punit_ddr_dvfs_enable(bool enable)
682{
683 int door_bell = 1 << 8;
684 int max_wait = 30;
685 int reg;
686
687 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
688 if (enable) {
689 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
690 } else {
691 reg |= (MRFLD_BIT1 | door_bell);
692 reg &= ~(MRFLD_BIT0);
693 }
694 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
695
696
697 while ((reg & door_bell) && max_wait--) {
698 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
699 usleep_range(100, 500);
700 }
701
702 if (max_wait == -1)
703 pr_info("DDR DVFS, door bell is not cleared within 3ms\n");
704}
705
706static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
707{
708 unsigned long timeout;
709 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
710 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
711
712 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
713
714
715 if (IS_CHT && enable)
716 punit_ddr_dvfs_enable(true);
717
718
719
720
721
722
723 if (IS_BYT && enable)
724 msleep(10);
725
726
727 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
728 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
729
730
731 if (IS_CHT && !enable)
732 punit_ddr_dvfs_enable(true);
733
734
735
736
737
738
739
740 timeout = jiffies + msecs_to_jiffies(50);
741 do {
742 u32 tmp;
743
744
745 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
746 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
747 if (tmp == val) {
748 trace_ipu_cstate(enable);
749 return 0;
750 }
751
752 if (time_after(jiffies, timeout))
753 break;
754
755
756 usleep_range(100, 150);
757 } while (1);
758
759 if (enable)
760 msleep(10);
761
762 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
763 return -EBUSY;
764}
765
766
767int atomisp_mrfld_power_down(struct atomisp_device *isp)
768{
769 return atomisp_mrfld_power(isp, false);
770}
771
772
773int atomisp_mrfld_power_up(struct atomisp_device *isp)
774{
775 return atomisp_mrfld_power(isp, true);
776}
777
778int atomisp_runtime_suspend(struct device *dev)
779{
780 struct atomisp_device *isp = (struct atomisp_device *)
781 dev_get_drvdata(dev);
782 int ret;
783
784 ret = atomisp_mrfld_pre_power_down(isp);
785 if (ret)
786 return ret;
787
788
789 ret = atomisp_ospm_dphy_down(isp);
790 if (ret)
791 return ret;
792 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
793 return atomisp_mrfld_power_down(isp);
794}
795
796int atomisp_runtime_resume(struct device *dev)
797{
798 struct atomisp_device *isp = (struct atomisp_device *)
799 dev_get_drvdata(dev);
800 int ret;
801
802 ret = atomisp_mrfld_power_up(isp);
803 if (ret)
804 return ret;
805
806 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
807 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) {
808
809 ret = atomisp_ospm_dphy_up(isp);
810 if (ret) {
811 dev_err(isp->dev, "Failed to power up ISP!.\n");
812 return -EINVAL;
813 }
814 }
815
816
817 if (isp->saved_regs.pcicmdsts)
818 atomisp_restore_iunit_reg(isp);
819
820 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
821 return 0;
822}
823
824static int __maybe_unused atomisp_suspend(struct device *dev)
825{
826 struct atomisp_device *isp = (struct atomisp_device *)
827 dev_get_drvdata(dev);
828
829 struct atomisp_sub_device *asd = &isp->asd[0];
830 unsigned long flags;
831 int ret;
832
833
834
835
836
837 if (atomisp_dev_users(isp))
838 return -EBUSY;
839
840 spin_lock_irqsave(&isp->lock, flags);
841 if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) {
842 spin_unlock_irqrestore(&isp->lock, flags);
843 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
844 return -EINVAL;
845 }
846 spin_unlock_irqrestore(&isp->lock, flags);
847
848 ret = atomisp_mrfld_pre_power_down(isp);
849 if (ret)
850 return ret;
851
852
853 ret = atomisp_ospm_dphy_down(isp);
854 if (ret) {
855 dev_err(isp->dev, "fail to power off ISP\n");
856 return ret;
857 }
858 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
859 return atomisp_mrfld_power_down(isp);
860}
861
862static int __maybe_unused atomisp_resume(struct device *dev)
863{
864 struct atomisp_device *isp = (struct atomisp_device *)
865 dev_get_drvdata(dev);
866 int ret;
867
868 ret = atomisp_mrfld_power_up(isp);
869 if (ret)
870 return ret;
871
872 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
873
874
875 ret = atomisp_ospm_dphy_up(isp);
876 if (ret) {
877 dev_err(isp->dev, "Failed to power up ISP!.\n");
878 return -EINVAL;
879 }
880
881
882 if (isp->saved_regs.pcicmdsts)
883 atomisp_restore_iunit_reg(isp);
884
885 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
886 return 0;
887}
888
889int atomisp_csi_lane_config(struct atomisp_device *isp)
890{
891 struct pci_dev *pdev = to_pci_dev(isp->dev);
892 static const struct {
893 u8 code;
894 u8 lanes[MRFLD_PORT_NUM];
895 } portconfigs[] = {
896
897 { 0x00, { 4, 1, 0 } },
898 { 0x01, { 3, 1, 0 } },
899 { 0x02, { 2, 1, 0 } },
900 { 0x03, { 1, 1, 0 } },
901 { 0x04, { 2, 1, 2 } },
902 { 0x08, { 3, 1, 1 } },
903 { 0x09, { 2, 1, 1 } },
904 { 0x0a, { 1, 1, 1 } },
905
906
907 { 0x10, { 4, 2, 0 } },
908 { 0x11, { 3, 2, 0 } },
909 { 0x12, { 2, 2, 0 } },
910 { 0x13, { 1, 2, 0 } },
911 { 0x14, { 2, 2, 2 } },
912 { 0x18, { 3, 2, 1 } },
913 { 0x19, { 2, 2, 1 } },
914 { 0x1a, { 1, 2, 1 } },
915 };
916
917 unsigned int i, j;
918 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 };
919 u32 csi_control;
920 int nportconfigs;
921 u32 port_config_mask;
922 int port3_lanes_shift;
923
924 if (isp->media_dev.hw_revision <
925 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
926 ATOMISP_HW_REVISION_SHIFT) {
927
928 port_config_mask = MRFLD_PORT_CONFIG_MASK;
929 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
930 } else {
931
932 port_config_mask = CHV_PORT_CONFIG_MASK;
933 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
934 }
935
936 if (isp->media_dev.hw_revision <
937 ATOMISP_HW_REVISION_ISP2401 <<
938 ATOMISP_HW_REVISION_SHIFT) {
939
940 nportconfigs = MRFLD_PORT_CONFIG_NUM;
941 } else {
942
943 nportconfigs = ARRAY_SIZE(portconfigs);
944 }
945
946 for (i = 0; i < isp->input_cnt; i++) {
947 struct camera_mipi_info *mipi_info;
948
949 if (isp->inputs[i].type != RAW_CAMERA &&
950 isp->inputs[i].type != SOC_CAMERA)
951 continue;
952
953 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera);
954 if (!mipi_info)
955 continue;
956
957 switch (mipi_info->port) {
958 case ATOMISP_CAMERA_PORT_PRIMARY:
959 sensor_lanes[0] = mipi_info->num_lanes;
960 break;
961 case ATOMISP_CAMERA_PORT_SECONDARY:
962 sensor_lanes[1] = mipi_info->num_lanes;
963 break;
964 case ATOMISP_CAMERA_PORT_TERTIARY:
965 sensor_lanes[2] = mipi_info->num_lanes;
966 break;
967 default:
968 dev_err(isp->dev,
969 "%s: invalid port: %d for the %dth sensor\n",
970 __func__, mipi_info->port, i);
971 return -EINVAL;
972 }
973 }
974
975 for (i = 0; i < nportconfigs; i++) {
976 for (j = 0; j < MRFLD_PORT_NUM; j++)
977 if (sensor_lanes[j] &&
978 sensor_lanes[j] != portconfigs[i].lanes[j])
979 break;
980
981 if (j == MRFLD_PORT_NUM)
982 break;
983 }
984
985 if (i >= nportconfigs) {
986 dev_err(isp->dev,
987 "%s: could not find the CSI port setting for %d-%d-%d\n",
988 __func__,
989 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]);
990 return -EINVAL;
991 }
992
993 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
994 csi_control &= ~port_config_mask;
995 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
996 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
997 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
998 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
999 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
1000 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
1001 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
1002
1003 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
1004
1005 dev_dbg(isp->dev,
1006 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
1007 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
1008 portconfigs[i].lanes[2], csi_control);
1009
1010 return 0;
1011}
1012
1013static int atomisp_subdev_probe(struct atomisp_device *isp)
1014{
1015 const struct atomisp_platform_data *pdata;
1016 struct intel_v4l2_subdev_table *subdevs;
1017 int ret, raw_index = -1, count;
1018
1019 pdata = atomisp_get_platform_data();
1020 if (!pdata) {
1021 dev_err(isp->dev, "no platform data available\n");
1022 return 0;
1023 }
1024
1025
1026 for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) {
1027 int camera_count = 0;
1028
1029 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
1030 if (subdevs->type == RAW_CAMERA ||
1031 subdevs->type == SOC_CAMERA)
1032 camera_count++;
1033 }
1034 if (camera_count)
1035 break;
1036 msleep(SUBDEV_WAIT_TIMEOUT);
1037 }
1038
1039 msleep(5 * SUBDEV_WAIT_TIMEOUT);
1040
1041
1042
1043 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
1044 struct v4l2_subdev *subdev;
1045 struct i2c_board_info *board_info =
1046 &subdevs->v4l2_subdev.board_info;
1047 struct i2c_adapter *adapter =
1048 i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id);
1049 int sensor_num, i;
1050
1051 dev_info(isp->dev, "Probing Subdev %s\n", board_info->type);
1052
1053 if (!adapter) {
1054 dev_err(isp->dev,
1055 "Failed to find i2c adapter for subdev %s\n",
1056 board_info->type);
1057 break;
1058 }
1059
1060
1061
1062
1063 subdev = atomisp_gmin_find_subdev(adapter, board_info);
1064 if (!subdev) {
1065 dev_warn(isp->dev, "Subdev %s not found\n",
1066 board_info->type);
1067 continue;
1068 }
1069 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev);
1070 if (ret) {
1071 dev_warn(isp->dev, "Subdev %s detection fail\n",
1072 board_info->type);
1073 continue;
1074 }
1075
1076 if (!subdev) {
1077 dev_warn(isp->dev, "Subdev %s detection fail\n",
1078 board_info->type);
1079 continue;
1080 }
1081
1082 dev_info(isp->dev, "Subdev %s successfully register\n",
1083 board_info->type);
1084
1085 switch (subdevs->type) {
1086 case RAW_CAMERA:
1087 dev_dbg(isp->dev, "raw_index: %d\n", raw_index);
1088 raw_index = isp->input_cnt;
1089 fallthrough;
1090 case SOC_CAMERA:
1091 dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt);
1092 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) {
1093 dev_warn(isp->dev,
1094 "too many atomisp inputs, ignored\n");
1095 break;
1096 }
1097
1098 isp->inputs[isp->input_cnt].type = subdevs->type;
1099 isp->inputs[isp->input_cnt].port = subdevs->port;
1100 isp->inputs[isp->input_cnt].camera = subdev;
1101 isp->inputs[isp->input_cnt].sensor_index = 0;
1102
1103
1104
1105
1106
1107 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0;
1108 isp->inputs[isp->input_cnt].camera_caps =
1109 atomisp_get_default_camera_caps();
1110 sensor_num = isp->inputs[isp->input_cnt]
1111 .camera_caps->sensor_num;
1112 isp->input_cnt++;
1113 for (i = 1; i < sensor_num; i++) {
1114 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) {
1115 dev_warn(isp->dev,
1116 "atomisp inputs out of range\n");
1117 break;
1118 }
1119 isp->inputs[isp->input_cnt] =
1120 isp->inputs[isp->input_cnt - 1];
1121 isp->inputs[isp->input_cnt].sensor_index = i;
1122 isp->input_cnt++;
1123 }
1124 break;
1125 case CAMERA_MOTOR:
1126 if (isp->motor) {
1127 dev_warn(isp->dev,
1128 "too many atomisp motors, ignored %s\n",
1129 board_info->type);
1130 continue;
1131 }
1132 isp->motor = subdev;
1133 break;
1134 case LED_FLASH:
1135 case XENON_FLASH:
1136 if (isp->flash) {
1137 dev_warn(isp->dev,
1138 "too many atomisp flash devices, ignored %s\n",
1139 board_info->type);
1140 continue;
1141 }
1142 isp->flash = subdev;
1143 break;
1144 default:
1145 dev_dbg(isp->dev, "unknown subdev probed\n");
1146 break;
1147 }
1148 }
1149
1150
1151
1152
1153
1154
1155 if (isp->motor && raw_index >= 0)
1156 isp->inputs[raw_index].motor = isp->motor;
1157
1158
1159 if (!isp->input_cnt)
1160 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1161 else
1162 dev_info(isp->dev, "detected %d camera sensors\n",
1163 isp->input_cnt);
1164
1165 return atomisp_csi_lane_config(isp);
1166}
1167
1168static void atomisp_unregister_entities(struct atomisp_device *isp)
1169{
1170 unsigned int i;
1171 struct v4l2_subdev *sd, *next;
1172
1173 for (i = 0; i < isp->num_of_streams; i++)
1174 atomisp_subdev_unregister_entities(&isp->asd[i]);
1175 atomisp_tpg_unregister_entities(&isp->tpg);
1176 atomisp_file_input_unregister_entities(&isp->file_dev);
1177 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
1178 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
1179
1180 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
1181 v4l2_device_unregister_subdev(sd);
1182
1183 v4l2_device_unregister(&isp->v4l2_dev);
1184 media_device_unregister(&isp->media_dev);
1185}
1186
1187static int atomisp_register_entities(struct atomisp_device *isp)
1188{
1189 int ret = 0;
1190 unsigned int i;
1191
1192 isp->media_dev.dev = isp->dev;
1193
1194 strscpy(isp->media_dev.model, "Intel Atom ISP",
1195 sizeof(isp->media_dev.model));
1196
1197 media_device_init(&isp->media_dev);
1198 isp->v4l2_dev.mdev = &isp->media_dev;
1199 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1200 if (ret < 0) {
1201 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
1202 __func__, ret);
1203 goto v4l2_device_failed;
1204 }
1205
1206 ret = atomisp_subdev_probe(isp);
1207 if (ret < 0)
1208 goto csi_and_subdev_probe_failed;
1209
1210
1211 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
1212 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
1213 &isp->v4l2_dev);
1214 if (ret == 0)
1215 continue;
1216
1217
1218 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
1219
1220 while (i--)
1221 atomisp_mipi_csi2_unregister_entities(
1222 &isp->csi2_port[i]);
1223
1224 goto csi_and_subdev_probe_failed;
1225 }
1226
1227 ret =
1228 atomisp_file_input_register_entities(&isp->file_dev, &isp->v4l2_dev);
1229 if (ret < 0) {
1230 dev_err(isp->dev, "atomisp_file_input_register_entities\n");
1231 goto file_input_register_failed;
1232 }
1233
1234 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev);
1235 if (ret < 0) {
1236 dev_err(isp->dev, "atomisp_tpg_register_entities\n");
1237 goto tpg_register_failed;
1238 }
1239
1240 for (i = 0; i < isp->num_of_streams; i++) {
1241 struct atomisp_sub_device *asd = &isp->asd[i];
1242
1243 ret = atomisp_subdev_register_entities(asd, &isp->v4l2_dev);
1244 if (ret < 0) {
1245 dev_err(isp->dev,
1246 "atomisp_subdev_register_entities fail\n");
1247 for (; i > 0; i--)
1248 atomisp_subdev_unregister_entities(
1249 &isp->asd[i - 1]);
1250 goto subdev_register_failed;
1251 }
1252 }
1253
1254 for (i = 0; i < isp->num_of_streams; i++) {
1255 struct atomisp_sub_device *asd = &isp->asd[i];
1256
1257 init_completion(&asd->init_done);
1258
1259 asd->delayed_init_workq =
1260 alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE,
1261 1);
1262 if (!asd->delayed_init_workq) {
1263 dev_err(isp->dev,
1264 "Failed to initialize delayed init workq\n");
1265 ret = -ENOMEM;
1266
1267 for (; i > 0; i--)
1268 destroy_workqueue(isp->asd[i - 1].
1269 delayed_init_workq);
1270 goto wq_alloc_failed;
1271 }
1272 INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work);
1273 }
1274
1275 for (i = 0; i < isp->input_cnt; i++) {
1276 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) {
1277 dev_err(isp->dev, "isp->inputs port %d not supported\n",
1278 isp->inputs[i].port);
1279 ret = -EINVAL;
1280 goto link_failed;
1281 }
1282 }
1283
1284 dev_dbg(isp->dev,
1285 "FILE_INPUT enable, camera_cnt: %d\n", isp->input_cnt);
1286 isp->inputs[isp->input_cnt].type = FILE_INPUT;
1287 isp->inputs[isp->input_cnt].port = -1;
1288 isp->inputs[isp->input_cnt].camera_caps =
1289 atomisp_get_default_camera_caps();
1290 isp->inputs[isp->input_cnt++].camera = &isp->file_dev.sd;
1291
1292 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) {
1293 dev_dbg(isp->dev,
1294 "TPG detected, camera_cnt: %d\n", isp->input_cnt);
1295 isp->inputs[isp->input_cnt].type = TEST_PATTERN;
1296 isp->inputs[isp->input_cnt].port = -1;
1297 isp->inputs[isp->input_cnt].camera_caps =
1298 atomisp_get_default_camera_caps();
1299 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd;
1300 } else {
1301 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n");
1302 }
1303
1304 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1305 if (ret < 0)
1306 goto link_failed;
1307
1308 return media_device_register(&isp->media_dev);
1309
1310link_failed:
1311 for (i = 0; i < isp->num_of_streams; i++)
1312 destroy_workqueue(isp->asd[i].
1313 delayed_init_workq);
1314wq_alloc_failed:
1315 for (i = 0; i < isp->num_of_streams; i++)
1316 atomisp_subdev_unregister_entities(
1317 &isp->asd[i]);
1318subdev_register_failed:
1319 atomisp_tpg_unregister_entities(&isp->tpg);
1320tpg_register_failed:
1321 atomisp_file_input_unregister_entities(&isp->file_dev);
1322file_input_register_failed:
1323 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
1324 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
1325csi_and_subdev_probe_failed:
1326 v4l2_device_unregister(&isp->v4l2_dev);
1327v4l2_device_failed:
1328 media_device_unregister(&isp->media_dev);
1329 media_device_cleanup(&isp->media_dev);
1330 return ret;
1331}
1332
1333static int atomisp_initialize_modules(struct atomisp_device *isp)
1334{
1335 int ret;
1336
1337 ret = atomisp_mipi_csi2_init(isp);
1338 if (ret < 0) {
1339 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1340 goto error_mipi_csi2;
1341 }
1342
1343 ret = atomisp_file_input_init(isp);
1344 if (ret < 0) {
1345 dev_err(isp->dev,
1346 "file input device initialization failed\n");
1347 goto error_file_input;
1348 }
1349
1350 ret = atomisp_tpg_init(isp);
1351 if (ret < 0) {
1352 dev_err(isp->dev, "tpg initialization failed\n");
1353 goto error_tpg;
1354 }
1355
1356 ret = atomisp_subdev_init(isp);
1357 if (ret < 0) {
1358 dev_err(isp->dev, "ISP subdev initialization failed\n");
1359 goto error_isp_subdev;
1360 }
1361
1362 return 0;
1363
1364error_isp_subdev:
1365error_tpg:
1366 atomisp_tpg_cleanup(isp);
1367error_file_input:
1368 atomisp_file_input_cleanup(isp);
1369error_mipi_csi2:
1370 atomisp_mipi_csi2_cleanup(isp);
1371 return ret;
1372}
1373
1374static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1375{
1376 atomisp_tpg_cleanup(isp);
1377 atomisp_file_input_cleanup(isp);
1378 atomisp_mipi_csi2_cleanup(isp);
1379}
1380
1381const struct firmware *
1382atomisp_load_firmware(struct atomisp_device *isp)
1383{
1384 const struct firmware *fw;
1385 int rc;
1386 char *fw_path = NULL;
1387
1388 if (skip_fwload)
1389 return NULL;
1390
1391 if (firmware_name[0] != '\0') {
1392 fw_path = firmware_name;
1393 } else {
1394 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT)
1395 == ATOMISP_HW_REVISION_ISP2401)
1396 fw_path = "shisp_2401a0_v21.bin";
1397
1398 if (isp->media_dev.hw_revision ==
1399 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT)
1400 | ATOMISP_HW_STEPPING_A0))
1401 fw_path = "shisp_2401a0_legacy_v21.bin";
1402
1403 if (isp->media_dev.hw_revision ==
1404 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT)
1405 | ATOMISP_HW_STEPPING_B0))
1406 fw_path = "shisp_2400b0_v21.bin";
1407 }
1408
1409 if (!fw_path) {
1410 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1411 isp->media_dev.hw_revision);
1412 return NULL;
1413 }
1414
1415 rc = request_firmware(&fw, fw_path, isp->dev);
1416 if (rc) {
1417 dev_err(isp->dev,
1418 "atomisp: Error %d while requesting firmware %s\n",
1419 rc, fw_path);
1420 return NULL;
1421 }
1422
1423 return fw;
1424}
1425
1426
1427
1428
1429
1430static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id)
1431{
1432 const char *name;
1433 const char *product;
1434
1435 product = dmi_get_system_info(DMI_PRODUCT_NAME);
1436
1437 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1438 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1439 name = "Merrifield";
1440 break;
1441 case ATOMISP_PCI_DEVICE_SOC_BYT:
1442 name = "Baytrail";
1443 break;
1444 case ATOMISP_PCI_DEVICE_SOC_ANN:
1445 name = "Anniedale";
1446 break;
1447 case ATOMISP_PCI_DEVICE_SOC_CHT:
1448 name = "Cherrytrail";
1449 break;
1450 default:
1451 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n",
1452 product, id->vendor, id->device);
1453 return false;
1454 }
1455
1456 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1457 dev_err(&pdev->dev, "%s revision %d is not unsupported\n",
1458 name, pdev->revision);
1459 return false;
1460 }
1461
1462
1463
1464
1465
1466
1467#if defined(ISP2400)
1468 if (IS_ISP2401) {
1469 dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n",
1470 name);
1471 return false;
1472 }
1473#else
1474 if (!IS_ISP2401) {
1475 dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n",
1476 name);
1477 return false;
1478 }
1479#endif
1480
1481 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n",
1482 name, pdev->revision, IS_ISP2401 ? '1' : '0', product);
1483
1484 return true;
1485}
1486
1487static int init_atomisp_wdts(struct atomisp_device *isp)
1488{
1489 int i, err;
1490
1491 atomic_set(&isp->wdt_work_queued, 0);
1492 isp->wdt_work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1);
1493 if (!isp->wdt_work_queue) {
1494 dev_err(isp->dev, "Failed to initialize wdt work queue\n");
1495 err = -ENOMEM;
1496 goto alloc_fail;
1497 }
1498 INIT_WORK(&isp->wdt_work, atomisp_wdt_work);
1499
1500 for (i = 0; i < isp->num_of_streams; i++) {
1501 struct atomisp_sub_device *asd = &isp->asd[i];
1502
1503 if (!IS_ISP2401) {
1504 timer_setup(&asd->wdt, atomisp_wdt, 0);
1505 } else {
1506 timer_setup(&asd->video_out_capture.wdt,
1507 atomisp_wdt, 0);
1508 timer_setup(&asd->video_out_preview.wdt,
1509 atomisp_wdt, 0);
1510 timer_setup(&asd->video_out_vf.wdt, atomisp_wdt, 0);
1511 timer_setup(&asd->video_out_video_capture.wdt,
1512 atomisp_wdt, 0);
1513 }
1514 }
1515 return 0;
1516alloc_fail:
1517 return err;
1518}
1519
1520#define ATOM_ISP_PCI_BAR 0
1521
1522static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1523{
1524 const struct atomisp_platform_data *pdata;
1525 struct atomisp_device *isp;
1526 unsigned int start;
1527 int err, val;
1528 u32 irq;
1529
1530 if (!is_valid_device(pdev, id))
1531 return -ENODEV;
1532
1533
1534 atomisp_dev = &pdev->dev;
1535
1536 pdata = atomisp_get_platform_data();
1537 if (!pdata)
1538 dev_warn(&pdev->dev, "no platform data available\n");
1539
1540 err = pcim_enable_device(pdev);
1541 if (err) {
1542 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err);
1543 return err;
1544 }
1545
1546 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1547 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1548
1549 err = pcim_iomap_regions(pdev, 1 << ATOM_ISP_PCI_BAR, pci_name(pdev));
1550 if (err) {
1551 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1552 goto ioremap_fail;
1553 }
1554
1555 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1556 if (!isp) {
1557 err = -ENOMEM;
1558 goto atomisp_dev_alloc_fail;
1559 }
1560
1561 isp->dev = &pdev->dev;
1562 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1563 isp->sw_contex.power_state = ATOM_ISP_POWER_UP;
1564 isp->saved_regs.ispmmadr = start;
1565
1566 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base);
1567
1568 rt_mutex_init(&isp->mutex);
1569 mutex_init(&isp->streamoff_mutex);
1570 spin_lock_init(&isp->lock);
1571
1572
1573 pdev->d3hot_delay = 0;
1574
1575 pci_set_drvdata(pdev, isp);
1576
1577 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1578 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1579 isp->media_dev.hw_revision =
1580 (ATOMISP_HW_REVISION_ISP2400
1581 << ATOMISP_HW_REVISION_SHIFT) |
1582 ATOMISP_HW_STEPPING_B0;
1583
1584 switch (id->device) {
1585 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1586 isp->dfs = &dfs_config_merr_1179;
1587 break;
1588 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1589 isp->dfs = &dfs_config_merr_117a;
1590
1591 break;
1592 default:
1593 isp->dfs = &dfs_config_merr;
1594 break;
1595 }
1596 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1597 break;
1598 case ATOMISP_PCI_DEVICE_SOC_BYT:
1599 isp->media_dev.hw_revision =
1600 (ATOMISP_HW_REVISION_ISP2400
1601 << ATOMISP_HW_REVISION_SHIFT) |
1602 ATOMISP_HW_STEPPING_B0;
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619 isp->dfs = &dfs_config_byt;
1620
1621
1622
1623
1624
1625
1626 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1627
1628
1629
1630
1631
1632
1633 pdev->d3cold_delay = 0;
1634 break;
1635 case ATOMISP_PCI_DEVICE_SOC_ANN:
1636 isp->media_dev.hw_revision = (
1637#ifdef ISP2401_NEW_INPUT_SYSTEM
1638 ATOMISP_HW_REVISION_ISP2401
1639#else
1640 ATOMISP_HW_REVISION_ISP2401_LEGACY
1641#endif
1642 << ATOMISP_HW_REVISION_SHIFT);
1643 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1644 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1645 isp->dfs = &dfs_config_merr;
1646 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1647 break;
1648 case ATOMISP_PCI_DEVICE_SOC_CHT:
1649 isp->media_dev.hw_revision = (
1650#ifdef ISP2401_NEW_INPUT_SYSTEM
1651 ATOMISP_HW_REVISION_ISP2401
1652#else
1653 ATOMISP_HW_REVISION_ISP2401_LEGACY
1654#endif
1655 << ATOMISP_HW_REVISION_SHIFT);
1656 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1657 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1658
1659 isp->dfs = &dfs_config_cht;
1660 pdev->d3cold_delay = 0;
1661
1662 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1663 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1664 case 0x00:
1665 isp->hpll_freq = HPLL_FREQ_800MHZ;
1666 break;
1667 case 0x01:
1668 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1669 break;
1670 case 0x02:
1671 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1672 break;
1673 default:
1674 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1675 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1676 }
1677 break;
1678 default:
1679 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1680 err = -ENODEV;
1681 goto atomisp_dev_alloc_fail;
1682 }
1683
1684 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1685
1686 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1687
1688
1689 if (!defer_fw_load) {
1690 isp->firmware = atomisp_load_firmware(isp);
1691 if (!isp->firmware) {
1692 err = -ENOENT;
1693 dev_dbg(&pdev->dev, "Firmware load failed\n");
1694 goto load_fw_fail;
1695 }
1696
1697 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1698 if (err) {
1699 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1700 goto fw_validation_fail;
1701 }
1702 } else {
1703 dev_info(&pdev->dev, "Firmware load will be deferred\n");
1704 }
1705
1706 pci_set_master(pdev);
1707
1708 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1709 if (err < 0) {
1710 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1711 goto enable_msi_fail;
1712 }
1713
1714 atomisp_msi_irq_init(isp);
1715
1716 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1717
1718
1719
1720
1721
1722
1723
1724
1725 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1726
1727 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
1728 ATOMISP_PCI_DEVICE_SOC_MRFLD) {
1729 u32 csi_afe_trim;
1730
1731
1732
1733
1734
1735 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim);
1736 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1737 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1738 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1739 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1740 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1741 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1742 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM <<
1743 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1744 (MRFLD_PCI_CSI2_HSRXCLKTRIM <<
1745 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1746 (MRFLD_PCI_CSI3_HSRXCLKTRIM <<
1747 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1748 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim);
1749 }
1750
1751 err = atomisp_initialize_modules(isp);
1752 if (err < 0) {
1753 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1754 goto initialize_modules_fail;
1755 }
1756
1757 err = atomisp_register_entities(isp);
1758 if (err < 0) {
1759 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1760 goto register_entities_fail;
1761 }
1762 err = atomisp_create_pads_links(isp);
1763 if (err < 0)
1764 goto register_entities_fail;
1765
1766 err = init_atomisp_wdts(isp);
1767 if (err != 0)
1768 goto wdt_work_queue_fail;
1769
1770
1771 atomisp_save_iunit_reg(isp);
1772
1773 pm_runtime_put_noidle(&pdev->dev);
1774 pm_runtime_allow(&pdev->dev);
1775
1776 hmm_init_mem_stat(repool_pgnr, dypool_enable, dypool_pgnr);
1777 err = hmm_pool_register(repool_pgnr, HMM_POOL_TYPE_RESERVED);
1778 if (err) {
1779 dev_err(&pdev->dev, "Failed to register reserved memory pool.\n");
1780 goto hmm_pool_fail;
1781 }
1782
1783
1784 hmm_init();
1785
1786 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1787 atomisp_isr, atomisp_isr_thread,
1788 IRQF_SHARED, "isp_irq", isp);
1789 if (err) {
1790 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1791 goto request_irq_fail;
1792 }
1793
1794
1795 if (!defer_fw_load) {
1796 err = atomisp_css_load_firmware(isp);
1797 if (err) {
1798 dev_err(&pdev->dev, "Failed to init css.\n");
1799 goto css_init_fail;
1800 }
1801 } else {
1802 dev_dbg(&pdev->dev, "Skip css init.\n");
1803 }
1804
1805 release_firmware(isp->firmware);
1806 isp->firmware = NULL;
1807 isp->css_env.isp_css_fw.data = NULL;
1808
1809 atomisp_drvfs_init(isp);
1810
1811 return 0;
1812
1813css_init_fail:
1814 devm_free_irq(&pdev->dev, pdev->irq, isp);
1815request_irq_fail:
1816 hmm_cleanup();
1817 hmm_pool_unregister(HMM_POOL_TYPE_RESERVED);
1818hmm_pool_fail:
1819 pm_runtime_get_noresume(&pdev->dev);
1820 destroy_workqueue(isp->wdt_work_queue);
1821wdt_work_queue_fail:
1822 atomisp_acc_cleanup(isp);
1823 atomisp_unregister_entities(isp);
1824register_entities_fail:
1825 atomisp_uninitialize_modules(isp);
1826initialize_modules_fail:
1827 cpu_latency_qos_remove_request(&isp->pm_qos);
1828 atomisp_msi_irq_uninit(isp);
1829 pci_free_irq_vectors(pdev);
1830enable_msi_fail:
1831fw_validation_fail:
1832 release_firmware(isp->firmware);
1833load_fw_fail:
1834
1835
1836
1837
1838
1839
1840
1841 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1842 irq = irq & 1 << INTR_IIR;
1843 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1844
1845 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1846 irq &= ~(1 << INTR_IER);
1847 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1848
1849 atomisp_msi_irq_uninit(isp);
1850
1851 atomisp_ospm_dphy_down(isp);
1852
1853
1854 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power_down(isp))
1855 dev_err(&pdev->dev, "Failed to switch off ISP\n");
1856
1857atomisp_dev_alloc_fail:
1858 pcim_iounmap_regions(pdev, 1 << ATOM_ISP_PCI_BAR);
1859
1860ioremap_fail:
1861 return err;
1862}
1863
1864static void atomisp_pci_remove(struct pci_dev *pdev)
1865{
1866 struct atomisp_device *isp = pci_get_drvdata(pdev);
1867
1868 dev_info(&pdev->dev, "Removing atomisp driver\n");
1869
1870 atomisp_drvfs_exit();
1871
1872 atomisp_acc_cleanup(isp);
1873
1874 ia_css_unload_firmware();
1875 hmm_cleanup();
1876
1877 pm_runtime_forbid(&pdev->dev);
1878 pm_runtime_get_noresume(&pdev->dev);
1879 cpu_latency_qos_remove_request(&isp->pm_qos);
1880
1881 atomisp_msi_irq_uninit(isp);
1882 atomisp_unregister_entities(isp);
1883
1884 destroy_workqueue(isp->wdt_work_queue);
1885 atomisp_file_input_cleanup(isp);
1886
1887 release_firmware(isp->firmware);
1888
1889 hmm_pool_unregister(HMM_POOL_TYPE_RESERVED);
1890}
1891
1892static const struct pci_device_id atomisp_pci_tbl[] = {
1893
1894 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1895 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1896 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1897
1898 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1899
1900 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1901
1902 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1903 {0,}
1904};
1905
1906MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1907
1908static const struct dev_pm_ops atomisp_pm_ops = {
1909 .runtime_suspend = atomisp_runtime_suspend,
1910 .runtime_resume = atomisp_runtime_resume,
1911 .suspend = atomisp_suspend,
1912 .resume = atomisp_resume,
1913};
1914
1915static struct pci_driver atomisp_pci_driver = {
1916 .driver = {
1917 .pm = &atomisp_pm_ops,
1918 },
1919 .name = "atomisp-isp2",
1920 .id_table = atomisp_pci_tbl,
1921 .probe = atomisp_pci_probe,
1922 .remove = atomisp_pci_remove,
1923};
1924
1925module_pci_driver(atomisp_pci_driver);
1926
1927MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1928MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1929MODULE_LICENSE("GPL");
1930MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1931
