LXR linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/dma

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Support for Intel Camera Imaging ISP subsystem.
   4 * Copyright (c) 2015, Intel Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 */
  15
  16#ifndef __DMA_GLOBAL_H_INCLUDED__
  17#define __DMA_GLOBAL_H_INCLUDED__
  18
  19#include <type_support.h>
  20
  21#define IS_DMA_VERSION_2
  22
  23#define HIVE_ISP_NUM_DMA_CONNS          3
  24#define HIVE_ISP_NUM_DMA_CHANNELS       32
  25
  26#define N_DMA_CHANNEL_ID        HIVE_ISP_NUM_DMA_CHANNELS
  27
  28#include "dma_v2_defs.h"
  29
  30/*
  31 * Command token bit mappings
  32 *
  33 * transfer / config
  34 *    param id[4] channel id[5] cmd id[6]
  35 *      | b14 .. b11 | b10 ... b6 | b5 ... b0 |
  36 *
  37 *
  38 * fast transfer:
  39 *    height[5]     width[8]      width[8]  channel id[5] cmd id[6]
  40 *      | b31 .. b26 | b25 .. b18 | b17 .. b11 | b10 ... b6 | b5 ... b0 |
  41 *
  42 */
  43
  44#define _DMA_PACKING_SETUP_PARAM        _DMA_V2_PACKING_SETUP_PARAM
  45#define _DMA_HEIGHT_PARAM                       _DMA_V2_HEIGHT_PARAM
  46#define _DMA_STRIDE_A_PARAM                     _DMA_V2_STRIDE_A_PARAM
  47#define _DMA_ELEM_CROPPING_A_PARAM      _DMA_V2_ELEM_CROPPING_A_PARAM
  48#define _DMA_WIDTH_A_PARAM                      _DMA_V2_WIDTH_A_PARAM
  49#define _DMA_STRIDE_B_PARAM                     _DMA_V2_STRIDE_B_PARAM
  50#define _DMA_ELEM_CROPPING_B_PARAM      _DMA_V2_ELEM_CROPPING_B_PARAM
  51#define _DMA_WIDTH_B_PARAM                      _DMA_V2_WIDTH_B_PARAM
  52
  53#define _DMA_ZERO_EXTEND     _DMA_V2_ZERO_EXTEND
  54#define _DMA_SIGN_EXTEND     _DMA_V2_SIGN_EXTEND
  55
  56typedef unsigned int dma_channel;
  57
  58typedef enum {
  59        dma_isp_to_bus_connection = HIVE_DMA_ISP_BUS_CONN,
  60        dma_isp_to_ddr_connection = HIVE_DMA_ISP_DDR_CONN,
  61        dma_bus_to_ddr_connection = HIVE_DMA_BUS_DDR_CONN,
  62} dma_connection;
  63
  64typedef enum {
  65        dma_zero_extension = _DMA_ZERO_EXTEND,
  66        dma_sign_extension = _DMA_SIGN_EXTEND
  67} dma_extension;
  68
  69#define DMA_PROP_SHIFT(val, param)       ((val) << _DMA_V2_ ## param ## _IDX)
  70#define DMA_PROP_MASK(param)             ((1U << _DMA_V2_ ## param ## _BITS) - 1)
  71#define DMA_PACK(val, param)             DMA_PROP_SHIFT((val) & DMA_PROP_MASK(param), param)
  72
  73#define DMA_PACK_COMMAND(cmd)            DMA_PACK(cmd, CMD)
  74#define DMA_PACK_CHANNEL(ch)             DMA_PACK(ch,  CHANNEL)
  75#define DMA_PACK_PARAM(par)              DMA_PACK(par, PARAM)
  76#define DMA_PACK_EXTENSION(ext)          DMA_PACK(ext, EXTENSION)
  77#define DMA_PACK_LEFT_CROPPING(lc)       DMA_PACK(lc,  LEFT_CROPPING)
  78#define DMA_PACK_WIDTH_A(w)              DMA_PACK(w,   SPEC_DEV_A_XB)
  79#define DMA_PACK_WIDTH_B(w)              DMA_PACK(w,   SPEC_DEV_B_XB)
  80#define DMA_PACK_HEIGHT(h)               DMA_PACK(h,   SPEC_YB)
  81
  82#define DMA_PACK_CMD_CHANNEL(cmd, ch)    (DMA_PACK_COMMAND(cmd) | DMA_PACK_CHANNEL(ch))
  83#define DMA_PACK_SETUP(conn, ext)        ((conn) | DMA_PACK_EXTENSION(ext))
  84#define DMA_PACK_CROP_ELEMS(elems, crop) ((elems) | DMA_PACK_LEFT_CROPPING(crop))
  85
  86#define hive_dma_snd(dma_id, token) OP_std_snd(dma_id, (unsigned int)(token))
  87
  88#define DMA_PACK_BLOCK_CMD(cmd, ch, width_a, width_b, height) \
  89  (DMA_PACK_COMMAND(cmd)     | \
  90   DMA_PACK_CHANNEL(ch)      | \
  91   DMA_PACK_WIDTH_A(width_a) | \
  92   DMA_PACK_WIDTH_B(width_b) | \
  93   DMA_PACK_HEIGHT(height))
  94
  95#define hive_dma_move_data(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \
  96{ \
  97  hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \
  98  hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read ? _DMA_V2_MOVE_B2A_COMMAND : _DMA_V2_MOVE_A2B_COMMAND, channel)); \
  99  hive_dma_snd(dma_id, read ? (unsigned int)(addr_b) : (unsigned int)(addr_a)); \
 100  hive_dma_snd(dma_id, read ? (unsigned int)(addr_a) : (unsigned int)(addr_b)); \
 101  hive_dma_snd(dma_id, to_is_var); \
 102  hive_dma_snd(dma_id, from_is_var); \
 103}
 104
 105#define hive_dma_move_data_no_ack(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \
 106{ \
 107  hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \
 108  hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read ? _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND : _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND, channel)); \
 109  hive_dma_snd(dma_id, read ? (unsigned int)(addr_b) : (unsigned int)(addr_a)); \
 110  hive_dma_snd(dma_id, read ? (unsigned int)(addr_a) : (unsigned int)(addr_b)); \
 111  hive_dma_snd(dma_id, to_is_var); \
 112  hive_dma_snd(dma_id, from_is_var); \
 113}
 114
 115#define hive_dma_move_b2a_data(dma_id, channel, to_addr, from_addr, to_is_var, from_is_var) \
 116{ \
 117  hive_dma_move_data(dma_id, true, channel, to_addr, from_addr, to_is_var, from_is_var) \
 118}
 119
 120#define hive_dma_move_a2b_data(dma_id, channel, from_addr, to_addr, from_is_var, to_is_var) \
 121{ \
 122  hive_dma_move_data(dma_id, false, channel, from_addr, to_addr, from_is_var, to_is_var) \
 123}
 124
 125#define hive_dma_set_data(dma_id, channel, address, value, is_var) \
 126{ \
 127  hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \
 128  hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_INIT_A_COMMAND, channel)); \
 129  hive_dma_snd(dma_id, value); \
 130  hive_dma_snd(dma_id, address); \
 131  hive_dma_snd(dma_id, is_var); \
 132}
 133
 134#define hive_dma_clear_data(dma_id, channel, address, is_var) hive_dma_set_data(dma_id, channel, address, 0, is_var)
 135
 136#define hive_dma_configure(dma_id, channel, connection, extension, height, \
 137        stride_A, elems_A, cropping_A, width_A, \
 138        stride_B, elems_B, cropping_B, width_B) \
 139{ \
 140  hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_CONFIG_CHANNEL_COMMAND, channel)); \
 141  hive_dma_snd(dma_id, DMA_PACK_SETUP(connection, extension)); \
 142  hive_dma_snd(dma_id, stride_A); \
 143  hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_A, cropping_A)); \
 144  hive_dma_snd(dma_id, width_A); \
 145  hive_dma_snd(dma_id, stride_B); \
 146  hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_B, cropping_B)); \
 147  hive_dma_snd(dma_id, width_B); \
 148  hive_dma_snd(dma_id, height); \
 149}
 150
 151#define hive_dma_execute(dma_id, channel, cmd, to_addr, from_addr_value, to_is_var, from_is_var) \
 152{ \
 153  hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \
 154  hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(cmd, channel)); \
 155  hive_dma_snd(dma_id, to_addr); \
 156  hive_dma_snd(dma_id, from_addr_value); \
 157  hive_dma_snd(dma_id, to_is_var); \
 158  if ((cmd & DMA_CLEAR_CMDBIT) == 0) { \
 159        hive_dma_snd(dma_id, from_is_var); \
 160  } \
 161}
 162
 163#define hive_dma_configure_fast(dma_id, channel, connection, extension, elems_A, elems_B) \
 164{ \
 165  hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_CONFIG_CHANNEL_COMMAND, channel)); \
 166  hive_dma_snd(dma_id, DMA_PACK_SETUP(connection, extension)); \
 167  hive_dma_snd(dma_id, 0); \
 168  hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_A, 0)); \
 169  hive_dma_snd(dma_id, 0); \
 170  hive_dma_snd(dma_id, 0); \
 171  hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_B, 0)); \
 172  hive_dma_snd(dma_id, 0); \
 173  hive_dma_snd(dma_id, 1); \
 174}
 175
 176#define hive_dma_set_parameter(dma_id, channel, param, value) \
 177{ \
 178  hive_dma_snd(dma_id, _DMA_V2_SET_CHANNEL_PARAM_COMMAND | DMA_PACK_CHANNEL(channel) | DMA_PACK_PARAM(param)); \
 179  hive_dma_snd(dma_id, value); \
 180}
 181
 182#define DMA_SPECIFIC_CMDBIT     0x01
 183#define DMA_CHECK_CMDBIT        0x02
 184#define DMA_RW_CMDBIT           0x04
 185#define DMA_CLEAR_CMDBIT        0x08
 186#define DMA_ACK_CMDBIT          0x10
 187#define DMA_CFG_CMDBIT          0x20
 188#define DMA_PARAM_CMDBIT        0x01
 189
 190/* Write complete check not necessary if there's no ack */
 191#define DMA_NOACK_CMD           (DMA_ACK_CMDBIT | DMA_CHECK_CMDBIT)
 192#define DMA_CFG_CMD                     (DMA_CFG_CMDBIT)
 193#define DMA_CFGPARAM_CMD        (DMA_CFG_CMDBIT | DMA_PARAM_CMDBIT)
 194
 195#define DMA_CMD_NEEDS_ACK(cmd) ((cmd & DMA_NOACK_CMD) == 0)
 196#define DMA_CMD_IS_TRANSFER(cmd) ((cmd & DMA_CFG_CMDBIT) == 0)
 197#define DMA_CMD_IS_WR(cmd) ((cmd & DMA_RW_CMDBIT) != 0)
 198#define DMA_CMD_IS_RD(cmd) ((cmd & DMA_RW_CMDBIT) == 0)
 199#define DMA_CMD_IS_CLR(cmd) ((cmd & DMA_CLEAR_CMDBIT) != 0)
 200#define DMA_CMD_IS_CFG(cmd) ((cmd & DMA_CFG_CMDBIT) != 0)
 201#define DMA_CMD_IS_PARAMCFG(cmd) ((cmd & DMA_CFGPARAM_CMD) == DMA_CFGPARAM_CMD)
 202
 203/* As a matter of convention */
 204#define DMA_TRANSFER_READ               DMA_TRANSFER_B2A
 205#define DMA_TRANSFER_WRITE              DMA_TRANSFER_A2B
 206/* store/load from the PoV of the system(memory) */
 207#define DMA_TRANSFER_STORE              DMA_TRANSFER_B2A
 208#define DMA_TRANSFER_LOAD               DMA_TRANSFER_A2B
 209#define DMA_TRANSFER_CLEAR              DMA_TRANSFER_CLEAR_A
 210
 211typedef enum {
 212        DMA_TRANSFER_CLEAR_A = DMA_CLEAR_CMDBIT,                                       /* 8 */
 213        DMA_TRANSFER_CLEAR_B = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT,                       /* 12 */
 214        DMA_TRANSFER_A2B = DMA_RW_CMDBIT,                                              /* 4 */
 215        DMA_TRANSFER_B2A = 0,                                                          /* 0 */
 216        DMA_TRANSFER_CLEAR_A_NOACK = DMA_CLEAR_CMDBIT | DMA_NOACK_CMD,                 /* 26 */
 217        DMA_TRANSFER_CLEAR_B_NOACK = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_NOACK_CMD, /* 30 */
 218        DMA_TRANSFER_A2B_NOACK = DMA_RW_CMDBIT | DMA_NOACK_CMD,                        /* 22 */
 219        DMA_TRANSFER_B2A_NOACK = DMA_NOACK_CMD,                                        /* 18 */
 220        DMA_FASTTRANSFER_CLEAR_A = DMA_CLEAR_CMDBIT | DMA_SPECIFIC_CMDBIT,
 221        DMA_FASTTRANSFER_CLEAR_B = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_SPECIFIC_CMDBIT,
 222        DMA_FASTTRANSFER_A2B = DMA_RW_CMDBIT | DMA_SPECIFIC_CMDBIT,
 223        DMA_FASTTRANSFER_B2A = DMA_SPECIFIC_CMDBIT,
 224        DMA_FASTTRANSFER_CLEAR_A_NOACK = DMA_CLEAR_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT,
 225        DMA_FASTTRANSFER_CLEAR_B_NOACK = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT,
 226        DMA_FASTTRANSFER_A2B_NOACK = DMA_RW_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT,
 227        DMA_FASTTRANSFER_B2A_NOACK = DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT,
 228} dma_transfer_type_t;
 229
 230typedef enum {
 231        DMA_CONFIG_SETUP = _DMA_V2_PACKING_SETUP_PARAM,
 232        DMA_CONFIG_HEIGHT = _DMA_V2_HEIGHT_PARAM,
 233        DMA_CONFIG_STRIDE_A_ = _DMA_V2_STRIDE_A_PARAM,
 234        DMA_CONFIG_CROP_ELEM_A = _DMA_V2_ELEM_CROPPING_A_PARAM,
 235        DMA_CONFIG_WIDTH_A = _DMA_V2_WIDTH_A_PARAM,
 236        DMA_CONFIG_STRIDE_B_ = _DMA_V2_STRIDE_B_PARAM,
 237        DMA_CONFIG_CROP_ELEM_B = _DMA_V2_ELEM_CROPPING_B_PARAM,
 238        DMA_CONFIG_WIDTH_B = _DMA_V2_WIDTH_B_PARAM,
 239} dma_config_type_t;
 240
 241struct dma_port_config {
 242        u8  crop, elems;
 243        u16 width;
 244        u32 stride;
 245};
 246
 247/* Descriptor for dma configuration */
 248struct dma_channel_config {
 249        u8  connection;
 250        u8  extension;
 251        u8  height;
 252        struct dma_port_config a, b;
 253};
 254
 255#endif /* __DMA_GLOBAL_H_INCLUDED__ */
 256