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12#ifndef HANTRO_H_
13#define HANTRO_H_
14
15#include <linux/platform_device.h>
16#include <linux/videodev2.h>
17#include <linux/wait.h>
18#include <linux/clk.h>
19
20#include <media/v4l2-ctrls.h>
21#include <media/v4l2-device.h>
22#include <media/v4l2-ioctl.h>
23#include <media/v4l2-mem2mem.h>
24#include <media/videobuf2-core.h>
25#include <media/videobuf2-dma-contig.h>
26
27#include "hantro_hw.h"
28
29struct hantro_ctx;
30struct hantro_codec_ops;
31
32#define HANTRO_JPEG_ENCODER BIT(0)
33#define HANTRO_ENCODERS 0x0000ffff
34#define HANTRO_MPEG2_DECODER BIT(16)
35#define HANTRO_VP8_DECODER BIT(17)
36#define HANTRO_H264_DECODER BIT(18)
37#define HANTRO_HEVC_DECODER BIT(19)
38#define HANTRO_DECODERS 0xffff0000
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46struct hantro_irq {
47 const char *name;
48 irqreturn_t (*handler)(int irq, void *priv);
49};
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74struct hantro_variant {
75 unsigned int enc_offset;
76 unsigned int dec_offset;
77 const struct hantro_fmt *enc_fmts;
78 unsigned int num_enc_fmts;
79 const struct hantro_fmt *dec_fmts;
80 unsigned int num_dec_fmts;
81 const struct hantro_fmt *postproc_fmts;
82 unsigned int num_postproc_fmts;
83 unsigned int codec;
84 const struct hantro_codec_ops *codec_ops;
85 int (*init)(struct hantro_dev *vpu);
86 int (*runtime_resume)(struct hantro_dev *vpu);
87 const struct hantro_irq *irqs;
88 int num_irqs;
89 const char * const *clk_names;
90 int num_clocks;
91 const char * const *reg_names;
92 int num_regs;
93 const struct hantro_postproc_regs *postproc_regs;
94};
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105enum hantro_codec_mode {
106 HANTRO_MODE_NONE = -1,
107 HANTRO_MODE_JPEG_ENC,
108 HANTRO_MODE_H264_DEC,
109 HANTRO_MODE_MPEG2_DEC,
110 HANTRO_MODE_VP8_DEC,
111 HANTRO_MODE_HEVC_DEC,
112};
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119struct hantro_ctrl {
120 unsigned int codec;
121 struct v4l2_ctrl_config cfg;
122};
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142struct hantro_func {
143 unsigned int id;
144 struct video_device vdev;
145 struct media_pad source_pad;
146 struct media_entity sink;
147 struct media_pad sink_pad;
148 struct media_entity proc;
149 struct media_pad proc_pads[2];
150 struct media_intf_devnode *intf_devnode;
151};
152
153static inline struct hantro_func *
154hantro_vdev_to_func(struct video_device *vdev)
155{
156 return container_of(vdev, struct hantro_func, vdev);
157}
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180struct hantro_dev {
181 struct v4l2_device v4l2_dev;
182 struct v4l2_m2m_dev *m2m_dev;
183 struct media_device mdev;
184 struct hantro_func *encoder;
185 struct hantro_func *decoder;
186 struct platform_device *pdev;
187 struct device *dev;
188 struct clk_bulk_data *clocks;
189 void __iomem **reg_bases;
190 void __iomem *enc_base;
191 void __iomem *dec_base;
192 void __iomem *ctrl_base;
193
194 struct mutex vpu_mutex;
195 spinlock_t irqlock;
196 const struct hantro_variant *variant;
197 struct delayed_work watchdog_work;
198};
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226struct hantro_ctx {
227 struct hantro_dev *dev;
228 struct v4l2_fh fh;
229 bool is_encoder;
230
231 u32 sequence_cap;
232 u32 sequence_out;
233
234 const struct hantro_fmt *vpu_src_fmt;
235 struct v4l2_pix_format_mplane src_fmt;
236 const struct hantro_fmt *vpu_dst_fmt;
237 struct v4l2_pix_format_mplane dst_fmt;
238
239 struct v4l2_ctrl_handler ctrl_handler;
240 int jpeg_quality;
241
242 const struct hantro_codec_ops *codec_ops;
243 struct hantro_postproc_ctx postproc;
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246 union {
247 struct hantro_h264_dec_hw_ctx h264_dec;
248 struct hantro_jpeg_enc_hw_ctx jpeg_enc;
249 struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
250 struct hantro_vp8_dec_hw_ctx vp8_dec;
251 struct hantro_hevc_dec_hw_ctx hevc_dec;
252 };
253};
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266struct hantro_fmt {
267 char *name;
268 u32 fourcc;
269 enum hantro_codec_mode codec_mode;
270 int header_size;
271 int max_depth;
272 enum hantro_enc_fmt enc_fmt;
273 struct v4l2_frmsize_stepwise frmsize;
274};
275
276struct hantro_reg {
277 u32 base;
278 u32 shift;
279 u32 mask;
280};
281
282struct hantro_postproc_regs {
283 struct hantro_reg pipeline_en;
284 struct hantro_reg max_burst;
285 struct hantro_reg clk_gate;
286 struct hantro_reg out_swap32;
287 struct hantro_reg out_endian;
288 struct hantro_reg out_luma_base;
289 struct hantro_reg input_width;
290 struct hantro_reg input_height;
291 struct hantro_reg output_width;
292 struct hantro_reg output_height;
293 struct hantro_reg input_fmt;
294 struct hantro_reg output_fmt;
295 struct hantro_reg orig_width;
296 struct hantro_reg display_width;
297};
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316extern int hantro_debug;
317
318#define vpu_debug(level, fmt, args...) \
319 do { \
320 if (hantro_debug & BIT(level)) \
321 pr_info("%s:%d: " fmt, \
322 __func__, __LINE__, ##args); \
323 } while (0)
324
325#define vpu_err(fmt, args...) \
326 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
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329static inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
330{
331 return container_of(fh, struct hantro_ctx, fh);
332}
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335static inline void vepu_write_relaxed(struct hantro_dev *vpu,
336 u32 val, u32 reg)
337{
338 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
339 writel_relaxed(val, vpu->enc_base + reg);
340}
341
342static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
343{
344 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
345 writel(val, vpu->enc_base + reg);
346}
347
348static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
349{
350 u32 val = readl(vpu->enc_base + reg);
351
352 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
353 return val;
354}
355
356static inline void vdpu_write_relaxed(struct hantro_dev *vpu,
357 u32 val, u32 reg)
358{
359 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
360 writel_relaxed(val, vpu->dec_base + reg);
361}
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363static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
364{
365 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
366 writel(val, vpu->dec_base + reg);
367}
368
369static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
370{
371 u32 val = readl(vpu->dec_base + reg);
372
373 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
374 return val;
375}
376
377static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
378 const struct hantro_reg *reg,
379 u32 val)
380{
381 u32 v;
382
383 v = vdpu_read(vpu, reg->base);
384 v &= ~(reg->mask << reg->shift);
385 v |= ((val & reg->mask) << reg->shift);
386 return v;
387}
388
389static inline void hantro_reg_write(struct hantro_dev *vpu,
390 const struct hantro_reg *reg,
391 u32 val)
392{
393 vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
394}
395
396static inline void hantro_reg_write_s(struct hantro_dev *vpu,
397 const struct hantro_reg *reg,
398 u32 val)
399{
400 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
401}
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403void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
404dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
405
406static inline struct vb2_v4l2_buffer *
407hantro_get_src_buf(struct hantro_ctx *ctx)
408{
409 return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
410}
411
412static inline struct vb2_v4l2_buffer *
413hantro_get_dst_buf(struct hantro_ctx *ctx)
414{
415 return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
416}
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418bool hantro_needs_postproc(const struct hantro_ctx *ctx,
419 const struct hantro_fmt *fmt);
420
421static inline dma_addr_t
422hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
423{
424 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
425 return ctx->postproc.dec_q[vb->index].dma;
426 return vb2_dma_contig_plane_dma_addr(vb, 0);
427}
428
429void hantro_postproc_disable(struct hantro_ctx *ctx);
430void hantro_postproc_enable(struct hantro_ctx *ctx);
431void hantro_postproc_free(struct hantro_ctx *ctx);
432int hantro_postproc_alloc(struct hantro_ctx *ctx);
433
434#endif
435