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8#include "hantro_hw.h"
9#include "hantro_g2_regs.h"
10
11#define HEVC_DEC_MODE 0xC
12
13#define BUS_WIDTH_32 0
14#define BUS_WIDTH_64 1
15#define BUS_WIDTH_128 2
16#define BUS_WIDTH_256 3
17
18static inline void hantro_write_addr(struct hantro_dev *vpu,
19 unsigned long offset,
20 dma_addr_t addr)
21{
22 vdpu_write(vpu, addr & 0xffffffff, offset);
23}
24
25static void prepare_tile_info_buffer(struct hantro_ctx *ctx)
26{
27 struct hantro_dev *vpu = ctx->dev;
28 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
29 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
30 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
31 u16 *p = (u16 *)((u8 *)ctx->hevc_dec.tile_sizes.cpu);
32 unsigned int num_tile_rows = pps->num_tile_rows_minus1 + 1;
33 unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;
34 unsigned int pic_width_in_ctbs, pic_height_in_ctbs;
35 unsigned int max_log2_ctb_size, ctb_size;
36 bool tiles_enabled, uniform_spacing;
37 u32 no_chroma = 0;
38
39 tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);
40 uniform_spacing = !!(pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING);
41
42 hantro_reg_write(vpu, &g2_tile_e, tiles_enabled);
43
44 max_log2_ctb_size = sps->log2_min_luma_coding_block_size_minus3 + 3 +
45 sps->log2_diff_max_min_luma_coding_block_size;
46 pic_width_in_ctbs = (sps->pic_width_in_luma_samples +
47 (1 << max_log2_ctb_size) - 1) >> max_log2_ctb_size;
48 pic_height_in_ctbs = (sps->pic_height_in_luma_samples + (1 << max_log2_ctb_size) - 1)
49 >> max_log2_ctb_size;
50 ctb_size = 1 << max_log2_ctb_size;
51
52 vpu_debug(1, "Preparing tile sizes buffer for %dx%d CTBs (CTB size %d)\n",
53 pic_width_in_ctbs, pic_height_in_ctbs, ctb_size);
54
55 if (tiles_enabled) {
56 unsigned int i, j, h;
57
58 vpu_debug(1, "Tiles enabled! %dx%d\n", num_tile_cols, num_tile_rows);
59
60 hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows);
61 hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols);
62
63
64 if (!uniform_spacing) {
65 u32 tmp_w = 0, tmp_h = 0;
66
67 for (i = 0; i < num_tile_rows; i++) {
68 if (i == num_tile_rows - 1)
69 h = pic_height_in_ctbs - tmp_h;
70 else
71 h = pps->row_height_minus1[i] + 1;
72 tmp_h += h;
73 if (i == 0 && h == 1 && ctb_size == 16)
74 no_chroma = 1;
75 for (j = 0, tmp_w = 0; j < num_tile_cols - 1; j++) {
76 tmp_w += pps->column_width_minus1[j] + 1;
77 *p++ = pps->column_width_minus1[j + 1];
78 *p++ = h;
79 if (i == 0 && h == 1 && ctb_size == 16)
80 no_chroma = 1;
81 }
82
83 *p++ = pic_width_in_ctbs - tmp_w;
84 *p++ = h;
85 }
86 } else {
87 u32 tmp, prev_h, prev_w;
88
89 for (i = 0, prev_h = 0; i < num_tile_rows; i++) {
90 tmp = (i + 1) * pic_height_in_ctbs / num_tile_rows;
91 h = tmp - prev_h;
92 prev_h = tmp;
93 if (i == 0 && h == 1 && ctb_size == 16)
94 no_chroma = 1;
95 for (j = 0, prev_w = 0; j < num_tile_cols; j++) {
96 tmp = (j + 1) * pic_width_in_ctbs / num_tile_cols;
97 *p++ = tmp - prev_w;
98 *p++ = h;
99 if (j == 0 &&
100 (pps->column_width_minus1[0] + 1) == 1 &&
101 ctb_size == 16)
102 no_chroma = 1;
103 prev_w = tmp;
104 }
105 }
106 }
107 } else {
108 hantro_reg_write(vpu, &g2_num_tile_rows, 1);
109 hantro_reg_write(vpu, &g2_num_tile_cols, 1);
110
111
112 p[0] = pic_width_in_ctbs;
113 p[1] = pic_height_in_ctbs;
114 }
115
116 if (no_chroma)
117 vpu_debug(1, "%s: no chroma!\n", __func__);
118}
119
120static void set_params(struct hantro_ctx *ctx)
121{
122 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
123 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
124 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
125 const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
126 struct hantro_dev *vpu = ctx->dev;
127 u32 min_log2_cb_size, max_log2_ctb_size, min_cb_size, max_ctb_size;
128 u32 pic_width_in_min_cbs, pic_height_in_min_cbs;
129 u32 pic_width_aligned, pic_height_aligned;
130 u32 partial_ctb_x, partial_ctb_y;
131
132 hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8);
133 hantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8);
134
135 hantro_reg_write(vpu, &g2_output_8_bits, 0);
136
137 hantro_reg_write(vpu, &g2_hdr_skip_length, ctrls->hevc_hdr_skip_length);
138
139 min_log2_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
140 max_log2_ctb_size = min_log2_cb_size + sps->log2_diff_max_min_luma_coding_block_size;
141
142 hantro_reg_write(vpu, &g2_min_cb_size, min_log2_cb_size);
143 hantro_reg_write(vpu, &g2_max_cb_size, max_log2_ctb_size);
144
145 min_cb_size = 1 << min_log2_cb_size;
146 max_ctb_size = 1 << max_log2_ctb_size;
147
148 pic_width_in_min_cbs = sps->pic_width_in_luma_samples / min_cb_size;
149 pic_height_in_min_cbs = sps->pic_height_in_luma_samples / min_cb_size;
150 pic_width_aligned = ALIGN(sps->pic_width_in_luma_samples, max_ctb_size);
151 pic_height_aligned = ALIGN(sps->pic_height_in_luma_samples, max_ctb_size);
152
153 partial_ctb_x = !!(sps->pic_width_in_luma_samples != pic_width_aligned);
154 partial_ctb_y = !!(sps->pic_height_in_luma_samples != pic_height_aligned);
155
156 hantro_reg_write(vpu, &g2_partial_ctb_x, partial_ctb_x);
157 hantro_reg_write(vpu, &g2_partial_ctb_y, partial_ctb_y);
158
159 hantro_reg_write(vpu, &g2_pic_width_in_cbs, pic_width_in_min_cbs);
160 hantro_reg_write(vpu, &g2_pic_height_in_cbs, pic_height_in_min_cbs);
161
162 hantro_reg_write(vpu, &g2_pic_width_4x4,
163 (pic_width_in_min_cbs * min_cb_size) / 4);
164 hantro_reg_write(vpu, &g2_pic_height_4x4,
165 (pic_height_in_min_cbs * min_cb_size) / 4);
166
167 hantro_reg_write(vpu, &hevc_max_inter_hierdepth,
168 sps->max_transform_hierarchy_depth_inter);
169 hantro_reg_write(vpu, &hevc_max_intra_hierdepth,
170 sps->max_transform_hierarchy_depth_intra);
171 hantro_reg_write(vpu, &hevc_min_trb_size,
172 sps->log2_min_luma_transform_block_size_minus2 + 2);
173 hantro_reg_write(vpu, &hevc_max_trb_size,
174 sps->log2_min_luma_transform_block_size_minus2 + 2 +
175 sps->log2_diff_max_min_luma_transform_block_size);
176
177 hantro_reg_write(vpu, &g2_tempor_mvp_e,
178 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED) &&
179 !(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC));
180 hantro_reg_write(vpu, &g2_strong_smooth_e,
181 !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED));
182 hantro_reg_write(vpu, &g2_asym_pred_e,
183 !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED));
184 hantro_reg_write(vpu, &g2_sao_e,
185 !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET));
186 hantro_reg_write(vpu, &g2_sign_data_hide,
187 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));
188
189 if (pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED) {
190 hantro_reg_write(vpu, &g2_cu_qpd_e, 1);
191 hantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth);
192 } else {
193 hantro_reg_write(vpu, &g2_cu_qpd_e, 0);
194 hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0);
195 }
196
197 if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) {
198 hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);
199 hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);
200 } else {
201 hantro_reg_write(vpu, &g2_cb_qp_offset, 0);
202 hantro_reg_write(vpu, &g2_cr_qp_offset, 0);
203 }
204
205 hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);
206 hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
207 hantro_reg_write(vpu, &g2_slice_hdr_ext_e,
208 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT));
209 hantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits);
210 hantro_reg_write(vpu, &g2_slice_chqp_present,
211 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT));
212 hantro_reg_write(vpu, &g2_weight_bipr_idc,
213 !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));
214 hantro_reg_write(vpu, &g2_transq_bypass,
215 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));
216 hantro_reg_write(vpu, &g2_list_mod_e,
217 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));
218 hantro_reg_write(vpu, &g2_entropy_sync_e,
219 !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));
220 hantro_reg_write(vpu, &g2_cabac_init_present,
221 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
222 hantro_reg_write(vpu, &g2_idr_pic_e,
223 !!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC));
224 hantro_reg_write(vpu, &hevc_parallel_merge,
225 pps->log2_parallel_merge_level_minus2 + 2);
226 hantro_reg_write(vpu, &g2_pcm_filt_d,
227 !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED));
228 hantro_reg_write(vpu, &g2_pcm_e,
229 !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED));
230 if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
231 hantro_reg_write(vpu, &g2_max_pcm_size,
232 sps->log2_diff_max_min_pcm_luma_coding_block_size +
233 sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);
234 hantro_reg_write(vpu, &g2_min_pcm_size,
235 sps->log2_min_pcm_luma_coding_block_size_minus3 + 3);
236 hantro_reg_write(vpu, &g2_bit_depth_pcm_y,
237 sps->pcm_sample_bit_depth_luma_minus1 + 1);
238 hantro_reg_write(vpu, &g2_bit_depth_pcm_c,
239 sps->pcm_sample_bit_depth_chroma_minus1 + 1);
240 } else {
241 hantro_reg_write(vpu, &g2_max_pcm_size, 0);
242 hantro_reg_write(vpu, &g2_min_pcm_size, 0);
243 hantro_reg_write(vpu, &g2_bit_depth_pcm_y, 0);
244 hantro_reg_write(vpu, &g2_bit_depth_pcm_c, 0);
245 }
246
247 hantro_reg_write(vpu, &g2_start_code_e, 1);
248 hantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26);
249 hantro_reg_write(vpu, &g2_weight_pred_e,
250 !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));
251 hantro_reg_write(vpu, &g2_cabac_init_present,
252 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
253 hantro_reg_write(vpu, &g2_const_intra_e,
254 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));
255 hantro_reg_write(vpu, &g2_transform_skip,
256 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));
257 hantro_reg_write(vpu, &g2_out_filtering_dis,
258 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));
259 hantro_reg_write(vpu, &g2_filt_ctrl_pres,
260 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));
261 hantro_reg_write(vpu, &g2_dependent_slice,
262 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));
263 hantro_reg_write(vpu, &g2_filter_override,
264 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED));
265 hantro_reg_write(vpu, &g2_refidx0_active,
266 pps->num_ref_idx_l0_default_active_minus1 + 1);
267 hantro_reg_write(vpu, &g2_refidx1_active,
268 pps->num_ref_idx_l1_default_active_minus1 + 1);
269 hantro_reg_write(vpu, &g2_apf_threshold, 8);
270}
271
272static int find_ref_pic_index(const struct v4l2_hevc_dpb_entry *dpb, int pic_order_cnt)
273{
274 int i;
275
276 for (i = 0; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
277 if (dpb[i].pic_order_cnt[0] == pic_order_cnt)
278 return i;
279 }
280
281 return 0x0;
282}
283
284static void set_ref_pic_list(struct hantro_ctx *ctx)
285{
286 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
287 struct hantro_dev *vpu = ctx->dev;
288 const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
289 const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
290 u32 list0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};
291 u32 list1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX] = {};
292 static const struct hantro_reg ref_pic_regs0[] = {
293 hevc_rlist_f0,
294 hevc_rlist_f1,
295 hevc_rlist_f2,
296 hevc_rlist_f3,
297 hevc_rlist_f4,
298 hevc_rlist_f5,
299 hevc_rlist_f6,
300 hevc_rlist_f7,
301 hevc_rlist_f8,
302 hevc_rlist_f9,
303 hevc_rlist_f10,
304 hevc_rlist_f11,
305 hevc_rlist_f12,
306 hevc_rlist_f13,
307 hevc_rlist_f14,
308 hevc_rlist_f15,
309 };
310 static const struct hantro_reg ref_pic_regs1[] = {
311 hevc_rlist_b0,
312 hevc_rlist_b1,
313 hevc_rlist_b2,
314 hevc_rlist_b3,
315 hevc_rlist_b4,
316 hevc_rlist_b5,
317 hevc_rlist_b6,
318 hevc_rlist_b7,
319 hevc_rlist_b8,
320 hevc_rlist_b9,
321 hevc_rlist_b10,
322 hevc_rlist_b11,
323 hevc_rlist_b12,
324 hevc_rlist_b13,
325 hevc_rlist_b14,
326 hevc_rlist_b15,
327 };
328 unsigned int i, j;
329
330
331 j = 0;
332 for (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list0); i++)
333 list0[j++] = find_ref_pic_index(dpb, decode_params->poc_st_curr_before[i]);
334 for (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list0); i++)
335 list0[j++] = find_ref_pic_index(dpb, decode_params->poc_st_curr_after[i]);
336 for (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list0); i++)
337 list0[j++] = find_ref_pic_index(dpb, decode_params->poc_lt_curr[i]);
338
339
340 i = 0;
341 while (j < ARRAY_SIZE(list0))
342 list0[j++] = list0[i++];
343
344 j = 0;
345 for (i = 0; i < decode_params->num_poc_st_curr_after && j < ARRAY_SIZE(list1); i++)
346 list1[j++] = find_ref_pic_index(dpb, decode_params->poc_st_curr_after[i]);
347 for (i = 0; i < decode_params->num_poc_st_curr_before && j < ARRAY_SIZE(list1); i++)
348 list1[j++] = find_ref_pic_index(dpb, decode_params->poc_st_curr_before[i]);
349 for (i = 0; i < decode_params->num_poc_lt_curr && j < ARRAY_SIZE(list1); i++)
350 list1[j++] = find_ref_pic_index(dpb, decode_params->poc_lt_curr[i]);
351
352 i = 0;
353 while (j < ARRAY_SIZE(list1))
354 list1[j++] = list1[i++];
355
356 for (i = 0; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
357 hantro_reg_write(vpu, &ref_pic_regs0[i], list0[i]);
358 hantro_reg_write(vpu, &ref_pic_regs1[i], list1[i]);
359 }
360}
361
362static int set_ref(struct hantro_ctx *ctx)
363{
364 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
365 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
366 const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
367 const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls->decode_params;
368 const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
369 dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
370 struct hantro_dev *vpu = ctx->dev;
371 size_t cr_offset = hantro_hevc_chroma_offset(sps);
372 size_t mv_offset = hantro_hevc_motion_vectors_offset(sps);
373 u32 max_ref_frames;
374 u16 dpb_longterm_e;
375 static const struct hantro_reg cur_poc[] = {
376 hevc_cur_poc_00,
377 hevc_cur_poc_01,
378 hevc_cur_poc_02,
379 hevc_cur_poc_03,
380 hevc_cur_poc_04,
381 hevc_cur_poc_05,
382 hevc_cur_poc_06,
383 hevc_cur_poc_07,
384 hevc_cur_poc_08,
385 hevc_cur_poc_09,
386 hevc_cur_poc_10,
387 hevc_cur_poc_11,
388 hevc_cur_poc_12,
389 hevc_cur_poc_13,
390 hevc_cur_poc_14,
391 hevc_cur_poc_15,
392 };
393 unsigned int i;
394
395 max_ref_frames = decode_params->num_poc_lt_curr +
396 decode_params->num_poc_st_curr_before +
397 decode_params->num_poc_st_curr_after;
398
399
400
401
402 max_ref_frames = max_ref_frames ? max_ref_frames : 1;
403 hantro_reg_write(vpu, &g2_num_ref_frames, max_ref_frames);
404 hantro_reg_write(vpu, &g2_filter_over_slices,
405 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED));
406 hantro_reg_write(vpu, &g2_filter_over_tiles,
407 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));
408
409
410
411
412
413 for (i = 0; i < decode_params->num_active_dpb_entries && i < ARRAY_SIZE(cur_poc); i++) {
414 char poc_diff = decode_params->pic_order_cnt_val - dpb[i].pic_order_cnt[0];
415
416 hantro_reg_write(vpu, &cur_poc[i], poc_diff);
417 }
418
419 if (i < ARRAY_SIZE(cur_poc)) {
420
421
422
423
424 hantro_reg_write(vpu, &cur_poc[i], 0);
425 i++;
426 }
427
428
429 for (; i < ARRAY_SIZE(cur_poc); i++)
430 hantro_reg_write(vpu, &cur_poc[i], decode_params->pic_order_cnt_val);
431
432 set_ref_pic_list(ctx);
433
434
435 ctx->hevc_dec.ref_bufs_used = 0;
436
437
438 dpb_longterm_e = 0;
439 for (i = 0; i < decode_params->num_active_dpb_entries &&
440 i < (V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1); i++) {
441 luma_addr = hantro_hevc_get_ref_buf(ctx, dpb[i].pic_order_cnt[0]);
442 if (!luma_addr)
443 return -ENOMEM;
444
445 chroma_addr = luma_addr + cr_offset;
446 mv_addr = luma_addr + mv_offset;
447
448 if (dpb[i].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR)
449 dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i);
450
451 hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr);
452 hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr);
453 hantro_write_addr(vpu, G2_REG_DMV_REF(i), mv_addr);
454 }
455
456 luma_addr = hantro_hevc_get_ref_buf(ctx, decode_params->pic_order_cnt_val);
457 if (!luma_addr)
458 return -ENOMEM;
459
460 chroma_addr = luma_addr + cr_offset;
461 mv_addr = luma_addr + mv_offset;
462
463 hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr);
464 hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr);
465 hantro_write_addr(vpu, G2_REG_DMV_REF(i++), mv_addr);
466
467 hantro_write_addr(vpu, G2_ADDR_DST, luma_addr);
468 hantro_write_addr(vpu, G2_ADDR_DST_CHR, chroma_addr);
469 hantro_write_addr(vpu, G2_ADDR_DST_MV, mv_addr);
470
471 hantro_hevc_ref_remove_unused(ctx);
472
473 for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
474 hantro_write_addr(vpu, G2_REG_ADDR_REF(i), 0);
475 hantro_write_addr(vpu, G2_REG_CHR_REF(i), 0);
476 hantro_write_addr(vpu, G2_REG_DMV_REF(i), 0);
477 }
478
479 hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e);
480
481 return 0;
482}
483
484static void set_buffers(struct hantro_ctx *ctx)
485{
486 struct vb2_v4l2_buffer *src_buf, *dst_buf;
487 struct hantro_dev *vpu = ctx->dev;
488 const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
489 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
490 size_t cr_offset = hantro_hevc_chroma_offset(sps);
491 dma_addr_t src_dma, dst_dma;
492 u32 src_len, src_buf_len;
493
494 src_buf = hantro_get_src_buf(ctx);
495 dst_buf = hantro_get_dst_buf(ctx);
496
497
498 src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
499 src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
500 src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0);
501
502 hantro_write_addr(vpu, G2_ADDR_STR, src_dma);
503 hantro_reg_write(vpu, &g2_stream_len, src_len);
504 hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len);
505 hantro_reg_write(vpu, &g2_strm_start_offset, 0);
506 hantro_reg_write(vpu, &g2_write_mvs_e, 1);
507
508
509 dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf);
510
511 hantro_write_addr(vpu, G2_RASTER_SCAN, dst_dma);
512 hantro_write_addr(vpu, G2_RASTER_SCAN_CHR, dst_dma + cr_offset);
513 hantro_write_addr(vpu, G2_ADDR_TILE_SIZE, ctx->hevc_dec.tile_sizes.dma);
514 hantro_write_addr(vpu, G2_TILE_FILTER, ctx->hevc_dec.tile_filter.dma);
515 hantro_write_addr(vpu, G2_TILE_SAO, ctx->hevc_dec.tile_sao.dma);
516 hantro_write_addr(vpu, G2_TILE_BSD, ctx->hevc_dec.tile_bsd.dma);
517}
518
519static void hantro_g2_check_idle(struct hantro_dev *vpu)
520{
521 int i;
522
523 for (i = 0; i < 3; i++) {
524 u32 status;
525
526
527 status = vdpu_read(vpu, G2_REG_INTERRUPT);
528 if (status & G2_REG_INTERRUPT_DEC_E) {
529 dev_warn(vpu->dev, "device still running, aborting");
530 status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS;
531 vdpu_write(vpu, status, G2_REG_INTERRUPT);
532 }
533 }
534}
535
536int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx)
537{
538 struct hantro_dev *vpu = ctx->dev;
539 int ret;
540
541 hantro_g2_check_idle(vpu);
542
543
544 ret = hantro_hevc_dec_prepare_run(ctx);
545 if (ret)
546 return ret;
547
548
549 set_params(ctx);
550
551
552 ret = set_ref(ctx);
553 if (ret)
554 return ret;
555
556 set_buffers(ctx);
557 prepare_tile_info_buffer(ctx);
558
559 hantro_end_prepare_run(ctx);
560
561 hantro_reg_write(vpu, &g2_mode, HEVC_DEC_MODE);
562 hantro_reg_write(vpu, &g2_clk_gate_e, 1);
563
564
565 hantro_reg_write(vpu, &g2_out_dis, 0);
566
567
568 hantro_reg_write(vpu, &g2_ref_compress_bypass, 1);
569
570
571 hantro_reg_write(vpu, &g2_out_rs_e, 1);
572
573
574 hantro_reg_write(vpu, &g2_buswidth, BUS_WIDTH_128);
575 hantro_reg_write(vpu, &g2_max_burst, 16);
576
577
578 hantro_reg_write(vpu, &g2_strm_swap, 0xf);
579 hantro_reg_write(vpu, &g2_dirmv_swap, 0xf);
580 hantro_reg_write(vpu, &g2_compress_swap, 0xf);
581
582
583 vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT);
584
585 return 0;
586}
587
