LXR linux/drivers/staging/media/hantro/hantro_h1_jpeg

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Hantro VPU codec driver
   4 *
   5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
   6 */
   7
   8#include <asm/unaligned.h>
   9#include <media/v4l2-mem2mem.h>
  10#include "hantro_jpeg.h"
  11#include "hantro.h"
  12#include "hantro_v4l2.h"
  13#include "hantro_hw.h"
  14#include "hantro_h1_regs.h"
  15
  16#define H1_JPEG_QUANT_TABLE_COUNT 16
  17
  18static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu,
  19                                       struct hantro_ctx *ctx)
  20{
  21        struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
  22        u32 reg;
  23
  24        reg = H1_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width)
  25                | H1_REG_IN_IMG_CTRL_OVRFLR_D4(0)
  26                | H1_REG_IN_IMG_CTRL_OVRFLB_D4(0)
  27                | H1_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
  28        vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL);
  29}
  30
  31static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu,
  32                                           struct hantro_ctx *ctx,
  33                                           struct vb2_buffer *src_buf)
  34{
  35        struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
  36        dma_addr_t src[3];
  37
  38        WARN_ON(pix_fmt->num_planes > 3);
  39
  40        vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma,
  41                           H1_REG_ADDR_OUTPUT_STREAM);
  42        vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size,
  43                           H1_REG_STR_BUF_LIMIT);
  44
  45        if (pix_fmt->num_planes == 1) {
  46                src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  47                /* single plane formats we supported are all interlaced */
  48                vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
  49        } else if (pix_fmt->num_planes == 2) {
  50                src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  51                src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
  52                vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
  53                vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1);
  54        } else {
  55                src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  56                src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
  57                src[2] = vb2_dma_contig_plane_dma_addr(src_buf, 2);
  58                vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
  59                vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1);
  60                vepu_write_relaxed(vpu, src[2], H1_REG_ADDR_IN_PLANE_2);
  61        }
  62}
  63
  64static void
  65hantro_h1_jpeg_enc_set_qtable(struct hantro_dev *vpu,
  66                              unsigned char *luma_qtable,
  67                              unsigned char *chroma_qtable)
  68{
  69        u32 reg, i;
  70        __be32 *luma_qtable_p;
  71        __be32 *chroma_qtable_p;
  72
  73        luma_qtable_p = (__be32 *)luma_qtable;
  74        chroma_qtable_p = (__be32 *)chroma_qtable;
  75
  76        /*
  77         * Quantization table registers must be written in contiguous blocks.
  78         * DO NOT collapse the below two "for" loops into one.
  79         */
  80        for (i = 0; i < H1_JPEG_QUANT_TABLE_COUNT; i++) {
  81                reg = get_unaligned_be32(&luma_qtable_p[i]);
  82                vepu_write_relaxed(vpu, reg, H1_REG_JPEG_LUMA_QUAT(i));
  83        }
  84
  85        for (i = 0; i < H1_JPEG_QUANT_TABLE_COUNT; i++) {
  86                reg = get_unaligned_be32(&chroma_qtable_p[i]);
  87                vepu_write_relaxed(vpu, reg, H1_REG_JPEG_CHROMA_QUAT(i));
  88        }
  89}
  90
  91int hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx)
  92{
  93        struct hantro_dev *vpu = ctx->dev;
  94        struct vb2_v4l2_buffer *src_buf, *dst_buf;
  95        struct hantro_jpeg_ctx jpeg_ctx;
  96        u32 reg;
  97
  98        src_buf = hantro_get_src_buf(ctx);
  99        dst_buf = hantro_get_dst_buf(ctx);
 100
 101        hantro_start_prepare_run(ctx);
 102
 103        memset(&jpeg_ctx, 0, sizeof(jpeg_ctx));
 104        jpeg_ctx.buffer = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
 105        jpeg_ctx.width = ctx->dst_fmt.width;
 106        jpeg_ctx.height = ctx->dst_fmt.height;
 107        jpeg_ctx.quality = ctx->jpeg_quality;
 108        hantro_jpeg_header_assemble(&jpeg_ctx);
 109
 110        /* Switch to JPEG encoder mode before writing registers */
 111        vepu_write_relaxed(vpu, H1_REG_ENC_CTRL_ENC_MODE_JPEG,
 112                           H1_REG_ENC_CTRL);
 113
 114        hantro_h1_set_src_img_ctrl(vpu, ctx);
 115        hantro_h1_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);
 116        hantro_h1_jpeg_enc_set_qtable(vpu,
 117                                      hantro_jpeg_get_qtable(0),
 118                                      hantro_jpeg_get_qtable(1));
 119
 120        reg = H1_REG_AXI_CTRL_OUTPUT_SWAP16
 121                | H1_REG_AXI_CTRL_INPUT_SWAP16
 122                | H1_REG_AXI_CTRL_BURST_LEN(16)
 123                | H1_REG_AXI_CTRL_OUTPUT_SWAP32
 124                | H1_REG_AXI_CTRL_INPUT_SWAP32
 125                | H1_REG_AXI_CTRL_OUTPUT_SWAP8
 126                | H1_REG_AXI_CTRL_INPUT_SWAP8;
 127        /* Make sure that all registers are written at this point. */
 128        vepu_write(vpu, reg, H1_REG_AXI_CTRL);
 129
 130        reg = H1_REG_ENC_CTRL_WIDTH(MB_WIDTH(ctx->src_fmt.width))
 131                | H1_REG_ENC_CTRL_HEIGHT(MB_HEIGHT(ctx->src_fmt.height))
 132                | H1_REG_ENC_CTRL_ENC_MODE_JPEG
 133                | H1_REG_ENC_PIC_INTRA
 134                | H1_REG_ENC_CTRL_EN_BIT;
 135
 136        hantro_end_prepare_run(ctx);
 137
 138        vepu_write(vpu, reg, H1_REG_ENC_CTRL);
 139
 140        return 0;
 141}
 142
 143void hantro_jpeg_enc_done(struct hantro_ctx *ctx)
 144{
 145        struct hantro_dev *vpu = ctx->dev;
 146        u32 bytesused = vepu_read(vpu, H1_REG_STR_BUF_LIMIT) / 8;
 147        struct vb2_v4l2_buffer *dst_buf = hantro_get_dst_buf(ctx);
 148
 149        /*
 150         * TODO: Rework the JPEG encoder to eliminate the need
 151         * for a bounce buffer.
 152         */
 153        memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0) +
 154               ctx->vpu_dst_fmt->header_size,
 155               ctx->jpeg_enc.bounce_buffer.cpu, bytesused);
 156        vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
 157                              ctx->vpu_dst_fmt->header_size + bytesused);
 158}
 159