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9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gcd.h>
12#include <linux/interrupt.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of_graph.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19#include <linux/types.h>
20
21#include <media/v4l2-device.h>
22#include <media/v4l2-event.h>
23#include <media/v4l2-fwnode.h>
24#include <media/v4l2-mc.h>
25#include <media/v4l2-subdev.h>
26#include <media/videobuf2-dma-contig.h>
27
28#include <media/imx.h>
29#include "imx-media.h"
30
31#define IMX7_CSI_PAD_SINK 0
32#define IMX7_CSI_PAD_SRC 1
33#define IMX7_CSI_PADS_NUM 2
34
35
36#define BIT_SWAP16_EN BIT(31)
37#define BIT_EXT_VSYNC BIT(30)
38#define BIT_EOF_INT_EN BIT(29)
39#define BIT_PRP_IF_EN BIT(28)
40#define BIT_CCIR_MODE BIT(27)
41#define BIT_COF_INT_EN BIT(26)
42#define BIT_SF_OR_INTEN BIT(25)
43#define BIT_RF_OR_INTEN BIT(24)
44#define BIT_SFF_DMA_DONE_INTEN BIT(22)
45#define BIT_STATFF_INTEN BIT(21)
46#define BIT_FB2_DMA_DONE_INTEN BIT(20)
47#define BIT_FB1_DMA_DONE_INTEN BIT(19)
48#define BIT_RXFF_INTEN BIT(18)
49#define BIT_SOF_POL BIT(17)
50#define BIT_SOF_INTEN BIT(16)
51#define BIT_MCLKDIV(n) ((n) << 12)
52#define BIT_MCLKDIV_MASK (0xf << 12)
53#define BIT_HSYNC_POL BIT(11)
54#define BIT_CCIR_EN BIT(10)
55#define BIT_MCLKEN BIT(9)
56#define BIT_FCC BIT(8)
57#define BIT_PACK_DIR BIT(7)
58#define BIT_CLR_STATFIFO BIT(6)
59#define BIT_CLR_RXFIFO BIT(5)
60#define BIT_GCLK_MODE BIT(4)
61#define BIT_INV_DATA BIT(3)
62#define BIT_INV_PCLK BIT(2)
63#define BIT_REDGE BIT(1)
64#define BIT_PIXEL_BIT BIT(0)
65
66
67#define BIT_DMA_BURST_TYPE_RFF_INCR4 (1 << 30)
68#define BIT_DMA_BURST_TYPE_RFF_INCR8 (2 << 30)
69#define BIT_DMA_BURST_TYPE_RFF_INCR16 (3 << 30)
70#define BIT_DMA_BURST_TYPE_RFF_MASK (3 << 30)
71
72
73#define BIT_FRMCNT(n) ((n) << 16)
74#define BIT_FRMCNT_MASK (0xffff << 16)
75#define BIT_FRMCNT_RST BIT(15)
76#define BIT_DMA_REFLASH_RFF BIT(14)
77#define BIT_DMA_REFLASH_SFF BIT(13)
78#define BIT_DMA_REQ_EN_RFF BIT(12)
79#define BIT_DMA_REQ_EN_SFF BIT(11)
80#define BIT_STATFF_LEVEL(n) ((n) << 8)
81#define BIT_STATFF_LEVEL_MASK (0x7 << 8)
82#define BIT_HRESP_ERR_EN BIT(7)
83#define BIT_RXFF_LEVEL(n) ((n) << 4)
84#define BIT_RXFF_LEVEL_MASK (0x7 << 4)
85#define BIT_TWO_8BIT_SENSOR BIT(3)
86#define BIT_ZERO_PACK_EN BIT(2)
87#define BIT_ECC_INT_EN BIT(1)
88#define BIT_ECC_AUTO_EN BIT(0)
89
90
91#define BIT_ADDR_CH_ERR_INT BIT(28)
92#define BIT_FIELD0_INT BIT(27)
93#define BIT_FIELD1_INT BIT(26)
94#define BIT_SFF_OR_INT BIT(25)
95#define BIT_RFF_OR_INT BIT(24)
96#define BIT_DMA_TSF_DONE_SFF BIT(22)
97#define BIT_STATFF_INT BIT(21)
98#define BIT_DMA_TSF_DONE_FB2 BIT(20)
99#define BIT_DMA_TSF_DONE_FB1 BIT(19)
100#define BIT_RXFF_INT BIT(18)
101#define BIT_EOF_INT BIT(17)
102#define BIT_SOF_INT BIT(16)
103#define BIT_F2_INT BIT(15)
104#define BIT_F1_INT BIT(14)
105#define BIT_COF_INT BIT(13)
106#define BIT_HRESP_ERR_INT BIT(7)
107#define BIT_ECC_INT BIT(1)
108#define BIT_DRDY BIT(0)
109
110
111#define BIT_IMAGE_WIDTH(n) ((n) << 16)
112#define BIT_IMAGE_HEIGHT(n) (n)
113
114
115#define BIT_CSI_HW_ENABLE BIT(31)
116#define BIT_MIPI_DATA_FORMAT_RAW8 (0x2a << 25)
117#define BIT_MIPI_DATA_FORMAT_RAW10 (0x2b << 25)
118#define BIT_MIPI_DATA_FORMAT_RAW12 (0x2c << 25)
119#define BIT_MIPI_DATA_FORMAT_RAW14 (0x2d << 25)
120#define BIT_MIPI_DATA_FORMAT_YUV422_8B (0x1e << 25)
121#define BIT_MIPI_DATA_FORMAT_MASK (0x3f << 25)
122#define BIT_DATA_FROM_MIPI BIT(22)
123#define BIT_MIPI_YU_SWAP BIT(21)
124#define BIT_MIPI_DOUBLE_CMPNT BIT(20)
125#define BIT_BASEADDR_CHG_ERR_EN BIT(9)
126#define BIT_BASEADDR_SWITCH_SEL BIT(5)
127#define BIT_BASEADDR_SWITCH_EN BIT(4)
128#define BIT_PARALLEL24_EN BIT(3)
129#define BIT_DEINTERLACE_EN BIT(2)
130#define BIT_TVDECODER_IN_EN BIT(1)
131#define BIT_NTSC_EN BIT(0)
132
133#define CSI_MCLK_VF 1
134#define CSI_MCLK_ENC 2
135#define CSI_MCLK_RAW 4
136#define CSI_MCLK_I2C 8
137
138#define CSI_CSICR1 0x00
139#define CSI_CSICR2 0x04
140#define CSI_CSICR3 0x08
141#define CSI_STATFIFO 0x0c
142#define CSI_CSIRXFIFO 0x10
143#define CSI_CSIRXCNT 0x14
144#define CSI_CSISR 0x18
145
146#define CSI_CSIDBG 0x1c
147#define CSI_CSIDMASA_STATFIFO 0x20
148#define CSI_CSIDMATS_STATFIFO 0x24
149#define CSI_CSIDMASA_FB1 0x28
150#define CSI_CSIDMASA_FB2 0x2c
151#define CSI_CSIFBUF_PARA 0x30
152#define CSI_CSIIMAG_PARA 0x34
153
154#define CSI_CSICR18 0x48
155#define CSI_CSICR19 0x4c
156
157struct imx7_csi {
158 struct device *dev;
159 struct v4l2_subdev sd;
160 struct v4l2_async_notifier notifier;
161 struct imx_media_video_dev *vdev;
162 struct imx_media_dev *imxmd;
163 struct media_pad pad[IMX7_CSI_PADS_NUM];
164
165
166 struct mutex lock;
167
168 spinlock_t irqlock;
169
170 struct v4l2_subdev *src_sd;
171
172 struct v4l2_mbus_framefmt format_mbus[IMX7_CSI_PADS_NUM];
173 const struct imx_media_pixfmt *cc[IMX7_CSI_PADS_NUM];
174 struct v4l2_fract frame_interval[IMX7_CSI_PADS_NUM];
175
176 void __iomem *regbase;
177 int irq;
178 struct clk *mclk;
179
180
181 struct imx_media_buffer *active_vb2_buf[2];
182 struct imx_media_dma_buf underrun_buf;
183
184 int buf_num;
185 u32 frame_sequence;
186
187 bool last_eof;
188 bool is_streaming;
189 bool is_csi2;
190
191 struct completion last_eof_completion;
192};
193
194static struct imx7_csi *
195imx7_csi_notifier_to_dev(struct v4l2_async_notifier *n)
196{
197 return container_of(n, struct imx7_csi, notifier);
198}
199
200
201
202
203
204static u32 imx7_csi_reg_read(struct imx7_csi *csi, unsigned int offset)
205{
206 return readl(csi->regbase + offset);
207}
208
209static void imx7_csi_reg_write(struct imx7_csi *csi, unsigned int value,
210 unsigned int offset)
211{
212 writel(value, csi->regbase + offset);
213}
214
215static u32 imx7_csi_irq_clear(struct imx7_csi *csi)
216{
217 u32 isr;
218
219 isr = imx7_csi_reg_read(csi, CSI_CSISR);
220 imx7_csi_reg_write(csi, isr, CSI_CSISR);
221
222 return isr;
223}
224
225static void imx7_csi_init_default(struct imx7_csi *csi)
226{
227 imx7_csi_reg_write(csi, BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE |
228 BIT_HSYNC_POL | BIT_FCC | BIT_MCLKDIV(1) |
229 BIT_MCLKEN, CSI_CSICR1);
230 imx7_csi_reg_write(csi, 0, CSI_CSICR2);
231 imx7_csi_reg_write(csi, BIT_FRMCNT_RST, CSI_CSICR3);
232
233 imx7_csi_reg_write(csi, BIT_IMAGE_WIDTH(800) | BIT_IMAGE_HEIGHT(600),
234 CSI_CSIIMAG_PARA);
235
236 imx7_csi_reg_write(csi, BIT_DMA_REFLASH_RFF, CSI_CSICR3);
237}
238
239static void imx7_csi_hw_enable_irq(struct imx7_csi *csi)
240{
241 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
242
243 cr1 |= BIT_RFF_OR_INT;
244 cr1 |= BIT_FB1_DMA_DONE_INTEN;
245 cr1 |= BIT_FB2_DMA_DONE_INTEN;
246
247 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
248}
249
250static void imx7_csi_hw_disable_irq(struct imx7_csi *csi)
251{
252 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1);
253
254 cr1 &= ~BIT_RFF_OR_INT;
255 cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
256 cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
257
258 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
259}
260
261static void imx7_csi_hw_enable(struct imx7_csi *csi)
262{
263 u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
264
265 cr |= BIT_CSI_HW_ENABLE;
266
267 imx7_csi_reg_write(csi, cr, CSI_CSICR18);
268}
269
270static void imx7_csi_hw_disable(struct imx7_csi *csi)
271{
272 u32 cr = imx7_csi_reg_read(csi, CSI_CSICR18);
273
274 cr &= ~BIT_CSI_HW_ENABLE;
275
276 imx7_csi_reg_write(csi, cr, CSI_CSICR18);
277}
278
279static void imx7_csi_dma_reflash(struct imx7_csi *csi)
280{
281 u32 cr3;
282
283 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
284 cr3 |= BIT_DMA_REFLASH_RFF;
285 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
286}
287
288static void imx7_csi_rx_fifo_clear(struct imx7_csi *csi)
289{
290 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1) & ~BIT_FCC;
291
292 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
293 imx7_csi_reg_write(csi, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);
294 imx7_csi_reg_write(csi, cr1 | BIT_FCC, CSI_CSICR1);
295}
296
297static void imx7_csi_dmareq_rff_enable(struct imx7_csi *csi)
298{
299 u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
300
301 cr3 |= BIT_DMA_REQ_EN_RFF;
302 cr3 |= BIT_HRESP_ERR_EN;
303 cr3 &= ~BIT_RXFF_LEVEL_MASK;
304 cr3 |= BIT_RXFF_LEVEL(2);
305
306 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
307}
308
309static void imx7_csi_dmareq_rff_disable(struct imx7_csi *csi)
310{
311 u32 cr3 = imx7_csi_reg_read(csi, CSI_CSICR3);
312
313 cr3 &= ~BIT_DMA_REQ_EN_RFF;
314 cr3 &= ~BIT_HRESP_ERR_EN;
315 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
316}
317
318static void imx7_csi_update_buf(struct imx7_csi *csi, dma_addr_t phys,
319 int buf_num)
320{
321 if (buf_num == 1)
322 imx7_csi_reg_write(csi, phys, CSI_CSIDMASA_FB2);
323 else
324 imx7_csi_reg_write(csi, phys, CSI_CSIDMASA_FB1);
325}
326
327static void imx7_csi_setup_vb2_buf(struct imx7_csi *csi)
328{
329 struct imx_media_video_dev *vdev = csi->vdev;
330 struct imx_media_buffer *buf;
331 struct vb2_buffer *vb2_buf;
332 dma_addr_t phys[2];
333 int i;
334
335 for (i = 0; i < 2; i++) {
336 buf = imx_media_capture_device_next_buf(vdev);
337 if (buf) {
338 csi->active_vb2_buf[i] = buf;
339 vb2_buf = &buf->vbuf.vb2_buf;
340 phys[i] = vb2_dma_contig_plane_dma_addr(vb2_buf, 0);
341 } else {
342 csi->active_vb2_buf[i] = NULL;
343 phys[i] = csi->underrun_buf.phys;
344 }
345
346 imx7_csi_update_buf(csi, phys[i], i);
347 }
348}
349
350static void imx7_csi_dma_unsetup_vb2_buf(struct imx7_csi *csi,
351 enum vb2_buffer_state return_status)
352{
353 struct imx_media_buffer *buf;
354 int i;
355
356
357 for (i = 0; i < 2; i++) {
358 buf = csi->active_vb2_buf[i];
359 if (buf) {
360 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
361
362 vb->timestamp = ktime_get_ns();
363 vb2_buffer_done(vb, return_status);
364 csi->active_vb2_buf[i] = NULL;
365 }
366 }
367}
368
369static int imx7_csi_dma_setup(struct imx7_csi *csi)
370{
371 struct imx_media_video_dev *vdev = csi->vdev;
372 int ret;
373
374 ret = imx_media_alloc_dma_buf(csi->dev, &csi->underrun_buf,
375 vdev->fmt.sizeimage);
376 if (ret < 0) {
377 v4l2_warn(&csi->sd, "consider increasing the CMA area\n");
378 return ret;
379 }
380
381 csi->frame_sequence = 0;
382 csi->last_eof = false;
383 init_completion(&csi->last_eof_completion);
384
385 imx7_csi_setup_vb2_buf(csi);
386
387 return 0;
388}
389
390static void imx7_csi_dma_cleanup(struct imx7_csi *csi,
391 enum vb2_buffer_state return_status)
392{
393 imx7_csi_dma_unsetup_vb2_buf(csi, return_status);
394 imx_media_free_dma_buf(csi->dev, &csi->underrun_buf);
395}
396
397static void imx7_csi_dma_stop(struct imx7_csi *csi)
398{
399 unsigned long timeout_jiffies;
400 unsigned long flags;
401 int ret;
402
403
404 spin_lock_irqsave(&csi->irqlock, flags);
405 csi->last_eof = true;
406 spin_unlock_irqrestore(&csi->irqlock, flags);
407
408
409
410
411 timeout_jiffies = msecs_to_jiffies(IMX_MEDIA_EOF_TIMEOUT);
412 ret = wait_for_completion_timeout(&csi->last_eof_completion,
413 timeout_jiffies);
414 if (ret == 0)
415 v4l2_warn(&csi->sd, "wait last EOF timeout\n");
416
417 imx7_csi_hw_disable_irq(csi);
418}
419
420static void imx7_csi_configure(struct imx7_csi *csi)
421{
422 struct imx_media_video_dev *vdev = csi->vdev;
423 struct v4l2_pix_format *out_pix = &vdev->fmt;
424 int width = out_pix->width;
425 u32 stride = 0;
426 u32 cr3 = BIT_FRMCNT_RST;
427 u32 cr1, cr18;
428
429 cr18 = imx7_csi_reg_read(csi, CSI_CSICR18);
430
431 cr18 &= ~(BIT_CSI_HW_ENABLE | BIT_MIPI_DATA_FORMAT_MASK |
432 BIT_DATA_FROM_MIPI | BIT_BASEADDR_CHG_ERR_EN |
433 BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
434 BIT_DEINTERLACE_EN);
435
436 if (out_pix->field == V4L2_FIELD_INTERLACED) {
437 cr18 |= BIT_DEINTERLACE_EN;
438 stride = out_pix->width;
439 }
440
441 if (!csi->is_csi2) {
442 cr1 = BIT_SOF_POL | BIT_REDGE | BIT_GCLK_MODE | BIT_HSYNC_POL
443 | BIT_FCC | BIT_MCLKDIV(1) | BIT_MCLKEN;
444
445 cr18 |= BIT_BASEADDR_SWITCH_EN | BIT_BASEADDR_SWITCH_SEL |
446 BIT_BASEADDR_CHG_ERR_EN;
447
448 if (out_pix->pixelformat == V4L2_PIX_FMT_UYVY ||
449 out_pix->pixelformat == V4L2_PIX_FMT_YUYV)
450 width *= 2;
451 } else {
452 cr1 = BIT_SOF_POL | BIT_REDGE | BIT_HSYNC_POL | BIT_FCC
453 | BIT_MCLKDIV(1) | BIT_MCLKEN;
454
455 cr18 |= BIT_DATA_FROM_MIPI;
456
457 switch (csi->format_mbus[IMX7_CSI_PAD_SINK].code) {
458 case MEDIA_BUS_FMT_Y8_1X8:
459 case MEDIA_BUS_FMT_SBGGR8_1X8:
460 case MEDIA_BUS_FMT_SGBRG8_1X8:
461 case MEDIA_BUS_FMT_SGRBG8_1X8:
462 case MEDIA_BUS_FMT_SRGGB8_1X8:
463 cr18 |= BIT_MIPI_DATA_FORMAT_RAW8;
464 break;
465 case MEDIA_BUS_FMT_Y10_1X10:
466 case MEDIA_BUS_FMT_SBGGR10_1X10:
467 case MEDIA_BUS_FMT_SGBRG10_1X10:
468 case MEDIA_BUS_FMT_SGRBG10_1X10:
469 case MEDIA_BUS_FMT_SRGGB10_1X10:
470 cr3 |= BIT_TWO_8BIT_SENSOR;
471 cr18 |= BIT_MIPI_DATA_FORMAT_RAW10;
472 break;
473 case MEDIA_BUS_FMT_Y12_1X12:
474 case MEDIA_BUS_FMT_SBGGR12_1X12:
475 case MEDIA_BUS_FMT_SGBRG12_1X12:
476 case MEDIA_BUS_FMT_SGRBG12_1X12:
477 case MEDIA_BUS_FMT_SRGGB12_1X12:
478 cr3 |= BIT_TWO_8BIT_SENSOR;
479 cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
480 break;
481 case MEDIA_BUS_FMT_Y14_1X14:
482 case MEDIA_BUS_FMT_SBGGR14_1X14:
483 case MEDIA_BUS_FMT_SGBRG14_1X14:
484 case MEDIA_BUS_FMT_SGRBG14_1X14:
485 case MEDIA_BUS_FMT_SRGGB14_1X14:
486 cr3 |= BIT_TWO_8BIT_SENSOR;
487 cr18 |= BIT_MIPI_DATA_FORMAT_RAW14;
488 break;
489
490
491
492
493 case MEDIA_BUS_FMT_UYVY8_2X8:
494 case MEDIA_BUS_FMT_UYVY8_1X16:
495 case MEDIA_BUS_FMT_YUYV8_2X8:
496 case MEDIA_BUS_FMT_YUYV8_1X16:
497 cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;
498 break;
499 }
500 }
501
502 imx7_csi_reg_write(csi, cr1, CSI_CSICR1);
503 imx7_csi_reg_write(csi, BIT_DMA_BURST_TYPE_RFF_INCR16, CSI_CSICR2);
504 imx7_csi_reg_write(csi, cr3, CSI_CSICR3);
505 imx7_csi_reg_write(csi, cr18, CSI_CSICR18);
506
507 imx7_csi_reg_write(csi, (width * out_pix->height) >> 2, CSI_CSIRXCNT);
508 imx7_csi_reg_write(csi, BIT_IMAGE_WIDTH(width) |
509 BIT_IMAGE_HEIGHT(out_pix->height),
510 CSI_CSIIMAG_PARA);
511 imx7_csi_reg_write(csi, stride, CSI_CSIFBUF_PARA);
512}
513
514static int imx7_csi_init(struct imx7_csi *csi)
515{
516 int ret;
517
518 ret = clk_prepare_enable(csi->mclk);
519 if (ret < 0)
520 return ret;
521
522 imx7_csi_configure(csi);
523
524 ret = imx7_csi_dma_setup(csi);
525 if (ret < 0)
526 return ret;
527
528 return 0;
529}
530
531static void imx7_csi_deinit(struct imx7_csi *csi,
532 enum vb2_buffer_state return_status)
533{
534 imx7_csi_dma_cleanup(csi, return_status);
535 imx7_csi_init_default(csi);
536 imx7_csi_dmareq_rff_disable(csi);
537 clk_disable_unprepare(csi->mclk);
538}
539
540static void imx7_csi_enable(struct imx7_csi *csi)
541{
542
543 imx7_csi_rx_fifo_clear(csi);
544 imx7_csi_dma_reflash(csi);
545
546 usleep_range(2000, 3000);
547
548
549 imx7_csi_irq_clear(csi);
550 imx7_csi_hw_enable_irq(csi);
551
552
553 imx7_csi_dmareq_rff_enable(csi);
554 imx7_csi_hw_enable(csi);
555}
556
557static void imx7_csi_disable(struct imx7_csi *csi)
558{
559 imx7_csi_dma_stop(csi);
560
561 imx7_csi_dmareq_rff_disable(csi);
562
563 imx7_csi_hw_disable_irq(csi);
564
565 imx7_csi_hw_disable(csi);
566}
567
568
569
570
571
572static void imx7_csi_error_recovery(struct imx7_csi *csi)
573{
574 imx7_csi_hw_disable(csi);
575
576 imx7_csi_rx_fifo_clear(csi);
577
578 imx7_csi_dma_reflash(csi);
579
580 imx7_csi_hw_enable(csi);
581}
582
583static void imx7_csi_vb2_buf_done(struct imx7_csi *csi)
584{
585 struct imx_media_video_dev *vdev = csi->vdev;
586 struct imx_media_buffer *done, *next;
587 struct vb2_buffer *vb;
588 dma_addr_t phys;
589
590 done = csi->active_vb2_buf[csi->buf_num];
591 if (done) {
592 done->vbuf.field = vdev->fmt.field;
593 done->vbuf.sequence = csi->frame_sequence;
594 vb = &done->vbuf.vb2_buf;
595 vb->timestamp = ktime_get_ns();
596 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
597 }
598 csi->frame_sequence++;
599
600
601 next = imx_media_capture_device_next_buf(vdev);
602 if (next) {
603 phys = vb2_dma_contig_plane_dma_addr(&next->vbuf.vb2_buf, 0);
604 csi->active_vb2_buf[csi->buf_num] = next;
605 } else {
606 phys = csi->underrun_buf.phys;
607 csi->active_vb2_buf[csi->buf_num] = NULL;
608 }
609
610 imx7_csi_update_buf(csi, phys, csi->buf_num);
611}
612
613static irqreturn_t imx7_csi_irq_handler(int irq, void *data)
614{
615 struct imx7_csi *csi = data;
616 u32 status;
617
618 spin_lock(&csi->irqlock);
619
620 status = imx7_csi_irq_clear(csi);
621
622 if (status & BIT_RFF_OR_INT) {
623 dev_warn(csi->dev, "Rx fifo overflow\n");
624 imx7_csi_error_recovery(csi);
625 }
626
627 if (status & BIT_HRESP_ERR_INT) {
628 dev_warn(csi->dev, "Hresponse error detected\n");
629 imx7_csi_error_recovery(csi);
630 }
631
632 if (status & BIT_ADDR_CH_ERR_INT) {
633 imx7_csi_hw_disable(csi);
634
635 imx7_csi_dma_reflash(csi);
636
637 imx7_csi_hw_enable(csi);
638 }
639
640 if ((status & BIT_DMA_TSF_DONE_FB1) &&
641 (status & BIT_DMA_TSF_DONE_FB2)) {
642
643
644
645
646
647
648
649
650 } else if (status & BIT_DMA_TSF_DONE_FB1) {
651 csi->buf_num = 0;
652 } else if (status & BIT_DMA_TSF_DONE_FB2) {
653 csi->buf_num = 1;
654 }
655
656 if ((status & BIT_DMA_TSF_DONE_FB1) ||
657 (status & BIT_DMA_TSF_DONE_FB2)) {
658 imx7_csi_vb2_buf_done(csi);
659
660 if (csi->last_eof) {
661 complete(&csi->last_eof_completion);
662 csi->last_eof = false;
663 }
664 }
665
666 spin_unlock(&csi->irqlock);
667
668 return IRQ_HANDLED;
669}
670
671
672
673
674
675static int imx7_csi_s_stream(struct v4l2_subdev *sd, int enable)
676{
677 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
678 int ret = 0;
679
680 mutex_lock(&csi->lock);
681
682 if (!csi->src_sd) {
683 ret = -EPIPE;
684 goto out_unlock;
685 }
686
687 if (csi->is_streaming == !!enable)
688 goto out_unlock;
689
690 if (enable) {
691 ret = imx7_csi_init(csi);
692 if (ret < 0)
693 goto out_unlock;
694
695 ret = v4l2_subdev_call(csi->src_sd, video, s_stream, 1);
696 if (ret < 0) {
697 imx7_csi_deinit(csi, VB2_BUF_STATE_QUEUED);
698 goto out_unlock;
699 }
700
701 imx7_csi_enable(csi);
702 } else {
703 imx7_csi_disable(csi);
704
705 v4l2_subdev_call(csi->src_sd, video, s_stream, 0);
706
707 imx7_csi_deinit(csi, VB2_BUF_STATE_ERROR);
708 }
709
710 csi->is_streaming = !!enable;
711
712out_unlock:
713 mutex_unlock(&csi->lock);
714
715 return ret;
716}
717
718static int imx7_csi_init_cfg(struct v4l2_subdev *sd,
719 struct v4l2_subdev_state *sd_state)
720{
721 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
722 struct v4l2_mbus_framefmt *mf;
723 int ret;
724 int i;
725
726 for (i = 0; i < IMX7_CSI_PADS_NUM; i++) {
727 mf = v4l2_subdev_get_try_format(sd, sd_state, i);
728
729 ret = imx_media_init_mbus_fmt(mf, 800, 600, 0, V4L2_FIELD_NONE,
730 &csi->cc[i]);
731 if (ret < 0)
732 return ret;
733 }
734
735 return 0;
736}
737
738static struct v4l2_mbus_framefmt *
739imx7_csi_get_format(struct imx7_csi *csi,
740 struct v4l2_subdev_state *sd_state,
741 unsigned int pad,
742 enum v4l2_subdev_format_whence which)
743{
744 if (which == V4L2_SUBDEV_FORMAT_TRY)
745 return v4l2_subdev_get_try_format(&csi->sd, sd_state, pad);
746
747 return &csi->format_mbus[pad];
748}
749
750static int imx7_csi_enum_mbus_code(struct v4l2_subdev *sd,
751 struct v4l2_subdev_state *sd_state,
752 struct v4l2_subdev_mbus_code_enum *code)
753{
754 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
755 struct v4l2_mbus_framefmt *in_fmt;
756 int ret = 0;
757
758 mutex_lock(&csi->lock);
759
760 in_fmt = imx7_csi_get_format(csi, sd_state, IMX7_CSI_PAD_SINK,
761 code->which);
762
763 switch (code->pad) {
764 case IMX7_CSI_PAD_SINK:
765 ret = imx_media_enum_mbus_formats(&code->code, code->index,
766 PIXFMT_SEL_ANY);
767 break;
768 case IMX7_CSI_PAD_SRC:
769 if (code->index != 0) {
770 ret = -EINVAL;
771 goto out_unlock;
772 }
773
774 code->code = in_fmt->code;
775 break;
776 default:
777 ret = -EINVAL;
778 }
779
780out_unlock:
781 mutex_unlock(&csi->lock);
782
783 return ret;
784}
785
786static int imx7_csi_get_fmt(struct v4l2_subdev *sd,
787 struct v4l2_subdev_state *sd_state,
788 struct v4l2_subdev_format *sdformat)
789{
790 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
791 struct v4l2_mbus_framefmt *fmt;
792 int ret = 0;
793
794 mutex_lock(&csi->lock);
795
796 fmt = imx7_csi_get_format(csi, sd_state, sdformat->pad,
797 sdformat->which);
798 if (!fmt) {
799 ret = -EINVAL;
800 goto out_unlock;
801 }
802
803 sdformat->format = *fmt;
804
805out_unlock:
806 mutex_unlock(&csi->lock);
807
808 return ret;
809}
810
811static int imx7_csi_try_fmt(struct imx7_csi *csi,
812 struct v4l2_subdev_state *sd_state,
813 struct v4l2_subdev_format *sdformat,
814 const struct imx_media_pixfmt **cc)
815{
816 const struct imx_media_pixfmt *in_cc;
817 struct v4l2_mbus_framefmt *in_fmt;
818 u32 code;
819
820 in_fmt = imx7_csi_get_format(csi, sd_state, IMX7_CSI_PAD_SINK,
821 sdformat->which);
822 if (!in_fmt)
823 return -EINVAL;
824
825 switch (sdformat->pad) {
826 case IMX7_CSI_PAD_SRC:
827 in_cc = imx_media_find_mbus_format(in_fmt->code,
828 PIXFMT_SEL_ANY);
829
830 sdformat->format.width = in_fmt->width;
831 sdformat->format.height = in_fmt->height;
832 sdformat->format.code = in_fmt->code;
833 sdformat->format.field = in_fmt->field;
834 *cc = in_cc;
835
836 sdformat->format.colorspace = in_fmt->colorspace;
837 sdformat->format.xfer_func = in_fmt->xfer_func;
838 sdformat->format.quantization = in_fmt->quantization;
839 sdformat->format.ycbcr_enc = in_fmt->ycbcr_enc;
840 break;
841 case IMX7_CSI_PAD_SINK:
842 *cc = imx_media_find_mbus_format(sdformat->format.code,
843 PIXFMT_SEL_ANY);
844 if (!*cc) {
845 imx_media_enum_mbus_formats(&code, 0,
846 PIXFMT_SEL_YUV_RGB);
847 *cc = imx_media_find_mbus_format(code,
848 PIXFMT_SEL_YUV_RGB);
849 sdformat->format.code = (*cc)->codes[0];
850 }
851
852 if (sdformat->format.field != V4L2_FIELD_INTERLACED)
853 sdformat->format.field = V4L2_FIELD_NONE;
854 break;
855 default:
856 return -EINVAL;
857 }
858
859 imx_media_try_colorimetry(&sdformat->format, false);
860
861 return 0;
862}
863
864static int imx7_csi_set_fmt(struct v4l2_subdev *sd,
865 struct v4l2_subdev_state *sd_state,
866 struct v4l2_subdev_format *sdformat)
867{
868 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
869 const struct imx_media_pixfmt *outcc;
870 struct v4l2_mbus_framefmt *outfmt;
871 const struct imx_media_pixfmt *cc;
872 struct v4l2_mbus_framefmt *fmt;
873 struct v4l2_subdev_format format;
874 int ret = 0;
875
876 if (sdformat->pad >= IMX7_CSI_PADS_NUM)
877 return -EINVAL;
878
879 mutex_lock(&csi->lock);
880
881 if (csi->is_streaming) {
882 ret = -EBUSY;
883 goto out_unlock;
884 }
885
886 ret = imx7_csi_try_fmt(csi, sd_state, sdformat, &cc);
887 if (ret < 0)
888 goto out_unlock;
889
890 fmt = imx7_csi_get_format(csi, sd_state, sdformat->pad,
891 sdformat->which);
892 if (!fmt) {
893 ret = -EINVAL;
894 goto out_unlock;
895 }
896
897 *fmt = sdformat->format;
898
899 if (sdformat->pad == IMX7_CSI_PAD_SINK) {
900
901 format.pad = IMX7_CSI_PAD_SRC;
902 format.which = sdformat->which;
903 format.format = sdformat->format;
904 if (imx7_csi_try_fmt(csi, sd_state, &format, &outcc)) {
905 ret = -EINVAL;
906 goto out_unlock;
907 }
908 outfmt = imx7_csi_get_format(csi, sd_state, IMX7_CSI_PAD_SRC,
909 sdformat->which);
910 *outfmt = format.format;
911
912 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
913 csi->cc[IMX7_CSI_PAD_SRC] = outcc;
914 }
915
916 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
917 csi->cc[sdformat->pad] = cc;
918
919out_unlock:
920 mutex_unlock(&csi->lock);
921
922 return ret;
923}
924
925static int imx7_csi_pad_link_validate(struct v4l2_subdev *sd,
926 struct media_link *link,
927 struct v4l2_subdev_format *source_fmt,
928 struct v4l2_subdev_format *sink_fmt)
929{
930 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
931 struct imx_media_video_dev *vdev = csi->vdev;
932 const struct v4l2_pix_format *out_pix = &vdev->fmt;
933 struct media_pad *pad;
934 int ret;
935
936 if (!csi->src_sd)
937 return -EPIPE;
938
939
940
941
942
943 ret = v4l2_subdev_link_validate_default(sd, link, source_fmt, sink_fmt);
944 if (ret)
945 return ret;
946
947 switch (csi->src_sd->entity.function) {
948 case MEDIA_ENT_F_VID_IF_BRIDGE:
949
950 csi->is_csi2 = true;
951 break;
952
953 case MEDIA_ENT_F_VID_MUX:
954
955 pad = imx_media_pipeline_pad(&csi->src_sd->entity, 0, 0, true);
956 if (!pad)
957 return -ENODEV;
958
959 csi->is_csi2 = pad->entity->function == MEDIA_ENT_F_VID_IF_BRIDGE;
960 break;
961
962 default:
963
964
965
966
967 csi->is_csi2 = false;
968 break;
969 }
970
971
972 switch (out_pix->pixelformat) {
973 case V4L2_PIX_FMT_UYVY:
974 case V4L2_PIX_FMT_YUYV:
975 case V4L2_PIX_FMT_GREY:
976 case V4L2_PIX_FMT_Y10:
977 case V4L2_PIX_FMT_Y12:
978 case V4L2_PIX_FMT_SBGGR8:
979 case V4L2_PIX_FMT_SGBRG8:
980 case V4L2_PIX_FMT_SGRBG8:
981 case V4L2_PIX_FMT_SRGGB8:
982 case V4L2_PIX_FMT_SBGGR16:
983 case V4L2_PIX_FMT_SGBRG16:
984 case V4L2_PIX_FMT_SGRBG16:
985 case V4L2_PIX_FMT_SRGGB16:
986 break;
987
988 default:
989 dev_dbg(csi->dev, "Invalid capture pixel format 0x%08x\n",
990 out_pix->pixelformat);
991 return -EINVAL;
992 }
993
994 return 0;
995}
996
997static int imx7_csi_registered(struct v4l2_subdev *sd)
998{
999 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1000 int ret;
1001 int i;
1002
1003 for (i = 0; i < IMX7_CSI_PADS_NUM; i++) {
1004
1005 ret = imx_media_init_mbus_fmt(&csi->format_mbus[i],
1006 800, 600, 0, V4L2_FIELD_NONE,
1007 &csi->cc[i]);
1008 if (ret < 0)
1009 return ret;
1010
1011
1012 csi->frame_interval[i].numerator = 1;
1013 csi->frame_interval[i].denominator = 30;
1014 }
1015
1016 csi->vdev = imx_media_capture_device_init(csi->sd.dev, &csi->sd,
1017 IMX7_CSI_PAD_SRC, false);
1018 if (IS_ERR(csi->vdev))
1019 return PTR_ERR(csi->vdev);
1020
1021 ret = imx_media_capture_device_register(csi->vdev,
1022 MEDIA_LNK_FL_IMMUTABLE);
1023 if (ret)
1024 imx_media_capture_device_remove(csi->vdev);
1025
1026 return ret;
1027}
1028
1029static void imx7_csi_unregistered(struct v4l2_subdev *sd)
1030{
1031 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1032
1033 imx_media_capture_device_unregister(csi->vdev);
1034 imx_media_capture_device_remove(csi->vdev);
1035}
1036
1037static const struct v4l2_subdev_video_ops imx7_csi_video_ops = {
1038 .s_stream = imx7_csi_s_stream,
1039};
1040
1041static const struct v4l2_subdev_pad_ops imx7_csi_pad_ops = {
1042 .init_cfg = imx7_csi_init_cfg,
1043 .enum_mbus_code = imx7_csi_enum_mbus_code,
1044 .get_fmt = imx7_csi_get_fmt,
1045 .set_fmt = imx7_csi_set_fmt,
1046 .link_validate = imx7_csi_pad_link_validate,
1047};
1048
1049static const struct v4l2_subdev_ops imx7_csi_subdev_ops = {
1050 .video = &imx7_csi_video_ops,
1051 .pad = &imx7_csi_pad_ops,
1052};
1053
1054static const struct v4l2_subdev_internal_ops imx7_csi_internal_ops = {
1055 .registered = imx7_csi_registered,
1056 .unregistered = imx7_csi_unregistered,
1057};
1058
1059
1060
1061
1062
1063static const struct media_entity_operations imx7_csi_entity_ops = {
1064 .link_validate = v4l2_subdev_link_validate,
1065 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1066};
1067
1068
1069
1070
1071
1072static int imx7_csi_notify_bound(struct v4l2_async_notifier *notifier,
1073 struct v4l2_subdev *sd,
1074 struct v4l2_async_subdev *asd)
1075{
1076 struct imx7_csi *csi = imx7_csi_notifier_to_dev(notifier);
1077 struct media_pad *sink = &csi->sd.entity.pads[IMX7_CSI_PAD_SINK];
1078
1079
1080
1081
1082
1083 if (sd->entity.function == MEDIA_ENT_F_VID_MUX)
1084 sd->grp_id = IMX_MEDIA_GRP_ID_CSI_MUX;
1085
1086 csi->src_sd = sd;
1087
1088 return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED |
1089 MEDIA_LNK_FL_IMMUTABLE);
1090}
1091
1092static const struct v4l2_async_notifier_operations imx7_csi_notify_ops = {
1093 .bound = imx7_csi_notify_bound,
1094};
1095
1096static int imx7_csi_async_register(struct imx7_csi *csi)
1097{
1098 struct v4l2_async_subdev *asd;
1099 struct fwnode_handle *ep;
1100 int ret;
1101
1102 v4l2_async_notifier_init(&csi->notifier);
1103
1104 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0,
1105 FWNODE_GRAPH_ENDPOINT_NEXT);
1106 if (ep) {
1107 asd = v4l2_async_notifier_add_fwnode_remote_subdev(
1108 &csi->notifier, ep, struct v4l2_async_subdev);
1109
1110 fwnode_handle_put(ep);
1111
1112 if (IS_ERR(asd)) {
1113 ret = PTR_ERR(asd);
1114
1115 if (ret != -EEXIST)
1116 return ret;
1117 }
1118 }
1119
1120 csi->notifier.ops = &imx7_csi_notify_ops;
1121
1122 ret = v4l2_async_subdev_notifier_register(&csi->sd, &csi->notifier);
1123 if (ret)
1124 return ret;
1125
1126 return v4l2_async_register_subdev(&csi->sd);
1127}
1128
1129static int imx7_csi_probe(struct platform_device *pdev)
1130{
1131 struct device *dev = &pdev->dev;
1132 struct device_node *node = dev->of_node;
1133 struct imx_media_dev *imxmd;
1134 struct imx7_csi *csi;
1135 int i, ret;
1136
1137 csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL);
1138 if (!csi)
1139 return -ENOMEM;
1140
1141 csi->dev = dev;
1142
1143 csi->mclk = devm_clk_get(&pdev->dev, "mclk");
1144 if (IS_ERR(csi->mclk)) {
1145 ret = PTR_ERR(csi->mclk);
1146 dev_err(dev, "Failed to get mclk: %d", ret);
1147 return ret;
1148 }
1149
1150 csi->irq = platform_get_irq(pdev, 0);
1151 if (csi->irq < 0)
1152 return csi->irq;
1153
1154 csi->regbase = devm_platform_ioremap_resource(pdev, 0);
1155 if (IS_ERR(csi->regbase))
1156 return PTR_ERR(csi->regbase);
1157
1158 spin_lock_init(&csi->irqlock);
1159 mutex_init(&csi->lock);
1160
1161
1162 ret = devm_request_irq(dev, csi->irq, imx7_csi_irq_handler, 0, "csi",
1163 (void *)csi);
1164 if (ret < 0) {
1165 dev_err(dev, "Request CSI IRQ failed.\n");
1166 goto destroy_mutex;
1167 }
1168
1169
1170 imxmd = imx_media_dev_init(dev, NULL);
1171 if (IS_ERR(imxmd)) {
1172 ret = PTR_ERR(imxmd);
1173 goto destroy_mutex;
1174 }
1175 platform_set_drvdata(pdev, &csi->sd);
1176
1177 ret = imx_media_of_add_csi(imxmd, node);
1178 if (ret < 0 && ret != -ENODEV && ret != -EEXIST)
1179 goto cleanup;
1180
1181 ret = imx_media_dev_notifier_register(imxmd, NULL);
1182 if (ret < 0)
1183 goto cleanup;
1184
1185 csi->imxmd = imxmd;
1186 v4l2_subdev_init(&csi->sd, &imx7_csi_subdev_ops);
1187 v4l2_set_subdevdata(&csi->sd, csi);
1188 csi->sd.internal_ops = &imx7_csi_internal_ops;
1189 csi->sd.entity.ops = &imx7_csi_entity_ops;
1190 csi->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1191 csi->sd.dev = &pdev->dev;
1192 csi->sd.owner = THIS_MODULE;
1193 csi->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1194 csi->sd.grp_id = IMX_MEDIA_GRP_ID_CSI;
1195 snprintf(csi->sd.name, sizeof(csi->sd.name), "csi");
1196
1197 for (i = 0; i < IMX7_CSI_PADS_NUM; i++)
1198 csi->pad[i].flags = (i == IMX7_CSI_PAD_SINK) ?
1199 MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
1200
1201 ret = media_entity_pads_init(&csi->sd.entity, IMX7_CSI_PADS_NUM,
1202 csi->pad);
1203 if (ret < 0)
1204 goto cleanup;
1205
1206 ret = imx7_csi_async_register(csi);
1207 if (ret)
1208 goto subdev_notifier_cleanup;
1209
1210 return 0;
1211
1212subdev_notifier_cleanup:
1213 v4l2_async_notifier_unregister(&csi->notifier);
1214 v4l2_async_notifier_cleanup(&csi->notifier);
1215
1216cleanup:
1217 v4l2_async_notifier_unregister(&imxmd->notifier);
1218 v4l2_async_notifier_cleanup(&imxmd->notifier);
1219 v4l2_device_unregister(&imxmd->v4l2_dev);
1220 media_device_unregister(&imxmd->md);
1221 media_device_cleanup(&imxmd->md);
1222
1223destroy_mutex:
1224 mutex_destroy(&csi->lock);
1225
1226 return ret;
1227}
1228
1229static int imx7_csi_remove(struct platform_device *pdev)
1230{
1231 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1232 struct imx7_csi *csi = v4l2_get_subdevdata(sd);
1233 struct imx_media_dev *imxmd = csi->imxmd;
1234
1235 v4l2_async_notifier_unregister(&imxmd->notifier);
1236 v4l2_async_notifier_cleanup(&imxmd->notifier);
1237
1238 media_device_unregister(&imxmd->md);
1239 v4l2_device_unregister(&imxmd->v4l2_dev);
1240 media_device_cleanup(&imxmd->md);
1241
1242 v4l2_async_notifier_unregister(&csi->notifier);
1243 v4l2_async_notifier_cleanup(&csi->notifier);
1244 v4l2_async_unregister_subdev(sd);
1245
1246 mutex_destroy(&csi->lock);
1247
1248 return 0;
1249}
1250
1251static const struct of_device_id imx7_csi_of_match[] = {
1252 { .compatible = "fsl,imx7-csi" },
1253 { .compatible = "fsl,imx6ul-csi" },
1254 { },
1255};
1256MODULE_DEVICE_TABLE(of, imx7_csi_of_match);
1257
1258static struct platform_driver imx7_csi_driver = {
1259 .probe = imx7_csi_probe,
1260 .remove = imx7_csi_remove,
1261 .driver = {
1262 .of_match_table = imx7_csi_of_match,
1263 .name = "imx7-csi",
1264 },
1265};
1266module_platform_driver(imx7_csi_driver);
1267
1268MODULE_DESCRIPTION("i.MX7 CSI subdev driver");
1269MODULE_AUTHOR("Rui Miguel Silva <rui.silva@linaro.org>");
1270MODULE_LICENSE("GPL v2");
1271MODULE_ALIAS("platform:imx7-csi");
1272