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11#include <linux/clk.h>
12#include <linux/debugfs.h>
13#include <linux/delay.h>
14#include <linux/errno.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/mutex.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/regulator/consumer.h>
25#include <linux/reset.h>
26#include <linux/spinlock.h>
27
28#include <media/v4l2-common.h>
29#include <media/v4l2-device.h>
30#include <media/v4l2-fwnode.h>
31#include <media/v4l2-mc.h>
32#include <media/v4l2-subdev.h>
33
34#define CSIS_DRIVER_NAME "imx7-mipi-csis"
35#define CSIS_SUBDEV_NAME CSIS_DRIVER_NAME
36
37#define CSIS_PAD_SINK 0
38#define CSIS_PAD_SOURCE 1
39#define CSIS_PADS_NUM 2
40
41#define MIPI_CSIS_DEF_PIX_WIDTH 640
42#define MIPI_CSIS_DEF_PIX_HEIGHT 480
43
44
45
46
47#define MIPI_CSIS_CMN_CTRL 0x04
48#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16)
49#define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10)
50#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2)
51#define MIPI_CSIS_CMN_CTRL_RESET BIT(1)
52#define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0)
53
54#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8
55#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8)
56
57
58#define MIPI_CSIS_CLK_CTRL 0x08
59#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
60#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
61#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
62#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
63#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4)
64#define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0)
65
66
67#define MIPI_CSIS_INT_MSK 0x10
68#define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31)
69#define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30)
70#define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29)
71#define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28)
72#define MIPI_CSIS_INT_MSK_FRAME_START BIT(24)
73#define MIPI_CSIS_INT_MSK_FRAME_END BIT(20)
74#define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16)
75#define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12)
76#define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8)
77#define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4)
78#define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3)
79#define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2)
80#define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1)
81#define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0)
82
83
84#define MIPI_CSIS_INT_SRC 0x14
85#define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31)
86#define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30)
87#define MIPI_CSIS_INT_SRC_EVEN BIT(30)
88#define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29)
89#define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28)
90#define MIPI_CSIS_INT_SRC_ODD (0x3 << 28)
91#define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28)
92#define MIPI_CSIS_INT_SRC_FRAME_START BIT(24)
93#define MIPI_CSIS_INT_SRC_FRAME_END BIT(20)
94#define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16)
95#define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12)
96#define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8)
97#define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4)
98#define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3)
99#define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2)
100#define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1)
101#define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0)
102#define MIPI_CSIS_INT_SRC_ERRORS 0xfffff
103
104
105#define MIPI_CSIS_DPHY_STATUS 0x20
106#define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8)
107#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4)
108#define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1)
109#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0)
110
111
112#define MIPI_CSIS_DPHY_CMN_CTRL 0x24
113#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24)
114#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24)
115#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22)
116#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22)
117#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6)
118#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5)
119#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1)
120#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0)
121#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0)
122
123
124#define MIPI_CSIS_DPHY_BCTRL_L 0x30
125#define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30)
126#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28)
127#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28)
128#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28)
129#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28)
130#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27)
131#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27)
132#define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26)
133#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24)
134#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24)
135#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24)
136#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24)
137#define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23)
138#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21)
139#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21)
140#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21)
141#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21)
142#define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20)
143#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18)
144#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18)
145#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18)
146#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18)
147#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17)
148#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15)
149#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15)
150#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15)
151#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14)
152#define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13)
153#define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13)
154#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12)
155#define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11)
156#define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10)
157#define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0)
158
159
160#define MIPI_CSIS_DPHY_BCTRL_H 0x34
161
162#define MIPI_CSIS_DPHY_SCTRL_L 0x38
163
164#define MIPI_CSIS_DPHY_SCTRL_H 0x3c
165
166
167#define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10)
168#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24)
169#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24)
170#define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12)
171#define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12)
172#define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12)
173#define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
174#define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2)
175#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
176
177
178#define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10)
179#define CSIS_MAX_PIX_WIDTH 0xffff
180#define CSIS_MAX_PIX_HEIGHT 0xffff
181
182
183#define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10)
184#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18
185#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12
186#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0
187
188
189#define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10)
190#define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10)
191#define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10)
192
193
194#define MIPI_CSIS_DBG_CTRL 0xc0
195#define MIPI_CSIS_DBG_INTR_MSK 0xc4
196#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25)
197#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24)
198#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20)
199#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16)
200#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12)
201#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8)
202#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4)
203#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0)
204#define MIPI_CSIS_DBG_INTR_SRC 0xc8
205#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25)
206#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24)
207#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20)
208#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16)
209#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12)
210#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8)
211#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4)
212#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0)
213
214
215#define MIPI_CSIS_PKTDATA_ODD 0x2000
216#define MIPI_CSIS_PKTDATA_EVEN 0x3000
217#define MIPI_CSIS_PKTDATA_SIZE SZ_4K
218
219#define DEFAULT_SCLK_CSIS_FREQ 166000000UL
220
221
222#define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18
223#define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19
224#define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a
225#define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c
226#define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d
227#define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e
228#define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f
229#define MIPI_CSI2_DATA_TYPE_RGB565 0x22
230#define MIPI_CSI2_DATA_TYPE_RGB666 0x23
231#define MIPI_CSI2_DATA_TYPE_RGB888 0x24
232#define MIPI_CSI2_DATA_TYPE_RAW6 0x28
233#define MIPI_CSI2_DATA_TYPE_RAW7 0x29
234#define MIPI_CSI2_DATA_TYPE_RAW8 0x2a
235#define MIPI_CSI2_DATA_TYPE_RAW10 0x2b
236#define MIPI_CSI2_DATA_TYPE_RAW12 0x2c
237#define MIPI_CSI2_DATA_TYPE_RAW14 0x2d
238#define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x))
239
240enum {
241 ST_POWERED = 1,
242 ST_STREAMING = 2,
243 ST_SUSPENDED = 4,
244};
245
246struct mipi_csis_event {
247 bool debug;
248 u32 mask;
249 const char * const name;
250 unsigned int counter;
251};
252
253static const struct mipi_csis_event mipi_csis_events[] = {
254
255 { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" },
256 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" },
257 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" },
258 { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" },
259 { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
260 { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" },
261 { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" },
262 { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" },
263 { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" },
264 { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" },
265 { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" },
266 { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" },
267 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" },
268 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" },
269
270 { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" },
271 { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" },
272 { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" },
273 { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" },
274
275 { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" },
276 { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" },
277 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" },
278 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" },
279};
280
281#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
282
283enum mipi_csis_clk {
284 MIPI_CSIS_CLK_PCLK,
285 MIPI_CSIS_CLK_WRAP,
286 MIPI_CSIS_CLK_PHY,
287 MIPI_CSIS_CLK_AXI,
288};
289
290static const char * const mipi_csis_clk_id[] = {
291 "pclk",
292 "wrap",
293 "phy",
294 "axi",
295};
296
297enum mipi_csis_version {
298 MIPI_CSIS_V3_3,
299 MIPI_CSIS_V3_6_3,
300};
301
302struct mipi_csis_info {
303 enum mipi_csis_version version;
304 unsigned int num_clocks;
305};
306
307struct csi_state {
308 struct device *dev;
309 void __iomem *regs;
310 struct clk_bulk_data *clks;
311 struct reset_control *mrst;
312 struct regulator *mipi_phy_regulator;
313 const struct mipi_csis_info *info;
314 u8 index;
315
316 struct v4l2_subdev sd;
317 struct media_pad pads[CSIS_PADS_NUM];
318 struct v4l2_async_notifier notifier;
319 struct v4l2_subdev *src_sd;
320
321 struct v4l2_fwnode_bus_mipi_csi2 bus;
322 u32 clk_frequency;
323 u32 hs_settle;
324 u32 clk_settle;
325
326 struct mutex lock;
327 const struct csis_pix_format *csis_fmt;
328 struct v4l2_mbus_framefmt format_mbus;
329 u32 state;
330
331 spinlock_t slock;
332 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
333 struct dentry *debugfs_root;
334 bool debug;
335};
336
337
338
339
340
341struct csis_pix_format {
342 u32 code;
343 u32 data_type;
344 u8 width;
345};
346
347static const struct csis_pix_format mipi_csis_formats[] = {
348
349 {
350 .code = MEDIA_BUS_FMT_UYVY8_1X16,
351 .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8,
352 .width = 16,
353 },
354
355 {
356 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
357 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
358 .width = 8,
359 }, {
360 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
361 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
362 .width = 8,
363 }, {
364 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
365 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
366 .width = 8,
367 }, {
368 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
369 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
370 .width = 8,
371 }, {
372 .code = MEDIA_BUS_FMT_Y8_1X8,
373 .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
374 .width = 8,
375 }, {
376 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
377 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
378 .width = 10,
379 }, {
380 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
381 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
382 .width = 10,
383 }, {
384 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
385 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
386 .width = 10,
387 }, {
388 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
389 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
390 .width = 10,
391 }, {
392 .code = MEDIA_BUS_FMT_Y10_1X10,
393 .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
394 .width = 10,
395 }, {
396 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
397 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
398 .width = 12,
399 }, {
400 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
401 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
402 .width = 12,
403 }, {
404 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
405 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
406 .width = 12,
407 }, {
408 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
409 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
410 .width = 12,
411 }, {
412 .code = MEDIA_BUS_FMT_Y12_1X12,
413 .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
414 .width = 12,
415 }, {
416 .code = MEDIA_BUS_FMT_SBGGR14_1X14,
417 .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
418 .width = 14,
419 }, {
420 .code = MEDIA_BUS_FMT_SGBRG14_1X14,
421 .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
422 .width = 14,
423 }, {
424 .code = MEDIA_BUS_FMT_SGRBG14_1X14,
425 .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
426 .width = 14,
427 }, {
428 .code = MEDIA_BUS_FMT_SRGGB14_1X14,
429 .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
430 .width = 14,
431 }
432};
433
434static const struct csis_pix_format *find_csis_format(u32 code)
435{
436 unsigned int i;
437
438 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
439 if (code == mipi_csis_formats[i].code)
440 return &mipi_csis_formats[i];
441 return NULL;
442}
443
444
445
446
447
448static inline u32 mipi_csis_read(struct csi_state *state, u32 reg)
449{
450 return readl(state->regs + reg);
451}
452
453static inline void mipi_csis_write(struct csi_state *state, u32 reg, u32 val)
454{
455 writel(val, state->regs + reg);
456}
457
458static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
459{
460 mipi_csis_write(state, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
461 mipi_csis_write(state, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
462}
463
464static void mipi_csis_sw_reset(struct csi_state *state)
465{
466 u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
467
468 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
469 val | MIPI_CSIS_CMN_CTRL_RESET);
470 usleep_range(10, 20);
471}
472
473static void mipi_csis_system_enable(struct csi_state *state, int on)
474{
475 u32 val, mask;
476
477 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
478 if (on)
479 val |= MIPI_CSIS_CMN_CTRL_ENABLE;
480 else
481 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
482 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
483
484 val = mipi_csis_read(state, MIPI_CSIS_DPHY_CMN_CTRL);
485 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
486 if (on) {
487 mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
488 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
489 }
490 mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, val);
491}
492
493
494static void __mipi_csis_set_format(struct csi_state *state)
495{
496 struct v4l2_mbus_framefmt *mf = &state->format_mbus;
497 u32 val;
498
499
500 val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0));
501 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK);
502 val |= MIPI_CSIS_ISPCFG_FMT(state->csis_fmt->data_type);
503 mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val);
504
505
506 val = mf->width | (mf->height << 16);
507 mipi_csis_write(state, MIPI_CSIS_ISP_RESOL_CH(0), val);
508}
509
510static int mipi_csis_calculate_params(struct csi_state *state)
511{
512 s64 link_freq;
513 u32 lane_rate;
514
515
516 link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler,
517 state->csis_fmt->width,
518 state->bus.num_data_lanes * 2);
519 if (link_freq < 0) {
520 dev_err(state->dev, "Unable to obtain link frequency: %d\n",
521 (int)link_freq);
522 return link_freq;
523 }
524
525 lane_rate = link_freq * 2;
526
527 if (lane_rate < 80000000 || lane_rate > 1500000000) {
528 dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate);
529 return -EINVAL;
530 }
531
532
533
534
535
536
537
538 state->hs_settle = (lane_rate - 5000000) / 45000000;
539 state->clk_settle = 0;
540
541 dev_dbg(state->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
542 lane_rate, state->clk_settle, state->hs_settle);
543
544 return 0;
545}
546
547static void mipi_csis_set_params(struct csi_state *state)
548{
549 int lanes = state->bus.num_data_lanes;
550 u32 val;
551
552 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
553 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
554 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
555 if (state->info->version == MIPI_CSIS_V3_3)
556 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
557 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
558
559 __mipi_csis_set_format(state);
560
561 mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL,
562 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle) |
563 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(state->clk_settle));
564
565 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
566 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
567 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
568 mipi_csis_write(state, MIPI_CSIS_ISP_SYNC_CH(0), val);
569
570 val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
571 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
572 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
573 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
574 mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val);
575
576 mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_L,
577 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV |
578 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ |
579 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V |
580 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV |
581 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV |
582 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV |
583 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000));
584 mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_H, 0);
585
586
587 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
588 mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
589 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
590 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
591}
592
593static int mipi_csis_clk_enable(struct csi_state *state)
594{
595 return clk_bulk_prepare_enable(state->info->num_clocks, state->clks);
596}
597
598static void mipi_csis_clk_disable(struct csi_state *state)
599{
600 clk_bulk_disable_unprepare(state->info->num_clocks, state->clks);
601}
602
603static int mipi_csis_clk_get(struct csi_state *state)
604{
605 unsigned int i;
606 int ret;
607
608 state->clks = devm_kcalloc(state->dev, state->info->num_clocks,
609 sizeof(*state->clks), GFP_KERNEL);
610
611 if (!state->clks)
612 return -ENOMEM;
613
614 for (i = 0; i < state->info->num_clocks; i++)
615 state->clks[i].id = mipi_csis_clk_id[i];
616
617 ret = devm_clk_bulk_get(state->dev, state->info->num_clocks,
618 state->clks);
619 if (ret < 0)
620 return ret;
621
622
623 ret = clk_set_rate(state->clks[MIPI_CSIS_CLK_WRAP].clk,
624 state->clk_frequency);
625 if (ret < 0)
626 dev_err(state->dev, "set rate=%d failed: %d\n",
627 state->clk_frequency, ret);
628
629 return ret;
630}
631
632static void mipi_csis_start_stream(struct csi_state *state)
633{
634 mipi_csis_sw_reset(state);
635 mipi_csis_set_params(state);
636 mipi_csis_system_enable(state, true);
637 mipi_csis_enable_interrupts(state, true);
638}
639
640static void mipi_csis_stop_stream(struct csi_state *state)
641{
642 mipi_csis_enable_interrupts(state, false);
643 mipi_csis_system_enable(state, false);
644}
645
646static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
647{
648 struct csi_state *state = dev_id;
649 unsigned long flags;
650 unsigned int i;
651 u32 status;
652 u32 dbg_status;
653
654 status = mipi_csis_read(state, MIPI_CSIS_INT_SRC);
655 dbg_status = mipi_csis_read(state, MIPI_CSIS_DBG_INTR_SRC);
656
657 spin_lock_irqsave(&state->slock, flags);
658
659
660 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || state->debug) {
661 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
662 struct mipi_csis_event *event = &state->events[i];
663
664 if ((!event->debug && (status & event->mask)) ||
665 (event->debug && (dbg_status & event->mask)))
666 event->counter++;
667 }
668 }
669 spin_unlock_irqrestore(&state->slock, flags);
670
671 mipi_csis_write(state, MIPI_CSIS_INT_SRC, status);
672 mipi_csis_write(state, MIPI_CSIS_DBG_INTR_SRC, dbg_status);
673
674 return IRQ_HANDLED;
675}
676
677
678
679
680
681static int mipi_csis_phy_enable(struct csi_state *state)
682{
683 if (state->info->version != MIPI_CSIS_V3_3)
684 return 0;
685
686 return regulator_enable(state->mipi_phy_regulator);
687}
688
689static int mipi_csis_phy_disable(struct csi_state *state)
690{
691 if (state->info->version != MIPI_CSIS_V3_3)
692 return 0;
693
694 return regulator_disable(state->mipi_phy_regulator);
695}
696
697static void mipi_csis_phy_reset(struct csi_state *state)
698{
699 if (state->info->version != MIPI_CSIS_V3_3)
700 return;
701
702 reset_control_assert(state->mrst);
703 msleep(20);
704 reset_control_deassert(state->mrst);
705}
706
707static int mipi_csis_phy_init(struct csi_state *state)
708{
709 if (state->info->version != MIPI_CSIS_V3_3)
710 return 0;
711
712
713 state->mrst = devm_reset_control_get_exclusive(state->dev, NULL);
714 if (IS_ERR(state->mrst))
715 return PTR_ERR(state->mrst);
716
717 state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy");
718 if (IS_ERR(state->mipi_phy_regulator))
719 return PTR_ERR(state->mipi_phy_regulator);
720
721 return regulator_set_voltage(state->mipi_phy_regulator, 1000000,
722 1000000);
723}
724
725
726
727
728
729static void mipi_csis_clear_counters(struct csi_state *state)
730{
731 unsigned long flags;
732 unsigned int i;
733
734 spin_lock_irqsave(&state->slock, flags);
735 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
736 state->events[i].counter = 0;
737 spin_unlock_irqrestore(&state->slock, flags);
738}
739
740static void mipi_csis_log_counters(struct csi_state *state, bool non_errors)
741{
742 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
743 : MIPI_CSIS_NUM_EVENTS - 8;
744 unsigned long flags;
745 unsigned int i;
746
747 spin_lock_irqsave(&state->slock, flags);
748
749 for (i = 0; i < num_events; ++i) {
750 if (state->events[i].counter > 0 || state->debug)
751 dev_info(state->dev, "%s events: %d\n",
752 state->events[i].name,
753 state->events[i].counter);
754 }
755 spin_unlock_irqrestore(&state->slock, flags);
756}
757
758static int mipi_csis_dump_regs(struct csi_state *state)
759{
760 static const struct {
761 u32 offset;
762 const char * const name;
763 } registers[] = {
764 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
765 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
766 { MIPI_CSIS_INT_MSK, "INT_MSK" },
767 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
768 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
769 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
770 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
771 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
772 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
773 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
774 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
775 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
776 };
777
778 unsigned int i;
779 u32 cfg;
780
781 dev_info(state->dev, "--- REGISTERS ---\n");
782
783 for (i = 0; i < ARRAY_SIZE(registers); i++) {
784 cfg = mipi_csis_read(state, registers[i].offset);
785 dev_info(state->dev, "%14s: 0x%08x\n", registers[i].name, cfg);
786 }
787
788 return 0;
789}
790
791static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
792{
793 struct csi_state *state = m->private;
794
795 return mipi_csis_dump_regs(state);
796}
797DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
798
799static void mipi_csis_debugfs_init(struct csi_state *state)
800{
801 state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL);
802
803 debugfs_create_bool("debug_enable", 0600, state->debugfs_root,
804 &state->debug);
805 debugfs_create_file("dump_regs", 0600, state->debugfs_root, state,
806 &mipi_csis_dump_regs_fops);
807}
808
809static void mipi_csis_debugfs_exit(struct csi_state *state)
810{
811 debugfs_remove_recursive(state->debugfs_root);
812}
813
814
815
816
817
818static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev)
819{
820 return container_of(sdev, struct csi_state, sd);
821}
822
823static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
824{
825 struct csi_state *state = mipi_sd_to_csis_state(sd);
826 int ret;
827
828 if (enable) {
829 ret = mipi_csis_calculate_params(state);
830 if (ret < 0)
831 return ret;
832
833 mipi_csis_clear_counters(state);
834
835 ret = pm_runtime_resume_and_get(state->dev);
836 if (ret < 0)
837 return ret;
838
839 ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
840 if (ret < 0 && ret != -ENOIOCTLCMD)
841 goto done;
842 }
843
844 mutex_lock(&state->lock);
845
846 if (enable) {
847 if (state->state & ST_SUSPENDED) {
848 ret = -EBUSY;
849 goto unlock;
850 }
851
852 mipi_csis_start_stream(state);
853 ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
854 if (ret < 0)
855 goto unlock;
856
857 mipi_csis_log_counters(state, true);
858
859 state->state |= ST_STREAMING;
860 } else {
861 v4l2_subdev_call(state->src_sd, video, s_stream, 0);
862 ret = v4l2_subdev_call(state->src_sd, core, s_power, 0);
863 if (ret == -ENOIOCTLCMD)
864 ret = 0;
865 mipi_csis_stop_stream(state);
866 state->state &= ~ST_STREAMING;
867 if (state->debug)
868 mipi_csis_log_counters(state, true);
869 }
870
871unlock:
872 mutex_unlock(&state->lock);
873
874done:
875 if (!enable || ret < 0)
876 pm_runtime_put(state->dev);
877
878 return ret;
879}
880
881static struct v4l2_mbus_framefmt *
882mipi_csis_get_format(struct csi_state *state,
883 struct v4l2_subdev_state *sd_state,
884 enum v4l2_subdev_format_whence which,
885 unsigned int pad)
886{
887 if (which == V4L2_SUBDEV_FORMAT_TRY)
888 return v4l2_subdev_get_try_format(&state->sd, sd_state, pad);
889
890 return &state->format_mbus;
891}
892
893static int mipi_csis_init_cfg(struct v4l2_subdev *sd,
894 struct v4l2_subdev_state *sd_state)
895{
896 struct csi_state *state = mipi_sd_to_csis_state(sd);
897 struct v4l2_mbus_framefmt *fmt_sink;
898 struct v4l2_mbus_framefmt *fmt_source;
899 enum v4l2_subdev_format_whence which;
900
901 which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
902 fmt_sink = mipi_csis_get_format(state, sd_state, which, CSIS_PAD_SINK);
903
904 fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16;
905 fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH;
906 fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT;
907 fmt_sink->field = V4L2_FIELD_NONE;
908
909 fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M;
910 fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
911 fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
912 fmt_sink->quantization =
913 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
914 fmt_sink->ycbcr_enc);
915
916
917
918
919
920
921 if (!sd_state)
922 return 0;
923
924 fmt_source = mipi_csis_get_format(state, sd_state, which,
925 CSIS_PAD_SOURCE);
926 *fmt_source = *fmt_sink;
927
928 return 0;
929}
930
931static int mipi_csis_get_fmt(struct v4l2_subdev *sd,
932 struct v4l2_subdev_state *sd_state,
933 struct v4l2_subdev_format *sdformat)
934{
935 struct csi_state *state = mipi_sd_to_csis_state(sd);
936 struct v4l2_mbus_framefmt *fmt;
937
938 fmt = mipi_csis_get_format(state, sd_state, sdformat->which,
939 sdformat->pad);
940
941 mutex_lock(&state->lock);
942 sdformat->format = *fmt;
943 mutex_unlock(&state->lock);
944
945 return 0;
946}
947
948static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,
949 struct v4l2_subdev_state *sd_state,
950 struct v4l2_subdev_mbus_code_enum *code)
951{
952 struct csi_state *state = mipi_sd_to_csis_state(sd);
953
954
955
956
957
958 if (code->pad == CSIS_PAD_SOURCE) {
959 struct v4l2_mbus_framefmt *fmt;
960
961 if (code->index > 0)
962 return -EINVAL;
963
964 fmt = mipi_csis_get_format(state, sd_state, code->which,
965 code->pad);
966 code->code = fmt->code;
967 return 0;
968 }
969
970 if (code->pad != CSIS_PAD_SINK)
971 return -EINVAL;
972
973 if (code->index >= ARRAY_SIZE(mipi_csis_formats))
974 return -EINVAL;
975
976 code->code = mipi_csis_formats[code->index].code;
977
978 return 0;
979}
980
981static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
982 struct v4l2_subdev_state *sd_state,
983 struct v4l2_subdev_format *sdformat)
984{
985 struct csi_state *state = mipi_sd_to_csis_state(sd);
986 struct csis_pix_format const *csis_fmt;
987 struct v4l2_mbus_framefmt *fmt;
988 unsigned int align;
989
990
991
992
993
994 if (sdformat->pad == CSIS_PAD_SOURCE)
995 return mipi_csis_get_fmt(sd, sd_state, sdformat);
996
997 if (sdformat->pad != CSIS_PAD_SINK)
998 return -EINVAL;
999
1000
1001
1002
1003
1004
1005
1006
1007 csis_fmt = find_csis_format(sdformat->format.code);
1008 if (!csis_fmt)
1009 csis_fmt = &mipi_csis_formats[0];
1010
1011 switch (csis_fmt->width % 8) {
1012 case 0:
1013 align = 0;
1014 break;
1015 case 4:
1016 align = 1;
1017 break;
1018 case 2:
1019 case 6:
1020 align = 2;
1021 break;
1022 default:
1023
1024 align = 3;
1025 break;
1026 }
1027
1028 v4l_bound_align_image(&sdformat->format.width, 1,
1029 CSIS_MAX_PIX_WIDTH, align,
1030 &sdformat->format.height, 1,
1031 CSIS_MAX_PIX_HEIGHT, 0, 0);
1032
1033 fmt = mipi_csis_get_format(state, sd_state, sdformat->which,
1034 sdformat->pad);
1035
1036 mutex_lock(&state->lock);
1037
1038 fmt->code = csis_fmt->code;
1039 fmt->width = sdformat->format.width;
1040 fmt->height = sdformat->format.height;
1041
1042 sdformat->format = *fmt;
1043
1044
1045 fmt = mipi_csis_get_format(state, sd_state, sdformat->which,
1046 CSIS_PAD_SOURCE);
1047 *fmt = sdformat->format;
1048
1049
1050 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
1051 state->csis_fmt = csis_fmt;
1052
1053 mutex_unlock(&state->lock);
1054
1055 return 0;
1056}
1057
1058static int mipi_csis_log_status(struct v4l2_subdev *sd)
1059{
1060 struct csi_state *state = mipi_sd_to_csis_state(sd);
1061
1062 mutex_lock(&state->lock);
1063 mipi_csis_log_counters(state, true);
1064 if (state->debug && (state->state & ST_POWERED))
1065 mipi_csis_dump_regs(state);
1066 mutex_unlock(&state->lock);
1067
1068 return 0;
1069}
1070
1071static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
1072 .log_status = mipi_csis_log_status,
1073};
1074
1075static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
1076 .s_stream = mipi_csis_s_stream,
1077};
1078
1079static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
1080 .init_cfg = mipi_csis_init_cfg,
1081 .enum_mbus_code = mipi_csis_enum_mbus_code,
1082 .get_fmt = mipi_csis_get_fmt,
1083 .set_fmt = mipi_csis_set_fmt,
1084};
1085
1086static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
1087 .core = &mipi_csis_core_ops,
1088 .video = &mipi_csis_video_ops,
1089 .pad = &mipi_csis_pad_ops,
1090};
1091
1092
1093
1094
1095
1096static int mipi_csis_link_setup(struct media_entity *entity,
1097 const struct media_pad *local_pad,
1098 const struct media_pad *remote_pad, u32 flags)
1099{
1100 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1101 struct csi_state *state = mipi_sd_to_csis_state(sd);
1102 struct v4l2_subdev *remote_sd;
1103
1104 dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name,
1105 local_pad->entity->name);
1106
1107
1108 if (!(local_pad->flags & MEDIA_PAD_FL_SINK))
1109 return 0;
1110
1111 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
1112
1113 if (flags & MEDIA_LNK_FL_ENABLED) {
1114 if (state->src_sd)
1115 return -EBUSY;
1116
1117 state->src_sd = remote_sd;
1118 } else {
1119 state->src_sd = NULL;
1120 }
1121
1122 return 0;
1123}
1124
1125static const struct media_entity_operations mipi_csis_entity_ops = {
1126 .link_setup = mipi_csis_link_setup,
1127 .link_validate = v4l2_subdev_link_validate,
1128 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1129};
1130
1131
1132
1133
1134
1135static struct csi_state *
1136mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
1137{
1138 return container_of(n, struct csi_state, notifier);
1139}
1140
1141static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
1142 struct v4l2_subdev *sd,
1143 struct v4l2_async_subdev *asd)
1144{
1145 struct csi_state *state = mipi_notifier_to_csis_state(notifier);
1146 struct media_pad *sink = &state->sd.entity.pads[CSIS_PAD_SINK];
1147
1148 return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
1149}
1150
1151static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
1152 .bound = mipi_csis_notify_bound,
1153};
1154
1155static int mipi_csis_async_register(struct csi_state *state)
1156{
1157 struct v4l2_fwnode_endpoint vep = {
1158 .bus_type = V4L2_MBUS_CSI2_DPHY,
1159 };
1160 struct v4l2_async_subdev *asd;
1161 struct fwnode_handle *ep;
1162 unsigned int i;
1163 int ret;
1164
1165 v4l2_async_notifier_init(&state->notifier);
1166
1167 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
1168 FWNODE_GRAPH_ENDPOINT_NEXT);
1169 if (!ep)
1170 return -ENOTCONN;
1171
1172 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
1173 if (ret)
1174 goto err_parse;
1175
1176 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
1177 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
1178 dev_err(state->dev,
1179 "data lanes reordering is not supported");
1180 ret = -EINVAL;
1181 goto err_parse;
1182 }
1183 }
1184
1185 state->bus = vep.bus.mipi_csi2;
1186
1187 dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes);
1188 dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags);
1189
1190 asd = v4l2_async_notifier_add_fwnode_remote_subdev(
1191 &state->notifier, ep, struct v4l2_async_subdev);
1192 if (IS_ERR(asd)) {
1193 ret = PTR_ERR(asd);
1194 goto err_parse;
1195 }
1196
1197 fwnode_handle_put(ep);
1198
1199 state->notifier.ops = &mipi_csis_notify_ops;
1200
1201 ret = v4l2_async_subdev_notifier_register(&state->sd, &state->notifier);
1202 if (ret)
1203 return ret;
1204
1205 return v4l2_async_register_subdev(&state->sd);
1206
1207err_parse:
1208 fwnode_handle_put(ep);
1209
1210 return ret;
1211}
1212
1213
1214
1215
1216
1217static int mipi_csis_pm_suspend(struct device *dev, bool runtime)
1218{
1219 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1220 struct csi_state *state = mipi_sd_to_csis_state(sd);
1221 int ret = 0;
1222
1223 mutex_lock(&state->lock);
1224 if (state->state & ST_POWERED) {
1225 mipi_csis_stop_stream(state);
1226 ret = mipi_csis_phy_disable(state);
1227 if (ret)
1228 goto unlock;
1229 mipi_csis_clk_disable(state);
1230 state->state &= ~ST_POWERED;
1231 if (!runtime)
1232 state->state |= ST_SUSPENDED;
1233 }
1234
1235unlock:
1236 mutex_unlock(&state->lock);
1237
1238 return ret ? -EAGAIN : 0;
1239}
1240
1241static int mipi_csis_pm_resume(struct device *dev, bool runtime)
1242{
1243 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1244 struct csi_state *state = mipi_sd_to_csis_state(sd);
1245 int ret = 0;
1246
1247 mutex_lock(&state->lock);
1248 if (!runtime && !(state->state & ST_SUSPENDED))
1249 goto unlock;
1250
1251 if (!(state->state & ST_POWERED)) {
1252 ret = mipi_csis_phy_enable(state);
1253 if (ret)
1254 goto unlock;
1255
1256 state->state |= ST_POWERED;
1257 mipi_csis_clk_enable(state);
1258 }
1259 if (state->state & ST_STREAMING)
1260 mipi_csis_start_stream(state);
1261
1262 state->state &= ~ST_SUSPENDED;
1263
1264unlock:
1265 mutex_unlock(&state->lock);
1266
1267 return ret ? -EAGAIN : 0;
1268}
1269
1270static int __maybe_unused mipi_csis_suspend(struct device *dev)
1271{
1272 return mipi_csis_pm_suspend(dev, false);
1273}
1274
1275static int __maybe_unused mipi_csis_resume(struct device *dev)
1276{
1277 return mipi_csis_pm_resume(dev, false);
1278}
1279
1280static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1281{
1282 return mipi_csis_pm_suspend(dev, true);
1283}
1284
1285static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1286{
1287 return mipi_csis_pm_resume(dev, true);
1288}
1289
1290static const struct dev_pm_ops mipi_csis_pm_ops = {
1291 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1292 NULL)
1293 SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume)
1294};
1295
1296
1297
1298
1299
1300static int mipi_csis_subdev_init(struct csi_state *state)
1301{
1302 struct v4l2_subdev *sd = &state->sd;
1303
1304 v4l2_subdev_init(sd, &mipi_csis_subdev_ops);
1305 sd->owner = THIS_MODULE;
1306 snprintf(sd->name, sizeof(sd->name), "%s.%d",
1307 CSIS_SUBDEV_NAME, state->index);
1308
1309 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1310 sd->ctrl_handler = NULL;
1311
1312 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1313 sd->entity.ops = &mipi_csis_entity_ops;
1314
1315 sd->dev = state->dev;
1316
1317 state->csis_fmt = &mipi_csis_formats[0];
1318 mipi_csis_init_cfg(sd, NULL);
1319
1320 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1321 | MEDIA_PAD_FL_MUST_CONNECT;
1322 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
1323 | MEDIA_PAD_FL_MUST_CONNECT;
1324 return media_entity_pads_init(&sd->entity, CSIS_PADS_NUM,
1325 state->pads);
1326}
1327
1328static int mipi_csis_parse_dt(struct csi_state *state)
1329{
1330 struct device_node *node = state->dev->of_node;
1331
1332 if (of_property_read_u32(node, "clock-frequency",
1333 &state->clk_frequency))
1334 state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
1335
1336 return 0;
1337}
1338
1339static int mipi_csis_probe(struct platform_device *pdev)
1340{
1341 struct device *dev = &pdev->dev;
1342 struct csi_state *state;
1343 int irq;
1344 int ret;
1345
1346 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1347 if (!state)
1348 return -ENOMEM;
1349
1350 mutex_init(&state->lock);
1351 spin_lock_init(&state->slock);
1352
1353 state->dev = dev;
1354 state->info = of_device_get_match_data(dev);
1355
1356 memcpy(state->events, mipi_csis_events, sizeof(state->events));
1357
1358
1359 ret = mipi_csis_parse_dt(state);
1360 if (ret < 0) {
1361 dev_err(dev, "Failed to parse device tree: %d\n", ret);
1362 return ret;
1363 }
1364
1365
1366 state->regs = devm_platform_ioremap_resource(pdev, 0);
1367 if (IS_ERR(state->regs))
1368 return PTR_ERR(state->regs);
1369
1370 irq = platform_get_irq(pdev, 0);
1371 if (irq < 0)
1372 return irq;
1373
1374 ret = mipi_csis_phy_init(state);
1375 if (ret < 0)
1376 return ret;
1377
1378 ret = mipi_csis_clk_get(state);
1379 if (ret < 0)
1380 return ret;
1381
1382
1383 mipi_csis_phy_reset(state);
1384
1385 ret = mipi_csis_clk_enable(state);
1386 if (ret < 0) {
1387 dev_err(state->dev, "failed to enable clocks: %d\n", ret);
1388 return ret;
1389 }
1390
1391
1392 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,
1393 dev_name(dev), state);
1394 if (ret) {
1395 dev_err(dev, "Interrupt request failed\n");
1396 goto disable_clock;
1397 }
1398
1399
1400 ret = mipi_csis_subdev_init(state);
1401 if (ret < 0)
1402 goto disable_clock;
1403
1404 platform_set_drvdata(pdev, &state->sd);
1405
1406 ret = mipi_csis_async_register(state);
1407 if (ret < 0) {
1408 dev_err(dev, "async register failed: %d\n", ret);
1409 goto cleanup;
1410 }
1411
1412
1413 mipi_csis_debugfs_init(state);
1414
1415
1416 pm_runtime_enable(dev);
1417 if (!pm_runtime_enabled(dev)) {
1418 ret = mipi_csis_pm_resume(dev, true);
1419 if (ret < 0)
1420 goto unregister_all;
1421 }
1422
1423 dev_info(dev, "lanes: %d, freq: %u\n",
1424 state->bus.num_data_lanes, state->clk_frequency);
1425
1426 return 0;
1427
1428unregister_all:
1429 mipi_csis_debugfs_exit(state);
1430cleanup:
1431 media_entity_cleanup(&state->sd.entity);
1432 v4l2_async_notifier_unregister(&state->notifier);
1433 v4l2_async_notifier_cleanup(&state->notifier);
1434 v4l2_async_unregister_subdev(&state->sd);
1435disable_clock:
1436 mipi_csis_clk_disable(state);
1437 mutex_destroy(&state->lock);
1438
1439 return ret;
1440}
1441
1442static int mipi_csis_remove(struct platform_device *pdev)
1443{
1444 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1445 struct csi_state *state = mipi_sd_to_csis_state(sd);
1446
1447 mipi_csis_debugfs_exit(state);
1448 v4l2_async_notifier_unregister(&state->notifier);
1449 v4l2_async_notifier_cleanup(&state->notifier);
1450 v4l2_async_unregister_subdev(&state->sd);
1451
1452 pm_runtime_disable(&pdev->dev);
1453 mipi_csis_pm_suspend(&pdev->dev, true);
1454 mipi_csis_clk_disable(state);
1455 media_entity_cleanup(&state->sd.entity);
1456 mutex_destroy(&state->lock);
1457 pm_runtime_set_suspended(&pdev->dev);
1458
1459 return 0;
1460}
1461
1462static const struct of_device_id mipi_csis_of_match[] = {
1463 {
1464 .compatible = "fsl,imx7-mipi-csi2",
1465 .data = &(const struct mipi_csis_info){
1466 .version = MIPI_CSIS_V3_3,
1467 .num_clocks = 3,
1468 },
1469 }, {
1470 .compatible = "fsl,imx8mm-mipi-csi2",
1471 .data = &(const struct mipi_csis_info){
1472 .version = MIPI_CSIS_V3_6_3,
1473 .num_clocks = 4,
1474 },
1475 },
1476 { },
1477};
1478MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1479
1480static struct platform_driver mipi_csis_driver = {
1481 .probe = mipi_csis_probe,
1482 .remove = mipi_csis_remove,
1483 .driver = {
1484 .of_match_table = mipi_csis_of_match,
1485 .name = CSIS_DRIVER_NAME,
1486 .pm = &mipi_csis_pm_ops,
1487 },
1488};
1489
1490module_platform_driver(mipi_csis_driver);
1491
1492MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver");
1493MODULE_LICENSE("GPL v2");
1494MODULE_ALIAS("platform:imx7-mipi-csi2");
1495