LXR linux/drivers/staging/media/tegra-video/csi.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2020 NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#ifndef __TEGRA_CSI_H__
   7#define __TEGRA_CSI_H__
   8
   9#include <media/media-entity.h>
  10#include <media/v4l2-async.h>
  11#include <media/v4l2-subdev.h>
  12
  13/*
  14 * Each CSI brick supports max of 4 lanes that can be used as either
  15 * one x4 port using both CILA and CILB partitions of a CSI brick or can
  16 * be used as two x2 ports with one x2 from CILA and the other x2 from
  17 * CILB.
  18 */
  19#define CSI_PORTS_PER_BRICK     2
  20#define CSI_LANES_PER_BRICK     4
  21
  22/* Maximum 2 CSI x4 ports can be ganged up for streaming */
  23#define GANG_PORTS_MAX  2
  24
  25/* each CSI channel can have one sink and one source pads */
  26#define TEGRA_CSI_PADS_NUM      2
  27
  28enum tegra_csi_cil_port {
  29        PORT_A = 0,
  30        PORT_B,
  31};
  32
  33enum tegra_csi_block {
  34        CSI_CIL_AB = 0,
  35        CSI_CIL_CD,
  36        CSI_CIL_EF,
  37};
  38
  39struct tegra_csi;
  40
  41/**
  42 * struct tegra_csi_channel - Tegra CSI channel
  43 *
  44 * @list: list head for this entry
  45 * @subdev: V4L2 subdevice associated with this channel
  46 * @pads: media pads for the subdevice entity
  47 * @numpads: number of pads.
  48 * @csi: Tegra CSI device structure
  49 * @of_node: csi device tree node
  50 * @numgangports: number of immediate ports ganged up to meet the
  51 *             channel bus-width
  52 * @numlanes: number of lanes used per port
  53 * @csi_port_nums: CSI channel port numbers
  54 * @pg_mode: test pattern generator mode for channel
  55 * @format: active format of the channel
  56 * @framerate: active framerate for TPG
  57 * @h_blank: horizontal blanking for TPG active format
  58 * @v_blank: vertical blanking for TPG active format
  59 * @mipi: mipi device for corresponding csi channel pads
  60 * @pixel_rate: active pixel rate from the sensor on this channel
  61 */
  62struct tegra_csi_channel {
  63        struct list_head list;
  64        struct v4l2_subdev subdev;
  65        struct media_pad pads[TEGRA_CSI_PADS_NUM];
  66        unsigned int numpads;
  67        struct tegra_csi *csi;
  68        struct device_node *of_node;
  69        u8 numgangports;
  70        unsigned int numlanes;
  71        u8 csi_port_nums[GANG_PORTS_MAX];
  72        u8 pg_mode;
  73        struct v4l2_mbus_framefmt format;
  74        unsigned int framerate;
  75        unsigned int h_blank;
  76        unsigned int v_blank;
  77        struct tegra_mipi_device *mipi;
  78        unsigned int pixel_rate;
  79};
  80
  81/**
  82 * struct tpg_framerate - Tegra CSI TPG framerate configuration
  83 *
  84 * @frmsize: frame resolution
  85 * @code: media bus format code
  86 * @h_blank: horizontal blanking used for TPG
  87 * @v_blank: vertical blanking interval used for TPG
  88 * @framerate: framerate achieved with the corresponding blanking intervals,
  89 *              format and resolution.
  90 */
  91struct tpg_framerate {
  92        struct v4l2_frmsize_discrete frmsize;
  93        u32 code;
  94        unsigned int h_blank;
  95        unsigned int v_blank;
  96        unsigned int framerate;
  97};
  98
  99/**
 100 * struct tegra_csi_ops - Tegra CSI operations
 101 *
 102 * @csi_start_streaming: programs csi hardware to enable streaming.
 103 * @csi_stop_streaming: programs csi hardware to disable streaming.
 104 * @csi_err_recover: csi hardware block recovery in case of any capture errors
 105 *              due to missing source stream or due to improper csi input from
 106 *              the external source.
 107 */
 108struct tegra_csi_ops {
 109        int (*csi_start_streaming)(struct tegra_csi_channel *csi_chan);
 110        void (*csi_stop_streaming)(struct tegra_csi_channel *csi_chan);
 111        void (*csi_err_recover)(struct tegra_csi_channel *csi_chan);
 112};
 113
 114/**
 115 * struct tegra_csi_soc - NVIDIA Tegra CSI SoC structure
 116 *
 117 * @ops: csi hardware operations
 118 * @csi_max_channels: supported max streaming channels
 119 * @clk_names: csi and cil clock names
 120 * @num_clks: total clocks count
 121 * @tpg_frmrate_table: csi tpg frame rate table with blanking intervals
 122 * @tpg_frmrate_table_size: size of frame rate table
 123 */
 124struct tegra_csi_soc {
 125        const struct tegra_csi_ops *ops;
 126        unsigned int csi_max_channels;
 127        const char * const *clk_names;
 128        unsigned int num_clks;
 129        const struct tpg_framerate *tpg_frmrate_table;
 130        unsigned int tpg_frmrate_table_size;
 131};
 132
 133/**
 134 * struct tegra_csi - NVIDIA Tegra CSI device structure
 135 *
 136 * @dev: device struct
 137 * @client: host1x_client struct
 138 * @iomem: register base
 139 * @clks: clock for CSI and CIL
 140 * @soc: pointer to SoC data structure
 141 * @ops: csi operations
 142 * @csi_chans: list head for CSI channels
 143 */
 144struct tegra_csi {
 145        struct device *dev;
 146        struct host1x_client client;
 147        void __iomem *iomem;
 148        struct clk_bulk_data *clks;
 149        const struct tegra_csi_soc *soc;
 150        const struct tegra_csi_ops *ops;
 151        struct list_head csi_chans;
 152};
 153
 154#if defined(CONFIG_ARCH_TEGRA_210_SOC)
 155extern const struct tegra_csi_soc tegra210_csi_soc;
 156#endif
 157
 158void tegra_csi_error_recover(struct v4l2_subdev *subdev);
 159void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan,
 160                                u8 csi_port_num,
 161                                u8 *clk_settle_time,
 162                                u8 *ths_settle_time);
 163#endif
 164