1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#ifndef __TEGRA_VI_H__ 7#define __TEGRA_VI_H__ 8 9#include <linux/host1x.h> 10#include <linux/list.h> 11 12#include <linux/mutex.h> 13#include <linux/spinlock.h> 14#include <linux/wait.h> 15 16#include <media/media-entity.h> 17#include <media/v4l2-async.h> 18#include <media/v4l2-ctrls.h> 19#include <media/v4l2-device.h> 20#include <media/v4l2-dev.h> 21#include <media/v4l2-subdev.h> 22#include <media/videobuf2-v4l2.h> 23 24#include "csi.h" 25 26#define V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY (V4L2_CTRL_CLASS_CAMERA | 0x1001) 27 28#define TEGRA_MIN_WIDTH 32U 29#define TEGRA_MAX_WIDTH 32768U 30#define TEGRA_MIN_HEIGHT 32U 31#define TEGRA_MAX_HEIGHT 32768U 32 33#define TEGRA_DEF_WIDTH 1920 34#define TEGRA_DEF_HEIGHT 1080 35#define TEGRA_IMAGE_FORMAT_DEF 32 36 37#define MAX_FORMAT_NUM 64 38#define SURFACE_ALIGN_BYTES 64 39 40enum tegra_vi_pg_mode { 41 TEGRA_VI_PG_DISABLED = 0, 42 TEGRA_VI_PG_DIRECT, 43 TEGRA_VI_PG_PATCH, 44}; 45 46/** 47 * struct tegra_vi_ops - Tegra VI operations 48 * @vi_start_streaming: starts media pipeline, subdevice streaming, sets up 49 * VI for capture and runs capture start and capture finish 50 * kthreads for capturing frames to buffer and returns them back. 51 * @vi_stop_streaming: stops media pipeline and subdevice streaming and returns 52 * back any queued buffers. 53 */ 54struct tegra_vi_ops { 55 int (*vi_start_streaming)(struct vb2_queue *vq, u32 count); 56 void (*vi_stop_streaming)(struct vb2_queue *vq); 57}; 58 59/** 60 * struct tegra_vi_soc - NVIDIA Tegra Video Input SoC structure 61 * 62 * @video_formats: supported video formats 63 * @nformats: total video formats 64 * @ops: vi operations 65 * @hw_revision: VI hw_revision 66 * @vi_max_channels: supported max streaming channels 67 * @vi_max_clk_hz: VI clock max frequency 68 */ 69struct tegra_vi_soc { 70 const struct tegra_video_format *video_formats; 71 const unsigned int nformats; 72 const struct tegra_vi_ops *ops; 73 u32 hw_revision; 74 unsigned int vi_max_channels; 75 unsigned int vi_max_clk_hz; 76}; 77 78/** 79 * struct tegra_vi - NVIDIA Tegra Video Input device structure 80 * 81 * @dev: device struct 82 * @client: host1x_client struct 83 * @iomem: register base 84 * @clk: main clock for VI block 85 * @vdd: vdd regulator for VI hardware, normally it is avdd_dsi_csi 86 * @soc: pointer to SoC data structure 87 * @ops: vi operations 88 * @vi_chans: list head for VI channels 89 */ 90struct tegra_vi { 91 struct device *dev; 92 struct host1x_client client; 93 void __iomem *iomem; 94 struct clk *clk; 95 struct regulator *vdd; 96 const struct tegra_vi_soc *soc; 97 const struct tegra_vi_ops *ops; 98 struct list_head vi_chans; 99}; 100 101/** 102 * struct tegra_vi_graph_entity - Entity in the video graph 103 * 104 * @asd: subdev asynchronous registration information 105 * @entity: media entity from the corresponding V4L2 subdev 106 * @subdev: V4L2 subdev 107 */ 108struct tegra_vi_graph_entity { 109 struct v4l2_async_subdev asd; 110 struct media_entity *entity; 111 struct v4l2_subdev *subdev; 112}; 113 114/** 115 * struct tegra_vi_channel - Tegra video channel 116 * 117 * @list: list head for this entry 118 * @video: V4L2 video device associated with the video channel 119 * @video_lock: protects the @format and @queue fields 120 * @pad: media pad for the video device entity 121 * 122 * @vi: Tegra video input device structure 123 * @frame_start_sp: host1x syncpoint pointer to synchronize programmed capture 124 * start condition with hardware frame start events through host1x 125 * syncpoint counters. 126 * @mw_ack_sp: host1x syncpoint pointer to synchronize programmed memory write 127 * ack trigger condition with hardware memory write done at end of 128 * frame through host1x syncpoint counters. 129 * @sp_incr_lock: protects cpu syncpoint increment. 130 * 131 * @kthread_start_capture: kthread to start capture of single frame when 132 * vb buffer is available. This thread programs VI CSI hardware 133 * for single frame capture and waits for frame start event from 134 * the hardware. On receiving frame start event, it wakes up 135 * kthread_finish_capture thread to wait for finishing frame data 136 * write to the memory. In case of missing frame start event, this 137 * thread returns buffer back to vb with VB2_BUF_STATE_ERROR. 138 * @start_wait: waitqueue for starting frame capture when buffer is available. 139 * @kthread_finish_capture: kthread to finish the buffer capture and return to. 140 * This thread is woken up by kthread_start_capture on receiving 141 * frame start event from the hardware and this thread waits for 142 * MW_ACK_DONE event which indicates completion of writing frame 143 * data to the memory. On receiving MW_ACK_DONE event, buffer is 144 * returned back to vb with VB2_BUF_STATE_DONE and in case of 145 * missing MW_ACK_DONE event, buffer is returned back to vb with 146 * VB2_BUF_STATE_ERROR. 147 * @done_wait: waitqueue for finishing capture data writes to memory. 148 * 149 * @format: active V4L2 pixel format 150 * @fmtinfo: format information corresponding to the active @format 151 * @queue: vb2 buffers queue 152 * @sequence: V4L2 buffers sequence number 153 * 154 * @capture: list of queued buffers for capture 155 * @start_lock: protects the capture queued list 156 * @done: list of capture done queued buffers 157 * @done_lock: protects the capture done queue list 158 * 159 * @portnos: VI channel port numbers 160 * @totalports: total number of ports used for this channel 161 * @numgangports: number of ports combined together as a gang for capture 162 * @of_node: device node of VI channel 163 * 164 * @ctrl_handler: V4L2 control handler of this video channel 165 * @syncpt_timeout_retry: syncpt timeout retry count for the capture 166 * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats 167 * @tpg_fmts_bitmap: a bitmap for supported TPG formats 168 * @pg_mode: test pattern generator mode (disabled/direct/patch) 169 * @notifier: V4L2 asynchronous subdevs notifier 170 */ 171struct tegra_vi_channel { 172 struct list_head list; 173 struct video_device video; 174 /* protects the @format and @queue fields */ 175 struct mutex video_lock; 176 struct media_pad pad; 177 178 struct tegra_vi *vi; 179 struct host1x_syncpt *frame_start_sp[GANG_PORTS_MAX]; 180 struct host1x_syncpt *mw_ack_sp[GANG_PORTS_MAX]; 181 /* protects the cpu syncpoint increment */ 182 spinlock_t sp_incr_lock[GANG_PORTS_MAX]; 183 184 struct task_struct *kthread_start_capture; 185 wait_queue_head_t start_wait; 186 struct task_struct *kthread_finish_capture; 187 wait_queue_head_t done_wait; 188 189 struct v4l2_pix_format format; 190 const struct tegra_video_format *fmtinfo; 191 struct vb2_queue queue; 192 u32 sequence; 193 194 struct list_head capture; 195 /* protects the capture queued list */ 196 spinlock_t start_lock; 197 struct list_head done; 198 /* protects the capture done queue list */ 199 spinlock_t done_lock; 200 201 unsigned char portnos[GANG_PORTS_MAX]; 202 u8 totalports; 203 u8 numgangports; 204 struct device_node *of_node; 205 206 struct v4l2_ctrl_handler ctrl_handler; 207 unsigned int syncpt_timeout_retry; 208 DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); 209 DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); 210 enum tegra_vi_pg_mode pg_mode; 211 212 struct v4l2_async_notifier notifier; 213}; 214 215/** 216 * struct tegra_channel_buffer - video channel buffer 217 * 218 * @buf: vb2 buffer base object 219 * @queue: buffer list entry in the channel queued buffers list 220 * @chan: channel that uses the buffer 221 * @addr: Tegra IOVA buffer address for VI output 222 * @mw_ack_sp_thresh: MW_ACK_DONE syncpoint threshold corresponding 223 * to the capture buffer. 224 */ 225struct tegra_channel_buffer { 226 struct vb2_v4l2_buffer buf; 227 struct list_head queue; 228 struct tegra_vi_channel *chan; 229 dma_addr_t addr; 230 u32 mw_ack_sp_thresh[GANG_PORTS_MAX]; 231}; 232 233/* 234 * VI channel input data type enum. 235 * These data type enum value gets programmed into corresponding Tegra VI 236 * channel register bits. 237 */ 238enum tegra_image_dt { 239 TEGRA_IMAGE_DT_YUV420_8 = 24, 240 TEGRA_IMAGE_DT_YUV420_10, 241 242 TEGRA_IMAGE_DT_YUV420CSPS_8 = 28, 243 TEGRA_IMAGE_DT_YUV420CSPS_10, 244 TEGRA_IMAGE_DT_YUV422_8, 245 TEGRA_IMAGE_DT_YUV422_10, 246 TEGRA_IMAGE_DT_RGB444, 247 TEGRA_IMAGE_DT_RGB555, 248 TEGRA_IMAGE_DT_RGB565, 249 TEGRA_IMAGE_DT_RGB666, 250 TEGRA_IMAGE_DT_RGB888, 251 252 TEGRA_IMAGE_DT_RAW6 = 40, 253 TEGRA_IMAGE_DT_RAW7, 254 TEGRA_IMAGE_DT_RAW8, 255 TEGRA_IMAGE_DT_RAW10, 256 TEGRA_IMAGE_DT_RAW12, 257 TEGRA_IMAGE_DT_RAW14, 258}; 259 260/** 261 * struct tegra_video_format - Tegra video format description 262 * 263 * @img_dt: image data type 264 * @bit_width: format width in bits per component 265 * @code: media bus format code 266 * @bpp: bytes per pixel (when stored in memory) 267 * @img_fmt: image format 268 * @fourcc: V4L2 pixel format FCC identifier 269 */ 270struct tegra_video_format { 271 enum tegra_image_dt img_dt; 272 unsigned int bit_width; 273 unsigned int code; 274 unsigned int bpp; 275 u32 img_fmt; 276 u32 fourcc; 277}; 278 279#if defined(CONFIG_ARCH_TEGRA_210_SOC) 280extern const struct tegra_vi_soc tegra210_vi_soc; 281#endif 282 283struct v4l2_subdev * 284tegra_channel_get_remote_csi_subdev(struct tegra_vi_channel *chan); 285struct v4l2_subdev * 286tegra_channel_get_remote_source_subdev(struct tegra_vi_channel *chan); 287int tegra_channel_set_stream(struct tegra_vi_channel *chan, bool on); 288void tegra_channel_release_buffers(struct tegra_vi_channel *chan, 289 enum vb2_buffer_state state); 290void tegra_channels_cleanup(struct tegra_vi *vi); 291#endif 292