1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Octeon HCD hardware register definitions. 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * Some parts of the code were originally released under BSD license: 10 * 11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 12 * reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: 17 * 18 * * Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 21 * * Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials provided 24 * with the distribution. 25 * 26 * * Neither the name of Cavium Networks nor the names of 27 * its contributors may be used to endorse or promote products 28 * derived from this software without specific prior written 29 * permission. 30 * 31 * This Software, including technical data, may be subject to U.S. export 32 * control laws, including the U.S. Export Administration Act and its associated 33 * regulations, and may be subject to export or import regulations in other 34 * countries. 35 * 36 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 37 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 38 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 39 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION 40 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 41 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 42 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 43 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 44 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 45 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 46 */ 47 48#ifndef __OCTEON_HCD_H__ 49#define __OCTEON_HCD_H__ 50 51#include <asm/bitfield.h> 52 53#define CVMX_USBCXBASE 0x00016F0010000000ull 54#define CVMX_USBCXREG1(reg, bid) \ 55 (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \ 56 ((bid) & 1) * 0x100000000000ull) 57#define CVMX_USBCXREG2(reg, bid, off) \ 58 (CVMX_ADD_IO_SEG(CVMX_USBCXBASE | reg) + \ 59 (((off) & 7) + ((bid) & 1) * 0x8000000000ull) * 32) 60 61#define CVMX_USBCX_GAHBCFG(bid) CVMX_USBCXREG1(0x008, bid) 62#define CVMX_USBCX_GHWCFG3(bid) CVMX_USBCXREG1(0x04c, bid) 63#define CVMX_USBCX_GINTMSK(bid) CVMX_USBCXREG1(0x018, bid) 64#define CVMX_USBCX_GINTSTS(bid) CVMX_USBCXREG1(0x014, bid) 65#define CVMX_USBCX_GNPTXFSIZ(bid) CVMX_USBCXREG1(0x028, bid) 66#define CVMX_USBCX_GNPTXSTS(bid) CVMX_USBCXREG1(0x02c, bid) 67#define CVMX_USBCX_GOTGCTL(bid) CVMX_USBCXREG1(0x000, bid) 68#define CVMX_USBCX_GRSTCTL(bid) CVMX_USBCXREG1(0x010, bid) 69#define CVMX_USBCX_GRXFSIZ(bid) CVMX_USBCXREG1(0x024, bid) 70#define CVMX_USBCX_GRXSTSPH(bid) CVMX_USBCXREG1(0x020, bid) 71#define CVMX_USBCX_GUSBCFG(bid) CVMX_USBCXREG1(0x00c, bid) 72#define CVMX_USBCX_HAINT(bid) CVMX_USBCXREG1(0x414, bid) 73#define CVMX_USBCX_HAINTMSK(bid) CVMX_USBCXREG1(0x418, bid) 74#define CVMX_USBCX_HCCHARX(off, bid) CVMX_USBCXREG2(0x500, bid, off) 75#define CVMX_USBCX_HCFG(bid) CVMX_USBCXREG1(0x400, bid) 76#define CVMX_USBCX_HCINTMSKX(off, bid) CVMX_USBCXREG2(0x50c, bid, off) 77#define CVMX_USBCX_HCINTX(off, bid) CVMX_USBCXREG2(0x508, bid, off) 78#define CVMX_USBCX_HCSPLTX(off, bid) CVMX_USBCXREG2(0x504, bid, off) 79#define CVMX_USBCX_HCTSIZX(off, bid) CVMX_USBCXREG2(0x510, bid, off) 80#define CVMX_USBCX_HFIR(bid) CVMX_USBCXREG1(0x404, bid) 81#define CVMX_USBCX_HFNUM(bid) CVMX_USBCXREG1(0x408, bid) 82#define CVMX_USBCX_HPRT(bid) CVMX_USBCXREG1(0x440, bid) 83#define CVMX_USBCX_HPTXFSIZ(bid) CVMX_USBCXREG1(0x100, bid) 84#define CVMX_USBCX_HPTXSTS(bid) CVMX_USBCXREG1(0x410, bid) 85 86#define CVMX_USBNXBID1(bid) (((bid) & 1) * 0x10000000ull) 87#define CVMX_USBNXBID2(bid) (((bid) & 1) * 0x100000000000ull) 88 89#define CVMX_USBNXREG1(reg, bid) \ 90 (CVMX_ADD_IO_SEG(0x0001180068000000ull | reg) + CVMX_USBNXBID1(bid)) 91#define CVMX_USBNXREG2(reg, bid) \ 92 (CVMX_ADD_IO_SEG(0x00016F0000000000ull | reg) + CVMX_USBNXBID2(bid)) 93 94#define CVMX_USBNX_CLK_CTL(bid) CVMX_USBNXREG1(0x10, bid) 95#define CVMX_USBNX_DMA0_INB_CHN0(bid) CVMX_USBNXREG2(0x818, bid) 96#define CVMX_USBNX_DMA0_OUTB_CHN0(bid) CVMX_USBNXREG2(0x858, bid) 97#define CVMX_USBNX_USBP_CTL_STATUS(bid) CVMX_USBNXREG1(0x18, bid) 98 99/** 100 * cvmx_usbc#_gahbcfg 101 * 102 * Core AHB Configuration Register (GAHBCFG) 103 * 104 * This register can be used to configure the core after power-on or a change in 105 * mode of operation. This register mainly contains AHB system-related 106 * configuration parameters. The AHB is the processor interface to the O2P USB 107 * core. In general, software need not know about this interface except to 108 * program the values as specified. 109 * 110 * The application must program this register as part of the O2P USB core 111 * initialization. Do not change this register after the initial programming. 112 */ 113union cvmx_usbcx_gahbcfg { 114 u32 u32; 115 /** 116 * struct cvmx_usbcx_gahbcfg_s 117 * @ptxfemplvl: Periodic TxFIFO Empty Level (PTxFEmpLvl) 118 * Software should set this bit to 0x1. 119 * Indicates when the Periodic TxFIFO Empty Interrupt bit in the 120 * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This 121 * bit is used only in Slave mode. 122 * * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic 123 * TxFIFO is half empty 124 * * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic 125 * TxFIFO is completely empty 126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) 127 * Software should set this bit to 0x1. 128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in 129 * the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. 130 * This bit is used only in Slave mode. 131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non- 132 * Periodic TxFIFO is half empty 133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non- 134 * Periodic TxFIFO is completely empty 135 * @dmaen: DMA Enable (DMAEn) 136 * * 1'b0: Core operates in Slave mode 137 * * 1'b1: Core operates in a DMA mode 138 * @hbstlen: Burst Length/Type (HBstLen) 139 * This field has not effect and should be left as 0x0. 140 * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk) 141 * Software should set this field to 0x1. 142 * The application uses this bit to mask or unmask the interrupt 143 * line assertion to itself. Irrespective of this bit's setting, 144 * the interrupt status registers are updated by the core. 145 * * 1'b0: Mask the interrupt assertion to the application. 146 * * 1'b1: Unmask the interrupt assertion to the application. 147 */ 148 struct cvmx_usbcx_gahbcfg_s { 149 __BITFIELD_FIELD(u32 reserved_9_31 : 23, 150 __BITFIELD_FIELD(u32 ptxfemplvl : 1, 151 __BITFIELD_FIELD(u32 nptxfemplvl : 1, 152 __BITFIELD_FIELD(u32 reserved_6_6 : 1, 153 __BITFIELD_FIELD(u32 dmaen : 1, 154 __BITFIELD_FIELD(u32 hbstlen : 4, 155 __BITFIELD_FIELD(u32 glblintrmsk : 1, 156 ;))))))) 157 } s; 158}; 159 160/** 161 * cvmx_usbc#_ghwcfg3 162 * 163 * User HW Config3 Register (GHWCFG3) 164 * 165 * This register contains the configuration options of the O2P USB core. 166 */ 167union cvmx_usbcx_ghwcfg3 { 168 u32 u32; 169 /** 170 * struct cvmx_usbcx_ghwcfg3_s 171 * @dfifodepth: DFIFO Depth (DfifoDepth) 172 * This value is in terms of 32-bit words. 173 * * Minimum value is 32 174 * * Maximum value is 32768 175 * @ahbphysync: AHB and PHY Synchronous (AhbPhySync) 176 * Indicates whether AHB and PHY clocks are synchronous to 177 * each other. 178 * * 1'b0: No 179 * * 1'b1: Yes 180 * This bit is tied to 1. 181 * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType) 182 * * 1'b0: Asynchronous reset is used in the core 183 * * 1'b1: Synchronous reset is used in the core 184 * @optfeature: Optional Features Removed (OptFeature) 185 * Indicates whether the User ID register, GPIO interface ports, 186 * and SOF toggle and counter ports were removed for gate count 187 * optimization. 188 * @vendor_control_interface_support: Vendor Control Interface Support 189 * * 1'b0: Vendor Control Interface is not available on the core. 190 * * 1'b1: Vendor Control Interface is available. 191 * @i2c_selection: I2C Selection 192 * * 1'b0: I2C Interface is not available on the core. 193 * * 1'b1: I2C Interface is available on the core. 194 * @otgen: OTG Function Enabled (OtgEn) 195 * The application uses this bit to indicate the O2P USB core's 196 * OTG capabilities. 197 * * 1'b0: Not OTG capable 198 * * 1'b1: OTG Capable 199 * @pktsizewidth: Width of Packet Size Counters (PktSizeWidth) 200 * * 3'b000: 4 bits 201 * * 3'b001: 5 bits 202 * * 3'b010: 6 bits 203 * * 3'b011: 7 bits 204 * * 3'b100: 8 bits 205 * * 3'b101: 9 bits 206 * * 3'b110: 10 bits 207 * * Others: Reserved 208 * @xfersizewidth: Width of Transfer Size Counters (XferSizeWidth) 209 * * 4'b0000: 11 bits 210 * * 4'b0001: 12 bits 211 * - ... 212 * * 4'b1000: 19 bits 213 * * Others: Reserved 214 */ 215 struct cvmx_usbcx_ghwcfg3_s { 216 __BITFIELD_FIELD(u32 dfifodepth : 16, 217 __BITFIELD_FIELD(u32 reserved_13_15 : 3, 218 __BITFIELD_FIELD(u32 ahbphysync : 1, 219 __BITFIELD_FIELD(u32 rsttype : 1, 220 __BITFIELD_FIELD(u32 optfeature : 1, 221 __BITFIELD_FIELD(u32 vendor_control_interface_support : 1, 222 __BITFIELD_FIELD(u32 i2c_selection : 1, 223 __BITFIELD_FIELD(u32 otgen : 1, 224 __BITFIELD_FIELD(u32 pktsizewidth : 3, 225 __BITFIELD_FIELD(u32 xfersizewidth : 4, 226 ;)))))))))) 227 } s; 228}; 229 230/** 231 * cvmx_usbc#_gintmsk 232 * 233 * Core Interrupt Mask Register (GINTMSK) 234 * 235 * This register works with the Core Interrupt register to interrupt the 236 * application. When an interrupt bit is masked, the interrupt associated with 237 * that bit will not be generated. However, the Core Interrupt (GINTSTS) 238 * register bit corresponding to that interrupt will still be set. 239 * Mask interrupt: 1'b0, Unmask interrupt: 1'b1 240 */ 241union cvmx_usbcx_gintmsk { 242 u32 u32; 243 /** 244 * struct cvmx_usbcx_gintmsk_s 245 * @wkupintmsk: Resume/Remote Wakeup Detected Interrupt Mask 246 * (WkUpIntMsk) 247 * @sessreqintmsk: Session Request/New Session Detected Interrupt Mask 248 * (SessReqIntMsk) 249 * @disconnintmsk: Disconnect Detected Interrupt Mask (DisconnIntMsk) 250 * @conidstschngmsk: Connector ID Status Change Mask (ConIDStsChngMsk) 251 * @ptxfempmsk: Periodic TxFIFO Empty Mask (PTxFEmpMsk) 252 * @hchintmsk: Host Channels Interrupt Mask (HChIntMsk) 253 * @prtintmsk: Host Port Interrupt Mask (PrtIntMsk) 254 * @fetsuspmsk: Data Fetch Suspended Mask (FetSuspMsk) 255 * @incomplpmsk: Incomplete Periodic Transfer Mask (incomplPMsk) 256 * Incomplete Isochronous OUT Transfer Mask 257 * (incompISOOUTMsk) 258 * @incompisoinmsk: Incomplete Isochronous IN Transfer Mask 259 * (incompISOINMsk) 260 * @oepintmsk: OUT Endpoints Interrupt Mask (OEPIntMsk) 261 * @inepintmsk: IN Endpoints Interrupt Mask (INEPIntMsk) 262 * @epmismsk: Endpoint Mismatch Interrupt Mask (EPMisMsk) 263 * @eopfmsk: End of Periodic Frame Interrupt Mask (EOPFMsk) 264 * @isooutdropmsk: Isochronous OUT Packet Dropped Interrupt Mask 265 * (ISOOutDropMsk) 266 * @enumdonemsk: Enumeration Done Mask (EnumDoneMsk) 267 * @usbrstmsk: USB Reset Mask (USBRstMsk) 268 * @usbsuspmsk: USB Suspend Mask (USBSuspMsk) 269 * @erlysuspmsk: Early Suspend Mask (ErlySuspMsk) 270 * @i2cint: I2C Interrupt Mask (I2CINT) 271 * @ulpickintmsk: ULPI Carkit Interrupt Mask (ULPICKINTMsk) 272 * I2C Carkit Interrupt Mask (I2CCKINTMsk) 273 * @goutnakeffmsk: Global OUT NAK Effective Mask (GOUTNakEffMsk) 274 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask 275 * (GINNakEffMsk) 276 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) 277 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk) 278 * @sofmsk: Start of (micro)Frame Mask (SofMsk) 279 * @otgintmsk: OTG Interrupt Mask (OTGIntMsk) 280 * @modemismsk: Mode Mismatch Interrupt Mask (ModeMisMsk) 281 */ 282 struct cvmx_usbcx_gintmsk_s { 283 __BITFIELD_FIELD(u32 wkupintmsk : 1, 284 __BITFIELD_FIELD(u32 sessreqintmsk : 1, 285 __BITFIELD_FIELD(u32 disconnintmsk : 1, 286 __BITFIELD_FIELD(u32 conidstschngmsk : 1, 287 __BITFIELD_FIELD(u32 reserved_27_27 : 1, 288 __BITFIELD_FIELD(u32 ptxfempmsk : 1, 289 __BITFIELD_FIELD(u32 hchintmsk : 1, 290 __BITFIELD_FIELD(u32 prtintmsk : 1, 291 __BITFIELD_FIELD(u32 reserved_23_23 : 1, 292 __BITFIELD_FIELD(u32 fetsuspmsk : 1, 293 __BITFIELD_FIELD(u32 incomplpmsk : 1, 294 __BITFIELD_FIELD(u32 incompisoinmsk : 1, 295 __BITFIELD_FIELD(u32 oepintmsk : 1, 296 __BITFIELD_FIELD(u32 inepintmsk : 1, 297 __BITFIELD_FIELD(u32 epmismsk : 1, 298 __BITFIELD_FIELD(u32 reserved_16_16 : 1, 299 __BITFIELD_FIELD(u32 eopfmsk : 1, 300 __BITFIELD_FIELD(u32 isooutdropmsk : 1, 301 __BITFIELD_FIELD(u32 enumdonemsk : 1, 302 __BITFIELD_FIELD(u32 usbrstmsk : 1, 303 __BITFIELD_FIELD(u32 usbsuspmsk : 1, 304 __BITFIELD_FIELD(u32 erlysuspmsk : 1, 305 __BITFIELD_FIELD(u32 i2cint : 1, 306 __BITFIELD_FIELD(u32 ulpickintmsk : 1, 307 __BITFIELD_FIELD(u32 goutnakeffmsk : 1, 308 __BITFIELD_FIELD(u32 ginnakeffmsk : 1, 309 __BITFIELD_FIELD(u32 nptxfempmsk : 1, 310 __BITFIELD_FIELD(u32 rxflvlmsk : 1, 311 __BITFIELD_FIELD(u32 sofmsk : 1, 312 __BITFIELD_FIELD(u32 otgintmsk : 1, 313 __BITFIELD_FIELD(u32 modemismsk : 1, 314 __BITFIELD_FIELD(u32 reserved_0_0 : 1, 315 ;)))))))))))))))))))))))))))))))) 316 } s; 317}; 318 319/** 320 * cvmx_usbc#_gintsts 321 * 322 * Core Interrupt Register (GINTSTS) 323 * 324 * This register interrupts the application for system-level events in the 325 * current mode of operation (Device mode or Host mode). It is shown in 326 * Interrupt. Some of the bits in this register are valid only in Host mode, 327 * while others are valid in Device mode only. This register also indicates the 328 * current mode of operation. In order to clear the interrupt status bits of 329 * type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status 330 * interrupts are read only; once software reads from or writes to the FIFO 331 * while servicing these interrupts, FIFO interrupt conditions are cleared 332 * automatically. 333 */ 334union cvmx_usbcx_gintsts { 335 u32 u32; 336 /** 337 * struct cvmx_usbcx_gintsts_s 338 * @wkupint: Resume/Remote Wakeup Detected Interrupt (WkUpInt) 339 * In Device mode, this interrupt is asserted when a resume is 340 * detected on the USB. In Host mode, this interrupt is asserted 341 * when a remote wakeup is detected on the USB. 342 * For more information on how to use this interrupt, see "Partial 343 * Power-Down and Clock Gating Programming Model" on 344 * page 353. 345 * @sessreqint: Session Request/New Session Detected Interrupt 346 * (SessReqInt) 347 * In Host mode, this interrupt is asserted when a session request 348 * is detected from the device. In Device mode, this interrupt is 349 * asserted when the utmiotg_bvalid signal goes high. 350 * For more information on how to use this interrupt, see "Partial 351 * Power-Down and Clock Gating Programming Model" on 352 * page 353. 353 * @disconnint: Disconnect Detected Interrupt (DisconnInt) 354 * Asserted when a device disconnect is detected. 355 * @conidstschng: Connector ID Status Change (ConIDStsChng) 356 * The core sets this bit when there is a change in connector ID 357 * status. 358 * @ptxfemp: Periodic TxFIFO Empty (PTxFEmp) 359 * Asserted when the Periodic Transmit FIFO is either half or 360 * completely empty and there is space for at least one entry to be 361 * written in the Periodic Request Queue. The half or completely 362 * empty status is determined by the Periodic TxFIFO Empty Level 363 * bit in the Core AHB Configuration register 364 * (GAHBCFG.PTxFEmpLvl). 365 * @hchint: Host Channels Interrupt (HChInt) 366 * The core sets this bit to indicate that an interrupt is pending 367 * on one of the channels of the core (in Host mode). The 368 * application must read the Host All Channels Interrupt (HAINT) 369 * register to determine the exact number of the channel on which 370 * the interrupt occurred, and then read the corresponding Host 371 * Channel-n Interrupt (HCINTn) register to determine the exact 372 * cause of the interrupt. The application must clear the 373 * appropriate status bit in the HCINTn register to clear this bit. 374 * @prtint: Host Port Interrupt (PrtInt) 375 * The core sets this bit to indicate a change in port status of 376 * one of the O2P USB core ports in Host mode. The application must 377 * read the Host Port Control and Status (HPRT) register to 378 * determine the exact event that caused this interrupt. The 379 * application must clear the appropriate status bit in the Host 380 * Port Control and Status register to clear this bit. 381 * @fetsusp: Data Fetch Suspended (FetSusp) 382 * This interrupt is valid only in DMA mode. This interrupt 383 * indicates that the core has stopped fetching data for IN 384 * endpoints due to the unavailability of TxFIFO space or Request 385 * Queue space. This interrupt is used by the application for an 386 * endpoint mismatch algorithm. 387 * @incomplp: Incomplete Periodic Transfer (incomplP) 388 * In Host mode, the core sets this interrupt bit when there are 389 * incomplete periodic transactions still pending which are 390 * scheduled for the current microframe. 391 * Incomplete Isochronous OUT Transfer (incompISOOUT) 392 * The Device mode, the core sets this interrupt to indicate that 393 * there is at least one isochronous OUT endpoint on which the 394 * transfer is not completed in the current microframe. This 395 * interrupt is asserted along with the End of Periodic Frame 396 * Interrupt (EOPF) bit in this register. 397 * @incompisoin: Incomplete Isochronous IN Transfer (incompISOIN) 398 * The core sets this interrupt to indicate that there is at least 399 * one isochronous IN endpoint on which the transfer is not 400 * completed in the current microframe. This interrupt is asserted 401 * along with the End of Periodic Frame Interrupt (EOPF) bit in 402 * this register. 403 * @oepint: OUT Endpoints Interrupt (OEPInt) 404 * The core sets this bit to indicate that an interrupt is pending 405 * on one of the OUT endpoints of the core (in Device mode). The 406 * application must read the Device All Endpoints Interrupt 407 * (DAINT) register to determine the exact number of the OUT 408 * endpoint on which the interrupt occurred, and then read the 409 * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) 410 * register to determine the exact cause of the interrupt. The 411 * application must clear the appropriate status bit in the 412 * corresponding DOEPINTn register to clear this bit. 413 * @iepint: IN Endpoints Interrupt (IEPInt) 414 * The core sets this bit to indicate that an interrupt is pending 415 * on one of the IN endpoints of the core (in Device mode). The 416 * application must read the Device All Endpoints Interrupt 417 * (DAINT) register to determine the exact number of the IN 418 * endpoint on which the interrupt occurred, and then read the 419 * corresponding Device IN Endpoint-n Interrupt (DIEPINTn) 420 * register to determine the exact cause of the interrupt. The 421 * application must clear the appropriate status bit in the 422 * corresponding DIEPINTn register to clear this bit. 423 * @epmis: Endpoint Mismatch Interrupt (EPMis) 424 * Indicates that an IN token has been received for a non-periodic 425 * endpoint, but the data for another endpoint is present in the 426 * top of the Non-Periodic Transmit FIFO and the IN endpoint 427 * mismatch count programmed by the application has expired. 428 * @eopf: End of Periodic Frame Interrupt (EOPF) 429 * Indicates that the period specified in the Periodic Frame 430 * Interval field of the Device Configuration register 431 * (DCFG.PerFrInt) has been reached in the current microframe. 432 * @isooutdrop: Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) 433 * The core sets this bit when it fails to write an isochronous OUT 434 * packet into the RxFIFO because the RxFIFO doesn't have 435 * enough space to accommodate a maximum packet size packet 436 * for the isochronous OUT endpoint. 437 * @enumdone: Enumeration Done (EnumDone) 438 * The core sets this bit to indicate that speed enumeration is 439 * complete. The application must read the Device Status (DSTS) 440 * register to obtain the enumerated speed. 441 * @usbrst: USB Reset (USBRst) 442 * The core sets this bit to indicate that a reset is detected on 443 * the USB. 444 * @usbsusp: USB Suspend (USBSusp) 445 * The core sets this bit to indicate that a suspend was detected 446 * on the USB. The core enters the Suspended state when there 447 * is no activity on the phy_line_state_i signal for an extended 448 * period of time. 449 * @erlysusp: Early Suspend (ErlySusp) 450 * The core sets this bit to indicate that an Idle state has been 451 * detected on the USB for 3 ms. 452 * @i2cint: I2C Interrupt (I2CINT) 453 * This bit is always 0x0. 454 * @ulpickint: ULPI Carkit Interrupt (ULPICKINT) 455 * This bit is always 0x0. 456 * @goutnakeff: Global OUT NAK Effective (GOUTNakEff) 457 * Indicates that the Set Global OUT NAK bit in the Device Control 458 * register (DCTL.SGOUTNak), set by the application, has taken 459 * effect in the core. This bit can be cleared by writing the Clear 460 * Global OUT NAK bit in the Device Control register 461 * (DCTL.CGOUTNak). 462 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff) 463 * Indicates that the Set Global Non-Periodic IN NAK bit in the 464 * Device Control register (DCTL.SGNPInNak), set by the 465 * application, has taken effect in the core. That is, the core has 466 * sampled the Global IN NAK bit set by the application. This bit 467 * can be cleared by clearing the Clear Global Non-Periodic IN 468 * NAK bit in the Device Control register (DCTL.CGNPInNak). 469 * This interrupt does not necessarily mean that a NAK handshake 470 * is sent out on the USB. The STALL bit takes precedence over 471 * the NAK bit. 472 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp) 473 * This interrupt is asserted when the Non-Periodic TxFIFO is 474 * either half or completely empty, and there is space for at least 475 * one entry to be written to the Non-Periodic Transmit Request 476 * Queue. The half or completely empty status is determined by 477 * the Non-Periodic TxFIFO Empty Level bit in the Core AHB 478 * Configuration register (GAHBCFG.NPTxFEmpLvl). 479 * @rxflvl: RxFIFO Non-Empty (RxFLvl) 480 * Indicates that there is at least one packet pending to be read 481 * from the RxFIFO. 482 * @sof: Start of (micro)Frame (Sof) 483 * In Host mode, the core sets this bit to indicate that an SOF 484 * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the 485 * USB. The application must write a 1 to this bit to clear the 486 * interrupt. 487 * In Device mode, in the core sets this bit to indicate that an 488 * SOF token has been received on the USB. The application can read 489 * the Device Status register to get the current (micro)frame 490 * number. This interrupt is seen only when the core is operating 491 * at either HS or FS. 492 * @otgint: OTG Interrupt (OTGInt) 493 * The core sets this bit to indicate an OTG protocol event. The 494 * application must read the OTG Interrupt Status (GOTGINT) 495 * register to determine the exact event that caused this 496 * interrupt. The application must clear the appropriate status bit 497 * in the GOTGINT register to clear this bit. 498 * @modemis: Mode Mismatch Interrupt (ModeMis) 499 * The core sets this bit when the application is trying to access: 500 * * A Host mode register, when the core is operating in Device 501 * mode 502 * * A Device mode register, when the core is operating in Host 503 * mode 504 * The register access is completed on the AHB with an OKAY 505 * response, but is ignored by the core internally and doesn't 506 * affect the operation of the core. 507 * @curmod: Current Mode of Operation (CurMod) 508 * Indicates the current mode of operation. 509 * * 1'b0: Device mode 510 * * 1'b1: Host mode 511 */ 512 struct cvmx_usbcx_gintsts_s { 513 __BITFIELD_FIELD(u32 wkupint : 1, 514 __BITFIELD_FIELD(u32 sessreqint : 1, 515 __BITFIELD_FIELD(u32 disconnint : 1, 516 __BITFIELD_FIELD(u32 conidstschng : 1, 517 __BITFIELD_FIELD(u32 reserved_27_27 : 1, 518 __BITFIELD_FIELD(u32 ptxfemp : 1, 519 __BITFIELD_FIELD(u32 hchint : 1, 520 __BITFIELD_FIELD(u32 prtint : 1, 521 __BITFIELD_FIELD(u32 reserved_23_23 : 1, 522 __BITFIELD_FIELD(u32 fetsusp : 1, 523 __BITFIELD_FIELD(u32 incomplp : 1, 524 __BITFIELD_FIELD(u32 incompisoin : 1, 525 __BITFIELD_FIELD(u32 oepint : 1, 526 __BITFIELD_FIELD(u32 iepint : 1, 527 __BITFIELD_FIELD(u32 epmis : 1, 528 __BITFIELD_FIELD(u32 reserved_16_16 : 1, 529 __BITFIELD_FIELD(u32 eopf : 1, 530 __BITFIELD_FIELD(u32 isooutdrop : 1, 531 __BITFIELD_FIELD(u32 enumdone : 1, 532 __BITFIELD_FIELD(u32 usbrst : 1, 533 __BITFIELD_FIELD(u32 usbsusp : 1, 534 __BITFIELD_FIELD(u32 erlysusp : 1, 535 __BITFIELD_FIELD(u32 i2cint : 1, 536 __BITFIELD_FIELD(u32 ulpickint : 1, 537 __BITFIELD_FIELD(u32 goutnakeff : 1, 538 __BITFIELD_FIELD(u32 ginnakeff : 1, 539 __BITFIELD_FIELD(u32 nptxfemp : 1, 540 __BITFIELD_FIELD(u32 rxflvl : 1, 541 __BITFIELD_FIELD(u32 sof : 1, 542 __BITFIELD_FIELD(u32 otgint : 1, 543 __BITFIELD_FIELD(u32 modemis : 1, 544 __BITFIELD_FIELD(u32 curmod : 1, 545 ;)))))))))))))))))))))))))))))))) 546 } s; 547}; 548 549/** 550 * cvmx_usbc#_gnptxfsiz 551 * 552 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ) 553 * 554 * The application can program the RAM size and the memory start address for the 555 * Non-Periodic TxFIFO. 556 */ 557union cvmx_usbcx_gnptxfsiz { 558 u32 u32; 559 /** 560 * struct cvmx_usbcx_gnptxfsiz_s 561 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep) 562 * This value is in terms of 32-bit words. 563 * Minimum value is 16 564 * Maximum value is 32768 565 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr) 566 * This field contains the memory start address for Non-Periodic 567 * Transmit FIFO RAM. 568 */ 569 struct cvmx_usbcx_gnptxfsiz_s { 570 __BITFIELD_FIELD(u32 nptxfdep : 16, 571 __BITFIELD_FIELD(u32 nptxfstaddr : 16, 572 ;)) 573 } s; 574}; 575 576/** 577 * cvmx_usbc#_gnptxsts 578 * 579 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS) 580 * 581 * This read-only register contains the free space information for the 582 * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue. 583 */ 584union cvmx_usbcx_gnptxsts { 585 u32 u32; 586 /** 587 * struct cvmx_usbcx_gnptxsts_s 588 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop) 589 * Entry in the Non-Periodic Tx Request Queue that is currently 590 * being processed by the MAC. 591 * * Bits [30:27]: Channel/endpoint number 592 * * Bits [26:25]: 593 * - 2'b00: IN/OUT token 594 * - 2'b01: Zero-length transmit packet (device IN/host OUT) 595 * - 2'b10: PING/CSPLIT token 596 * - 2'b11: Channel halt command 597 * * Bit [24]: Terminate (last entry for selected channel/endpoint) 598 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available 599 * (NPTxQSpcAvail) 600 * Indicates the amount of free space available in the Non- 601 * Periodic Transmit Request Queue. This queue holds both IN 602 * and OUT requests in Host mode. Device mode has only IN 603 * requests. 604 * * 8'h0: Non-Periodic Transmit Request Queue is full 605 * * 8'h1: 1 location available 606 * * 8'h2: 2 locations available 607 * * n: n locations available (0..8) 608 * * Others: Reserved 609 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail) 610 * Indicates the amount of free space available in the Non- 611 * Periodic TxFIFO. 612 * Values are in terms of 32-bit words. 613 * * 16'h0: Non-Periodic TxFIFO is full 614 * * 16'h1: 1 word available 615 * * 16'h2: 2 words available 616 * * 16'hn: n words available (where 0..32768) 617 * * 16'h8000: 32768 words available 618 * * Others: Reserved 619 */ 620 struct cvmx_usbcx_gnptxsts_s { 621 __BITFIELD_FIELD(u32 reserved_31_31 : 1, 622 __BITFIELD_FIELD(u32 nptxqtop : 7, 623 __BITFIELD_FIELD(u32 nptxqspcavail : 8, 624 __BITFIELD_FIELD(u32 nptxfspcavail : 16, 625 ;)))) 626 } s; 627}; 628 629/** 630 * cvmx_usbc#_grstctl 631 * 632 * Core Reset Register (GRSTCTL) 633 * 634 * The application uses this register to reset various hardware features inside 635 * the core. 636 */ 637union cvmx_usbcx_grstctl { 638 u32 u32; 639 /** 640 * struct cvmx_usbcx_grstctl_s 641 * @ahbidle: AHB Master Idle (AHBIdle) 642 * Indicates that the AHB Master State Machine is in the IDLE 643 * condition. 644 * @dmareq: DMA Request Signal (DMAReq) 645 * Indicates that the DMA request is in progress. Used for debug. 646 * @txfnum: TxFIFO Number (TxFNum) 647 * This is the FIFO number that must be flushed using the TxFIFO 648 * Flush bit. This field must not be changed until the core clears 649 * the TxFIFO Flush bit. 650 * * 5'h0: Non-Periodic TxFIFO flush 651 * * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic 652 * TxFIFO flush in Host mode 653 * * 5'h2: Periodic TxFIFO 2 flush in Device mode 654 * - ... 655 * * 5'hF: Periodic TxFIFO 15 flush in Device mode 656 * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the 657 * core 658 * @txfflsh: TxFIFO Flush (TxFFlsh) 659 * This bit selectively flushes a single or all transmit FIFOs, but 660 * cannot do so if the core is in the midst of a transaction. 661 * The application must only write this bit after checking that the 662 * core is neither writing to the TxFIFO nor reading from the 663 * TxFIFO. 664 * The application must wait until the core clears this bit before 665 * performing any operations. This bit takes 8 clocks (of phy_clk 666 * or hclk, whichever is slower) to clear. 667 * @rxfflsh: RxFIFO Flush (RxFFlsh) 668 * The application can flush the entire RxFIFO using this bit, but 669 * must first ensure that the core is not in the middle of a 670 * transaction. 671 * The application must only write to this bit after checking that 672 * the core is neither reading from the RxFIFO nor writing to the 673 * RxFIFO. 674 * The application must wait until the bit is cleared before 675 * performing any other operations. This bit will take 8 clocks 676 * (slowest of PHY or AHB clock) to clear. 677 * @intknqflsh: IN Token Sequence Learning Queue Flush (INTknQFlsh) 678 * The application writes this bit to flush the IN Token Sequence 679 * Learning Queue. 680 * @frmcntrrst: Host Frame Counter Reset (FrmCntrRst) 681 * The application writes this bit to reset the (micro)frame number 682 * counter inside the core. When the (micro)frame counter is reset, 683 * the subsequent SOF sent out by the core will have a 684 * (micro)frame number of 0. 685 * @hsftrst: HClk Soft Reset (HSftRst) 686 * The application uses this bit to flush the control logic in the 687 * AHB Clock domain. Only AHB Clock Domain pipelines are reset. 688 * * FIFOs are not flushed with this bit. 689 * * All state machines in the AHB clock domain are reset to the 690 * Idle state after terminating the transactions on the AHB, 691 * following the protocol. 692 * * CSR control bits used by the AHB clock domain state 693 * machines are cleared. 694 * * To clear this interrupt, status mask bits that control the 695 * interrupt status and are generated by the AHB clock domain 696 * state machine are cleared. 697 * * Because interrupt status bits are not cleared, the application 698 * can get the status of any core events that occurred after it set 699 * this bit. 700 * This is a self-clearing bit that the core clears after all 701 * necessary logic is reset in the core. This may take several 702 * clocks, depending on the core's current state. 703 * @csftrst: Core Soft Reset (CSftRst) 704 * Resets the hclk and phy_clock domains as follows: 705 * * Clears the interrupts and all the CSR registers except the 706 * following register bits: 707 * - PCGCCTL.RstPdwnModule 708 * - PCGCCTL.GateHclk 709 * - PCGCCTL.PwrClmp 710 * - PCGCCTL.StopPPhyLPwrClkSelclk 711 * - GUSBCFG.PhyLPwrClkSel 712 * - GUSBCFG.DDRSel 713 * - GUSBCFG.PHYSel 714 * - GUSBCFG.FSIntf 715 * - GUSBCFG.ULPI_UTMI_Sel 716 * - GUSBCFG.PHYIf 717 * - HCFG.FSLSPclkSel 718 * - DCFG.DevSpd 719 * * All module state machines (except the AHB Slave Unit) are 720 * reset to the IDLE state, and all the transmit FIFOs and the 721 * receive FIFO are flushed. 722 * * Any transactions on the AHB Master are terminated as soon 723 * as possible, after gracefully completing the last data phase of 724 * an AHB transfer. Any transactions on the USB are terminated 725 * immediately. 726 * The application can write to this bit any time it wants to reset 727 * the core. This is a self-clearing bit and the core clears this 728 * bit after all the necessary logic is reset in the core, which 729 * may take several clocks, depending on the current state of the 730 * core. Once this bit is cleared software should wait at least 3 731 * PHY clocks before doing any access to the PHY domain 732 * (synchronization delay). Software should also should check that 733 * bit 31 of this register is 1 (AHB Master is IDLE) before 734 * starting any operation. 735 * Typically software reset is used during software development 736 * and also when you dynamically change the PHY selection bits 737 * in the USB configuration registers listed above. When you 738 * change the PHY, the corresponding clock for the PHY is 739 * selected and used in the PHY domain. Once a new clock is 740 * selected, the PHY domain has to be reset for proper operation. 741 */ 742 struct cvmx_usbcx_grstctl_s { 743 __BITFIELD_FIELD(u32 ahbidle : 1, 744 __BITFIELD_FIELD(u32 dmareq : 1, 745 __BITFIELD_FIELD(u32 reserved_11_29 : 19, 746 __BITFIELD_FIELD(u32 txfnum : 5, 747 __BITFIELD_FIELD(u32 txfflsh : 1, 748 __BITFIELD_FIELD(u32 rxfflsh : 1, 749 __BITFIELD_FIELD(u32 intknqflsh : 1, 750 __BITFIELD_FIELD(u32 frmcntrrst : 1, 751 __BITFIELD_FIELD(u32 hsftrst : 1, 752 __BITFIELD_FIELD(u32 csftrst : 1, 753 ;)))))))))) 754 } s; 755}; 756 757/** 758 * cvmx_usbc#_grxfsiz 759 * 760 * Receive FIFO Size Register (GRXFSIZ) 761 * 762 * The application can program the RAM size that must be allocated to the 763 * RxFIFO. 764 */ 765union cvmx_usbcx_grxfsiz { 766 u32 u32; 767 /** 768 * struct cvmx_usbcx_grxfsiz_s 769 * @rxfdep: RxFIFO Depth (RxFDep) 770 * This value is in terms of 32-bit words. 771 * * Minimum value is 16 772 * * Maximum value is 32768 773 */ 774 struct cvmx_usbcx_grxfsiz_s { 775 __BITFIELD_FIELD(u32 reserved_16_31 : 16, 776 __BITFIELD_FIELD(u32 rxfdep : 16, 777 ;)) 778 } s; 779}; 780 781/** 782 * cvmx_usbc#_grxstsph 783 * 784 * Receive Status Read and Pop Register, Host Mode (GRXSTSPH) 785 * 786 * A read to the Receive Status Read and Pop register returns and additionally 787 * pops the top data entry out of the RxFIFO. 788 * This Description is only valid when the core is in Host Mode. For Device Mode 789 * use USBC_GRXSTSPD instead. 790 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the 791 * same offset in the O2P USB core. The offset difference shown in this 792 * document is for software clarity and is actually ignored by the 793 * hardware. 794 */ 795union cvmx_usbcx_grxstsph { 796 u32 u32; 797 /** 798 * struct cvmx_usbcx_grxstsph_s 799 * @pktsts: Packet Status (PktSts) 800 * Indicates the status of the received packet 801 * * 4'b0010: IN data packet received 802 * * 4'b0011: IN transfer completed (triggers an interrupt) 803 * * 4'b0101: Data toggle error (triggers an interrupt) 804 * * 4'b0111: Channel halted (triggers an interrupt) 805 * * Others: Reserved 806 * @dpid: Data PID (DPID) 807 * * 2'b00: DATA0 808 * * 2'b10: DATA1 809 * * 2'b01: DATA2 810 * * 2'b11: MDATA 811 * @bcnt: Byte Count (BCnt) 812 * Indicates the byte count of the received IN data packet 813 * @chnum: Channel Number (ChNum) 814 * Indicates the channel number to which the current received 815 * packet belongs. 816 */ 817 struct cvmx_usbcx_grxstsph_s { 818 __BITFIELD_FIELD(u32 reserved_21_31 : 11, 819 __BITFIELD_FIELD(u32 pktsts : 4, 820 __BITFIELD_FIELD(u32 dpid : 2, 821 __BITFIELD_FIELD(u32 bcnt : 11, 822 __BITFIELD_FIELD(u32 chnum : 4, 823 ;))))) 824 } s; 825}; 826 827/** 828 * cvmx_usbc#_gusbcfg 829 * 830 * Core USB Configuration Register (GUSBCFG) 831 * 832 * This register can be used to configure the core after power-on or a changing 833 * to Host mode or Device mode. It contains USB and USB-PHY related 834 * configuration parameters. The application must program this register before 835 * starting any transactions on either the AHB or the USB. Do not make changes 836 * to this register after the initial programming. 837 */ 838union cvmx_usbcx_gusbcfg { 839 u32 u32; 840 /** 841 * struct cvmx_usbcx_gusbcfg_s 842 * @otgi2csel: UTMIFS or I2C Interface Select (OtgI2CSel) 843 * This bit is always 0x0. 844 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel) 845 * Software should set this bit to 0x0. 846 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In 847 * FS and LS modes, the PHY can usually operate on a 48-MHz 848 * clock to save power. 849 * * 1'b0: 480-MHz Internal PLL clock 850 * * 1'b1: 48-MHz External Clock 851 * In 480 MHz mode, the UTMI interface operates at either 60 or 852 * 30-MHz, depending upon whether 8- or 16-bit data width is 853 * selected. In 48-MHz mode, the UTMI interface operates at 48 854 * MHz in FS mode and at either 48 or 6 MHz in LS mode 855 * (depending on the PHY vendor). 856 * This bit drives the utmi_fsls_low_power core output signal, and 857 * is valid only for UTMI+ PHYs. 858 * @usbtrdtim: USB Turnaround Time (USBTrdTim) 859 * Sets the turnaround time in PHY clocks. 860 * Specifies the response time for a MAC request to the Packet 861 * FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). 862 * This must be programmed to 0x5. 863 * @hnpcap: HNP-Capable (HNPCap) 864 * This bit is always 0x0. 865 * @srpcap: SRP-Capable (SRPCap) 866 * This bit is always 0x0. 867 * @ddrsel: ULPI DDR Select (DDRSel) 868 * Software should set this bit to 0x0. 869 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial 870 * Software should set this bit to 0x0. 871 * @fsintf: Full-Speed Serial Interface Select (FSIntf) 872 * Software should set this bit to 0x0. 873 * @ulpi_utmi_sel: ULPI or UTMI+ Select (ULPI_UTMI_Sel) 874 * This bit is always 0x0. 875 * @phyif: PHY Interface (PHYIf) 876 * This bit is always 0x1. 877 * @toutcal: HS/FS Timeout Calibration (TOutCal) 878 * The number of PHY clocks that the application programs in this 879 * field is added to the high-speed/full-speed interpacket timeout 880 * duration in the core to account for any additional delays 881 * introduced by the PHY. This may be required, since the delay 882 * introduced by the PHY in generating the linestate condition may 883 * vary from one PHY to another. 884 * The USB standard timeout value for high-speed operation is 885 * 736 to 816 (inclusive) bit times. The USB standard timeout 886 * value for full-speed operation is 16 to 18 (inclusive) bit 887 * times. The application must program this field based on the 888 * speed of enumeration. The number of bit times added per PHY 889 * clock are: 890 * High-speed operation: 891 * * One 30-MHz PHY clock = 16 bit times 892 * * One 60-MHz PHY clock = 8 bit times 893 * Full-speed operation: 894 * * One 30-MHz PHY clock = 0.4 bit times 895 * * One 60-MHz PHY clock = 0.2 bit times 896 * * One 48-MHz PHY clock = 0.25 bit times 897 */ 898 struct cvmx_usbcx_gusbcfg_s { 899 __BITFIELD_FIELD(u32 reserved_17_31 : 15, 900 __BITFIELD_FIELD(u32 otgi2csel : 1, 901 __BITFIELD_FIELD(u32 phylpwrclksel : 1, 902 __BITFIELD_FIELD(u32 reserved_14_14 : 1, 903 __BITFIELD_FIELD(u32 usbtrdtim : 4, 904 __BITFIELD_FIELD(u32 hnpcap : 1, 905 __BITFIELD_FIELD(u32 srpcap : 1, 906 __BITFIELD_FIELD(u32 ddrsel : 1, 907 __BITFIELD_FIELD(u32 physel : 1, 908 __BITFIELD_FIELD(u32 fsintf : 1, 909 __BITFIELD_FIELD(u32 ulpi_utmi_sel : 1, 910 __BITFIELD_FIELD(u32 phyif : 1, 911 __BITFIELD_FIELD(u32 toutcal : 3, 912 ;))))))))))))) 913 } s; 914}; 915 916/** 917 * cvmx_usbc#_haint 918 * 919 * Host All Channels Interrupt Register (HAINT) 920 * 921 * When a significant event occurs on a channel, the Host All Channels Interrupt 922 * register interrupts the application using the Host Channels Interrupt bit of 923 * the Core Interrupt register (GINTSTS.HChInt). This is shown in Interrupt. 924 * There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in 925 * this register are set and cleared when the application sets and clears bits 926 * in the corresponding Host Channel-n Interrupt register. 927 */ 928union cvmx_usbcx_haint { 929 u32 u32; 930 /** 931 * struct cvmx_usbcx_haint_s 932 * @haint: Channel Interrupts (HAINT) 933 * One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 934 */ 935 struct cvmx_usbcx_haint_s { 936 __BITFIELD_FIELD(u32 reserved_16_31 : 16, 937 __BITFIELD_FIELD(u32 haint : 16, 938 ;)) 939 } s; 940}; 941 942/** 943 * cvmx_usbc#_haintmsk 944 * 945 * Host All Channels Interrupt Mask Register (HAINTMSK) 946 * 947 * The Host All Channel Interrupt Mask register works with the Host All Channel 948 * Interrupt register to interrupt the application when an event occurs on a 949 * channel. There is one interrupt mask bit per channel, up to a maximum of 16 950 * bits. 951 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 952 */ 953union cvmx_usbcx_haintmsk { 954 u32 u32; 955 /** 956 * struct cvmx_usbcx_haintmsk_s 957 * @haintmsk: Channel Interrupt Mask (HAINTMsk) 958 * One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 959 */ 960 struct cvmx_usbcx_haintmsk_s { 961 __BITFIELD_FIELD(u32 reserved_16_31 : 16, 962 __BITFIELD_FIELD(u32 haintmsk : 16, 963 ;)) 964 } s; 965}; 966 967/** 968 * cvmx_usbc#_hcchar# 969 * 970 * Host Channel-n Characteristics Register (HCCHAR) 971 * 972 */ 973union cvmx_usbcx_hccharx { 974 u32 u32; 975 /** 976 * struct cvmx_usbcx_hccharx_s 977 * @chena: Channel Enable (ChEna) 978 * This field is set by the application and cleared by the OTG 979 * host. 980 * * 1'b0: Channel disabled 981 * * 1'b1: Channel enabled 982 * @chdis: Channel Disable (ChDis) 983 * The application sets this bit to stop transmitting/receiving 984 * data on a channel, even before the transfer for that channel is 985 * complete. The application must wait for the Channel Disabled 986 * interrupt before treating the channel as disabled. 987 * @oddfrm: Odd Frame (OddFrm) 988 * This field is set (reset) by the application to indicate that 989 * the OTG host must perform a transfer in an odd (micro)frame. 990 * This field is applicable for only periodic (isochronous and 991 * interrupt) transactions. 992 * * 1'b0: Even (micro)frame 993 * * 1'b1: Odd (micro)frame 994 * @devaddr: Device Address (DevAddr) 995 * This field selects the specific device serving as the data 996 * source or sink. 997 * @ec: Multi Count (MC) / Error Count (EC) 998 * When the Split Enable bit of the Host Channel-n Split Control 999 * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates 1000 * to the host the number of transactions that should be executed
1001 * per microframe for this endpoint. 1002 * * 2'b00: Reserved. This field yields undefined results. 1003 * * 2'b01: 1 transaction 1004 * * 2'b10: 2 transactions to be issued for this endpoint per 1005 * microframe 1006 * * 2'b11: 3 transactions to be issued for this endpoint per 1007 * microframe 1008 * When HCSPLTn.SpltEna is set (1'b1), this field indicates the 1009 * number of immediate retries to be performed for a periodic split 1010 * transactions on transaction errors. This field must be set to at 1011 * least 2'b01. 1012 * @eptype: Endpoint Type (EPType) 1013 * Indicates the transfer type selected. 1014 * * 2'b00: Control 1015 * * 2'b01: Isochronous 1016 * * 2'b10: Bulk 1017 * * 2'b11: Interrupt 1018 * @lspddev: Low-Speed Device (LSpdDev) 1019 * This field is set by the application to indicate that this 1020 * channel is communicating to a low-speed device. 1021 * @epdir: Endpoint Direction (EPDir) 1022 * Indicates whether the transaction is IN or OUT. 1023 * * 1'b0: OUT 1024 * * 1'b1: IN 1025 * @epnum: Endpoint Number (EPNum) 1026 * Indicates the endpoint number on the device serving as the 1027 * data source or sink. 1028 * @mps: Maximum Packet Size (MPS) 1029 * Indicates the maximum packet size of the associated endpoint. 1030 */ 1031 struct cvmx_usbcx_hccharx_s { 1032 __BITFIELD_FIELD(u32 chena : 1, 1033 __BITFIELD_FIELD(u32 chdis : 1, 1034 __BITFIELD_FIELD(u32 oddfrm : 1, 1035 __BITFIELD_FIELD(u32 devaddr : 7, 1036 __BITFIELD_FIELD(u32 ec : 2, 1037 __BITFIELD_FIELD(u32 eptype : 2, 1038 __BITFIELD_FIELD(u32 lspddev : 1, 1039 __BITFIELD_FIELD(u32 reserved_16_16 : 1, 1040 __BITFIELD_FIELD(u32 epdir : 1, 1041 __BITFIELD_FIELD(u32 epnum : 4, 1042 __BITFIELD_FIELD(u32 mps : 11, 1043 ;))))))))))) 1044 } s; 1045}; 1046 1047/** 1048 * cvmx_usbc#_hcfg 1049 * 1050 * Host Configuration Register (HCFG) 1051 * 1052 * This register configures the core after power-on. Do not make changes to this 1053 * register after initializing the host. 1054 */ 1055union cvmx_usbcx_hcfg { 1056 u32 u32; 1057 /** 1058 * struct cvmx_usbcx_hcfg_s 1059 * @fslssupp: FS- and LS-Only Support (FSLSSupp) 1060 * The application uses this bit to control the core's enumeration 1061 * speed. Using this bit, the application can make the core 1062 * enumerate as a FS host, even if the connected device supports 1063 * HS traffic. Do not make changes to this field after initial 1064 * programming. 1065 * * 1'b0: HS/FS/LS, based on the maximum speed supported by 1066 * the connected device 1067 * * 1'b1: FS/LS-only, even if the connected device can support HS 1068 * @fslspclksel: FS/LS PHY Clock Select (FSLSPclkSel) 1069 * When the core is in FS Host mode 1070 * * 2'b00: PHY clock is running at 30/60 MHz 1071 * * 2'b01: PHY clock is running at 48 MHz 1072 * * Others: Reserved 1073 * When the core is in LS Host mode 1074 * * 2'b00: PHY clock is running at 30/60 MHz. When the 1075 * UTMI+/ULPI PHY Low Power mode is not selected, use 1076 * 30/60 MHz. 1077 * * 2'b01: PHY clock is running at 48 MHz. When the UTMI+ 1078 * PHY Low Power mode is selected, use 48MHz if the PHY 1079 * supplies a 48 MHz clock during LS mode. 1080 * * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, 1081 * use 6 MHz when the UTMI+ PHY Low Power mode is 1082 * selected and the PHY supplies a 6 MHz clock during LS 1083 * mode. If you select a 6 MHz clock during LS mode, you must 1084 * do a soft reset. 1085 * * 2'b11: Reserved 1086 */ 1087 struct cvmx_usbcx_hcfg_s { 1088 __BITFIELD_FIELD(u32 reserved_3_31 : 29, 1089 __BITFIELD_FIELD(u32 fslssupp : 1, 1090 __BITFIELD_FIELD(u32 fslspclksel : 2, 1091 ;))) 1092 } s; 1093}; 1094 1095/** 1096 * cvmx_usbc#_hcint# 1097 * 1098 * Host Channel-n Interrupt Register (HCINT) 1099 * 1100 * This register indicates the status of a channel with respect to USB- and 1101 * AHB-related events. The application must read this register when the Host 1102 * Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is 1103 * set. Before the application can read this register, it must first read 1104 * the Host All Channels Interrupt (HAINT) register to get the exact channel 1105 * number for the Host Channel-n Interrupt register. The application must clear 1106 * the appropriate bit in this register to clear the corresponding bits in the 1107 * HAINT and GINTSTS registers. 1108 */ 1109union cvmx_usbcx_hcintx { 1110 u32 u32; 1111 /** 1112 * struct cvmx_usbcx_hcintx_s 1113 * @datatglerr: Data Toggle Error (DataTglErr) 1114 * @frmovrun: Frame Overrun (FrmOvrun) 1115 * @bblerr: Babble Error (BblErr) 1116 * @xacterr: Transaction Error (XactErr) 1117 * @nyet: NYET Response Received Interrupt (NYET) 1118 * @ack: ACK Response Received Interrupt (ACK) 1119 * @nak: NAK Response Received Interrupt (NAK) 1120 * @stall: STALL Response Received Interrupt (STALL) 1121 * @ahberr: This bit is always 0x0. 1122 * @chhltd: Channel Halted (ChHltd) 1123 * Indicates the transfer completed abnormally either because of 1124 * any USB transaction error or in response to disable request by 1125 * the application. 1126 * @xfercompl: Transfer Completed (XferCompl) 1127 * Transfer completed normally without any errors. 1128 */ 1129 struct cvmx_usbcx_hcintx_s { 1130 __BITFIELD_FIELD(u32 reserved_11_31 : 21, 1131 __BITFIELD_FIELD(u32 datatglerr : 1, 1132 __BITFIELD_FIELD(u32 frmovrun : 1, 1133 __BITFIELD_FIELD(u32 bblerr : 1, 1134 __BITFIELD_FIELD(u32 xacterr : 1, 1135 __BITFIELD_FIELD(u32 nyet : 1, 1136 __BITFIELD_FIELD(u32 ack : 1, 1137 __BITFIELD_FIELD(u32 nak : 1, 1138 __BITFIELD_FIELD(u32 stall : 1, 1139 __BITFIELD_FIELD(u32 ahberr : 1, 1140 __BITFIELD_FIELD(u32 chhltd : 1, 1141 __BITFIELD_FIELD(u32 xfercompl : 1, 1142 ;)))))))))))) 1143 } s; 1144}; 1145 1146/** 1147 * cvmx_usbc#_hcintmsk# 1148 * 1149 * Host Channel-n Interrupt Mask Register (HCINTMSKn) 1150 * 1151 * This register reflects the mask for each channel status described in the 1152 * previous section. 1153 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1 1154 */ 1155union cvmx_usbcx_hcintmskx { 1156 u32 u32; 1157 /** 1158 * struct cvmx_usbcx_hcintmskx_s 1159 * @datatglerrmsk: Data Toggle Error Mask (DataTglErrMsk) 1160 * @frmovrunmsk: Frame Overrun Mask (FrmOvrunMsk) 1161 * @bblerrmsk: Babble Error Mask (BblErrMsk) 1162 * @xacterrmsk: Transaction Error Mask (XactErrMsk) 1163 * @nyetmsk: NYET Response Received Interrupt Mask (NyetMsk) 1164 * @ackmsk: ACK Response Received Interrupt Mask (AckMsk) 1165 * @nakmsk: NAK Response Received Interrupt Mask (NakMsk) 1166 * @stallmsk: STALL Response Received Interrupt Mask (StallMsk) 1167 * @ahberrmsk: AHB Error Mask (AHBErrMsk) 1168 * @chhltdmsk: Channel Halted Mask (ChHltdMsk) 1169 * @xfercomplmsk: Transfer Completed Mask (XferComplMsk) 1170 */ 1171 struct cvmx_usbcx_hcintmskx_s { 1172 __BITFIELD_FIELD(u32 reserved_11_31 : 21, 1173 __BITFIELD_FIELD(u32 datatglerrmsk : 1, 1174 __BITFIELD_FIELD(u32 frmovrunmsk : 1, 1175 __BITFIELD_FIELD(u32 bblerrmsk : 1, 1176 __BITFIELD_FIELD(u32 xacterrmsk : 1, 1177 __BITFIELD_FIELD(u32 nyetmsk : 1, 1178 __BITFIELD_FIELD(u32 ackmsk : 1, 1179 __BITFIELD_FIELD(u32 nakmsk : 1, 1180 __BITFIELD_FIELD(u32 stallmsk : 1, 1181 __BITFIELD_FIELD(u32 ahberrmsk : 1, 1182 __BITFIELD_FIELD(u32 chhltdmsk : 1, 1183 __BITFIELD_FIELD(u32 xfercomplmsk : 1, 1184 ;)))))))))))) 1185 } s; 1186}; 1187 1188/** 1189 * cvmx_usbc#_hcsplt# 1190 * 1191 * Host Channel-n Split Control Register (HCSPLT) 1192 * 1193 */ 1194union cvmx_usbcx_hcspltx { 1195 u32 u32; 1196 /** 1197 * struct cvmx_usbcx_hcspltx_s 1198 * @spltena: Split Enable (SpltEna) 1199 * The application sets this field to indicate that this channel is 1200 * enabled to perform split transactions. 1201 * @compsplt: Do Complete Split (CompSplt) 1202 * The application sets this field to request the OTG host to 1203 * perform a complete split transaction. 1204 * @xactpos: Transaction Position (XactPos) 1205 * This field is used to determine whether to send all, first, 1206 * middle, or last payloads with each OUT transaction. 1207 * * 2'b11: All. This is the entire data payload is of this 1208 * transaction (which is less than or equal to 188 bytes). 1209 * * 2'b10: Begin. This is the first data payload of this 1210 * transaction (which is larger than 188 bytes). 1211 * * 2'b00: Mid. This is the middle payload of this transaction 1212 * (which is larger than 188 bytes). 1213 * * 2'b01: End. This is the last payload of this transaction 1214 * (which is larger than 188 bytes). 1215 * @hubaddr: Hub Address (HubAddr) 1216 * This field holds the device address of the transaction 1217 * translator's hub. 1218 * @prtaddr: Port Address (PrtAddr) 1219 * This field is the port number of the recipient transaction 1220 * translator. 1221 */ 1222 struct cvmx_usbcx_hcspltx_s { 1223 __BITFIELD_FIELD(u32 spltena : 1, 1224 __BITFIELD_FIELD(u32 reserved_17_30 : 14, 1225 __BITFIELD_FIELD(u32 compsplt : 1, 1226 __BITFIELD_FIELD(u32 xactpos : 2, 1227 __BITFIELD_FIELD(u32 hubaddr : 7, 1228 __BITFIELD_FIELD(u32 prtaddr : 7, 1229 ;)))))) 1230 } s; 1231}; 1232 1233/** 1234 * cvmx_usbc#_hctsiz# 1235 * 1236 * Host Channel-n Transfer Size Register (HCTSIZ) 1237 * 1238 */ 1239union cvmx_usbcx_hctsizx { 1240 u32 u32; 1241 /** 1242 * struct cvmx_usbcx_hctsizx_s 1243 * @dopng: Do Ping (DoPng) 1244 * Setting this field to 1 directs the host to do PING protocol. 1245 * @pid: PID (Pid) 1246 * The application programs this field with the type of PID to use 1247 * for the initial transaction. The host will maintain this field 1248 * for the rest of the transfer. 1249 * * 2'b00: DATA0 1250 * * 2'b01: DATA2 1251 * * 2'b10: DATA1 1252 * * 2'b11: MDATA (non-control)/SETUP (control) 1253 * @pktcnt: Packet Count (PktCnt) 1254 * This field is programmed by the application with the expected 1255 * number of packets to be transmitted (OUT) or received (IN). 1256 * The host decrements this count on every successful 1257 * transmission or reception of an OUT/IN packet. Once this count 1258 * reaches zero, the application is interrupted to indicate normal 1259 * completion. 1260 * @xfersize: Transfer Size (XferSize) 1261 * For an OUT, this field is the number of data bytes the host will 1262 * send during the transfer. 1263 * For an IN, this field is the buffer size that the application 1264 * has reserved for the transfer. The application is expected to 1265 * program this field as an integer multiple of the maximum packet 1266 * size for IN transactions (periodic and non-periodic). 1267 */ 1268 struct cvmx_usbcx_hctsizx_s { 1269 __BITFIELD_FIELD(u32 dopng : 1, 1270 __BITFIELD_FIELD(u32 pid : 2, 1271 __BITFIELD_FIELD(u32 pktcnt : 10, 1272 __BITFIELD_FIELD(u32 xfersize : 19, 1273 ;)))) 1274 } s; 1275}; 1276 1277/** 1278 * cvmx_usbc#_hfir 1279 * 1280 * Host Frame Interval Register (HFIR) 1281 * 1282 * This register stores the frame interval information for the current speed to 1283 * which the O2P USB core has enumerated. 1284 */ 1285union cvmx_usbcx_hfir { 1286 u32 u32; 1287 /** 1288 * struct cvmx_usbcx_hfir_s 1289 * @frint: Frame Interval (FrInt) 1290 * The value that the application programs to this field specifies 1291 * the interval between two consecutive SOFs (FS) or micro- 1292 * SOFs (HS) or Keep-Alive tokens (HS). This field contains the 1293 * number of PHY clocks that constitute the required frame 1294 * interval. The default value set in this field for a FS operation 1295 * when the PHY clock frequency is 60 MHz. The application can 1296 * write a value to this register only after the Port Enable bit of 1297 * the Host Port Control and Status register (HPRT.PrtEnaPort) 1298 * has been set. If no value is programmed, the core calculates 1299 * the value based on the PHY clock specified in the FS/LS PHY 1300 * Clock Select field of the Host Configuration register 1301 * (HCFG.FSLSPclkSel). Do not change the value of this field 1302 * after the initial configuration. 1303 * * 125 us (PHY clock frequency for HS) 1304 * * 1 ms (PHY clock frequency for FS/LS) 1305 */ 1306 struct cvmx_usbcx_hfir_s { 1307 __BITFIELD_FIELD(u32 reserved_16_31 : 16, 1308 __BITFIELD_FIELD(u32 frint : 16, 1309 ;)) 1310 } s; 1311}; 1312 1313/** 1314 * cvmx_usbc#_hfnum 1315 * 1316 * Host Frame Number/Frame Time Remaining Register (HFNUM) 1317 * 1318 * This register indicates the current frame number. 1319 * It also indicates the time remaining (in terms of the number of PHY clocks) 1320 * in the current (micro)frame. 1321 */ 1322union cvmx_usbcx_hfnum { 1323 u32 u32; 1324 /** 1325 * struct cvmx_usbcx_hfnum_s 1326 * @frrem: Frame Time Remaining (FrRem) 1327 * Indicates the amount of time remaining in the current 1328 * microframe (HS) or frame (FS/LS), in terms of PHY clocks. 1329 * This field decrements on each PHY clock. When it reaches 1330 * zero, this field is reloaded with the value in the Frame 1331 * Interval register and a new SOF is transmitted on the USB. 1332 * @frnum: Frame Number (FrNum) 1333 * This field increments when a new SOF is transmitted on the 1334 * USB, and is reset to 0 when it reaches 16'h3FFF. 1335 */ 1336 struct cvmx_usbcx_hfnum_s { 1337 __BITFIELD_FIELD(u32 frrem : 16, 1338 __BITFIELD_FIELD(u32 frnum : 16, 1339 ;)) 1340 } s; 1341}; 1342 1343/** 1344 * cvmx_usbc#_hprt 1345 * 1346 * Host Port Control and Status Register (HPRT) 1347 * 1348 * This register is available in both Host and Device modes. 1349 * Currently, the OTG Host supports only one port. 1350 * A single register holds USB port-related information such as USB reset, 1351 * enable, suspend, resume, connect status, and test mode for each port. The 1352 * R_SS_WC bits in this register can trigger an interrupt to the application 1353 * through the Host Port Interrupt bit of the Core Interrupt register 1354 * (GINTSTS.PrtInt). On a Port Interrupt, the application must read this 1355 * register and clear the bit that caused the interrupt. For the R_SS_WC bits, 1356 * the application must write a 1 to the bit to clear the interrupt. 1357 */ 1358union cvmx_usbcx_hprt { 1359 u32 u32; 1360 /** 1361 * struct cvmx_usbcx_hprt_s 1362 * @prtspd: Port Speed (PrtSpd) 1363 * Indicates the speed of the device attached to this port. 1364 * * 2'b00: High speed 1365 * * 2'b01: Full speed 1366 * * 2'b10: Low speed 1367 * * 2'b11: Reserved 1368 * @prttstctl: Port Test Control (PrtTstCtl) 1369 * The application writes a nonzero value to this field to put 1370 * the port into a Test mode, and the corresponding pattern is 1371 * signaled on the port. 1372 * * 4'b0000: Test mode disabled 1373 * * 4'b0001: Test_J mode 1374 * * 4'b0010: Test_K mode 1375 * * 4'b0011: Test_SE0_NAK mode 1376 * * 4'b0100: Test_Packet mode 1377 * * 4'b0101: Test_Force_Enable 1378 * * Others: Reserved 1379 * PrtSpd must be zero (i.e. the interface must be in high-speed 1380 * mode) to use the PrtTstCtl test modes. 1381 * @prtpwr: Port Power (PrtPwr) 1382 * The application uses this field to control power to this port, 1383 * and the core clears this bit on an overcurrent condition. 1384 * * 1'b0: Power off 1385 * * 1'b1: Power on 1386 * @prtlnsts: Port Line Status (PrtLnSts) 1387 * Indicates the current logic level USB data lines 1388 * * Bit [10]: Logic level of D- 1389 * * Bit [11]: Logic level of D+ 1390 * @prtrst: Port Reset (PrtRst) 1391 * When the application sets this bit, a reset sequence is 1392 * started on this port. The application must time the reset 1393 * period and clear this bit after the reset sequence is 1394 * complete. 1395 * * 1'b0: Port not in reset 1396 * * 1'b1: Port in reset 1397 * The application must leave this bit set for at least a 1398 * minimum duration mentioned below to start a reset on the 1399 * port. The application can leave it set for another 10 ms in 1400 * addition to the required minimum duration, before clearing 1401 * the bit, even though there is no maximum limit set by the 1402 * USB standard. 1403 * * High speed: 50 ms 1404 * * Full speed/Low speed: 10 ms 1405 * @prtsusp: Port Suspend (PrtSusp) 1406 * The application sets this bit to put this port in Suspend 1407 * mode. The core only stops sending SOFs when this is set. 1408 * To stop the PHY clock, the application must set the Port 1409 * Clock Stop bit, which will assert the suspend input pin of 1410 * the PHY. 1411 * The read value of this bit reflects the current suspend 1412 * status of the port. This bit is cleared by the core after a 1413 * remote wakeup signal is detected or the application sets 1414 * the Port Reset bit or Port Resume bit in this register or the 1415 * Resume/Remote Wakeup Detected Interrupt bit or 1416 * Disconnect Detected Interrupt bit in the Core Interrupt 1417 * register (GINTSTS.WkUpInt or GINTSTS.DisconnInt, 1418 * respectively). 1419 * * 1'b0: Port not in Suspend mode 1420 * * 1'b1: Port in Suspend mode 1421 * @prtres: Port Resume (PrtRes) 1422 * The application sets this bit to drive resume signaling on 1423 * the port. The core continues to drive the resume signal 1424 * until the application clears this bit. 1425 * If the core detects a USB remote wakeup sequence, as 1426 * indicated by the Port Resume/Remote Wakeup Detected 1427 * Interrupt bit of the Core Interrupt register 1428 * (GINTSTS.WkUpInt), the core starts driving resume 1429 * signaling without application intervention and clears this bit 1430 * when it detects a disconnect condition. The read value of 1431 * this bit indicates whether the core is currently driving 1432 * resume signaling. 1433 * * 1'b0: No resume driven 1434 * * 1'b1: Resume driven 1435 * @prtovrcurrchng: Port Overcurrent Change (PrtOvrCurrChng) 1436 * The core sets this bit when the status of the Port 1437 * Overcurrent Active bit (bit 4) in this register changes. 1438 * @prtovrcurract: Port Overcurrent Active (PrtOvrCurrAct) 1439 * Indicates the overcurrent condition of the port. 1440 * * 1'b0: No overcurrent condition 1441 * * 1'b1: Overcurrent condition 1442 * @prtenchng: Port Enable/Disable Change (PrtEnChng) 1443 * The core sets this bit when the status of the Port Enable bit 1444 * [2] of this register changes. 1445 * @prtena: Port Enable (PrtEna) 1446 * A port is enabled only by the core after a reset sequence, 1447 * and is disabled by an overcurrent condition, a disconnect 1448 * condition, or by the application clearing this bit. The 1449 * application cannot set this bit by a register write. It can only 1450 * clear it to disable the port. This bit does not trigger any 1451 * interrupt to the application. 1452 * * 1'b0: Port disabled 1453 * * 1'b1: Port enabled 1454 * @prtconndet: Port Connect Detected (PrtConnDet) 1455 * The core sets this bit when a device connection is detected 1456 * to trigger an interrupt to the application using the Host Port 1457 * Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). 1458 * The application must write a 1 to this bit to clear the 1459 * interrupt. 1460 * @prtconnsts: Port Connect Status (PrtConnSts) 1461 * * 0: No device is attached to the port. 1462 * * 1: A device is attached to the port. 1463 */ 1464 struct cvmx_usbcx_hprt_s { 1465 __BITFIELD_FIELD(u32 reserved_19_31 : 13, 1466 __BITFIELD_FIELD(u32 prtspd : 2, 1467 __BITFIELD_FIELD(u32 prttstctl : 4, 1468 __BITFIELD_FIELD(u32 prtpwr : 1, 1469 __BITFIELD_FIELD(u32 prtlnsts : 2, 1470 __BITFIELD_FIELD(u32 reserved_9_9 : 1, 1471 __BITFIELD_FIELD(u32 prtrst : 1, 1472 __BITFIELD_FIELD(u32 prtsusp : 1, 1473 __BITFIELD_FIELD(u32 prtres : 1, 1474 __BITFIELD_FIELD(u32 prtovrcurrchng : 1, 1475 __BITFIELD_FIELD(u32 prtovrcurract : 1, 1476 __BITFIELD_FIELD(u32 prtenchng : 1, 1477 __BITFIELD_FIELD(u32 prtena : 1, 1478 __BITFIELD_FIELD(u32 prtconndet : 1, 1479 __BITFIELD_FIELD(u32 prtconnsts : 1, 1480 ;))))))))))))))) 1481 } s; 1482}; 1483 1484/** 1485 * cvmx_usbc#_hptxfsiz 1486 * 1487 * Host Periodic Transmit FIFO Size Register (HPTXFSIZ) 1488 * 1489 * This register holds the size and the memory start address of the Periodic 1490 * TxFIFO, as shown in Figures 310 and 311. 1491 */ 1492union cvmx_usbcx_hptxfsiz { 1493 u32 u32; 1494 /** 1495 * struct cvmx_usbcx_hptxfsiz_s 1496 * @ptxfsize: Host Periodic TxFIFO Depth (PTxFSize) 1497 * This value is in terms of 32-bit words. 1498 * * Minimum value is 16 1499 * * Maximum value is 32768 1500 * @ptxfstaddr: Host Periodic TxFIFO Start Address (PTxFStAddr) 1501 */ 1502 struct cvmx_usbcx_hptxfsiz_s { 1503 __BITFIELD_FIELD(u32 ptxfsize : 16, 1504 __BITFIELD_FIELD(u32 ptxfstaddr : 16, 1505 ;)) 1506 } s; 1507}; 1508 1509/** 1510 * cvmx_usbc#_hptxsts 1511 * 1512 * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS) 1513 * 1514 * This read-only register contains the free space information for the Periodic 1515 * TxFIFO and the Periodic Transmit Request Queue 1516 */ 1517union cvmx_usbcx_hptxsts { 1518 u32 u32; 1519 /** 1520 * struct cvmx_usbcx_hptxsts_s 1521 * @ptxqtop: Top of the Periodic Transmit Request Queue (PTxQTop) 1522 * This indicates the entry in the Periodic Tx Request Queue that 1523 * is currently being processes by the MAC. 1524 * This register is used for debugging. 1525 * * Bit [31]: Odd/Even (micro)frame 1526 * - 1'b0: send in even (micro)frame 1527 * - 1'b1: send in odd (micro)frame 1528 * * Bits [30:27]: Channel/endpoint number 1529 * * Bits [26:25]: Type 1530 * - 2'b00: IN/OUT 1531 * - 2'b01: Zero-length packet 1532 * - 2'b10: CSPLIT 1533 * - 2'b11: Disable channel command 1534 * * Bit [24]: Terminate (last entry for the selected 1535 * channel/endpoint) 1536 * @ptxqspcavail: Periodic Transmit Request Queue Space Available 1537 * (PTxQSpcAvail) 1538 * Indicates the number of free locations available to be written 1539 * in the Periodic Transmit Request Queue. This queue holds both 1540 * IN and OUT requests. 1541 * * 8'h0: Periodic Transmit Request Queue is full 1542 * * 8'h1: 1 location available 1543 * * 8'h2: 2 locations available 1544 * * n: n locations available (0..8) 1545 * * Others: Reserved 1546 * @ptxfspcavail: Periodic Transmit Data FIFO Space Available 1547 * (PTxFSpcAvail) 1548 * Indicates the number of free locations available to be written 1549 * to in the Periodic TxFIFO. 1550 * Values are in terms of 32-bit words 1551 * * 16'h0: Periodic TxFIFO is full 1552 * * 16'h1: 1 word available 1553 * * 16'h2: 2 words available 1554 * * 16'hn: n words available (where 0..32768) 1555 * * 16'h8000: 32768 words available 1556 * * Others: Reserved 1557 */ 1558 struct cvmx_usbcx_hptxsts_s { 1559 __BITFIELD_FIELD(u32 ptxqtop : 8, 1560 __BITFIELD_FIELD(u32 ptxqspcavail : 8, 1561 __BITFIELD_FIELD(u32 ptxfspcavail : 16, 1562 ;))) 1563 } s; 1564}; 1565 1566/** 1567 * cvmx_usbn#_clk_ctl 1568 * 1569 * USBN_CLK_CTL = USBN's Clock Control 1570 * 1571 * This register is used to control the frequency of the hclk and the 1572 * hreset and phy_rst signals. 1573 */ 1574union cvmx_usbnx_clk_ctl { 1575 u64 u64; 1576 /** 1577 * struct cvmx_usbnx_clk_ctl_s 1578 * @divide2: The 'hclk' used by the USB subsystem is derived 1579 * from the eclk. 1580 * Also see the field DIVIDE. DIVIDE2<1> must currently 1581 * be zero because it is not implemented, so the maximum 1582 * ratio of eclk/hclk is currently 16. 1583 * The actual divide number for hclk is: 1584 * (DIVIDE2 + 1) * (DIVIDE + 1) 1585 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to 1586 * generate the hclk in the USB Subsystem is held 1587 * in reset. This bit must be set to '0' before 1588 * changing the value os DIVIDE in this register. 1589 * The reset to the HCLK_DIVIDERis also asserted 1590 * when core reset is asserted. 1591 * @p_x_on: Force USB-PHY on during suspend. 1592 * '1' USB-PHY XO block is powered-down during 1593 * suspend. 1594 * '0' USB-PHY XO block is powered-up during 1595 * suspend. 1596 * The value of this field must be set while POR is 1597 * active. 1598 * @p_rtype: PHY reference clock type 1599 * On CN50XX/CN52XX/CN56XX the values are: 1600 * '0' The USB-PHY uses a 12MHz crystal as a clock source 1601 * at the USB_XO and USB_XI pins. 1602 * '1' Reserved. 1603 * '2' The USB_PHY uses 12/24/48MHz 2.5V board clock at the 1604 * USB_XO pin. USB_XI should be tied to ground in this 1605 * case. 1606 * '3' Reserved. 1607 * On CN3xxx bits 14 and 15 are p_xenbn and p_rclk and values are: 1608 * '0' Reserved. 1609 * '1' Reserved. 1610 * '2' The PHY PLL uses the XO block output as a reference. 1611 * The XO block uses an external clock supplied on the 1612 * XO pin. USB_XI should be tied to ground for this 1613 * usage. 1614 * '3' The XO block uses the clock from a crystal. 1615 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to 1616 * remain powered in Suspend Mode. 1617 * '1' The USB-PHY XO Bias, Bandgap and PLL are 1618 * powered down in suspend mode. 1619 * The value of this field must be set while POR is 1620 * active. 1621 * @p_c_sel: Phy clock speed select. 1622 * Selects the reference clock / crystal frequency. 1623 * '11': Reserved 1624 * '10': 48 MHz (reserved when a crystal is used) 1625 * '01': 24 MHz (reserved when a crystal is used) 1626 * '00': 12 MHz 1627 * The value of this field must be set while POR is 1628 * active. 1629 * NOTE: if a crystal is used as a reference clock, 1630 * this field must be set to 12 MHz. 1631 * @cdiv_byp: Used to enable the bypass input to the USB_CLK_DIV. 1632 * @sd_mode: Scaledown mode for the USBC. Control timing events 1633 * in the USBC, for normal operation this must be '0'. 1634 * @s_bist: Starts bist on the hclk memories, during the '0' 1635 * to '1' transition. 1636 * @por: Power On Reset for the PHY. 1637 * Resets all the PHYS registers and state machines. 1638 * @enable: When '1' allows the generation of the hclk. When 1639 * '0' the hclk will not be generated. SEE DIVIDE 1640 * field of this register. 1641 * @prst: When this field is '0' the reset associated with 1642 * the phy_clk functionality in the USB Subsystem is 1643 * help in reset. This bit should not be set to '1' 1644 * until the time it takes 6 clocks (hclk or phy_clk, 1645 * whichever is slower) has passed. Under normal 1646 * operation once this bit is set to '1' it should not 1647 * be set to '0'. 1648 * @hrst: When this field is '0' the reset associated with 1649 * the hclk functioanlity in the USB Subsystem is 1650 * held in reset.This bit should not be set to '1' 1651 * until 12ms after phy_clk is stable. Under normal 1652 * operation, once this bit is set to '1' it should 1653 * not be set to '0'. 1654 * @divide: The frequency of 'hclk' used by the USB subsystem 1655 * is the eclk frequency divided by the value of 1656 * (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 1657 * DIVIDE2 of this register. 1658 * The hclk frequency should be less than 125Mhz. 1659 * After writing a value to this field the SW should 1660 * read the field for the value written. 1661 * The ENABLE field of this register should not be set 1662 * until AFTER this field is set and then read. 1663 */ 1664 struct cvmx_usbnx_clk_ctl_s { 1665 __BITFIELD_FIELD(u64 reserved_20_63 : 44, 1666 __BITFIELD_FIELD(u64 divide2 : 2, 1667 __BITFIELD_FIELD(u64 hclk_rst : 1, 1668 __BITFIELD_FIELD(u64 p_x_on : 1, 1669 __BITFIELD_FIELD(u64 p_rtype : 2, 1670 __BITFIELD_FIELD(u64 p_com_on : 1, 1671 __BITFIELD_FIELD(u64 p_c_sel : 2, 1672 __BITFIELD_FIELD(u64 cdiv_byp : 1, 1673 __BITFIELD_FIELD(u64 sd_mode : 2, 1674 __BITFIELD_FIELD(u64 s_bist : 1, 1675 __BITFIELD_FIELD(u64 por : 1, 1676 __BITFIELD_FIELD(u64 enable : 1, 1677 __BITFIELD_FIELD(u64 prst : 1, 1678 __BITFIELD_FIELD(u64 hrst : 1, 1679 __BITFIELD_FIELD(u64 divide : 3, 1680 ;))))))))))))))) 1681 } s; 1682}; 1683 1684/** 1685 * cvmx_usbn#_usbp_ctl_status 1686 * 1687 * USBN_USBP_CTL_STATUS = USBP Control And Status Register 1688 * 1689 * Contains general control and status information for the USBN block. 1690 */ 1691union cvmx_usbnx_usbp_ctl_status { 1692 u64 u64; 1693 /** 1694 * struct cvmx_usbnx_usbp_ctl_status_s 1695 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment 1696 * @txvreftune: HS DC Voltage Level Adjustment 1697 * @txfslstune: FS/LS Source Impedance Adjustment 1698 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment 1699 * @sqrxtune: Squelch Threshold Adjustment 1700 * @compdistune: Disconnect Threshold Adjustment 1701 * @otgtune: VBUS Valid Threshold Adjustment 1702 * @otgdisable: OTG Block Disable 1703 * @portreset: Per_Port Reset 1704 * @drvvbus: Drive VBUS 1705 * @lsbist: Low-Speed BIST Enable. 1706 * @fsbist: Full-Speed BIST Enable. 1707 * @hsbist: High-Speed BIST Enable. 1708 * @bist_done: PHY Bist Done. 1709 * Asserted at the end of the PHY BIST sequence. 1710 * @bist_err: PHY Bist Error. 1711 * Indicates an internal error was detected during 1712 * the BIST sequence. 1713 * @tdata_out: PHY Test Data Out. 1714 * Presents either internally generated signals or 1715 * test register contents, based upon the value of 1716 * test_data_out_sel. 1717 * @siddq: Drives the USBP (USB-PHY) SIDDQ input. 1718 * Normally should be set to zero. 1719 * When customers have no intent to use USB PHY 1720 * interface, they should: 1721 * - still provide 3.3V to USB_VDD33, and 1722 * - tie USB_REXT to 3.3V supply, and 1723 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 1724 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable 1725 * @dma_bmode: When set to 1 the L2C DMA address will be updated 1726 * with byte-counts between packets. When set to 0 1727 * the L2C DMA address is incremented to the next 1728 * 4-byte aligned address after adding byte-count. 1729 * @usbc_end: Bigendian input to the USB Core. This should be 1730 * set to '0' for operation. 1731 * @usbp_bist: PHY, This is cleared '0' to run BIST on the USBP. 1732 * @tclk: PHY Test Clock, used to load TDATA_IN to the USBP. 1733 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY. 1734 * This signal enables the pull-down resistance on 1735 * the D+ line. '1' pull down-resistance is connected 1736 * to D+/ '0' pull down resistance is not connected 1737 * to D+. When an A/B device is acting as a host 1738 * (downstream-facing port), dp_pulldown and 1739 * dm_pulldown are enabled. This must not toggle 1740 * during normal operation. 1741 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY. 1742 * This signal enables the pull-down resistance on 1743 * the D- line. '1' pull down-resistance is connected 1744 * to D-. '0' pull down resistance is not connected 1745 * to D-. When an A/B device is acting as a host 1746 * (downstream-facing port), dp_pulldown and 1747 * dm_pulldown are enabled. This must not toggle 1748 * during normal operation. 1749 * @hst_mode: When '0' the USB is acting as HOST, when '1' 1750 * USB is acting as device. This field needs to be 1751 * set while the USB is in reset. 1752 * @tuning: Transmitter Tuning for High-Speed Operation. 1753 * Tunes the current supply and rise/fall output 1754 * times for high-speed operation. 1755 * [20:19] == 11: Current supply increased 1756 * approximately 9% 1757 * [20:19] == 10: Current supply increased 1758 * approximately 4.5% 1759 * [20:19] == 01: Design default. 1760 * [20:19] == 00: Current supply decreased 1761 * approximately 4.5% 1762 * [22:21] == 11: Rise and fall times are increased. 1763 * [22:21] == 10: Design default. 1764 * [22:21] == 01: Rise and fall times are decreased. 1765 * [22:21] == 00: Rise and fall times are decreased 1766 * further as compared to the 01 setting. 1767 * @tx_bs_enh: Transmit Bit Stuffing on [15:8]. 1768 * Enables or disables bit stuffing on data[15:8] 1769 * when bit-stuffing is enabled. 1770 * @tx_bs_en: Transmit Bit Stuffing on [7:0]. 1771 * Enables or disables bit stuffing on data[7:0] 1772 * when bit-stuffing is enabled. 1773 * @loop_enb: PHY Loopback Test Enable. 1774 * '1': During data transmission the receive is 1775 * enabled. 1776 * '0': During data transmission the receive is 1777 * disabled. 1778 * Must be '0' for normal operation. 1779 * @vtest_enb: Analog Test Pin Enable. 1780 * '1' The PHY's analog_test pin is enabled for the 1781 * input and output of applicable analog test signals. 1782 * '0' THe analog_test pin is disabled. 1783 * @bist_enb: Built-In Self Test Enable. 1784 * Used to activate BIST in the PHY. 1785 * @tdata_sel: Test Data Out Select. 1786 * '1' test_data_out[3:0] (PHY) register contents 1787 * are output. '0' internally generated signals are 1788 * output. 1789 * @taddr_in: Mode Address for Test Interface. 1790 * Specifies the register address for writing to or 1791 * reading from the PHY test interface register. 1792 * @tdata_in: Internal Testing Register Input Data and Select 1793 * This is a test bus. Data is present on [3:0], 1794 * and its corresponding select (enable) is present 1795 * on bits [7:4]. 1796 * @ate_reset: Reset input from automatic test equipment. 1797 * This is a test signal. When the USB Core is 1798 * powered up (not in Susned Mode), an automatic 1799 * tester can use this to disable phy_clock and 1800 * free_clk, then re-enable them with an aligned 1801 * phase. 1802 * '1': The phy_clk and free_clk outputs are 1803 * disabled. "0": The phy_clock and free_clk outputs 1804 * are available within a specific period after the 1805 * de-assertion. 1806 */ 1807 struct cvmx_usbnx_usbp_ctl_status_s { 1808 __BITFIELD_FIELD(u64 txrisetune : 1, 1809 __BITFIELD_FIELD(u64 txvreftune : 4, 1810 __BITFIELD_FIELD(u64 txfslstune : 4, 1811 __BITFIELD_FIELD(u64 txhsxvtune : 2, 1812 __BITFIELD_FIELD(u64 sqrxtune : 3, 1813 __BITFIELD_FIELD(u64 compdistune : 3, 1814 __BITFIELD_FIELD(u64 otgtune : 3, 1815 __BITFIELD_FIELD(u64 otgdisable : 1, 1816 __BITFIELD_FIELD(u64 portreset : 1, 1817 __BITFIELD_FIELD(u64 drvvbus : 1, 1818 __BITFIELD_FIELD(u64 lsbist : 1, 1819 __BITFIELD_FIELD(u64 fsbist : 1, 1820 __BITFIELD_FIELD(u64 hsbist : 1, 1821 __BITFIELD_FIELD(u64 bist_done : 1, 1822 __BITFIELD_FIELD(u64 bist_err : 1, 1823 __BITFIELD_FIELD(u64 tdata_out : 4, 1824 __BITFIELD_FIELD(u64 siddq : 1, 1825 __BITFIELD_FIELD(u64 txpreemphasistune : 1, 1826 __BITFIELD_FIELD(u64 dma_bmode : 1, 1827 __BITFIELD_FIELD(u64 usbc_end : 1, 1828 __BITFIELD_FIELD(u64 usbp_bist : 1, 1829 __BITFIELD_FIELD(u64 tclk : 1, 1830 __BITFIELD_FIELD(u64 dp_pulld : 1, 1831 __BITFIELD_FIELD(u64 dm_pulld : 1, 1832 __BITFIELD_FIELD(u64 hst_mode : 1, 1833 __BITFIELD_FIELD(u64 tuning : 4, 1834 __BITFIELD_FIELD(u64 tx_bs_enh : 1, 1835 __BITFIELD_FIELD(u64 tx_bs_en : 1, 1836 __BITFIELD_FIELD(u64 loop_enb : 1, 1837 __BITFIELD_FIELD(u64 vtest_enb : 1, 1838 __BITFIELD_FIELD(u64 bist_enb : 1, 1839 __BITFIELD_FIELD(u64 tdata_sel : 1, 1840 __BITFIELD_FIELD(u64 taddr_in : 4, 1841 __BITFIELD_FIELD(u64 tdata_in : 8, 1842 __BITFIELD_FIELD(u64 ate_reset : 1, 1843 ;))))))))))))))))))))))))))))))))))) 1844 } s; 1845}; 1846 1847#endif /* __OCTEON_HCD_H__ */ 1848