LXR linux/drivers/staging/r8188eu/include/odm.h

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4#ifndef __HALDMOUTSRC_H__
   5#define __HALDMOUTSRC_H__
   6
   7/*  Definition */
   8/*  Define all team support ability. */
   9
  10/*  Define for all teams. Please Define the constant in your precomp header. */
  11
  12/* define               DM_ODM_SUPPORT_AP                       0 */
  13/* define               DM_ODM_SUPPORT_ADSL                     0 */
  14/* define               DM_ODM_SUPPORT_CE                       0 */
  15/* define               DM_ODM_SUPPORT_MP                       1 */
  16
  17/*  Define ODM SW team support flag. */
  18
  19/*  Antenna Switch Relative Definition. */
  20
  21/*  Add new function SwAntDivCheck8192C(). */
  22/*  This is the main function of Antenna diversity function before link. */
  23/*  Mainly, it just retains last scan result and scan again. */
  24/*  After that, it compares the scan result to see which one gets better
  25 *  RSSI. It selects antenna with better receiving power and returns better
  26 *  scan result. */
  27
  28#define TP_MODE                 0
  29#define RSSI_MODE               1
  30#define TRAFFIC_LOW             0
  31#define TRAFFIC_HIGH            1
  32
  33/* 3 Tx Power Tracking */
  34/* 3============================================================ */
  35#define         DPK_DELTA_MAPPING_NUM   13
  36#define         index_mapping_HP_NUM    15
  37
  38/*  */
  39/* 3 PSD Handler */
  40/* 3============================================================ */
  41
  42#define AFH_PSD         1       /* 0:normal PSD scan, 1: only do 20 pts PSD */
  43#define MODE_40M        0       /* 0:20M, 1:40M */
  44#define PSD_TH2         3
  45#define PSD_CHM         20   /*  Minimum channel number for BT AFH */
  46#define SIR_STEP_SIZE   3
  47#define Smooth_Size_1   5
  48#define Smooth_TH_1     3
  49#define Smooth_Size_2   10
  50#define Smooth_TH_2     4
  51#define Smooth_Size_3   20
  52#define Smooth_TH_3     4
  53#define Smooth_Step_Size 5
  54#define Adaptive_SIR    1
  55#define PSD_RESCAN      4
  56#define PSD_SCAN_INTERVAL       700 /* ms */
  57
  58/* 8723A High Power IGI Setting */
  59#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
  60#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
  61#define DM_DIG_HIGH_PWR_THRESHOLD       0x3a
  62
  63/*  LPS define */
  64#define DM_DIG_FA_TH0_LPS               4 /*  4 in lps */
  65#define DM_DIG_FA_TH1_LPS               15 /*  15 lps */
  66#define DM_DIG_FA_TH2_LPS               30 /*  30 lps */
  67#define RSSI_OFFSET_DIG                 0x05;
  68
  69/* ANT Test */
  70#define ANTTESTALL              0x00    /* Ant A or B will be Testing */
  71#define ANTTESTA                0x01    /* Ant A will be Testing */
  72#define ANTTESTB                0x02    /* Ant B will be testing */
  73
  74/*  structure and define */
  75
  76/*  Add for AP/ADSLpseudo DM structuer requirement. */
  77/*  We need to remove to other position??? */
  78struct rtl8192cd_priv {
  79        u8              temp;
  80};
  81
  82struct rtw_dig {
  83        u8              Dig_Enable_Flag;
  84        u8              Dig_Ext_Port_Stage;
  85
  86        int             RssiLowThresh;
  87        int             RssiHighThresh;
  88
  89        u32             FALowThresh;
  90        u32             FAHighThresh;
  91
  92        u8              CurSTAConnectState;
  93        u8              PreSTAConnectState;
  94        u8              CurMultiSTAConnectState;
  95
  96        u8              PreIGValue;
  97        u8              CurIGValue;
  98        u8              BackupIGValue;
  99
 100        s8              BackoffVal;
 101        s8              BackoffVal_range_max;
 102        s8              BackoffVal_range_min;
 103        u8              rx_gain_range_max;
 104        u8              rx_gain_range_min;
 105        u8              Rssi_val_min;
 106
 107        u8              PreCCK_CCAThres;
 108        u8              CurCCK_CCAThres;
 109        u8              PreCCKPDState;
 110        u8              CurCCKPDState;
 111
 112        u8              LargeFAHit;
 113        u8              ForbiddenIGI;
 114        u32             Recover_cnt;
 115
 116        u8              DIG_Dynamic_MIN_0;
 117        u8              DIG_Dynamic_MIN_1;
 118        bool            bMediaConnect_0;
 119        bool            bMediaConnect_1;
 120
 121        u32             AntDiv_RSSI_max;
 122        u32             RSSI_max;
 123};
 124
 125struct rtl_ps {
 126        u8              pre_cca_state;
 127        u8              cur_cca_state;
 128
 129        u8              pre_rf_state;
 130        u8              cur_rf_state;
 131
 132        int             rssi_val_min;
 133
 134        u8              initialize;
 135        u32             reg_874;
 136        u32             reg_c70;
 137        u32             reg_85c;
 138        u32             reg_a74;
 139
 140};
 141
 142struct false_alarm_stats {
 143        u32     Cnt_Parity_Fail;
 144        u32     Cnt_Rate_Illegal;
 145        u32     Cnt_Crc8_fail;
 146        u32     Cnt_Mcs_fail;
 147        u32     Cnt_Ofdm_fail;
 148        u32     Cnt_Cck_fail;
 149        u32     Cnt_all;
 150        u32     Cnt_Fast_Fsync;
 151        u32     Cnt_SB_Search_fail;
 152        u32     Cnt_OFDM_CCA;
 153        u32     Cnt_CCK_CCA;
 154        u32     Cnt_CCA_all;
 155        u32     Cnt_BW_USC;     /* Gary */
 156        u32     Cnt_BW_LSC;     /* Gary */
 157};
 158
 159struct dyn_primary_cca {
 160        u8              pri_cca_flag;
 161        u8              intf_flag;
 162        u8              intf_type;
 163        u8              dup_rts_flag;
 164        u8              monitor_flag;
 165};
 166
 167struct rx_hpc {
 168        u8              RXHP_flag;
 169        u8              PSD_func_trigger;
 170        u8              PSD_bitmap_RXHP[80];
 171        u8              Pre_IGI;
 172        u8              Cur_IGI;
 173        u8              Pre_pw_th;
 174        u8              Cur_pw_th;
 175        bool            First_time_enter;
 176        bool            RXHP_enable;
 177        u8              TP_Mode;
 178        struct timer_list PSDTimer;
 179};
 180
 181#define ASSOCIATE_ENTRY_NUM     32 /*  Max size of AsocEntry[]. */
 182#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
 183
 184/*  This indicates two different steps. */
 185/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
 186 *  the signal on the air. */
 187/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in
 188 *  SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
 189 *  switch antenna. */
 190
 191#define SWAW_STEP_PEAK          0
 192#define SWAW_STEP_DETERMINE     1
 193
 194#define TP_MODE                 0
 195#define RSSI_MODE               1
 196#define TRAFFIC_LOW             0
 197#define TRAFFIC_HIGH            1
 198
 199struct sw_ant_switch {
 200        u8      try_flag;
 201        s32     PreRSSI;
 202        u8      CurAntenna;
 203        u8      PreAntenna;
 204        u8      RSSI_Trying;
 205        u8      TestMode;
 206        u8      bTriggerAntennaSwitch;
 207        u8      SelectAntennaMap;
 208        u8      RSSI_target;
 209
 210        /*  Before link Antenna Switch check */
 211        u8      SWAS_NoLink_State;
 212        u32     SWAS_NoLink_BK_Reg860;
 213        bool    ANTA_ON;        /* To indicate Ant A is or not */
 214        bool    ANTB_ON;        /* To indicate Ant B is on or not */
 215
 216        s32     RSSI_sum_A;
 217        s32     RSSI_sum_B;
 218        s32     RSSI_cnt_A;
 219        s32     RSSI_cnt_B;
 220        u64     lastTxOkCnt;
 221        u64     lastRxOkCnt;
 222        u64     TXByteCnt_A;
 223        u64     TXByteCnt_B;
 224        u64     RXByteCnt_A;
 225        u64     RXByteCnt_B;
 226        u8      TrafficLoad;
 227        struct timer_list SwAntennaSwitchTimer;
 228        /* Hybrid Antenna Diversity */
 229        u32     CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 230        u32     CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 231        u32     OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 232        u32     OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 233        u32     RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
 234        u32     RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
 235        u8      TxAnt[ASSOCIATE_ENTRY_NUM];
 236        u8      TargetSTA;
 237        u8      antsel;
 238        u8      RxIdleAnt;
 239};
 240
 241struct edca_turbo {
 242        bool bCurrentTurboEDCA;
 243        bool bIsCurRDLState;
 244        u32     prv_traffic_idx; /*  edca turbo */
 245};
 246
 247struct odm_rate_adapt {
 248        u8      Type;           /*  DM_Type_ByFW/DM_Type_ByDriver */
 249        u8      HighRSSIThresh; /*  if RSSI > HighRSSIThresh    => RATRState is DM_RATR_STA_HIGH */
 250        u8      LowRSSIThresh;  /*  if RSSI <= LowRSSIThresh    => RATRState is DM_RATR_STA_LOW */
 251        u8      RATRState;      /*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
 252        u32     LastRATR;       /*  RATR Register Content */
 253};
 254
 255#define IQK_MAC_REG_NUM         4
 256#define IQK_ADDA_REG_NUM        16
 257#define IQK_BB_REG_NUM_MAX      10
 258#define IQK_BB_REG_NUM          9
 259#define HP_THERMAL_NUM          8
 260
 261#define AVG_THERMAL_NUM         8
 262#define IQK_Matrix_REG_NUM      8
 263#define IQK_Matrix_Settings_NUM 1+24+21
 264
 265#define DM_Type_ByFWi           0
 266#define DM_Type_ByDriver        1
 267
 268/*  Declare for common info */
 269
 270struct odm_phy_status_info {
 271        u8      RxPWDBAll;
 272        u8      SignalQuality;   /*  in 0-100 index. */
 273        u8      RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
 274        u8      RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/*  in 0~100 index */
 275        s8      RxPower; /*  in dBm Translate from PWdB */
 276        s8      RecvSignalPower;/*  Real power in dBm for this packet, no
 277                                 * beautification and aggregation. Keep this raw
 278                                 * info to be used for the other procedures. */
 279        u8      BTRxRSSIPercentage;
 280        u8      SignalStrength; /*  in 0-100 index. */
 281        u8      RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
 282        u8      RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
 283};
 284
 285struct odm_phy_dbg_info {
 286        /* ODM Write,debug info */
 287        s8      RxSNRdB[MAX_PATH_NUM_92CS];
 288        u64     NumQryPhyStatus;
 289        u64     NumQryPhyStatusCCK;
 290        u64     NumQryPhyStatusOFDM;
 291        /* Others */
 292        s32     RxEVM[MAX_PATH_NUM_92CS];
 293};
 294
 295struct odm_per_pkt_info {
 296        s8      Rate;
 297        u8      StationID;
 298        bool    bPacketMatchBSSID;
 299        bool    bPacketToSelf;
 300        bool    bPacketBeacon;
 301};
 302
 303struct odm_mac_status_info {
 304        u8      test;
 305};
 306
 307enum odm_ability {
 308        /*  BB Team */
 309        ODM_DIG                 = 0x00000001,
 310        ODM_HIGH_POWER          = 0x00000002,
 311        ODM_CCK_CCA_TH          = 0x00000004,
 312        ODM_FA_STATISTICS       = 0x00000008,
 313        ODM_RAMASK              = 0x00000010,
 314        ODM_RSSI_MONITOR        = 0x00000020,
 315        ODM_SW_ANTDIV           = 0x00000040,
 316        ODM_HW_ANTDIV           = 0x00000080,
 317        ODM_BB_PWRSV            = 0x00000100,
 318        ODM_2TPATHDIV           = 0x00000200,
 319        ODM_1TPATHDIV           = 0x00000400,
 320        ODM_PSD2AFH             = 0x00000800
 321};
 322
 323/*  2011/20/20 MH For MP driver RT_WLAN_STA =  struct sta_info */
 324/*  Please declare below ODM relative info in your STA info structure. */
 325
 326struct odm_sta_info {
 327        /*  Driver Write */
 328        bool    bUsed;          /*  record the sta status link or not? */
 329        u8      IOTPeer;        /*  Enum value. HT_IOT_PEER_E */
 330
 331        /*  ODM Write */
 332        /* 1 PHY_STATUS_INFO */
 333        u8      RSSI_Path[4];           /*  */
 334        u8      RSSI_Ave;
 335        u8      RXEVM[4];
 336        u8      RXSNR[4];
 337};
 338
 339/*  2011/10/20 MH Define Common info enum for all team. */
 340
 341enum odm_common_info_def {
 342        /*  Fixed value: */
 343
 344        /* HOOK BEFORE REG INIT----------- */
 345        ODM_CMNINFO_PLATFORM = 0,
 346        ODM_CMNINFO_ABILITY,            /* ODM_ABILITY_E */
 347        ODM_CMNINFO_INTERFACE,          /* ODM_INTERFACE_E */
 348        ODM_CMNINFO_MP_TEST_CHIP,
 349        ODM_CMNINFO_IC_TYPE,            /* ODM_IC_TYPE_E */
 350        ODM_CMNINFO_CUT_VER,            /* ODM_CUT_VERSION_E */
 351        ODM_CMNINFO_FAB_VER,            /* ODM_FAB_E */
 352        ODM_CMNINFO_RF_TYPE,            /* RF_PATH_E or ODM_RF_TYPE_E? */
 353        ODM_CMNINFO_BOARD_TYPE,         /* ODM_BOARD_TYPE_E */
 354        ODM_CMNINFO_EXT_LNA,            /* true */
 355        ODM_CMNINFO_EXT_PA,
 356        ODM_CMNINFO_EXT_TRSW,
 357        ODM_CMNINFO_PATCH_ID,           /* CUSTOMER ID */
 358        ODM_CMNINFO_BINHCT_TEST,
 359        ODM_CMNINFO_BWIFI_TEST,
 360        ODM_CMNINFO_SMART_CONCURRENT,
 361        /* HOOK BEFORE REG INIT-----------  */
 362
 363        /*  Dynamic value: */
 364/*  POINTER REFERENCE-----------  */
 365        ODM_CMNINFO_MAC_PHY_MODE,       /*  ODM_MAC_PHY_MODE_E */
 366        ODM_CMNINFO_TX_UNI,
 367        ODM_CMNINFO_RX_UNI,
 368        ODM_CMNINFO_WM_MODE,            /*  ODM_WIRELESS_MODE_E */
 369        ODM_CMNINFO_BAND,               /*  ODM_BAND_TYPE_E */
 370        ODM_CMNINFO_SEC_CHNL_OFFSET,    /*  ODM_SEC_CHNL_OFFSET_E */
 371        ODM_CMNINFO_SEC_MODE,           /*  ODM_SECURITY_E */
 372        ODM_CMNINFO_BW,                 /*  ODM_BW_E */
 373        ODM_CMNINFO_CHNL,
 374
 375        ODM_CMNINFO_DMSP_GET_VALUE,
 376        ODM_CMNINFO_BUDDY_ADAPTOR,
 377        ODM_CMNINFO_DMSP_IS_MASTER,
 378        ODM_CMNINFO_SCAN,
 379        ODM_CMNINFO_POWER_SAVING,
 380        ODM_CMNINFO_ONE_PATH_CCA,       /*  ODM_CCA_PATH_E */
 381        ODM_CMNINFO_DRV_STOP,
 382        ODM_CMNINFO_PNP_IN,
 383        ODM_CMNINFO_INIT_ON,
 384        ODM_CMNINFO_ANT_TEST,
 385        ODM_CMNINFO_NET_CLOSED,
 386        ODM_CMNINFO_MP_MODE,
 387/*  POINTER REFERENCE----------- */
 388
 389/* CALL BY VALUE------------- */
 390        ODM_CMNINFO_WIFI_DIRECT,
 391        ODM_CMNINFO_WIFI_DISPLAY,
 392        ODM_CMNINFO_LINK,
 393        ODM_CMNINFO_RSSI_MIN,
 394        ODM_CMNINFO_RA_THRESHOLD_HIGH,          /*  u8 */
 395        ODM_CMNINFO_RA_THRESHOLD_LOW,           /*  u8 */
 396        ODM_CMNINFO_RF_ANTENNA_TYPE,            /*  u8 */
 397        ODM_CMNINFO_BT_DISABLED,
 398        ODM_CMNINFO_BT_OPERATION,
 399        ODM_CMNINFO_BT_DIG,
 400        ODM_CMNINFO_BT_BUSY,                    /* Check Bt is using or not */
 401        ODM_CMNINFO_BT_DISABLE_EDCA,
 402/* CALL BY VALUE-------------*/
 403
 404        /*  Dynamic ptr array hook itms. */
 405        ODM_CMNINFO_STA_STATUS,
 406        ODM_CMNINFO_PHY_STATUS,
 407        ODM_CMNINFO_MAC_STATUS,
 408        ODM_CMNINFO_MAX,
 409};
 410
 411/*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
 412
 413enum odm_ability_def {
 414        /*  BB ODM section BIT 0-15 */
 415        ODM_BB_DIG                      = BIT(0),
 416        ODM_BB_RA_MASK                  = BIT(1),
 417        ODM_BB_DYNAMIC_TXPWR            = BIT(2),
 418        ODM_BB_FA_CNT                   = BIT(3),
 419        ODM_BB_RSSI_MONITOR             = BIT(4),
 420        ODM_BB_CCK_PD                   = BIT(5),
 421        ODM_BB_ANT_DIV                  = BIT(6),
 422        ODM_BB_PWR_SAVE                 = BIT(7),
 423        ODM_BB_PWR_TRA                  = BIT(8),
 424        ODM_BB_RATE_ADAPTIVE            = BIT(9),
 425        ODM_BB_PATH_DIV                 = BIT(10),
 426        ODM_BB_PSD                      = BIT(11),
 427        ODM_BB_RXHP                     = BIT(12),
 428
 429        /*  MAC DM section BIT 16-23 */
 430        ODM_MAC_EDCA_TURBO              = BIT(16),
 431        ODM_MAC_EARLY_MODE              = BIT(17),
 432
 433        /*  RF ODM section BIT 24-31 */
 434        ODM_RF_TX_PWR_TRACK             = BIT(24),
 435        ODM_RF_RX_GAIN_TRACK            = BIT(25),
 436        ODM_RF_CALIBRATION              = BIT(26),
 437};
 438
 439/*      ODM_CMNINFO_INTERFACE */
 440enum odm_interface_def {
 441        ODM_ITRF_PCIE   =       0x1,
 442        ODM_ITRF_USB    =       0x2,
 443        ODM_ITRF_SDIO   =       0x4,
 444        ODM_ITRF_ALL    =       0x7,
 445};
 446
 447/*  ODM_CMNINFO_IC_TYPE */
 448enum odm_ic_type {
 449        ODM_RTL8192S    =       BIT(0),
 450        ODM_RTL8192C    =       BIT(1),
 451        ODM_RTL8192D    =       BIT(2),
 452        ODM_RTL8723A    =       BIT(3),
 453        ODM_RTL8188E    =       BIT(4),
 454        ODM_RTL8812     =       BIT(5),
 455        ODM_RTL8821     =       BIT(6),
 456};
 457
 458#define ODM_IC_11N_SERIES                                               \
 459        (ODM_RTL8192S | ODM_RTL8192C | ODM_RTL8192D |                   \
 460         ODM_RTL8723A | ODM_RTL8188E)
 461#define ODM_IC_11AC_SERIES              (ODM_RTL8812)
 462
 463/* ODM_CMNINFO_CUT_VER */
 464enum odm_cut_version {
 465        ODM_CUT_A       =       1,
 466        ODM_CUT_B       =       2,
 467        ODM_CUT_C       =       3,
 468        ODM_CUT_D       =       4,
 469        ODM_CUT_E       =       5,
 470        ODM_CUT_F       =       6,
 471        ODM_CUT_TEST    =       7,
 472};
 473
 474/*  ODM_CMNINFO_FAB_VER */
 475enum odm_fab_Version {
 476        ODM_TSMC        =       0,
 477        ODM_UMC         =       1,
 478};
 479
 480/*  ODM_CMNINFO_RF_TYPE */
 481/*  For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5)) */
 482enum odm_rf_path {
 483        ODM_RF_TX_A     =       BIT(0),
 484        ODM_RF_TX_B     =       BIT(1),
 485        ODM_RF_TX_C     =       BIT(2),
 486        ODM_RF_TX_D     =       BIT(3),
 487        ODM_RF_RX_A     =       BIT(4),
 488        ODM_RF_RX_B     =       BIT(5),
 489        ODM_RF_RX_C     =       BIT(6),
 490        ODM_RF_RX_D     =       BIT(7),
 491};
 492
 493enum odm_rf_type {
 494        ODM_1T1R        =       0,
 495        ODM_1T2R        =       1,
 496        ODM_2T2R        =       2,
 497        ODM_2T3R        =       3,
 498        ODM_2T4R        =       4,
 499        ODM_3T3R        =       5,
 500        ODM_3T4R        =       6,
 501        ODM_4T4R        =       7,
 502};
 503
 504/*  ODM Dynamic common info value definition */
 505
 506enum odm_mac_phy_mode {
 507        ODM_SMSP        = 0,
 508        ODM_DMSP        = 1,
 509        ODM_DMDP        = 2,
 510};
 511
 512enum odm_bt_coexist {
 513        ODM_BT_BUSY             = 1,
 514        ODM_BT_ON               = 2,
 515        ODM_BT_OFF              = 3,
 516        ODM_BT_NONE             = 4,
 517};
 518
 519/*  ODM_CMNINFO_OP_MODE */
 520enum odm_operation_mode {
 521        ODM_NO_LINK             = BIT(0),
 522        ODM_LINK                = BIT(1),
 523        ODM_SCAN                = BIT(2),
 524        ODM_POWERSAVE           = BIT(3),
 525        ODM_AP_MODE             = BIT(4),
 526        ODM_CLIENT_MODE         = BIT(5),
 527        ODM_AD_HOC              = BIT(6),
 528        ODM_WIFI_DIRECT         = BIT(7),
 529        ODM_WIFI_DISPLAY        = BIT(8),
 530};
 531
 532/*  ODM_CMNINFO_WM_MODE */
 533enum odm_wireless_mode {
 534        ODM_WM_UNKNOW   = 0x0,
 535        ODM_WM_B        = BIT(0),
 536        ODM_WM_G        = BIT(1),
 537        ODM_WM_N24G     = BIT(3),
 538        ODM_WM_AUTO     = BIT(5),
 539};
 540
 541/*  ODM_CMNINFO_BAND */
 542enum odm_band_type {
 543        ODM_BAND_2_4G   = BIT(0),
 544};
 545
 546/*  ODM_CMNINFO_SEC_CHNL_OFFSET */
 547enum odm_sec_chnl_offset {
 548        ODM_DONT_CARE   = 0,
 549        ODM_BELOW       = 1,
 550        ODM_ABOVE       = 2
 551};
 552
 553/*  ODM_CMNINFO_SEC_MODE */
 554enum odm_security {
 555        ODM_SEC_OPEN            = 0,
 556        ODM_SEC_WEP40           = 1,
 557        ODM_SEC_TKIP            = 2,
 558        ODM_SEC_RESERVE         = 3,
 559        ODM_SEC_AESCCMP         = 4,
 560        ODM_SEC_WEP104          = 5,
 561        ODM_WEP_WPA_MIXED       = 6, /*  WEP + WPA */
 562        ODM_SEC_SMS4            = 7,
 563};
 564
 565/*  ODM_CMNINFO_BW */
 566enum odm_bw {
 567        ODM_BW20M               = 0,
 568        ODM_BW40M               = 1,
 569};
 570
 571/*  ODM_CMNINFO_BOARD_TYPE */
 572enum odm_board_type {
 573        ODM_BOARD_NORMAL        = 0,
 574        ODM_BOARD_HIGHPWR       = 1,
 575        ODM_BOARD_MINICARD      = 2,
 576        ODM_BOARD_SLIM          = 3,
 577        ODM_BOARD_COMBO         = 4,
 578};
 579
 580/*  ODM_CMNINFO_ONE_PATH_CCA */
 581enum odm_cca_path {
 582        ODM_CCA_2R              = 0,
 583        ODM_CCA_1R_A            = 1,
 584        ODM_CCA_1R_B            = 2,
 585};
 586
 587struct odm_ra_info {
 588        u8 RateID;
 589        u32 RateMask;
 590        u32 RAUseRate;
 591        u8 RateSGI;
 592        u8 RssiStaRA;
 593        u8 PreRssiStaRA;
 594        u8 SGIEnable;
 595        u8 DecisionRate;
 596        u8 PreRate;
 597        u8 HighestRate;
 598        u8 LowestRate;
 599        u32 NscUp;
 600        u32 NscDown;
 601        u16 RTY[5];
 602        u32 TOTAL;
 603        u16 DROP;
 604        u8 Active;
 605        u16 RptTime;
 606        u8 RAWaitingCounter;
 607        u8 RAPendingCounter;
 608        u8 PTActive;    /*  on or off */
 609        u8 PTTryState;  /*  0 trying state, 1 for decision state */
 610        u8 PTStage;     /*  0~6 */
 611        u8 PTStopCount; /* Stop PT counter */
 612        u8 PTPreRate;   /*  if rate change do PT */
 613        u8 PTPreRssi;   /*  if RSSI change 5% do PT */
 614        u8 PTModeSS;    /*  decide whitch rate should do PT */
 615        u8 RAstage;     /*  StageRA, decide how many times RA will be done
 616                         * between PT */
 617        u8 PTSmoothFactor;
 618};
 619
 620struct ijk_matrix_regs_set {
 621        bool    bIQKDone;
 622        s32     Value[1][IQK_Matrix_REG_NUM];
 623};
 624
 625struct odm_rf_cal {
 626        /* for tx power tracking */
 627        u32     RegA24; /*  for TempCCK */
 628        s32     RegE94;
 629        s32     RegE9C;
 630        s32     RegEB4;
 631        s32     RegEBC;
 632
 633        u8      TXPowercount;
 634        bool    bTXPowerTrackingInit;
 635        bool    bTXPowerTracking;
 636        u8      TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
 637                                      * as default */
 638        u8      TM_Trigger;
 639        u8      InternalPA5G[2];        /* pathA / pathB */
 640
 641        u8      ThermalMeter[2];    /* ThermalMeter, index 0 for RFIC0,
 642                                     * and 1 for RFIC1 */
 643        u8      ThermalValue;
 644        u8      ThermalValue_LCK;
 645        u8      ThermalValue_IQK;
 646        u8      ThermalValue_DPK;
 647        u8      ThermalValue_AVG[AVG_THERMAL_NUM];
 648        u8      ThermalValue_AVG_index;
 649        u8      ThermalValue_RxGain;
 650        u8      ThermalValue_Crystal;
 651        u8      ThermalValue_DPKstore;
 652        u8      ThermalValue_DPKtrack;
 653        bool    TxPowerTrackingInProgress;
 654        bool    bDPKenable;
 655
 656        bool    bReloadtxpowerindex;
 657        u8      bRfPiEnable;
 658        u32     TXPowerTrackingCallbackCnt; /* cosa add for debug */
 659
 660        u8      bCCKinCH14;
 661        u8      CCK_index;
 662        u8      OFDM_index[2];
 663        bool bDoneTxpower;
 664
 665        u8      ThermalValue_HP[HP_THERMAL_NUM];
 666        u8      ThermalValue_HP_index;
 667        struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
 668
 669        u8      Delta_IQK;
 670        u8      Delta_LCK;
 671
 672        /* for IQK */
 673        u32     RegC04;
 674        u32     Reg874;
 675        u32     RegC08;
 676        u32     RegB68;
 677        u32     RegB6C;
 678        u32     Reg870;
 679        u32     Reg860;
 680        u32     Reg864;
 681
 682        bool    bIQKInitialized;
 683        bool    bLCKInProgress;
 684        bool    bAntennaDetected;
 685        u32     ADDA_backup[IQK_ADDA_REG_NUM];
 686        u32     IQK_MAC_backup[IQK_MAC_REG_NUM];
 687        u32     IQK_BB_backup_recover[9];
 688        u32     IQK_BB_backup[IQK_BB_REG_NUM];
 689
 690        /* for APK */
 691        u32     APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
 692        u8      bAPKdone;
 693        u8      bAPKThermalMeterIgnore;
 694        u8      bDPdone;
 695        u8      bDPPathAOK;
 696        u8      bDPPathBOK;
 697};
 698
 699/*  ODM Dynamic common info value definition */
 700
 701struct fast_ant_train {
 702        u8      Bssid[6];
 703        u8      antsel_rx_keep_0;
 704        u8      antsel_rx_keep_1;
 705        u8      antsel_rx_keep_2;
 706        u32     antSumRSSI[7];
 707        u32     antRSSIcnt[7];
 708        u32     antAveRSSI[7];
 709        u8      FAT_State;
 710        u32     TrainIdx;
 711        u8      antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
 712        u8      antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
 713        u8      antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
 714        u32     MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 715        u32     AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 716        u32     MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 717        u32     AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 718        u8      RxIdleAnt;
 719        bool    bBecomeLinked;
 720};
 721
 722enum fat_state {
 723        FAT_NORMAL_STATE                = 0,
 724        FAT_TRAINING_STATE              = 1,
 725};
 726
 727enum ant_div_type {
 728        NO_ANTDIV                       = 0xFF,
 729        CG_TRX_HW_ANTDIV                = 0x01,
 730        CGCS_RX_HW_ANTDIV               = 0x02,
 731        FIXED_HW_ANTDIV                 = 0x03,
 732        CG_TRX_SMART_ANTDIV             = 0x04,
 733        CGCS_RX_SW_ANTDIV               = 0x05,
 734};
 735
 736/* Copy from SD4 defined structure. We use to support PHY DM integration. */
 737struct odm_dm_struct {
 738        /*      Add for different team use temporarily */
 739        struct adapter *Adapter;        /*  For CE/NIC team */
 740        struct rtl8192cd_priv *priv;    /*  For AP/ADSL team */
 741        /*  WHen you use above pointers, they must be initialized. */
 742        bool    odm_ready;
 743
 744        struct rtl8192cd_priv *fake_priv;
 745
 746/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 747        bool    bCckHighPower;
 748        u8      RFPathRxEnable;         /*  ODM_CMNINFO_RFPATH_ENABLE */
 749        u8      ControlChannel;
 750/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 751
 752/* 1  COMMON INFORMATION */
 753        /*  Init Value */
 754/* HOOK BEFORE REG INIT----------- */
 755        /*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
 756        u8      SupportPlatform;
 757        /*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */
 758        u32     SupportAbility;
 759        /*  ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
 760        u8      SupportInterface;
 761        /*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
 762         *  other type = 1/2/3/... */
 763        u32     SupportICType;
 764        /*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
 765        u8      CutVersion;
 766        /*  Fab Version TSMC/UMC = 0/1 */
 767        u8      FabVersion;
 768        /*  RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
 769        u8      RFType;
 770        /*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
 771        u8      BoardType;
 772        /*  with external LNA  NO/Yes = 0/1 */
 773        u8      ExtLNA;
 774        /*  with external PA  NO/Yes = 0/1 */
 775        u8      ExtPA;
 776        /*  with external TRSW  NO/Yes = 0/1 */
 777        u8      ExtTRSW;
 778        u8      PatchID; /* Customer ID */
 779        bool    bInHctTest;
 780        bool    bWIFITest;
 781
 782        bool    bDualMacSmartConcurrent;
 783        u32     BK_SupportAbility;
 784        u8      AntDivType;
 785/* HOOK BEFORE REG INIT----------- */
 786
 787        /*  Dynamic Value */
 788/*  POINTER REFERENCE----------- */
 789
 790        u8      u8_temp;
 791        bool    bool_temp;
 792        struct adapter *adapter_temp;
 793
 794        /*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
 795        u8      *pMacPhyMode;
 796        /* TX Unicast byte count */
 797        u64     *pNumTxBytesUnicast;
 798        /* RX Unicast byte count */
 799        u64     *pNumRxBytesUnicast;
 800        /*  Wireless mode B/G/A/N = BIT(0)/BIT(1)/BIT(2)/BIT(3) */
 801        u8      *pWirelessMode; /* ODM_WIRELESS_MODE_E */
 802        /*  Frequence band 2.4G/5G = 0/1 */
 803        u8      *pBandType;
 804        /*  Secondary channel offset don't_care/below/above = 0/1/2 */
 805        u8      *pSecChOffset;
 806        /*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
 807        u8      *pSecurity;
 808        /*  BW info 20M/40M/80M = 0/1/2 */
 809        u8      *pBandWidth;
 810        /*  Central channel location Ch1/Ch2/.... */
 811        u8      *pChannel;      /* central channel number */
 812        /*  Common info for 92D DMSP */
 813
 814        bool    *pbGetValueFromOtherMac;
 815        struct adapter **pBuddyAdapter;
 816        bool    *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
 817        /*  Common info for Status */
 818        bool    *pbScanInProcess;
 819        bool    *pbPowerSaving;
 820        /*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
 821        u8      *pOnePathCCA;
 822        /* pMgntInfo->AntennaTest */
 823        u8      *pAntennaTest;
 824        bool    *pbNet_closed;
 825/*  POINTER REFERENCE----------- */
 826        /*  */
 827/* CALL BY VALUE------------- */
 828        bool    bWIFI_Direct;
 829        bool    bWIFI_Display;
 830        bool    bLinked;
 831        u8      RSSI_Min;
 832        u8      InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
 833        bool    bIsMPChip;
 834        bool    bOneEntryOnly;
 835        /*  Common info for BTDM */
 836        bool    bBtDisabled;    /*  BT is disabled */
 837        bool    bBtHsOperation; /*  BT HS mode is under progress */
 838        u8      btHsDigVal;     /*  use BT rssi to decide the DIG value */
 839        bool    bBtDisableEdcaTurbo;/* Under some condition, don't enable the
 840                                     * EDCA Turbo */
 841        bool    bBtBusy;                        /*  BT is busy. */
 842/* CALL BY VALUE------------- */
 843
 844        /* 2 Define STA info. */
 845        /*  _ODM_STA_INFO */
 846        /*  For MP, we need to reduce one array pointer for default port.?? */
 847        struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
 848
 849        u16     CurrminRptTime;
 850        struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
 851                        * array index. STA MacID=0,
 852                        * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
 853        /*  */
 854        /*  2012/02/14 MH Add to share 88E ra with other SW team. */
 855        /*  We need to colelct all support abilit to a proper area. */
 856        /*  */
 857        bool    RaSupport88E;
 858
 859        /*  Define ........... */
 860
 861        /*  Latest packet phy info (ODM write) */
 862        struct odm_phy_dbg_info PhyDbgInfo;
 863
 864        /*  Latest packet phy info (ODM write) */
 865        struct odm_mac_status_info *pMacInfo;
 866
 867        /*  Different Team independt structure?? */
 868
 869        /* ODM Structure */
 870        struct fast_ant_train DM_FatTable;
 871        struct rtw_dig  DM_DigTable;
 872        struct rtl_ps   DM_PSTable;
 873        struct dyn_primary_cca DM_PriCCA;
 874        struct rx_hpc   DM_RXHP_Table;
 875        struct false_alarm_stats FalseAlmCnt;
 876        struct false_alarm_stats FlaseAlmCntBuddyAdapter;
 877        struct sw_ant_switch DM_SWAT_Table;
 878        bool            RSSI_test;
 879
 880        struct edca_turbo DM_EDCA_Table;
 881        u32             WMMEDCA_BE;
 882        /*  Copy from SD4 structure */
 883        /*  */
 884        /*  ================================================== */
 885        /*  */
 886
 887        bool    *pbDriverStopped;
 888        bool    *pbDriverIsGoingToPnpSetPowerSleep;
 889        bool    *pinit_adpt_in_progress;
 890
 891        /* PSD */
 892        bool    bUserAssignLevel;
 893        struct timer_list PSDTimer;
 894        u8      RSSI_BT;                        /* come from BT */
 895        bool    bPSDinProcess;
 896        bool    bDMInitialGainEnable;
 897
 898        /* for rate adaptive, in fact,  88c/92c fw will handle this */
 899        u8      bUseRAMask;
 900
 901        struct odm_rate_adapt RateAdaptive;
 902
 903        struct odm_rf_cal RFCalibrateInfo;
 904
 905        /*  TX power tracking */
 906        u8      BbSwingIdxOfdm;
 907        u8      BbSwingIdxOfdmCurrent;
 908        u8      BbSwingIdxOfdmBase;
 909        bool    BbSwingFlagOfdm;
 910        u8      BbSwingIdxCck;
 911        u8      BbSwingIdxCckCurrent;
 912        u8      BbSwingIdxCckBase;
 913        bool    BbSwingFlagCck;
 914        u8      *mp_mode;
 915        /*  ODM system resource. */
 916
 917        /*  ODM relative time. */
 918        struct timer_list PathDivSwitchTimer;
 919        /* 2011.09.27 add for Path Diversity */
 920        struct timer_list CCKPathDiversityTimer;
 921        struct timer_list FastAntTrainingTimer;
 922};              /*  DM_Dynamic_Mechanism_Structure */
 923
 924enum ODM_RF_CONTENT {
 925        odm_radioa_txt = 0x1000,
 926        odm_radiob_txt = 0x1001,
 927        odm_radioc_txt = 0x1002,
 928        odm_radiod_txt = 0x1003
 929};
 930
 931enum odm_bb_config_type {
 932    CONFIG_BB_PHY_REG,
 933    CONFIG_BB_AGC_TAB,
 934    CONFIG_BB_AGC_TAB_2G,
 935    CONFIG_BB_PHY_REG_PG,
 936};
 937
 938/*  Status code */
 939enum rt_status {
 940        RT_STATUS_SUCCESS,
 941        RT_STATUS_FAILURE,
 942        RT_STATUS_PENDING,
 943        RT_STATUS_RESOURCE,
 944        RT_STATUS_INVALID_CONTEXT,
 945        RT_STATUS_INVALID_PARAMETER,
 946        RT_STATUS_NOT_SUPPORT,
 947        RT_STATUS_OS_API_FAILED,
 948};
 949
 950/* 3=========================================================== */
 951/* 3 DIG */
 952/* 3=========================================================== */
 953
 954enum dm_dig_op {
 955        RT_TYPE_THRESH_HIGH     = 0,
 956        RT_TYPE_THRESH_LOW      = 1,
 957        RT_TYPE_BACKOFF         = 2,
 958        RT_TYPE_RX_GAIN_MIN     = 3,
 959        RT_TYPE_RX_GAIN_MAX     = 4,
 960        RT_TYPE_ENABLE          = 5,
 961        RT_TYPE_DISABLE         = 6,
 962        DIG_OP_TYPE_MAX
 963};
 964
 965#define         DM_DIG_THRESH_HIGH      40
 966#define         DM_DIG_THRESH_LOW       35
 967
 968#define         DM_SCAN_RSSI_TH         0x14 /* scan return issue for LC */
 969
 970#define         DM_false_ALARM_THRESH_LOW       400
 971#define         DM_false_ALARM_THRESH_HIGH      1000
 972
 973#define         DM_DIG_MAX_NIC                  0x4e
 974#define         DM_DIG_MIN_NIC                  0x1e /* 0x22/0x1c */
 975
 976#define         DM_DIG_MAX_AP                   0x32
 977#define         DM_DIG_MIN_AP                   0x20
 978
 979#define         DM_DIG_MAX_NIC_HP               0x46
 980#define         DM_DIG_MIN_NIC_HP               0x2e
 981
 982#define         DM_DIG_MAX_AP_HP                0x42
 983#define         DM_DIG_MIN_AP_HP                0x30
 984
 985/* vivi 92c&92d has different definition, 20110504 */
 986/* this is for 92c */
 987#define         DM_DIG_FA_TH0                   0x200/* 0x20 */
 988#define         DM_DIG_FA_TH1                   0x300/* 0x100 */
 989#define         DM_DIG_FA_TH2                   0x400/* 0x200 */
 990/* this is for 92d */
 991#define         DM_DIG_FA_TH0_92D               0x100
 992#define         DM_DIG_FA_TH1_92D               0x400
 993#define         DM_DIG_FA_TH2_92D               0x600
 994
 995#define         DM_DIG_BACKOFF_MAX              12
 996#define         DM_DIG_BACKOFF_MIN              -4
 997#define         DM_DIG_BACKOFF_DEFAULT          10
 998
 999/* 3=========================================================== */
1000/* 3 AGC RX High Power Mode */

1001/* 3=========================================================== */
1002#define   LNA_Low_Gain_1                0x64
1003#define   LNA_Low_Gain_2                0x5A
1004#define   LNA_Low_Gain_3                0x58
1005
1006#define   FA_RXHP_TH1                   5000
1007#define   FA_RXHP_TH2                   1500
1008#define   FA_RXHP_TH3                   800
1009#define   FA_RXHP_TH4                   600
1010#define   FA_RXHP_TH5                   500
1011
1012/* 3=========================================================== */
1013/* 3 EDCA */
1014/* 3=========================================================== */
1015
1016/* 3=========================================================== */
1017/* 3 Dynamic Tx Power */
1018/* 3=========================================================== */
1019/* Dynamic Tx Power Control Threshold */
1020#define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74
1021#define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67
1022#define         TX_POWER_NEAR_FIELD_THRESH_AP           0x3F
1023
1024#define         TxHighPwrLevel_Normal           0
1025#define         TxHighPwrLevel_Level1           1
1026#define         TxHighPwrLevel_Level2           2
1027#define         TxHighPwrLevel_BT1              3
1028#define         TxHighPwrLevel_BT2              4
1029#define         TxHighPwrLevel_15               5
1030#define         TxHighPwrLevel_35               6
1031#define         TxHighPwrLevel_50               7
1032#define         TxHighPwrLevel_70               8
1033#define         TxHighPwrLevel_100              9
1034
1035/* 3=========================================================== */
1036/* 3 Rate Adaptive */
1037/* 3=========================================================== */
1038#define         DM_RATR_STA_INIT                0
1039#define         DM_RATR_STA_HIGH                1
1040#define         DM_RATR_STA_MIDDLE              2
1041#define         DM_RATR_STA_LOW                 3
1042
1043/* 3=========================================================== */
1044/* 3 BB Power Save */
1045/* 3=========================================================== */
1046
1047enum dm_1r_cca {
1048        CCA_1R = 0,
1049        CCA_2R = 1,
1050        CCA_MAX = 2,
1051};
1052
1053enum dm_rf {
1054        RF_Save = 0,
1055        RF_Normal = 1,
1056        RF_MAX = 2,
1057};
1058
1059/* 3=========================================================== */
1060/* 3 Antenna Diversity */
1061/* 3=========================================================== */
1062enum dm_swas {
1063        Antenna_A = 1,
1064        Antenna_B = 2,
1065        Antenna_MAX = 3,
1066};
1067
1068/*  Maximal number of antenna detection mechanism needs to perform. */
1069#define MAX_ANTENNA_DETECTION_CNT       10
1070
1071/*  Extern Global Variables. */
1072#define OFDM_TABLE_SIZE_92C     37
1073#define OFDM_TABLE_SIZE_92D     43
1074#define CCK_TABLE_SIZE          33
1075
1076extern  u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1077extern  u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1078extern  u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
1079
1080/*  check Sta pointer valid or not */
1081#define IS_STA_VALID(pSta)              (pSta)
1082/*  20100514 Joseph: Add definition for antenna switching test after link. */
1083/*  This indicates two different the steps. */
1084/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1085 *  signal on the air. */
1086/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1087 *  SWAW_STEP_PEAK */
1088/*  with original RSSI to determine if it is necessary to switch antenna. */
1089#define SWAW_STEP_PEAK          0
1090#define SWAW_STEP_DETERMINE     1
1091
1092void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);
1093void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1094
1095void ODM_SetAntenna(struct odm_dm_struct *pDM_Odm, u8 Antenna);
1096
1097#define dm_RF_Saving    ODM_RF_Saving
1098void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1099
1100#define SwAntDivRestAfterLink   ODM_SwAntDivRestAfterLink
1101void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm);
1102
1103#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1104void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1105
1106bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1107                      bool bForceUpdate, u8 *pRATRState);
1108
1109#define dm_SWAW_RSSI_Check      ODM_SwAntDivChkPerPktRssi
1110void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID,
1111                               struct odm_phy_status_info *pPhyInfo);
1112
1113u32 ConvertTo_dB(u32 Value);
1114
1115u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point,
1116               u8 initial_gain_psd);
1117
1118void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm);
1119
1120u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1121                        u32 ra_mask, u8 rssi_level);
1122
1123void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1124
1125void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1126
1127void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1128                     enum odm_common_info_def CmnInfo, u32 Value);
1129
1130void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1131                     enum odm_common_info_def CmnInfo, void *pValue);
1132
1133void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1134                             enum odm_common_info_def CmnInfo,
1135                             u16 Index, void *pValue);
1136
1137void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1138
1139void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm);
1140
1141void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm);
1142
1143void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm);
1144
1145void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId,
1146                              u32 PWDBAll, bool isCCKrate);
1147
1148void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm);
1149
1150bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode);
1151
1152void odm_dtc(struct odm_dm_struct *pDM_Odm);
1153
1154#endif
1155