LXR linux/drivers/staging/r8188eu/include/rtl8188e

   1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2/* Copyright(c) 2007 - 2011 Realtek Corporation. */
   3
   4#ifndef __RTL8188E_HAL_H__
   5#define __RTL8188E_HAL_H__
   6
   7/* include HAL Related header after HAL Related compiling flags */
   8#include "rtl8188e_spec.h"
   9#include "Hal8188EPhyReg.h"
  10#include "Hal8188EPhyCfg.h"
  11#include "rtl8188e_rf.h"
  12#include "rtl8188e_dm.h"
  13#include "rtl8188e_recv.h"
  14#include "rtl8188e_xmit.h"
  15#include "rtl8188e_cmd.h"
  16#include "Hal8188EPwrSeq.h"
  17#include "rtl8188e_sreset.h"
  18#include "rtw_efuse.h"
  19
  20#include "odm_precomp.h"
  21
  22/*  Fw Array */
  23#define Rtl8188E_FwImageArray           Rtl8188EFwImgArray
  24#define Rtl8188E_FWImgArrayLength       Rtl8188EFWImgArrayLength
  25
  26#define RTL8188E_FW_UMC_IMG                     "rtl8188E\\rtl8188efw.bin"
  27#define RTL8188E_PHY_REG                        "rtl8188E\\PHY_REG_1T.txt"
  28#define RTL8188E_PHY_RADIO_A                    "rtl8188E\\radio_a_1T.txt"
  29#define RTL8188E_PHY_RADIO_B                    "rtl8188E\\radio_b_1T.txt"
  30#define RTL8188E_AGC_TAB                        "rtl8188E\\AGC_TAB_1T.txt"
  31#define RTL8188E_PHY_MACREG                     "rtl8188E\\MAC_REG.txt"
  32#define RTL8188E_PHY_REG_PG                     "rtl8188E\\PHY_REG_PG.txt"
  33#define RTL8188E_PHY_REG_MP                     "rtl8188E\\PHY_REG_MP.txt"
  34
  35/*              RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
  36#define Rtl8188E_NIC_PWR_ON_FLOW                rtl8188E_power_on_flow
  37#define Rtl8188E_NIC_RF_OFF_FLOW                rtl8188E_radio_off_flow
  38#define Rtl8188E_NIC_DISABLE_FLOW               rtl8188E_card_disable_flow
  39#define Rtl8188E_NIC_ENABLE_FLOW                rtl8188E_card_enable_flow
  40#define Rtl8188E_NIC_SUSPEND_FLOW               rtl8188E_suspend_flow
  41#define Rtl8188E_NIC_RESUME_FLOW                rtl8188E_resume_flow
  42#define Rtl8188E_NIC_PDN_FLOW                   rtl8188E_hwpdn_flow
  43#define Rtl8188E_NIC_LPS_ENTER_FLOW             rtl8188E_enter_lps_flow
  44#define Rtl8188E_NIC_LPS_LEAVE_FLOW             rtl8188E_leave_lps_flow
  45
  46#define DRVINFO_SZ      4 /*  unit is 8bytes */
  47#define PageNum_128(_Len)       (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
  48
  49/*  download firmware related data structure */
  50#define FW_8188E_SIZE                   0x4000 /* 16384,16k */
  51#define FW_8188E_START_ADDRESS          0x1000
  52#define FW_8188E_END_ADDRESS            0x1FFF /* 0x5FFF */
  53
  54#define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  55
  56#define IS_FW_HEADER_EXIST(_pFwHdr)                             \
  57        ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||  \
  58        (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||   \
  59        (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 ||   \
  60        (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0)
  61
  62/*  This structure must be careful with byte-ordering */
  63
  64struct rt_firmware_hdr {
  65        /*  8-byte alinment required */
  66        /*  LONG WORD 0 ---- */
  67        __le16          Signature;      /* 92C0: test chip; 92C,
  68                                         * 88C0: test chip; 88C1: MP A-cut;
  69                                         * 92C1: MP A-cut */
  70        u8              Category;       /*  AP/NIC and USB/PCI */
  71        u8              Function;       /*  Reserved for different FW function
  72                                         *  indcation, for further use when
  73                                         *  driver needs to download different
  74                                         *  FW for different conditions */
  75        __le16          Version;        /*  FW Version */
  76        u8              Subversion;     /*  FW Subversion, default 0x00 */
  77        u16             Rsvd1;
  78
  79        /*  LONG WORD 1 ---- */
  80        u8              Month;  /*  Release time Month field */
  81        u8              Date;   /*  Release time Date field */
  82        u8              Hour;   /*  Release time Hour field */
  83        u8              Minute; /*  Release time Minute field */
  84        __le16          RamCodeSize;    /*  The size of RAM code */
  85        u8              Foundry;
  86        u8              Rsvd2;
  87
  88        /*  LONG WORD 2 ---- */
  89        __le32          SvnIdx; /*  The SVN entry index */
  90        u32             Rsvd3;
  91
  92        /*  LONG WORD 3 ---- */
  93        u32             Rsvd4;
  94        u32             Rsvd5;
  95};
  96
  97#define DRIVER_EARLY_INT_TIME           0x05
  98#define BCN_DMA_ATIME_INT_TIME          0x02
  99
 100enum usb_rx_agg_mode {
 101        USB_RX_AGG_DISABLE,
 102        USB_RX_AGG_DMA,
 103        USB_RX_AGG_USB,
 104        USB_RX_AGG_MIX
 105};
 106
 107#define MAX_RX_DMA_BUFFER_SIZE_88E                              \
 108      0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
 109              * WOLPattern(16*24)) */
 110
 111#define MAX_TX_REPORT_BUFFER_SIZE               0x0400 /*  1k */
 112
 113/*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
 114#define MAX_TX_QUEUE                    9
 115
 116#define TX_SELE_HQ                      BIT(0)          /*  High Queue */
 117#define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
 118#define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
 119
 120/*  Note: We will divide number of page equally for each queue other
 121 *  than public queue! */
 122/*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
 123/*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
 124/*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
 125 *  null-data */
 126
 127#define TX_TOTAL_PAGE_NUMBER_88E                0xA9/*   169 (21632=> 21k) */
 128
 129#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
 130
 131/* Note: For Normal Chip Setting ,modify later */
 132#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER                 \
 133        TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
 134#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E                 \
 135        (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
 136
 137/*      Chip specific */
 138#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 139#define CHIP_BONDING_92C_1T2R   0x1
 140#define CHIP_BONDING_88C_USB_MCARD      0x2
 141#define CHIP_BONDING_88C_USB_HP 0x1
 142#include "HalVerDef.h"
 143#include "hal_com.h"
 144
 145/*      Channel Plan */
 146enum ChannelPlan {
 147        CHPL_FCC        = 0,
 148        CHPL_IC         = 1,
 149        CHPL_ETSI       = 2,
 150        CHPL_SPA        = 3,
 151        CHPL_FRANCE     = 4,
 152        CHPL_MKK        = 5,
 153        CHPL_MKK1       = 6,
 154        CHPL_ISRAEL     = 7,
 155        CHPL_TELEC      = 8,
 156        CHPL_GLOBAL     = 9,
 157        CHPL_WORLD      = 10,
 158};
 159
 160struct txpowerinfo24g {
 161        u8 IndexCCK_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
 162        u8 IndexBW40_Base[RF_PATH_MAX][MAX_CHNL_GROUP_24G];
 163        /* If only one tx, only BW20 and OFDM are used. */
 164        s8 CCK_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 165        s8 OFDM_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 166        s8 BW20_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 167        s8 BW40_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 168};
 169
 170#define EFUSE_REAL_CONTENT_LEN          512
 171#define EFUSE_MAX_SECTION               16
 172#define EFUSE_IC_ID_OFFSET              506 /* For some inferior IC purpose*/
 173#define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 174/*  To prevent out of boundary programming case, */
 175/*  leave 1byte and program full section */
 176/*  9bytes + 1byt + 5bytes and pre 1byte. */
 177/*  For worst case: */
 178/*  | 1byte|----8bytes----|1byte|--5bytes--| */
 179/*  |         |            Reserved(14bytes)          | */
 180
 181/*  PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
 182#define EFUSE_OOB_PROTECT_BYTES                 15
 183
 184#define         HWSET_MAX_SIZE_88E              512
 185
 186#define         EFUSE_REAL_CONTENT_LEN_88E      256
 187#define         EFUSE_MAP_LEN_88E               512
 188#define EFUSE_MAP_LEN                   EFUSE_MAP_LEN_88E
 189#define         EFUSE_MAX_SECTION_88E           64
 190#define         EFUSE_MAX_WORD_UNIT_88E         4
 191#define         EFUSE_IC_ID_OFFSET_88E          506
 192#define         AVAILABLE_EFUSE_ADDR_88E(addr)                  \
 193        (addr < EFUSE_REAL_CONTENT_LEN_88E)
 194/*  To prevent out of boundary programming case, leave 1byte and program
 195 *  full section */
 196/*  9bytes + 1byt + 5bytes and pre 1byte. */
 197/*  For worst case: */
 198/*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
 199/*  PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
 200#define         EFUSE_OOB_PROTECT_BYTES_88E     18
 201#define         EFUSE_PROTECT_BYTES_BANK_88E    16
 202
 203/*                      EFUSE for BT definition */
 204#define EFUSE_BT_REAL_CONTENT_LEN       1536    /*  512*3 */
 205#define EFUSE_BT_MAP_LEN                1024    /*  1k bytes */
 206#define EFUSE_BT_MAX_SECTION            128     /*  1024/8 */
 207
 208#define EFUSE_PROTECT_BYTES_BANK        16
 209
 210/*  For RTL8723 WiFi/BT/GPS multi-function configuration. */
 211enum rt_multi_func {
 212        RT_MULTI_FUNC_NONE = 0x00,
 213        RT_MULTI_FUNC_WIFI = 0x01,
 214        RT_MULTI_FUNC_BT = 0x02,
 215        RT_MULTI_FUNC_GPS = 0x04,
 216};
 217
 218/*  For RTL8723 regulator mode. */
 219enum rt_regulator_mode {
 220        RT_SWITCHING_REGULATOR = 0,
 221        RT_LDO_REGULATOR = 1,
 222};
 223
 224struct hal_data_8188e {
 225        struct HAL_VERSION      VersionID;
 226        enum rt_multi_func MultiFunc; /*  For multi-function consideration. */
 227        enum rt_regulator_mode RegulatorMode; /*  switching regulator or LDO */
 228        u16     CustomerID;
 229
 230        u16     FirmwareVersion;
 231        u16     FirmwareVersionRev;
 232        u16     FirmwareSubVersion;
 233        u16     FirmwareSignature;
 234        u8      PGMaxGroup;
 235        /* current WIFI_PHY values */
 236        u32     ReceiveConfig;
 237        enum wireless_mode CurrentWirelessMode;
 238        enum ht_channel_width CurrentChannelBW;
 239        u8      CurrentChannel;
 240        u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 241
 242        u16     BasicRateSet;
 243
 244        /* rf_ctrl */
 245        u8      rf_chip;
 246        u8      rf_type;
 247        u8      NumTotalRFPath;
 248
 249        u8      BoardType;
 250
 251        /*  EEPROM setting. */
 252        u16     EEPROMVID;
 253        u16     EEPROMPID;
 254        u16     EEPROMSVID;
 255        u16     EEPROMSDID;
 256        u8      EEPROMCustomerID;
 257        u8      EEPROMSubCustomerID;
 258        u8      EEPROMVersion;
 259        u8      EEPROMRegulatory;
 260
 261        u8      bTXPowerDataReadFromEEPORM;
 262        u8      EEPROMThermalMeter;
 263        u8      bAPKThermalMeterIgnore;
 264
 265        bool    EepromOrEfuse;
 266        struct efuse_hal        EfuseHal;
 267
 268        u8      Index24G_CCK_Base[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 269        u8      Index24G_BW40_Base[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 270        /* If only one tx, only BW20 and OFDM are used. */
 271        s8      CCK_24G_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 272        s8      OFDM_24G_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 273        s8      BW20_24G_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 274        s8      BW40_24G_Diff[RF_PATH_MAX][MAX_TX_COUNT];
 275
 276        u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 277        /*  For HT 40MHZ pwr */
 278        u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 279        /*  For HT 40MHZ pwr */
 280        u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 281        /*  HT 20<->40 Pwr diff */
 282        u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 283        /*  For HT<->legacy pwr diff */
 284        u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 285        /*  For power group */
 286        u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 287        u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 288
 289        u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 290        /*  The current Tx Power Level */
 291        u8      CurrentCckTxPwrIdx;
 292        u8      CurrentOfdm24GTxPwrIdx;
 293        u8      CurrentBW2024GTxPwrIdx;
 294        u8      CurrentBW4024GTxPwrIdx;
 295
 296        /*  Read/write are allow for following hardware information variables */
 297        u8      framesync;
 298        u32     framesyncC34;
 299        u8      framesyncMonitor;
 300        u8      DefaultInitialGain[4];
 301        u8      pwrGroupCnt;
 302        u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 303        u32     CCKTxPowerLevelOriginalOffset;
 304
 305        u8      CrystalCap;
 306        u32     AntennaTxPath;                  /*  Antenna path Tx */
 307        u32     AntennaRxPath;                  /*  Antenna path Rx */
 308        u8      BluetoothCoexist;
 309        u8      ExternalPA;
 310
 311        u8      bLedOpenDrain; /* Open-drain support for controlling the LED.*/
 312
 313        u8      b1x1RecvCombine;        /*  for 1T1R receive combining */
 314
 315        u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 316
 317        struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
 318
 319        u32     RfRegChnlVal[2];
 320
 321        /* RDG enable */
 322        bool     bRDGEnable;
 323
 324        /* for host message to fw */
 325        u8      LastHMEBoxNum;
 326
 327        u8      fw_ractrl;
 328        u8      RegTxPause;
 329        /*  Beacon function related global variable. */
 330        u32     RegBcnCtrlVal;
 331        u8      RegFwHwTxQCtrl;
 332        u8      RegReg542;
 333        u8      RegCR_1;
 334
 335        struct dm_priv  dmpriv;
 336        struct odm_dm_struct odmpriv;
 337        struct sreset_priv srestpriv;
 338
 339        u8      CurAntenna;
 340        u8      AntDivCfg;
 341        u8      TRxAntDivType;
 342
 343        u8      bDumpRxPkt;/* for debug */
 344        u8      bDumpTxPkt;/* for debug */
 345        u8      FwRsvdPageStartOffset; /* Reserve page start offset except
 346                                        *  beacon in TxQ. */
 347
 348        /*  2010/08/09 MH Add CU power down mode. */
 349        bool            pwrdown;
 350
 351        /*  Add for dual MAC  0--Mac0 1--Mac1 */
 352        u32     interfaceIndex;
 353
 354        u8      OutEpQueueSel;
 355        u8      OutEpNumber;
 356
 357        /*  Add for USB aggreation mode dynamic shceme. */
 358        bool            UsbRxHighSpeedMode;
 359
 360        /*  2010/11/22 MH Add for slim combo debug mode selective. */
 361        /*  This is used for fix the drawback of CU TSMC-A/UMC-A cut.
 362         * HW auto suspend ability. Close BT clock. */
 363        bool            SlimComboDbg;
 364
 365        u16     EfuseUsedBytes;
 366
 367#ifdef CONFIG_88EU_P2P
 368        struct P2P_PS_Offload_t p2p_ps_offload;
 369#endif
 370
 371        /*  Auto FSM to Turn On, include clock, isolation, power control
 372         *  for MAC only */
 373        u8      bMacPwrCtrlOn;
 374
 375        u32     UsbBulkOutSize;
 376
 377        /*  Interrupt relatd register information. */
 378        u32     IntArray[3];/* HISR0,HISR1,HSISR */
 379        u32     IntrMask[3];
 380        u8      C2hArray[16];
 381        u8      UsbTxAggMode;
 382        u8      UsbTxAggDescNum;
 383        u16     HwRxPageSize;           /*  Hardware setting */
 384        u32     MaxUsbRxAggBlock;
 385
 386        enum usb_rx_agg_mode UsbRxAggMode;
 387        u8      UsbRxAggBlockCount;     /*  USB Block count. Block size is
 388                                         * 512-byte in high speed and 64-byte
 389                                         * in full speed */
 390        u8      UsbRxAggBlockTimeout;
 391        u8      UsbRxAggPageCount;      /*  8192C DMA page count */
 392        u8      UsbRxAggPageTimeout;
 393};
 394
 395#define GET_HAL_DATA(__pAdapter)                                \
 396        ((struct hal_data_8188e *)((__pAdapter)->HalData))
 397#define GET_RF_TYPE(priv)               (GET_HAL_DATA(priv)->rf_type)
 398
 399#define INCLUDE_MULTI_FUNC_BT(_Adapter)                         \
 400        (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
 401#define INCLUDE_MULTI_FUNC_GPS(_Adapter)                        \
 402        (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
 403
 404/*  rtl8188e_hal_init.c */
 405s32 rtl8188e_FirmwareDownload(struct adapter *padapter);
 406void _8051Reset88E(struct adapter *padapter);
 407void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
 408
 409s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
 410
 411/*  EFuse */
 412u8 GetEEPROMSize8188E(struct adapter *padapter);
 413void Hal_InitPGData88E(struct adapter *padapter);
 414void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
 415void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
 416                            bool AutoLoadFail);
 417
 418void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
 419                                bool AutoLoadFail);
 420void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
 421                                 bool AutoLoadFail);
 422void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
 423                                 bool AutoLoadFail);
 424void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter,u8 *PROMContent,
 425                                 bool AutoLoadFail);
 426void Hal_ReadThermalMeter_88E(struct adapter *  dapter, u8 *PROMContent,
 427                              bool AutoloadFail);
 428void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
 429                              bool AutoLoadFail);
 430void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
 431                                bool AutoLoadFail);
 432void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
 433                                bool AutoLoadFail);
 434
 435bool HalDetectPwrDownMode88E(struct adapter *Adapter);
 436
 437void Hal_InitChannelPlan(struct adapter *padapter);
 438void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
 439
 440/*  register */
 441void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits);
 442
 443void rtl8188e_clone_haldata(struct adapter *dst, struct adapter *src);
 444void rtl8188e_start_thread(struct adapter *padapter);
 445void rtl8188e_stop_thread(struct adapter *padapter);
 446
 447void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter  *Adapter, int len);
 448s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
 449void rtw_cancel_all_timer(struct adapter *padapter);
 450void _ps_open_RF(struct adapter *adapt);
 451
 452#endif /* __RTL8188E_HAL_H__ */
 453