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18#ifndef __MAC_H__
19#define __MAC_H__
20
21#include "tmacro.h"
22#include "upc.h"
23
24
25
26#define MAC_MAX_CONTEXT_SIZE_PAGE0 256
27#define MAC_MAX_CONTEXT_SIZE_PAGE1 128
28
29
30#define MAC_REG_BCFG0 0x00
31#define MAC_REG_BCFG1 0x01
32#define MAC_REG_FCR0 0x02
33#define MAC_REG_FCR1 0x03
34#define MAC_REG_BISTCMD 0x04
35#define MAC_REG_BISTSR0 0x05
36#define MAC_REG_BISTSR1 0x06
37#define MAC_REG_BISTSR2 0x07
38#define MAC_REG_I2MCSR 0x08
39#define MAC_REG_I2MTGID 0x09
40#define MAC_REG_I2MTGAD 0x0A
41#define MAC_REG_I2MCFG 0x0B
42#define MAC_REG_I2MDIPT 0x0C
43#define MAC_REG_I2MDOPT 0x0E
44#define MAC_REG_PMC0 0x10
45#define MAC_REG_PMC1 0x11
46#define MAC_REG_STICKHW 0x12
47#define MAC_REG_LOCALID 0x14
48#define MAC_REG_TESTCFG 0x15
49#define MAC_REG_JUMPER0 0x16
50#define MAC_REG_JUMPER1 0x17
51#define MAC_REG_TMCTL0 0x18
52#define MAC_REG_TMCTL1 0x19
53#define MAC_REG_TMDATA0 0x1C
54
55
56#define MAC_REG_LRT 0x20
57#define MAC_REG_SRT 0x21
58#define MAC_REG_SIFS 0x22
59#define MAC_REG_DIFS 0x23
60#define MAC_REG_EIFS 0x24
61#define MAC_REG_SLOT 0x25
62#define MAC_REG_BI 0x26
63#define MAC_REG_CWMAXMIN0 0x28
64#define MAC_REG_LINKOFFTOTM 0x2A
65#define MAC_REG_SWTMOT 0x2B
66#define MAC_REG_MIBCNTR 0x2C
67#define MAC_REG_RTSOKCNT 0x2C
68#define MAC_REG_RTSFAILCNT 0x2D
69#define MAC_REG_ACKFAILCNT 0x2E
70#define MAC_REG_FCSERRCNT 0x2F
71
72
73#define MAC_REG_TSFCNTR 0x30
74#define MAC_REG_NEXTTBTT 0x38
75#define MAC_REG_TSFOFST 0x40
76#define MAC_REG_TFTCTL 0x48
77
78
79#define MAC_REG_ENCFG 0x4C
80#define MAC_REG_PAGE1SEL 0x4F
81#define MAC_REG_CFG 0x50
82#define MAC_REG_TEST 0x52
83#define MAC_REG_HOSTCR 0x54
84#define MAC_REG_MACCR 0x55
85#define MAC_REG_RCR 0x56
86#define MAC_REG_TCR 0x57
87#define MAC_REG_IMR 0x58
88#define MAC_REG_ISR 0x5C
89
90
91#define MAC_REG_PSCFG 0x60
92#define MAC_REG_PSCTL 0x61
93#define MAC_REG_PSPWRSIG 0x62
94#define MAC_REG_BBCR13 0x63
95#define MAC_REG_AIDATIM 0x64
96#define MAC_REG_PWBT 0x66
97#define MAC_REG_WAKEOKTMR 0x68
98#define MAC_REG_CALTMR 0x69
99#define MAC_REG_SYNSPACCNT 0x6A
100#define MAC_REG_WAKSYNOPT 0x6B
101
102
103#define MAC_REG_BBREGCTL 0x6C
104#define MAC_REG_CHANNEL 0x6D
105#define MAC_REG_BBREGADR 0x6E
106#define MAC_REG_BBREGDATA 0x6F
107#define MAC_REG_IFREGCTL 0x70
108#define MAC_REG_IFDATA 0x71
109#define MAC_REG_ITRTMSET 0x74
110#define MAC_REG_PAPEDELAY 0x77
111#define MAC_REG_SOFTPWRCTL 0x78
112#define MAC_REG_GPIOCTL0 0x7A
113#define MAC_REG_GPIOCTL1 0x7B
114
115
116#define MAC_REG_TXDMACTL0 0x7C
117#define MAC_REG_TXDMAPTR0 0x80
118#define MAC_REG_AC0DMACTL 0x84
119#define MAC_REG_AC0DMAPTR 0x88
120#define MAC_REG_BCNDMACTL 0x8C
121#define MAC_REG_BCNDMAPTR 0x90
122#define MAC_REG_RXDMACTL0 0x94
123#define MAC_REG_RXDMAPTR0 0x98
124#define MAC_REG_RXDMACTL1 0x9C
125#define MAC_REG_RXDMAPTR1 0xA0
126#define MAC_REG_SYNCDMACTL 0xA4
127#define MAC_REG_SYNCDMAPTR 0xA8
128#define MAC_REG_ATIMDMACTL 0xAC
129#define MAC_REG_ATIMDMAPTR 0xB0
130
131
132#define MAC_REG_MISCFFNDEX 0xB4
133#define MAC_REG_MISCFFCTL 0xB6
134#define MAC_REG_MISCFFDATA 0xB8
135
136
137#define MAC_REG_TMDATA1 0xBC
138
139
140#define MAC_REG_WAKEUPEN0 0xC0
141#define MAC_REG_WAKEUPEN1 0xC1
142#define MAC_REG_WAKEUPSR0 0xC2
143#define MAC_REG_WAKEUPSR1 0xC3
144#define MAC_REG_WAKE128_0 0xC4
145#define MAC_REG_WAKE128_1 0xD4
146#define MAC_REG_WAKE128_2 0xE4
147#define MAC_REG_WAKE128_3 0xF4
148
149
150#define MAC_REG_CRC_128_0 0x04
151#define MAC_REG_CRC_128_1 0x06
152#define MAC_REG_CRC_128_2 0x08
153#define MAC_REG_CRC_128_3 0x0A
154
155
156#define MAC_REG_PAR0 0x0C
157#define MAC_REG_PAR4 0x10
158#define MAC_REG_BSSID0 0x14
159#define MAC_REG_BSSID4 0x18
160#define MAC_REG_MAR0 0x1C
161#define MAC_REG_MAR4 0x20
162
163
164#define MAC_REG_RSPINF_B_1 0x24
165#define MAC_REG_RSPINF_B_2 0x28
166#define MAC_REG_RSPINF_B_5 0x2C
167#define MAC_REG_RSPINF_B_11 0x30
168#define MAC_REG_RSPINF_A_6 0x34
169#define MAC_REG_RSPINF_A_9 0x36
170#define MAC_REG_RSPINF_A_12 0x38
171#define MAC_REG_RSPINF_A_18 0x3A
172#define MAC_REG_RSPINF_A_24 0x3C
173#define MAC_REG_RSPINF_A_36 0x3E
174#define MAC_REG_RSPINF_A_48 0x40
175#define MAC_REG_RSPINF_A_54 0x42
176#define MAC_REG_RSPINF_A_72 0x44
177
178
179#define MAC_REG_QUIETINIT 0x60
180#define MAC_REG_QUIETGAP 0x62
181#define MAC_REG_QUIETDUR 0x64
182#define MAC_REG_MSRCTL 0x66
183#define MAC_REG_MSRBBSTS 0x67
184#define MAC_REG_MSRSTART 0x68
185#define MAC_REG_MSRDURATION 0x70
186#define MAC_REG_CCAFRACTION 0x72
187#define MAC_REG_PWRCCK 0x73
188#define MAC_REG_PWROFDM 0x7C
189
190
191#define BCFG0_PERROFF 0x40
192#define BCFG0_MRDMDIS 0x20
193#define BCFG0_MRDLDIS 0x10
194#define BCFG0_MWMEN 0x08
195#define BCFG0_VSERREN 0x02
196#define BCFG0_LATMEN 0x01
197
198
199#define BCFG1_CFUNOPT 0x80
200#define BCFG1_CREQOPT 0x40
201#define BCFG1_DMA8 0x10
202#define BCFG1_ARBITOPT 0x08
203#define BCFG1_PCIMEN 0x04
204#define BCFG1_MIOEN 0x02
205#define BCFG1_CISDLYEN 0x01
206
207
208#define BISTCMD_TSTPAT5 0x00
209#define BISTCMD_TSTPATA 0x80
210#define BISTCMD_TSTERR 0x20
211#define BISTCMD_TSTPATF 0x18
212#define BISTCMD_TSTPAT0 0x10
213#define BISTCMD_TSTMODE 0x04
214#define BISTCMD_TSTITTX 0x03
215#define BISTCMD_TSTATRX 0x02
216#define BISTCMD_TSTATTX 0x01
217#define BISTCMD_TSTRX 0x00
218#define BISTSR0_BISTGO 0x01
219#define BISTSR1_TSTSR 0x01
220#define BISTSR2_CMDPRTEN 0x02
221#define BISTSR2_RAMTSTEN 0x01
222
223
224#define I2MCFG_BOUNDCTL 0x80
225#define I2MCFG_WAITCTL 0x20
226#define I2MCFG_SCLOECTL 0x10
227#define I2MCFG_WBUSYCTL 0x08
228#define I2MCFG_NORETRY 0x04
229#define I2MCFG_I2MLDSEQ 0x02
230#define I2MCFG_I2CMFAST 0x01
231
232
233#define I2MCSR_EEMW 0x80
234#define I2MCSR_EEMR 0x40
235#define I2MCSR_AUTOLD 0x08
236#define I2MCSR_NACK 0x02
237#define I2MCSR_DONE 0x01
238
239
240#define SPS_RST 0x80
241#define PCISTIKY 0x40
242#define PME_OVR 0x02
243
244
245#define STICKHW_DS1_SHADOW 0x02
246#define STICKHW_DS0_SHADOW 0x01
247
248
249#define TMCTL_TSUSP 0x04
250#define TMCTL_TMD 0x02
251#define TMCTL_TE 0x01
252
253
254#define TFTCTL_HWUTSF 0x80
255#define TFTCTL_TBTTSYNC 0x40
256#define TFTCTL_HWUTSFEN 0x20
257#define TFTCTL_TSFCNTRRD 0x10
258#define TFTCTL_TBTTSYNCEN 0x08
259#define TFTCTL_TSFSYNCEN 0x04
260#define TFTCTL_TSFCNTRST 0x02
261#define TFTCTL_TSFCNTREN 0x01
262
263
264#define EnCFG_BarkerPream 0x00020000
265#define EnCFG_NXTBTTCFPSTR 0x00010000
266#define EnCFG_BcnSusClr 0x00000200
267#define EnCFG_BcnSusInd 0x00000100
268#define EnCFG_CFP_ProtectEn 0x00000040
269#define EnCFG_ProtectMd 0x00000020
270#define EnCFG_HwParCFP 0x00000010
271#define EnCFG_CFNULRSP 0x00000004
272#define EnCFG_BBType_MASK 0x00000003
273#define EnCFG_BBType_g 0x00000002
274#define EnCFG_BBType_b 0x00000001
275#define EnCFG_BBType_a 0x00000000
276
277
278#define PAGE1_SEL 0x01
279
280
281#define CFG_TKIPOPT 0x80
282#define CFG_RXDMAOPT 0x40
283#define CFG_TMOT_SW 0x20
284#define CFG_TMOT_HWLONG 0x10
285#define CFG_TMOT_HW 0x00
286#define CFG_CFPENDOPT 0x08
287#define CFG_BCNSUSEN 0x04
288#define CFG_NOTXTIMEOUT 0x02
289#define CFG_NOBUFOPT 0x01
290
291
292#define TEST_LBEXT 0x80
293#define TEST_LBINT 0x40
294#define TEST_LBNONE 0x00
295#define TEST_SOFTINT 0x20
296#define TEST_CONTTX 0x10
297#define TEST_TXPE 0x08
298#define TEST_NAVDIS 0x04
299#define TEST_NOCTS 0x02
300#define TEST_NOACK 0x01
301
302
303#define HOSTCR_TXONST 0x80
304#define HOSTCR_RXONST 0x40
305#define HOSTCR_ADHOC 0x20
306#define HOSTCR_AP 0x10
307#define HOSTCR_TXON 0x08
308#define HOSTCR_RXON 0x04
309#define HOSTCR_MACEN 0x02
310#define HOSTCR_SOFTRST 0x01
311
312
313#define MACCR_SYNCFLUSHOK 0x04
314#define MACCR_SYNCFLUSH 0x02
315#define MACCR_CLRNAV 0x01
316
317
318#define LED_ACTSET 0x01
319#define LED_RFOFF 0x02
320#define LED_NOCONNECT 0x04
321
322
323#define RCR_SSID 0x80
324#define RCR_RXALLTYPE 0x40
325#define RCR_UNICAST 0x20
326#define RCR_BROADCAST 0x10
327#define RCR_MULTICAST 0x08
328#define RCR_WPAERR 0x04
329#define RCR_ERRCRC 0x02
330#define RCR_BSSID 0x01
331
332
333#define TCR_SYNCDCFOPT 0x02
334#define TCR_AUTOBCNTX 0x01
335
336
337#define IMR_MEASURESTART 0x80000000
338#define IMR_QUIETSTART 0x20000000
339#define IMR_RADARDETECT 0x10000000
340#define IMR_MEASUREEND 0x08000000
341#define IMR_SOFTTIMER1 0x00200000
342#define IMR_RXDMA1 0x00001000
343#define IMR_RXNOBUF 0x00000800
344#define IMR_MIBNEARFULL 0x00000400
345#define IMR_SOFTINT 0x00000200
346#define IMR_FETALERR 0x00000100
347#define IMR_WATCHDOG 0x00000080
348#define IMR_SOFTTIMER 0x00000040
349#define IMR_GPIO 0x00000020
350#define IMR_TBTT 0x00000010
351#define IMR_RXDMA0 0x00000008
352#define IMR_BNTX 0x00000004
353#define IMR_AC0DMA 0x00000002
354#define IMR_TXDMA0 0x00000001
355
356
357#define ISR_MEASURESTART 0x80000000
358#define ISR_QUIETSTART 0x20000000
359#define ISR_RADARDETECT 0x10000000
360#define ISR_MEASUREEND 0x08000000
361#define ISR_SOFTTIMER1 0x00200000
362#define ISR_RXDMA1 0x00001000
363#define ISR_RXNOBUF 0x00000800
364#define ISR_MIBNEARFULL 0x00000400
365#define ISR_SOFTINT 0x00000200
366#define ISR_FETALERR 0x00000100
367#define ISR_WATCHDOG 0x00000080
368#define ISR_SOFTTIMER 0x00000040
369#define ISR_GPIO 0x00000020
370#define ISR_TBTT 0x00000010
371#define ISR_RXDMA0 0x00000008
372#define ISR_BNTX 0x00000004
373#define ISR_AC0DMA 0x00000002
374#define ISR_TXDMA0 0x00000001
375
376
377#define PSCFG_PHILIPMD 0x40
378#define PSCFG_WAKECALEN 0x20
379#define PSCFG_WAKETMREN 0x10
380#define PSCFG_BBPSPROG 0x08
381#define PSCFG_WAKESYN 0x04
382#define PSCFG_SLEEPSYN 0x02
383#define PSCFG_AUTOSLEEP 0x01
384
385
386#define PSCTL_WAKEDONE 0x20
387#define PSCTL_PS 0x10
388#define PSCTL_GO2DOZE 0x08
389#define PSCTL_LNBCN 0x04
390#define PSCTL_ALBCN 0x02
391#define PSCTL_PSEN 0x01
392
393
394#define PSSIG_WPE3 0x80
395#define PSSIG_WPE2 0x40
396#define PSSIG_WPE1 0x20
397#define PSSIG_WRADIOPE 0x10
398#define PSSIG_SPE3 0x08
399#define PSSIG_SPE2 0x04
400#define PSSIG_SPE1 0x02
401#define PSSIG_SRADIOPE 0x01
402
403
404#define BBREGCTL_DONE 0x04
405#define BBREGCTL_REGR 0x02
406#define BBREGCTL_REGW 0x01
407
408
409#define IFREGCTL_DONE 0x04
410#define IFREGCTL_IFRF 0x02
411#define IFREGCTL_REGW 0x01
412
413
414#define SOFTPWRCTL_RFLEOPT 0x0800
415#define SOFTPWRCTL_TXPEINV 0x0200
416#define SOFTPWRCTL_SWPECTI 0x0100
417#define SOFTPWRCTL_SWPAPE 0x0020
418#define SOFTPWRCTL_SWCALEN 0x0010
419#define SOFTPWRCTL_SWRADIO_PE 0x0008
420#define SOFTPWRCTL_SWPE2 0x0004
421#define SOFTPWRCTL_SWPE1 0x0002
422#define SOFTPWRCTL_SWPE3 0x0001
423
424
425#define GPIO1_DATA1 0x20
426#define GPIO1_MD1 0x10
427#define GPIO1_DATA0 0x02
428#define GPIO1_MD0 0x01
429
430
431#define DMACTL_CLRRUN 0x00080000
432#define DMACTL_RUN 0x00000008
433#define DMACTL_WAKE 0x00000004
434#define DMACTL_DEAD 0x00000002
435#define DMACTL_ACTIVE 0x00000001
436
437
438#define RX_PERPKT 0x00000100
439#define RX_PERPKTCLR 0x01000000
440
441
442#define BEACON_READY 0x01
443
444
445#define MISCFFCTL_WRITE 0x0001
446
447
448#define WAKEUPEN0_DIRPKT 0x10
449#define WAKEUPEN0_LINKOFF 0x08
450#define WAKEUPEN0_ATIMEN 0x04
451#define WAKEUPEN0_TIMEN 0x02
452#define WAKEUPEN0_MAGICEN 0x01
453
454
455#define WAKEUPEN1_128_3 0x08
456#define WAKEUPEN1_128_2 0x04
457#define WAKEUPEN1_128_1 0x02
458#define WAKEUPEN1_128_0 0x01
459
460
461#define WAKEUPSR0_DIRPKT 0x10
462#define WAKEUPSR0_LINKOFF 0x08
463#define WAKEUPSR0_ATIMEN 0x04
464#define WAKEUPSR0_TIMEN 0x02
465#define WAKEUPSR0_MAGICEN 0x01
466
467
468#define WAKEUPSR1_128_3 0x08
469#define WAKEUPSR1_128_2 0x04
470#define WAKEUPSR1_128_1 0x02
471#define WAKEUPSR1_128_0 0x01
472
473
474#define GPIO0_MD 0x01
475#define GPIO0_DATA 0x02
476#define GPIO0_INTMD 0x04
477#define GPIO1_MD 0x10
478#define GPIO1_DATA 0x20
479
480
481#define MSRCTL_FINISH 0x80
482#define MSRCTL_READY 0x40
483#define MSRCTL_RADARDETECT 0x20
484#define MSRCTL_EN 0x10
485#define MSRCTL_QUIETTXCHK 0x08
486#define MSRCTL_QUIETRPT 0x04
487#define MSRCTL_QUIETINT 0x02
488#define MSRCTL_QUIETEN 0x01
489
490
491#define MSRCTL1_TXPWR 0x08
492#define MSRCTL1_CSAPAREN 0x04
493#define MSRCTL1_TXPAUSE 0x01
494
495
496#define MAC_LB_EXT 0x02
497#define MAC_LB_INTERNAL 0x01
498#define MAC_LB_NONE 0x00
499
500#define Default_BI 0x200
501
502
503#define MISCFIFO_KEYETRY0 32
504#define MISCFIFO_KEYENTRYSIZE 22
505#define MISCFIFO_SYNINFO_IDX 10
506#define MISCFIFO_SYNDATA_IDX 11
507#define MISCFIFO_SYNDATASIZE 21
508
509
510#define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \
511 IMR_RXDMA1 | \
512 IMR_RXNOBUF | \
513 IMR_MIBNEARFULL | \
514 IMR_SOFTINT | \
515 IMR_FETALERR | \
516 IMR_WATCHDOG | \
517 IMR_SOFTTIMER | \
518 IMR_GPIO | \
519 IMR_TBTT | \
520 IMR_RXDMA0 | \
521 IMR_BNTX | \
522 IMR_AC0DMA | \
523 IMR_TXDMA0)
524
525
526#define W_MAX_TIMEOUT 0xFFF0U
527
528
529#define CB_DELAY_LOOP_WAIT 10
530
531
532#define REV_ID_VT3253_A0 0x00
533#define REV_ID_VT3253_A1 0x01
534#define REV_ID_VT3253_B0 0x08
535#define REV_ID_VT3253_B1 0x09
536
537
538
539
540
541#define MACvRegBitsOn(iobase, byRegOfs, byBits) \
542do { \
543 unsigned char byData; \
544 VNSvInPortB(iobase + byRegOfs, &byData); \
545 VNSvOutPortB(iobase + byRegOfs, byData | (byBits)); \
546} while (0)
547
548#define MACvWordRegBitsOn(iobase, byRegOfs, wBits) \
549do { \
550 unsigned short wData; \
551 VNSvInPortW(iobase + byRegOfs, &wData); \
552 VNSvOutPortW(iobase + byRegOfs, wData | (wBits)); \
553} while (0)
554
555#define MACvDWordRegBitsOn(iobase, byRegOfs, dwBits) \
556do { \
557 unsigned long dwData; \
558 VNSvInPortD(iobase + byRegOfs, &dwData); \
559 VNSvOutPortD(iobase + byRegOfs, dwData | (dwBits)); \
560} while (0)
561
562#define MACvRegBitsOnEx(iobase, byRegOfs, byMask, byBits) \
563do { \
564 unsigned char byData; \
565 VNSvInPortB(iobase + byRegOfs, &byData); \
566 byData &= byMask; \
567 VNSvOutPortB(iobase + byRegOfs, byData | (byBits)); \
568} while (0)
569
570#define MACvRegBitsOff(iobase, byRegOfs, byBits) \
571do { \
572 unsigned char byData; \
573 VNSvInPortB(iobase + byRegOfs, &byData); \
574 VNSvOutPortB(iobase + byRegOfs, byData & ~(byBits)); \
575} while (0)
576
577#define MACvWordRegBitsOff(iobase, byRegOfs, wBits) \
578do { \
579 unsigned short wData; \
580 VNSvInPortW(iobase + byRegOfs, &wData); \
581 VNSvOutPortW(iobase + byRegOfs, wData & ~(wBits)); \
582} while (0)
583
584#define MACvDWordRegBitsOff(iobase, byRegOfs, dwBits) \
585do { \
586 unsigned long dwData; \
587 VNSvInPortD(iobase + byRegOfs, &dwData); \
588 VNSvOutPortD(iobase + byRegOfs, dwData & ~(dwBits)); \
589} while (0)
590
591#define MACvGetCurrRx0DescAddr(iobase, pdwCurrDescAddr) \
592 VNSvInPortD(iobase + MAC_REG_RXDMAPTR0, \
593 (unsigned long *)pdwCurrDescAddr)
594
595#define MACvGetCurrRx1DescAddr(iobase, pdwCurrDescAddr) \
596 VNSvInPortD(iobase + MAC_REG_RXDMAPTR1, \
597 (unsigned long *)pdwCurrDescAddr)
598
599#define MACvGetCurrTx0DescAddr(iobase, pdwCurrDescAddr) \
600 VNSvInPortD(iobase + MAC_REG_TXDMAPTR0, \
601 (unsigned long *)pdwCurrDescAddr)
602
603#define MACvGetCurrAC0DescAddr(iobase, pdwCurrDescAddr) \
604 VNSvInPortD(iobase + MAC_REG_AC0DMAPTR, \
605 (unsigned long *)pdwCurrDescAddr)
606
607#define MACvGetCurrSyncDescAddr(iobase, pdwCurrDescAddr) \
608 VNSvInPortD(iobase + MAC_REG_SYNCDMAPTR, \
609 (unsigned long *)pdwCurrDescAddr)
610
611#define MACvGetCurrATIMDescAddr(iobase, pdwCurrDescAddr) \
612 VNSvInPortD(iobase + MAC_REG_ATIMDMAPTR, \
613 (unsigned long *)pdwCurrDescAddr)
614
615
616#define MACvSetCurrBCNTxDescAddr(iobase, dwCurrDescAddr) \
617 VNSvOutPortD(iobase + MAC_REG_BCNDMAPTR, \
618 dwCurrDescAddr)
619
620
621#define MACvSetCurrBCNLength(iobase, wCurrBCNLength) \
622 VNSvOutPortW(iobase + MAC_REG_BCNDMACTL + 2, \
623 wCurrBCNLength)
624
625#define MACvReadBSSIDAddress(iobase, pbyEtherAddr) \
626do { \
627 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
628 VNSvInPortB(iobase + MAC_REG_BSSID0, \
629 (unsigned char *)pbyEtherAddr); \
630 VNSvInPortB(iobase + MAC_REG_BSSID0 + 1, \
631 pbyEtherAddr + 1); \
632 VNSvInPortB(iobase + MAC_REG_BSSID0 + 2, \
633 pbyEtherAddr + 2); \
634 VNSvInPortB(iobase + MAC_REG_BSSID0 + 3, \
635 pbyEtherAddr + 3); \
636 VNSvInPortB(iobase + MAC_REG_BSSID0 + 4, \
637 pbyEtherAddr + 4); \
638 VNSvInPortB(iobase + MAC_REG_BSSID0 + 5, \
639 pbyEtherAddr + 5); \
640 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
641} while (0)
642
643#define MACvWriteBSSIDAddress(iobase, pbyEtherAddr) \
644do { \
645 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
646 VNSvOutPortB(iobase + MAC_REG_BSSID0, \
647 *(pbyEtherAddr)); \
648 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 1, \
649 *(pbyEtherAddr + 1)); \
650 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 2, \
651 *(pbyEtherAddr + 2)); \
652 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 3, \
653 *(pbyEtherAddr + 3)); \
654 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 4, \
655 *(pbyEtherAddr + 4)); \
656 VNSvOutPortB(iobase + MAC_REG_BSSID0 + 5, \
657 *(pbyEtherAddr + 5)); \
658 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
659} while (0)
660
661#define MACvReadEtherAddress(iobase, pbyEtherAddr) \
662do { \
663 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
664 VNSvInPortB(iobase + MAC_REG_PAR0, \
665 (unsigned char *)pbyEtherAddr); \
666 VNSvInPortB(iobase + MAC_REG_PAR0 + 1, \
667 pbyEtherAddr + 1); \
668 VNSvInPortB(iobase + MAC_REG_PAR0 + 2, \
669 pbyEtherAddr + 2); \
670 VNSvInPortB(iobase + MAC_REG_PAR0 + 3, \
671 pbyEtherAddr + 3); \
672 VNSvInPortB(iobase + MAC_REG_PAR0 + 4, \
673 pbyEtherAddr + 4); \
674 VNSvInPortB(iobase + MAC_REG_PAR0 + 5, \
675 pbyEtherAddr + 5); \
676 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
677} while (0)
678
679#define MACvWriteEtherAddress(iobase, pbyEtherAddr) \
680do { \
681 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
682 VNSvOutPortB(iobase + MAC_REG_PAR0, \
683 *pbyEtherAddr); \
684 VNSvOutPortB(iobase + MAC_REG_PAR0 + 1, \
685 *(pbyEtherAddr + 1)); \
686 VNSvOutPortB(iobase + MAC_REG_PAR0 + 2, \
687 *(pbyEtherAddr + 2)); \
688 VNSvOutPortB(iobase + MAC_REG_PAR0 + 3, \
689 *(pbyEtherAddr + 3)); \
690 VNSvOutPortB(iobase + MAC_REG_PAR0 + 4, \
691 *(pbyEtherAddr + 4)); \
692 VNSvOutPortB(iobase + MAC_REG_PAR0 + 5, \
693 *(pbyEtherAddr + 5)); \
694 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
695} while (0)
696
697#define MACvClearISR(iobase) \
698 VNSvOutPortD(iobase + MAC_REG_ISR, IMR_MASK_VALUE)
699
700#define MACvStart(iobase) \
701 VNSvOutPortB(iobase + MAC_REG_HOSTCR, \
702 (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON))
703
704#define MACvRx0PerPktMode(iobase) \
705 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKT)
706
707#define MACvRx0BufferFillMode(iobase) \
708 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, RX_PERPKTCLR)
709
710#define MACvRx1PerPktMode(iobase) \
711 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKT)
712
713#define MACvRx1BufferFillMode(iobase) \
714 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, RX_PERPKTCLR)
715
716#define MACvRxOn(iobase) \
717 MACvRegBitsOn(iobase, MAC_REG_HOSTCR, HOSTCR_RXON)
718
719#define MACvReceive0(iobase) \
720do { \
721 unsigned long dwData; \
722 VNSvInPortD(iobase + MAC_REG_RXDMACTL0, &dwData); \
723 if (dwData & DMACTL_RUN) \
724 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
725 else \
726 VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
727} while (0)
728
729#define MACvReceive1(iobase) \
730do { \
731 unsigned long dwData; \
732 VNSvInPortD(iobase + MAC_REG_RXDMACTL1, &dwData); \
733 if (dwData & DMACTL_RUN) \
734 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
735 else \
736 VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
737} while (0)
738
739#define MACvTxOn(iobase) \
740 MACvRegBitsOn(iobase, MAC_REG_HOSTCR, HOSTCR_TXON)
741
742#define MACvTransmit0(iobase) \
743do { \
744 unsigned long dwData; \
745 VNSvInPortD(iobase + MAC_REG_TXDMACTL0, &dwData); \
746 if (dwData & DMACTL_RUN) \
747 VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
748 else \
749 VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
750} while (0)
751
752#define MACvTransmitAC0(iobase) \
753do { \
754 unsigned long dwData; \
755 VNSvInPortD(iobase + MAC_REG_AC0DMACTL, &dwData); \
756 if (dwData & DMACTL_RUN) \
757 VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
758 else \
759 VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
760} while (0)
761
762#define MACvTransmitSYNC(iobase) \
763do { \
764 unsigned long dwData; \
765 VNSvInPortD(iobase + MAC_REG_SYNCDMACTL, &dwData); \
766 if (dwData & DMACTL_RUN) \
767 VNSvOutPortD(iobase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
768 else \
769 VNSvOutPortD(iobase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
770} while (0)
771
772#define MACvTransmitATIM(iobase) \
773do { \
774 unsigned long dwData; \
775 VNSvInPortD(iobase + MAC_REG_ATIMDMACTL, &dwData); \
776 if (dwData & DMACTL_RUN) \
777 VNSvOutPortD(iobase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
778 else \
779 VNSvOutPortD(iobase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
780} while (0)
781
782#define MACvTransmitBCN(iobase) \
783 VNSvOutPortB(iobase + MAC_REG_BCNDMACTL, BEACON_READY)
784
785#define MACvClearStckDS(iobase) \
786do { \
787 unsigned char byOrgValue; \
788 VNSvInPortB(iobase + MAC_REG_STICKHW, &byOrgValue); \
789 byOrgValue = byOrgValue & 0xFC; \
790 VNSvOutPortB(iobase + MAC_REG_STICKHW, byOrgValue); \
791} while (0)
792
793#define MACvReadISR(iobase, pdwValue) \
794 VNSvInPortD(iobase + MAC_REG_ISR, pdwValue)
795
796#define MACvWriteISR(iobase, dwValue) \
797 VNSvOutPortD(iobase + MAC_REG_ISR, dwValue)
798
799#define MACvIntEnable(iobase, dwMask) \
800 VNSvOutPortD(iobase + MAC_REG_IMR, dwMask)
801
802#define MACvIntDisable(iobase) \
803 VNSvOutPortD(iobase + MAC_REG_IMR, 0)
804
805#define MACvSelectPage0(iobase) \
806 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0)
807
808#define MACvSelectPage1(iobase) \
809 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1)
810
811#define MACvReadMIBCounter(iobase, pdwCounter) \
812 VNSvInPortD(iobase + MAC_REG_MIBCNTR, pdwCounter)
813
814#define MACvPwrEvntDisable(iobase) \
815 VNSvOutPortW(iobase + MAC_REG_WAKEUPEN0, 0x0000)
816
817#define MACvEnableProtectMD(iobase) \
818do { \
819 unsigned long dwOrgValue; \
820 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
821 dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
822 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
823} while (0)
824
825#define MACvDisableProtectMD(iobase) \
826do { \
827 unsigned long dwOrgValue; \
828 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
829 dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
830 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
831} while (0)
832
833#define MACvEnableBarkerPreambleMd(iobase) \
834do { \
835 unsigned long dwOrgValue; \
836 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
837 dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
838 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
839} while (0)
840
841#define MACvDisableBarkerPreambleMd(iobase) \
842do { \
843 unsigned long dwOrgValue; \
844 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
845 dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
846 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
847} while (0)
848
849#define MACvSetBBType(iobase, byTyp) \
850do { \
851 unsigned long dwOrgValue; \
852 VNSvInPortD(iobase + MAC_REG_ENCFG, &dwOrgValue); \
853 dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
854 dwOrgValue = dwOrgValue | (unsigned long)byTyp; \
855 VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
856} while (0)
857
858#define MACvReadATIMW(iobase, pwCounter) \
859 VNSvInPortW(iobase + MAC_REG_AIDATIM, pwCounter)
860
861#define MACvWriteATIMW(iobase, wCounter) \
862 VNSvOutPortW(iobase + MAC_REG_AIDATIM, wCounter)
863
864#define MACvWriteCRC16_128(iobase, byRegOfs, wCRC) \
865do { \
866 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 1); \
867 VNSvOutPortW(iobase + byRegOfs, wCRC); \
868 VNSvOutPortB(iobase + MAC_REG_PAGE1SEL, 0); \
869} while (0)
870
871#define MACvGPIOIn(iobase, pbyValue) \
872 VNSvInPortB(iobase + MAC_REG_GPIOCTL1, pbyValue)
873
874#define MACvSetRFLE_LatchBase(iobase) \
875 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
876
877bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
878 unsigned char byTestBits);
879
880bool MACbIsIntDisable(struct vnt_private *priv);
881
882void MACvSetShortRetryLimit(struct vnt_private *priv,
883 unsigned char byRetryLimit);
884
885void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit);
886
887void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode);
888
889void MACvSaveContext(struct vnt_private *priv, unsigned char *pbyCxtBuf);
890void MACvRestoreContext(struct vnt_private *priv, unsigned char *pbyCxtBuf);
891
892bool MACbSoftwareReset(struct vnt_private *priv);
893bool MACbSafeSoftwareReset(struct vnt_private *priv);
894bool MACbSafeRxOff(struct vnt_private *priv);
895bool MACbSafeTxOff(struct vnt_private *priv);
896bool MACbSafeStop(struct vnt_private *priv);
897bool MACbShutdown(struct vnt_private *priv);
898void MACvInitialize(struct vnt_private *priv);
899void MACvSetCurrRx0DescAddr(struct vnt_private *priv,
900 u32 curr_desc_addr);
901void MACvSetCurrRx1DescAddr(struct vnt_private *priv,
902 u32 curr_desc_addr);
903void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
904 u32 curr_desc_addr);
905void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
906 u32 curr_desc_addr);
907void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
908 u32 curr_desc_addr);
909void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv,
910 u32 curr_desc_addr);
911void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv,
912 u32 curr_desc_addr);
913void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay);
914void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime);
915
916void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset,
917 u32 dwData);
918
919bool MACbPSWakeup(struct vnt_private *priv);
920
921void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
922 unsigned int uEntryIdx, unsigned int uKeyIdx,
923 unsigned char *pbyAddr, u32 *pdwKey,
924 unsigned char byLocalID);
925void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx);
926
927#endif
928
