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8#ifndef WFX_HIF_API_GENERAL_H
9#define WFX_HIF_API_GENERAL_H
10
11#ifdef __KERNEL__
12#include <linux/types.h>
13#include <linux/if_ether.h>
14#else
15#include <net/ethernet.h>
16#include <stdint.h>
17#define __packed __attribute__((__packed__))
18#endif
19
20#define HIF_ID_IS_INDICATION 0x80
21#define HIF_COUNTER_MAX 7
22
23struct hif_msg {
24 __le16 len;
25 u8 id;
26 u8 reserved:1;
27 u8 interface:2;
28 u8 seqnum:3;
29 u8 encrypted:2;
30 u8 body[];
31} __packed;
32
33enum hif_general_requests_ids {
34 HIF_REQ_ID_CONFIGURATION = 0x09,
35 HIF_REQ_ID_CONTROL_GPIO = 0x26,
36 HIF_REQ_ID_SET_SL_MAC_KEY = 0x27,
37 HIF_REQ_ID_SL_EXCHANGE_PUB_KEYS = 0x28,
38 HIF_REQ_ID_SL_CONFIGURE = 0x29,
39 HIF_REQ_ID_PREVENT_ROLLBACK = 0x2a,
40 HIF_REQ_ID_PTA_SETTINGS = 0x2b,
41 HIF_REQ_ID_PTA_PRIORITY = 0x2c,
42 HIF_REQ_ID_PTA_STATE = 0x2d,
43 HIF_REQ_ID_SHUT_DOWN = 0x32,
44};
45
46enum hif_general_confirmations_ids {
47 HIF_CNF_ID_CONFIGURATION = 0x09,
48 HIF_CNF_ID_CONTROL_GPIO = 0x26,
49 HIF_CNF_ID_SET_SL_MAC_KEY = 0x27,
50 HIF_CNF_ID_SL_EXCHANGE_PUB_KEYS = 0x28,
51 HIF_CNF_ID_SL_CONFIGURE = 0x29,
52 HIF_CNF_ID_PREVENT_ROLLBACK = 0x2a,
53 HIF_CNF_ID_PTA_SETTINGS = 0x2b,
54 HIF_CNF_ID_PTA_PRIORITY = 0x2c,
55 HIF_CNF_ID_PTA_STATE = 0x2d,
56 HIF_CNF_ID_SHUT_DOWN = 0x32,
57};
58
59enum hif_general_indications_ids {
60 HIF_IND_ID_EXCEPTION = 0xe0,
61 HIF_IND_ID_STARTUP = 0xe1,
62 HIF_IND_ID_WAKEUP = 0xe2,
63 HIF_IND_ID_GENERIC = 0xe3,
64 HIF_IND_ID_ERROR = 0xe4,
65 HIF_IND_ID_SL_EXCHANGE_PUB_KEYS = 0xe5
66};
67
68#define HIF_STATUS_SUCCESS (cpu_to_le32(0x0000))
69#define HIF_STATUS_FAIL (cpu_to_le32(0x0001))
70#define HIF_STATUS_INVALID_PARAMETER (cpu_to_le32(0x0002))
71#define HIF_STATUS_WARNING (cpu_to_le32(0x0003))
72#define HIF_STATUS_UNKNOWN_REQUEST (cpu_to_le32(0x0004))
73#define HIF_STATUS_RX_FAIL_DECRYPT (cpu_to_le32(0x0010))
74#define HIF_STATUS_RX_FAIL_MIC (cpu_to_le32(0x0011))
75#define HIF_STATUS_RX_FAIL_NO_KEY (cpu_to_le32(0x0012))
76#define HIF_STATUS_TX_FAIL_RETRIES (cpu_to_le32(0x0013))
77#define HIF_STATUS_TX_FAIL_TIMEOUT (cpu_to_le32(0x0014))
78#define HIF_STATUS_TX_FAIL_REQUEUE (cpu_to_le32(0x0015))
79#define HIF_STATUS_REFUSED (cpu_to_le32(0x0016))
80#define HIF_STATUS_BUSY (cpu_to_le32(0x0017))
81#define HIF_STATUS_SLK_SET_KEY_SUCCESS (cpu_to_le32(0x005A))
82#define HIF_STATUS_SLK_SET_KEY_ALREADY_BURNED (cpu_to_le32(0x006B))
83#define HIF_STATUS_SLK_SET_KEY_DISALLOWED_MODE (cpu_to_le32(0x007C))
84#define HIF_STATUS_SLK_SET_KEY_UNKNOWN_MODE (cpu_to_le32(0x008D))
85#define HIF_STATUS_SLK_NEGO_SUCCESS (cpu_to_le32(0x009E))
86#define HIF_STATUS_SLK_NEGO_FAILED (cpu_to_le32(0x00AF))
87#define HIF_STATUS_ROLLBACK_SUCCESS (cpu_to_le32(0x1234))
88#define HIF_STATUS_ROLLBACK_FAIL (cpu_to_le32(0x1256))
89
90enum hif_api_rate_index {
91 API_RATE_INDEX_B_1MBPS = 0,
92 API_RATE_INDEX_B_2MBPS = 1,
93 API_RATE_INDEX_B_5P5MBPS = 2,
94 API_RATE_INDEX_B_11MBPS = 3,
95 API_RATE_INDEX_PBCC_22MBPS = 4,
96 API_RATE_INDEX_PBCC_33MBPS = 5,
97 API_RATE_INDEX_G_6MBPS = 6,
98 API_RATE_INDEX_G_9MBPS = 7,
99 API_RATE_INDEX_G_12MBPS = 8,
100 API_RATE_INDEX_G_18MBPS = 9,
101 API_RATE_INDEX_G_24MBPS = 10,
102 API_RATE_INDEX_G_36MBPS = 11,
103 API_RATE_INDEX_G_48MBPS = 12,
104 API_RATE_INDEX_G_54MBPS = 13,
105 API_RATE_INDEX_N_6P5MBPS = 14,
106 API_RATE_INDEX_N_13MBPS = 15,
107 API_RATE_INDEX_N_19P5MBPS = 16,
108 API_RATE_INDEX_N_26MBPS = 17,
109 API_RATE_INDEX_N_39MBPS = 18,
110 API_RATE_INDEX_N_52MBPS = 19,
111 API_RATE_INDEX_N_58P5MBPS = 20,
112 API_RATE_INDEX_N_65MBPS = 21,
113 API_RATE_NUM_ENTRIES = 22
114};
115
116enum hif_fw_type {
117 HIF_FW_TYPE_ETF = 0x0,
118 HIF_FW_TYPE_WFM = 0x1,
119 HIF_FW_TYPE_WSM = 0x2
120};
121
122struct hif_ind_startup {
123
124
125
126 __le32 status;
127 u16 hardware_id;
128 u8 opn[14];
129 u8 uid[8];
130 u16 num_inp_ch_bufs;
131 u16 size_inp_ch_buf;
132 u8 num_links_ap;
133 u8 num_interfaces;
134 u8 mac_addr[2][ETH_ALEN];
135 u8 api_version_minor;
136 u8 api_version_major;
137 u8 link_mode:2;
138 u8 reserved1:6;
139 u8 reserved2;
140 u8 reserved3;
141 u8 reserved4;
142 u8 firmware_build;
143 u8 firmware_minor;
144 u8 firmware_major;
145 u8 firmware_type;
146 u8 disabled_channel_list[2];
147 u8 region_sel_mode:4;
148 u8 reserved5:4;
149 u8 phy1_region:3;
150 u8 phy0_region:3;
151 u8 otp_phy_ver:2;
152 u32 supported_rate_mask;
153 u8 firmware_label[128];
154} __packed;
155
156struct hif_ind_wakeup {
157} __packed;
158
159struct hif_req_configuration {
160 __le16 length;
161 u8 pds_data[];
162} __packed;
163
164struct hif_cnf_configuration {
165 __le32 status;
166} __packed;
167
168enum hif_gpio_mode {
169 HIF_GPIO_MODE_D0 = 0x0,
170 HIF_GPIO_MODE_D1 = 0x1,
171 HIF_GPIO_MODE_OD0 = 0x2,
172 HIF_GPIO_MODE_OD1 = 0x3,
173 HIF_GPIO_MODE_TRISTATE = 0x4,
174 HIF_GPIO_MODE_TOGGLE = 0x5,
175 HIF_GPIO_MODE_READ = 0x6
176};
177
178struct hif_req_control_gpio {
179 u8 gpio_label;
180 u8 gpio_mode;
181} __packed;
182
183struct hif_cnf_control_gpio {
184 __le32 status;
185 __le32 value;
186} __packed;
187
188enum hif_generic_indication_type {
189 HIF_GENERIC_INDICATION_TYPE_RAW = 0x0,
190 HIF_GENERIC_INDICATION_TYPE_STRING = 0x1,
191 HIF_GENERIC_INDICATION_TYPE_RX_STATS = 0x2,
192 HIF_GENERIC_INDICATION_TYPE_TX_POWER_LOOP_INFO = 0x3,
193};
194
195struct hif_rx_stats {
196 __le32 nb_rx_frame;
197 __le32 nb_crc_frame;
198 __le32 per_total;
199 __le32 throughput;
200 __le32 nb_rx_by_rate[API_RATE_NUM_ENTRIES];
201 __le16 per[API_RATE_NUM_ENTRIES];
202 __le16 snr[API_RATE_NUM_ENTRIES];
203 __le16 rssi[API_RATE_NUM_ENTRIES];
204 __le16 cfo[API_RATE_NUM_ENTRIES];
205 __le32 date;
206 __le32 pwr_clk_freq;
207 u8 is_ext_pwr_clk;
208 s8 current_temp;
209} __packed;
210
211struct hif_tx_power_loop_info {
212 __le16 tx_gain_dig;
213 __le16 tx_gain_pa;
214 __le16 target_pout;
215 __le16 p_estimation;
216 __le16 vpdet;
217 u8 measurement_index;
218 u8 reserved;
219} __packed;
220
221struct hif_ind_generic {
222 __le32 type;
223 union {
224 struct hif_rx_stats rx_stats;
225 struct hif_tx_power_loop_info tx_power_loop_info;
226 } data;
227} __packed;
228
229enum hif_error {
230 HIF_ERROR_FIRMWARE_ROLLBACK = 0x00,
231 HIF_ERROR_FIRMWARE_DEBUG_ENABLED = 0x01,
232 HIF_ERROR_SLK_OUTDATED_SESSION_KEY = 0x02,
233 HIF_ERROR_SLK_SESSION_KEY = 0x03,
234 HIF_ERROR_OOR_VOLTAGE = 0x04,
235 HIF_ERROR_PDS_PAYLOAD = 0x05,
236 HIF_ERROR_OOR_TEMPERATURE = 0x06,
237 HIF_ERROR_SLK_REQ_DURING_KEY_EXCHANGE = 0x07,
238 HIF_ERROR_SLK_MULTI_TX_UNSUPPORTED = 0x08,
239 HIF_ERROR_SLK_OVERFLOW = 0x09,
240 HIF_ERROR_SLK_DECRYPTION = 0x0a,
241 HIF_ERROR_SLK_WRONG_ENCRYPTION_STATE = 0x0b,
242 HIF_ERROR_HIF_BUS_FREQUENCY_TOO_LOW = 0x0c,
243 HIF_ERROR_HIF_RX_DATA_TOO_LARGE = 0x0e,
244 HIF_ERROR_HIF_TX_QUEUE_FULL = 0x0d,
245 HIF_ERROR_HIF_BUS = 0x0f,
246 HIF_ERROR_PDS_TESTFEATURE = 0x10,
247 HIF_ERROR_SLK_UNCONFIGURED = 0x11,
248};
249
250struct hif_ind_error {
251 __le32 type;
252 u8 data[];
253} __packed;
254
255struct hif_ind_exception {
256 __le32 type;
257 u8 data[];
258} __packed;
259
260enum hif_secure_link_state {
261 SEC_LINK_UNAVAILABLE = 0x0,
262 SEC_LINK_RESERVED = 0x1,
263 SEC_LINK_EVAL = 0x2,
264 SEC_LINK_ENFORCED = 0x3
265};
266
267#endif
268
