// SPDX-License-Identifier: GPL-2.0+
/*
 * Synopsys DesignWare 8250 driver.
 *
 * Copyright 2011 Picochip, Jamie Iles.
 * Copyright 2013 Intel Corporation
 *
 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
 * LCR is written whilst busy.  If it is, then a busy detect interrupt is
 * raised, the LCR needs to be rewritten and the uart status register read.
 */
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/workqueue.h>
#include <linux/notifier.h>
#include <linux/slab.h>
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/pm_runtime.h>

#include <asm/byteorder.h>

#include "8250_dwlib.h"

/* Offsets for the DesignWare specific registers */
#define DW_UART_USR     0x1f /* UART Status Register */

/* DesignWare specific register fields */
#define DW_UART_MCR_SIRE                BIT(6)

struct dw8250_data {
        struct dw8250_port_data data;

        u8                      usr_reg;
        int                     msr_mask_on;
        int                     msr_mask_off;
        struct clk              *clk;
        struct clk              *pclk;
        struct notifier_block   clk_notifier;
        struct work_struct      clk_work;
        struct reset_control    *rst;

        unsigned int            skip_autocfg:1;
        unsigned int            uart_16550_compatible:1;
};

static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
{
        return container_of(data, struct dw8250_data, data);
}

static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
{
        return container_of(nb, struct dw8250_data, clk_notifier);
}

static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
{
        return container_of(work, struct dw8250_data, clk_work);
}

static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
{
        struct dw8250_data *d = to_dw8250_data(p->private_data);

        /* Override any modem control signals if needed */
        if (offset == UART_MSR) {
                value |= d->msr_mask_on;
                value &= ~d->msr_mask_off;
        }

        return value;
}

static void dw8250_force_idle(struct uart_port *p)
{
        struct uart_8250_port *up = up_to_u8250p(p);

        serial8250_clear_and_reinit_fifos(up);
        (void)p->serial_in(p, UART_RX);
}

static void dw8250_check_lcr(struct uart_port *p, int value)
{
        void __iomem *offset = p->membase + (UART_LCR << p->regshift);
        int tries = 1000;

        /* Make sure LCR write wasn't ignored */
        while (tries--) {
                unsigned int lcr = p->serial_in(p, UART_LCR);

                if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
                        return;

                dw8250_force_idle(p);

#ifdef CONFIG_64BIT
                if (p->type == PORT_OCTEON)
                        __raw_writeq(value & 0xff, offset);
                else
#endif
                if (p->iotype == UPIO_MEM32)
                        writel(value, offset);
                else if (p->iotype == UPIO_MEM32BE)
                        iowrite32be(value, offset);
                else
                        writeb(value, offset);
        }
        /*
         * FIXME: this deadlocks if port->lock is already held
         * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
         */
}

/* Returns once the transmitter is empty or we run out of retries */
static void dw8250_tx_wait_empty(struct uart_port *p)
{
        unsigned int tries = 20000;
        unsigned int delay_threshold = tries - 1000;
        unsigned int lsr;

        while (tries--) {
                lsr = readb (p->membase + (UART_LSR << p->regshift));
                if (lsr & UART_LSR_TEMT)
                        break;

                /* The device is first given a chance to empty without delay,
                 * to avoid slowdowns at high bitrates. If after 1000 tries
                 * the buffer has still not emptied, allow more time for low-
                 * speed links. */
                if (tries < delay_threshold)
                        udelay (1);
        }
}

static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
{
        struct dw8250_data *d = to_dw8250_data(p->private_data);

        /* Allow the TX to drain before we reconfigure */
        if (offset == UART_LCR)
                dw8250_tx_wait_empty(p);

        writeb(value, p->membase + (offset << p->regshift));

        if (offset == UART_LCR && !d->uart_16550_compatible)
                dw8250_check_lcr(p, value);
}


static void dw8250_serial_out(struct uart_port *p, int offset, int value)
{
        struct dw8250_data *d = to_dw8250_data(p->private_data);

        writeb(value, p->membase + (offset << p->regshift));

        if (offset == UART_LCR && !d->uart_16550_compatible)
                dw8250_check_lcr(p, value);
}

static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
{
        unsigned int value = readb(p->membase + (offset << p->regshift));

        return dw8250_modify_msr(p, offset, value);
}

#ifdef CONFIG_64BIT
static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
{
        unsigned int value;

        value = (u8)__raw_readq(p->membase + (offset << p->regshift));

        return dw8250_modify_msr(p, offset, value);
}

static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
{
        struct dw8250_data *d = to_dw8250_data(p->private_data);

        value &= 0xff;
        __raw_writeq(value, p->membase + (offset << p->regshift));
        /* Read back to ensure register write ordering. */
        __raw_readq(p->membase + (UART_LCR << p->regshift));

        if (offset == UART_LCR && !d->uart_16550_compatible)
                dw8250_check_lcr(p, value);
}
#endif /* CONFIG_64BIT */

static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
{
        struct dw8250_data *d = to_dw8250_data(p->private_data);

        writel(value, p->membase + (offset << p->regshift));

        if (offset == UART_LCR && !d->uart_16550_compatible)
                dw8250_check_lcr(p, value);
}

static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
{
        unsigned int value = readl(p->membase + (offset << p->regshift));

        return dw8250_modify_msr(p, offset, value);
}

static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
{
        struct dw8250_data *d = to_dw8250_data(p->private_data);

        iowrite32be(value, p->membase + (offset << p->regshift));

        if (offset == UART_LCR && !d->uart_16550_compatible)
                dw8250_check_lcr(p, value);
}

static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
{
       unsigned int value = ioread32be(p->membase + (offset << p->regshift));

       return dw8250_modify_msr(p, offset, value);
}


static int dw8250_handle_irq(struct uart_port *p)
{
        struct uart_8250_port *up = up_to_u8250p(p);
        struct dw8250_data *d = to_dw8250_data(p->private_data);
        unsigned int iir = p->serial_in(p, UART_IIR);
        unsigned int status;
        unsigned long flags;

        /*
         * There are ways to get Designware-based UARTs into a state where
         * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
         * data available.  If we see such a case then we'll do a bogus
         * read.  If we don't do this then the "RX TIMEOUT" interrupt will
         * fire forever.
         *
         * This problem has only been observed so far when not in DMA mode
         * so we limit the workaround only to non-DMA mode.
         */
        if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
                spin_lock_irqsave(&p->lock, flags);
                status = p->serial_in(p, UART_LSR);

                if (!(status & (UART_LSR_DR | UART_LSR_BI)))
                        (void) p->serial_in(p, UART_RX);

                spin_unlock_irqrestore(&p->lock, flags);
        }

        if (serial8250_handle_irq(p, iir))
                return 1;

        if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
                /* Clear the USR */
                (void)p->serial_in(p, d->usr_reg);

                return 1;
        }

        return 0;
}

static void dw8250_clk_work_cb(struct work_struct *work)
{
        struct dw8250_data *d = work_to_dw8250_data(work);
        struct uart_8250_port *up;
        unsigned long rate;

        rate = clk_get_rate(d->clk);
        if (rate <= 0)
                return;

        up = serial8250_get_port(d->data.line);

        serial8250_update_uartclk(&up->port, rate);
}

static int dw8250_clk_notifier_cb(struct notifier_block *nb,
                                  unsigned long event, void *data)
{
        struct dw8250_data *d = clk_to_dw8250_data(nb);

        /*
         * We have no choice but to defer the uartclk update due to two
         * deadlocks. First one is caused by a recursive mutex lock which
         * happens when clk_set_rate() is called from dw8250_set_termios().
         * Second deadlock is more tricky and is caused by an inverted order of
         * the clk and tty-port mutexes lock. It happens if clock rate change
         * is requested asynchronously while set_termios() is executed between
         * tty-port mutex lock and clk_set_rate() function invocation and
         * vise-versa. Anyway if we didn't have the reference clock alteration
         * in the dw8250_set_termios() method we wouldn't have needed this
         * deferred event handling complication.
         */
        if (event == POST_RATE_CHANGE) {
                queue_work(system_unbound_wq, &d->clk_work);
                return NOTIFY_OK;
        }

        return NOTIFY_DONE;
}

static void
dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
{
        if (!state)
                pm_runtime_get_sync(port->dev);

        serial8250_do_pm(port, state, old);

        if (state)
                pm_runtime_put_sync_suspend(port->dev);
}

static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
                               struct ktermios *old)
{
        unsigned long newrate = tty_termios_baud_rate(termios) * 16;
        struct dw8250_data *d = to_dw8250_data(p->private_data);
        long rate;
        int ret;

        clk_disable_unprepare(d->clk);
        rate = clk_round_rate(d->clk, newrate);
        if (rate > 0) {
                /*
                 * Premilinary set the uartclk to the new clock rate so the
                 * clock update event handler caused by the clk_set_rate()
                 * calling wouldn't actually update the UART divisor since
                 * we about to do this anyway.
                 */
                swap(p->uartclk, rate);
                ret = clk_set_rate(d->clk, newrate);
                if (ret)
                        swap(p->uartclk, rate);
        }
        clk_prepare_enable(d->clk);

        p->status &= ~UPSTAT_AUTOCTS;
        if (termios->c_cflag & CRTSCTS)
                p->status |= UPSTAT_AUTOCTS;

        serial8250_do_set_termios(p, termios, old);
}

static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
{
        struct uart_8250_port *up = up_to_u8250p(p);
        unsigned int mcr = p->serial_in(p, UART_MCR);

        if (up->capabilities & UART_CAP_IRDA) {
                if (termios->c_line == N_IRDA)
                        mcr |= DW_UART_MCR_SIRE;
                else
                        mcr &= ~DW_UART_MCR_SIRE;

                p->serial_out(p, UART_MCR, mcr);
        }
        serial8250_do_set_ldisc(p, termios);
}

/*
 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
 * channel on platforms that have DMA engines, but don't have any channels
 * assigned to the UART.
 *
 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
 * core problem is fixed, this function is no longer needed.
 */
static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
{
        return false;
}

static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
{
        return param == chan->device->dev;
}

static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
{
        if (p->dev->of_node) {
                struct device_node *np = p->dev->of_node;
                int id;

                /* get index of serial line, if found in DT aliases */
                id = of_alias_get_id(np, "serial");
                if (id >= 0)
                        p->line = id;
#ifdef CONFIG_64BIT
                if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
                        p->serial_in = dw8250_serial_inq;
                        p->serial_out = dw8250_serial_outq;
                        p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
                        p->type = PORT_OCTEON;
                        data->usr_reg = 0x27;
                        data->skip_autocfg = true;
                }
#endif
                if (of_device_is_big_endian(p->dev->of_node)) {
                        p->iotype = UPIO_MEM32BE;
                        p->serial_in = dw8250_serial_in32be;
                        p->serial_out = dw8250_serial_out32be;
                }
                if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
                        p->serial_out = dw8250_serial_out38x;

        } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
                p->iotype = UPIO_MEM32;
                p->regshift = 2;
                p->serial_in = dw8250_serial_in32;
                data->uart_16550_compatible = true;
        }

        /* Platforms with iDMA 64-bit */
        if (platform_get_resource_byname(to_platform_device(p->dev),
                                         IORESOURCE_MEM, "lpss_priv")) {
                data->data.dma.rx_param = p->dev->parent;
                data->data.dma.tx_param = p->dev->parent;
                data->data.dma.fn = dw8250_idma_filter;
        }
}

static int dw8250_probe(struct platform_device *pdev)
{
        struct uart_8250_port uart = {}, *up = &uart;
        struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        struct uart_port *p = &up->port;
        struct device *dev = &pdev->dev;
        struct dw8250_data *data;
        int irq;
        int err;
        u32 val;

        if (!regs) {
                dev_err(dev, "no registers defined\n");
                return -EINVAL;
        }

        irq = platform_get_irq(pdev, 0);
        if (irq < 0)
                return irq;

        spin_lock_init(&p->lock);
        p->mapbase      = regs->start;
        p->irq          = irq;
        p->handle_irq   = dw8250_handle_irq;
        p->pm           = dw8250_do_pm;
        p->type         = PORT_8250;
        p->flags        = UPF_SHARE_IRQ | UPF_FIXED_PORT;
        p->dev          = dev;
        p->iotype       = UPIO_MEM;
        p->serial_in    = dw8250_serial_in;
        p->serial_out   = dw8250_serial_out;
        p->set_ldisc    = dw8250_set_ldisc;
        p->set_termios  = dw8250_set_termios;

        p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
        if (!p->membase)
                return -ENOMEM;

        data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
        if (!data)
                return -ENOMEM;

        data->data.dma.fn = dw8250_fallback_dma_filter;
        data->usr_reg = DW_UART_USR;
        p->private_data = &data->data;

        data->uart_16550_compatible = device_property_read_bool(dev,
                                                "snps,uart-16550-compatible");

        err = device_property_read_u32(dev, "reg-shift", &val);
        if (!err)
                p->regshift = val;

        err = device_property_read_u32(dev, "reg-io-width", &val);
        if (!err && val == 4) {
                p->iotype = UPIO_MEM32;
                p->serial_in = dw8250_serial_in32;
                p->serial_out = dw8250_serial_out32;
        }

        if (device_property_read_bool(dev, "dcd-override")) {
                /* Always report DCD as active */
                data->msr_mask_on |= UART_MSR_DCD;
                data->msr_mask_off |= UART_MSR_DDCD;
        }

        if (device_property_read_bool(dev, "dsr-override")) {
                /* Always report DSR as active */
                data->msr_mask_on |= UART_MSR_DSR;
                data->msr_mask_off |= UART_MSR_DDSR;
        }

        if (device_property_read_bool(dev, "cts-override")) {
                /* Always report CTS as active */
                data->msr_mask_on |= UART_MSR_CTS;
                data->msr_mask_off |= UART_MSR_DCTS;
        }

        if (device_property_read_bool(dev, "ri-override")) {
                /* Always report Ring indicator as inactive */
                data->msr_mask_off |= UART_MSR_RI;
                data->msr_mask_off |= UART_MSR_TERI;
        }

        /* Always ask for fixed clock rate from a property. */
        device_property_read_u32(dev, "clock-frequency", &p->uartclk);

        /* If there is separate baudclk, get the rate from it. */
        data->clk = devm_clk_get_optional(dev, "baudclk");
        if (data->clk == NULL)
                data->clk = devm_clk_get_optional(dev, NULL);
        if (IS_ERR(data->clk))
                return PTR_ERR(data->clk);

        INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
        data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;

        err = clk_prepare_enable(data->clk);
        if (err)
                dev_warn(dev, "could not enable optional baudclk: %d\n", err);

        if (data->clk)
                p->uartclk = clk_get_rate(data->clk);

        /* If no clock rate is defined, fail. */
        if (!p->uartclk) {
                dev_err(dev, "clock rate not defined\n");
                err = -EINVAL;
                goto err_clk;
        }

        data->pclk = devm_clk_get_optional(dev, "apb_pclk");
        if (IS_ERR(data->pclk)) {
                err = PTR_ERR(data->pclk);
                goto err_clk;
        }

        err = clk_prepare_enable(data->pclk);
        if (err) {
                dev_err(dev, "could not enable apb_pclk\n");
                goto err_clk;
        }

        data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
        if (IS_ERR(data->rst)) {
                err = PTR_ERR(data->rst);
                goto err_pclk;
        }
        reset_control_deassert(data->rst);

        dw8250_quirks(p, data);

        /* If the Busy Functionality is not implemented, don't handle it */
        if (data->uart_16550_compatible)
                p->handle_irq = NULL;

        if (!data->skip_autocfg)
                dw8250_setup_port(p);

        /* If we have a valid fifosize, try hooking up DMA */
        if (p->fifosize) {
                data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
                data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
                up->dma = &data->data.dma;
        }

        data->data.line = serial8250_register_8250_port(up);
        if (data->data.line < 0) {
                err = data->data.line;
                goto err_reset;
        }

        /*
         * Some platforms may provide a reference clock shared between several
         * devices. In this case any clock state change must be known to the
         * UART port at least post factum.
         */
        if (data->clk) {
                err = clk_notifier_register(data->clk, &data->clk_notifier);
                if (err)
                        dev_warn(p->dev, "Failed to set the clock notifier\n");
                else
                        queue_work(system_unbound_wq, &data->clk_work);
        }

        platform_set_drvdata(pdev, data);

        pm_runtime_set_active(dev);
        pm_runtime_enable(dev);

        return 0;

err_reset:
        reset_control_assert(data->rst);

err_pclk:
        clk_disable_unprepare(data->pclk);

err_clk:
        clk_disable_unprepare(data->clk);

        return err;
}

static int dw8250_remove(struct platform_device *pdev)
{
        struct dw8250_data *data = platform_get_drvdata(pdev);
        struct device *dev = &pdev->dev;

        pm_runtime_get_sync(dev);

        if (data->clk) {
                clk_notifier_unregister(data->clk, &data->clk_notifier);

                flush_work(&data->clk_work);
        }

        serial8250_unregister_port(data->data.line);

        reset_control_assert(data->rst);

        clk_disable_unprepare(data->pclk);

        clk_disable_unprepare(data->clk);

        pm_runtime_disable(dev);
        pm_runtime_put_noidle(dev);

        return 0;
}

#ifdef CONFIG_PM_SLEEP
static int dw8250_suspend(struct device *dev)
{
        struct dw8250_data *data = dev_get_drvdata(dev);

        serial8250_suspend_port(data->data.line);

        return 0;
}

static int dw8250_resume(struct device *dev)
{
        struct dw8250_data *data = dev_get_drvdata(dev);

        serial8250_resume_port(data->data.line);

        return 0;
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int dw8250_runtime_suspend(struct device *dev)
{
        struct dw8250_data *data = dev_get_drvdata(dev);

        clk_disable_unprepare(data->clk);

        clk_disable_unprepare(data->pclk);

        return 0;
}

static int dw8250_runtime_resume(struct device *dev)
{
        struct dw8250_data *data = dev_get_drvdata(dev);

        clk_prepare_enable(data->pclk);

        clk_prepare_enable(data->clk);

        return 0;
}
#endif

static const struct dev_pm_ops dw8250_pm_ops = {
        SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
        SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
};

static const struct of_device_id dw8250_of_match[] = {
        { .compatible = "snps,dw-apb-uart" },
        { .compatible = "cavium,octeon-3860-uart" },
        { .compatible = "marvell,armada-38x-uart" },
        { .compatible = "renesas,rzn1-uart" },
        { /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);

static const struct acpi_device_id dw8250_acpi_match[] = {
        { "INT33C4", 0 },
        { "INT33C5", 0 },
        { "INT3434", 0 },
        { "INT3435", 0 },
        { "80860F0A", 0 },
        { "8086228A", 0 },
        { "APMC0D08", 0},
        { "AMD0020", 0 },
        { "AMDI0020", 0 },
        { "AMDI0022", 0 },
        { "BRCM2032", 0 },
        { "HISI0031", 0 },
        { },
};
MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);

static struct platform_driver dw8250_platform_driver = {
        .driver = {
                .name           = "dw-apb-uart",
                .pm             = &dw8250_pm_ops,
                .of_match_table = dw8250_of_match,
                .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
        },
        .probe                  = dw8250_probe,
        .remove                 = dw8250_remove,
};

module_platform_driver(dw8250_platform_driver);

MODULE_AUTHOR("Jamie Iles");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
MODULE_ALIAS("platform:dw-apb-uart");