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8#include <linux/clk.h>
9#include <linux/console.h>
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/dmaengine.h>
13#include <linux/dmapool.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/of_dma.h>
20#include <linux/serial_core.h>
21#include <linux/slab.h>
22#include <linux/tty_flip.h>
23
24
25#define UARTBDH 0x00
26#define UARTBDL 0x01
27#define UARTCR1 0x02
28#define UARTCR2 0x03
29#define UARTSR1 0x04
30#define UARTCR3 0x06
31#define UARTDR 0x07
32#define UARTCR4 0x0a
33#define UARTCR5 0x0b
34#define UARTMODEM 0x0d
35#define UARTPFIFO 0x10
36#define UARTCFIFO 0x11
37#define UARTSFIFO 0x12
38#define UARTTWFIFO 0x13
39#define UARTTCFIFO 0x14
40#define UARTRWFIFO 0x15
41
42#define UARTBDH_LBKDIE 0x80
43#define UARTBDH_RXEDGIE 0x40
44#define UARTBDH_SBR_MASK 0x1f
45
46#define UARTCR1_LOOPS 0x80
47#define UARTCR1_RSRC 0x20
48#define UARTCR1_M 0x10
49#define UARTCR1_WAKE 0x08
50#define UARTCR1_ILT 0x04
51#define UARTCR1_PE 0x02
52#define UARTCR1_PT 0x01
53
54#define UARTCR2_TIE 0x80
55#define UARTCR2_TCIE 0x40
56#define UARTCR2_RIE 0x20
57#define UARTCR2_ILIE 0x10
58#define UARTCR2_TE 0x08
59#define UARTCR2_RE 0x04
60#define UARTCR2_RWU 0x02
61#define UARTCR2_SBK 0x01
62
63#define UARTSR1_TDRE 0x80
64#define UARTSR1_TC 0x40
65#define UARTSR1_RDRF 0x20
66#define UARTSR1_IDLE 0x10
67#define UARTSR1_OR 0x08
68#define UARTSR1_NF 0x04
69#define UARTSR1_FE 0x02
70#define UARTSR1_PE 0x01
71
72#define UARTCR3_R8 0x80
73#define UARTCR3_T8 0x40
74#define UARTCR3_TXDIR 0x20
75#define UARTCR3_TXINV 0x10
76#define UARTCR3_ORIE 0x08
77#define UARTCR3_NEIE 0x04
78#define UARTCR3_FEIE 0x02
79#define UARTCR3_PEIE 0x01
80
81#define UARTCR4_MAEN1 0x80
82#define UARTCR4_MAEN2 0x40
83#define UARTCR4_M10 0x20
84#define UARTCR4_BRFA_MASK 0x1f
85#define UARTCR4_BRFA_OFF 0
86
87#define UARTCR5_TDMAS 0x80
88#define UARTCR5_RDMAS 0x20
89
90#define UARTMODEM_RXRTSE 0x08
91#define UARTMODEM_TXRTSPOL 0x04
92#define UARTMODEM_TXRTSE 0x02
93#define UARTMODEM_TXCTSE 0x01
94
95#define UARTPFIFO_TXFE 0x80
96#define UARTPFIFO_FIFOSIZE_MASK 0x7
97#define UARTPFIFO_TXSIZE_OFF 4
98#define UARTPFIFO_RXFE 0x08
99#define UARTPFIFO_RXSIZE_OFF 0
100
101#define UARTCFIFO_TXFLUSH 0x80
102#define UARTCFIFO_RXFLUSH 0x40
103#define UARTCFIFO_RXOFE 0x04
104#define UARTCFIFO_TXOFE 0x02
105#define UARTCFIFO_RXUFE 0x01
106
107#define UARTSFIFO_TXEMPT 0x80
108#define UARTSFIFO_RXEMPT 0x40
109#define UARTSFIFO_RXOF 0x04
110#define UARTSFIFO_TXOF 0x02
111#define UARTSFIFO_RXUF 0x01
112
113
114
115
116#define UART_GLOBAL 0x8
117
118
119#define UARTBAUD 0x00
120#define UARTSTAT 0x04
121#define UARTCTRL 0x08
122#define UARTDATA 0x0C
123#define UARTMATCH 0x10
124#define UARTMODIR 0x14
125#define UARTFIFO 0x18
126#define UARTWATER 0x1c
127
128#define UARTBAUD_MAEN1 0x80000000
129#define UARTBAUD_MAEN2 0x40000000
130#define UARTBAUD_M10 0x20000000
131#define UARTBAUD_TDMAE 0x00800000
132#define UARTBAUD_RDMAE 0x00200000
133#define UARTBAUD_MATCFG 0x00400000
134#define UARTBAUD_BOTHEDGE 0x00020000
135#define UARTBAUD_RESYNCDIS 0x00010000
136#define UARTBAUD_LBKDIE 0x00008000
137#define UARTBAUD_RXEDGIE 0x00004000
138#define UARTBAUD_SBNS 0x00002000
139#define UARTBAUD_SBR 0x00000000
140#define UARTBAUD_SBR_MASK 0x1fff
141#define UARTBAUD_OSR_MASK 0x1f
142#define UARTBAUD_OSR_SHIFT 24
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219#define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
220
221#define UARTWATER_COUNT_MASK 0xff
222#define UARTWATER_TXCNT_OFF 8
223#define UARTWATER_RXCNT_OFF 24
224#define UARTWATER_WATER_MASK 0xff
225#define UARTWATER_TXWATER_OFF 0
226#define UARTWATER_RXWATER_OFF 16
227
228#define UART_GLOBAL_RST 0x2
229#define GLOBAL_RST_MIN_US 20
230#define GLOBAL_RST_MAX_US 40
231
232
233#define DMA_RX_TIMEOUT (10)
234
235#define DRIVER_NAME "fsl-lpuart"
236#define DEV_NAME "ttyLP"
237#define UART_NR 6
238
239
240#define IMX_REG_OFF 0x10
241
242static DEFINE_IDA(fsl_lpuart_ida);
243
244enum lpuart_type {
245 VF610_LPUART,
246 LS1021A_LPUART,
247 LS1028A_LPUART,
248 IMX7ULP_LPUART,
249 IMX8QXP_LPUART,
250};
251
252struct lpuart_port {
253 struct uart_port port;
254 enum lpuart_type devtype;
255 struct clk *ipg_clk;
256 struct clk *baud_clk;
257 unsigned int txfifo_size;
258 unsigned int rxfifo_size;
259
260 bool lpuart_dma_tx_use;
261 bool lpuart_dma_rx_use;
262 struct dma_chan *dma_tx_chan;
263 struct dma_chan *dma_rx_chan;
264 struct dma_async_tx_descriptor *dma_tx_desc;
265 struct dma_async_tx_descriptor *dma_rx_desc;
266 dma_cookie_t dma_tx_cookie;
267 dma_cookie_t dma_rx_cookie;
268 unsigned int dma_tx_bytes;
269 unsigned int dma_rx_bytes;
270 bool dma_tx_in_progress;
271 unsigned int dma_rx_timeout;
272 struct timer_list lpuart_timer;
273 struct scatterlist rx_sgl, tx_sgl[2];
274 struct circ_buf rx_ring;
275 int rx_dma_rng_buf_len;
276 unsigned int dma_tx_nents;
277 wait_queue_head_t dma_wait;
278 bool id_allocated;
279};
280
281struct lpuart_soc_data {
282 enum lpuart_type devtype;
283 char iotype;
284 u8 reg_off;
285};
286
287static const struct lpuart_soc_data vf_data = {
288 .devtype = VF610_LPUART,
289 .iotype = UPIO_MEM,
290};
291
292static const struct lpuart_soc_data ls1021a_data = {
293 .devtype = LS1021A_LPUART,
294 .iotype = UPIO_MEM32BE,
295};
296
297static const struct lpuart_soc_data ls1028a_data = {
298 .devtype = LS1028A_LPUART,
299 .iotype = UPIO_MEM32,
300};
301
302static struct lpuart_soc_data imx7ulp_data = {
303 .devtype = IMX7ULP_LPUART,
304 .iotype = UPIO_MEM32,
305 .reg_off = IMX_REG_OFF,
306};
307
308static struct lpuart_soc_data imx8qxp_data = {
309 .devtype = IMX8QXP_LPUART,
310 .iotype = UPIO_MEM32,
311 .reg_off = IMX_REG_OFF,
312};
313
314static const struct of_device_id lpuart_dt_ids[] = {
315 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
316 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
317 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
318 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
319 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
320 { }
321};
322MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
323
324
325static void lpuart_dma_tx_complete(void *arg);
326
327static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
328{
329 return (sport->devtype == LS1021A_LPUART ||
330 sport->devtype == LS1028A_LPUART);
331}
332
333static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
334{
335 return sport->devtype == IMX7ULP_LPUART;
336}
337
338static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
339{
340 return sport->devtype == IMX8QXP_LPUART;
341}
342
343static inline u32 lpuart32_read(struct uart_port *port, u32 off)
344{
345 switch (port->iotype) {
346 case UPIO_MEM32:
347 return readl(port->membase + off);
348 case UPIO_MEM32BE:
349 return ioread32be(port->membase + off);
350 default:
351 return 0;
352 }
353}
354
355static inline void lpuart32_write(struct uart_port *port, u32 val,
356 u32 off)
357{
358 switch (port->iotype) {
359 case UPIO_MEM32:
360 writel(val, port->membase + off);
361 break;
362 case UPIO_MEM32BE:
363 iowrite32be(val, port->membase + off);
364 break;
365 }
366}
367
368static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
369{
370 int ret = 0;
371
372 if (is_en) {
373 ret = clk_prepare_enable(sport->ipg_clk);
374 if (ret)
375 return ret;
376
377 ret = clk_prepare_enable(sport->baud_clk);
378 if (ret) {
379 clk_disable_unprepare(sport->ipg_clk);
380 return ret;
381 }
382 } else {
383 clk_disable_unprepare(sport->baud_clk);
384 clk_disable_unprepare(sport->ipg_clk);
385 }
386
387 return 0;
388}
389
390static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
391{
392 if (is_imx8qxp_lpuart(sport))
393 return clk_get_rate(sport->baud_clk);
394
395 return clk_get_rate(sport->ipg_clk);
396}
397
398#define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
399#define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
400
401static int lpuart_global_reset(struct lpuart_port *sport)
402{
403 struct uart_port *port = &sport->port;
404 void __iomem *global_addr;
405 int ret;
406
407 if (uart_console(port))
408 return 0;
409
410 ret = clk_prepare_enable(sport->ipg_clk);
411 if (ret) {
412 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
413 return ret;
414 }
415
416 if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
417 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
418 writel(UART_GLOBAL_RST, global_addr);
419 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
420 writel(0, global_addr);
421 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
422 }
423
424 clk_disable_unprepare(sport->ipg_clk);
425 return 0;
426}
427
428static void lpuart_stop_tx(struct uart_port *port)
429{
430 unsigned char temp;
431
432 temp = readb(port->membase + UARTCR2);
433 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
434 writeb(temp, port->membase + UARTCR2);
435}
436
437static void lpuart32_stop_tx(struct uart_port *port)
438{
439 unsigned long temp;
440
441 temp = lpuart32_read(port, UARTCTRL);
442 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
443 lpuart32_write(port, temp, UARTCTRL);
444}
445
446static void lpuart_stop_rx(struct uart_port *port)
447{
448 unsigned char temp;
449
450 temp = readb(port->membase + UARTCR2);
451 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
452}
453
454static void lpuart32_stop_rx(struct uart_port *port)
455{
456 unsigned long temp;
457
458 temp = lpuart32_read(port, UARTCTRL);
459 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
460}
461
462static void lpuart_dma_tx(struct lpuart_port *sport)
463{
464 struct circ_buf *xmit = &sport->port.state->xmit;
465 struct scatterlist *sgl = sport->tx_sgl;
466 struct device *dev = sport->port.dev;
467 struct dma_chan *chan = sport->dma_tx_chan;
468 int ret;
469
470 if (sport->dma_tx_in_progress)
471 return;
472
473 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
474
475 if (xmit->tail < xmit->head || xmit->head == 0) {
476 sport->dma_tx_nents = 1;
477 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
478 } else {
479 sport->dma_tx_nents = 2;
480 sg_init_table(sgl, 2);
481 sg_set_buf(sgl, xmit->buf + xmit->tail,
482 UART_XMIT_SIZE - xmit->tail);
483 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
484 }
485
486 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
487 DMA_TO_DEVICE);
488 if (!ret) {
489 dev_err(dev, "DMA mapping error for TX.\n");
490 return;
491 }
492
493 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
494 ret, DMA_MEM_TO_DEV,
495 DMA_PREP_INTERRUPT);
496 if (!sport->dma_tx_desc) {
497 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
498 DMA_TO_DEVICE);
499 dev_err(dev, "Cannot prepare TX slave DMA!\n");
500 return;
501 }
502
503 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
504 sport->dma_tx_desc->callback_param = sport;
505 sport->dma_tx_in_progress = true;
506 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
507 dma_async_issue_pending(chan);
508}
509
510static bool lpuart_stopped_or_empty(struct uart_port *port)
511{
512 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
513}
514
515static void lpuart_dma_tx_complete(void *arg)
516{
517 struct lpuart_port *sport = arg;
518 struct scatterlist *sgl = &sport->tx_sgl[0];
519 struct circ_buf *xmit = &sport->port.state->xmit;
520 struct dma_chan *chan = sport->dma_tx_chan;
521 unsigned long flags;
522
523 spin_lock_irqsave(&sport->port.lock, flags);
524 if (!sport->dma_tx_in_progress) {
525 spin_unlock_irqrestore(&sport->port.lock, flags);
526 return;
527 }
528
529 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
530 DMA_TO_DEVICE);
531
532 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
533
534 sport->port.icount.tx += sport->dma_tx_bytes;
535 sport->dma_tx_in_progress = false;
536 spin_unlock_irqrestore(&sport->port.lock, flags);
537
538 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
539 uart_write_wakeup(&sport->port);
540
541 if (waitqueue_active(&sport->dma_wait)) {
542 wake_up(&sport->dma_wait);
543 return;
544 }
545
546 spin_lock_irqsave(&sport->port.lock, flags);
547
548 if (!lpuart_stopped_or_empty(&sport->port))
549 lpuart_dma_tx(sport);
550
551 spin_unlock_irqrestore(&sport->port.lock, flags);
552}
553
554static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
555{
556 switch (sport->port.iotype) {
557 case UPIO_MEM32:
558 return sport->port.mapbase + UARTDATA;
559 case UPIO_MEM32BE:
560 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
561 }
562 return sport->port.mapbase + UARTDR;
563}
564
565static int lpuart_dma_tx_request(struct uart_port *port)
566{
567 struct lpuart_port *sport = container_of(port,
568 struct lpuart_port, port);
569 struct dma_slave_config dma_tx_sconfig = {};
570 int ret;
571
572 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
573 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
574 dma_tx_sconfig.dst_maxburst = 1;
575 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
576 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
577
578 if (ret) {
579 dev_err(sport->port.dev,
580 "DMA slave config failed, err = %d\n", ret);
581 return ret;
582 }
583
584 return 0;
585}
586
587static bool lpuart_is_32(struct lpuart_port *sport)
588{
589 return sport->port.iotype == UPIO_MEM32 ||
590 sport->port.iotype == UPIO_MEM32BE;
591}
592
593static void lpuart_flush_buffer(struct uart_port *port)
594{
595 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
596 struct dma_chan *chan = sport->dma_tx_chan;
597 u32 val;
598
599 if (sport->lpuart_dma_tx_use) {
600 if (sport->dma_tx_in_progress) {
601 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
602 sport->dma_tx_nents, DMA_TO_DEVICE);
603 sport->dma_tx_in_progress = false;
604 }
605 dmaengine_terminate_all(chan);
606 }
607
608 if (lpuart_is_32(sport)) {
609 val = lpuart32_read(&sport->port, UARTFIFO);
610 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
611 lpuart32_write(&sport->port, val, UARTFIFO);
612 } else {
613 val = readb(sport->port.membase + UARTCFIFO);
614 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
615 writeb(val, sport->port.membase + UARTCFIFO);
616 }
617}
618
619static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
620 u8 bit)
621{
622 while (!(readb(port->membase + offset) & bit))
623 cpu_relax();
624}
625
626static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
627 u32 bit)
628{
629 while (!(lpuart32_read(port, offset) & bit))
630 cpu_relax();
631}
632
633#if defined(CONFIG_CONSOLE_POLL)
634
635static int lpuart_poll_init(struct uart_port *port)
636{
637 struct lpuart_port *sport = container_of(port,
638 struct lpuart_port, port);
639 unsigned long flags;
640 unsigned char temp;
641
642 sport->port.fifosize = 0;
643
644 spin_lock_irqsave(&sport->port.lock, flags);
645
646 writeb(0, sport->port.membase + UARTCR2);
647
648 temp = readb(sport->port.membase + UARTPFIFO);
649
650 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
651 sport->port.membase + UARTPFIFO);
652
653
654 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
655 sport->port.membase + UARTCFIFO);
656
657
658 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
659 readb(sport->port.membase + UARTDR);
660 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
661 }
662
663 writeb(0, sport->port.membase + UARTTWFIFO);
664 writeb(1, sport->port.membase + UARTRWFIFO);
665
666
667 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
668 spin_unlock_irqrestore(&sport->port.lock, flags);
669
670 return 0;
671}
672
673static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
674{
675
676 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
677 writeb(c, port->membase + UARTDR);
678}
679
680static int lpuart_poll_get_char(struct uart_port *port)
681{
682 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
683 return NO_POLL_CHAR;
684
685 return readb(port->membase + UARTDR);
686}
687
688static int lpuart32_poll_init(struct uart_port *port)
689{
690 unsigned long flags;
691 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
692 u32 temp;
693
694 sport->port.fifosize = 0;
695
696 spin_lock_irqsave(&sport->port.lock, flags);
697
698
699 lpuart32_write(&sport->port, 0, UARTCTRL);
700
701 temp = lpuart32_read(&sport->port, UARTFIFO);
702
703
704 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
705
706
707 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
708
709
710 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
711 lpuart32_read(&sport->port, UARTDATA);
712 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
713 }
714
715
716 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
717 spin_unlock_irqrestore(&sport->port.lock, flags);
718
719 return 0;
720}
721
722static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
723{
724 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
725 lpuart32_write(port, c, UARTDATA);
726}
727
728static int lpuart32_poll_get_char(struct uart_port *port)
729{
730 if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
731 return NO_POLL_CHAR;
732
733 return lpuart32_read(port, UARTDATA);
734}
735#endif
736
737static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
738{
739 struct circ_buf *xmit = &sport->port.state->xmit;
740
741 if (sport->port.x_char) {
742 writeb(sport->port.x_char, sport->port.membase + UARTDR);
743 sport->port.icount.tx++;
744 sport->port.x_char = 0;
745 return;
746 }
747
748 if (lpuart_stopped_or_empty(&sport->port)) {
749 lpuart_stop_tx(&sport->port);
750 return;
751 }
752
753 while (!uart_circ_empty(xmit) &&
754 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
755 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
756 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
757 sport->port.icount.tx++;
758 }
759
760 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
761 uart_write_wakeup(&sport->port);
762
763 if (uart_circ_empty(xmit))
764 lpuart_stop_tx(&sport->port);
765}
766
767static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
768{
769 struct circ_buf *xmit = &sport->port.state->xmit;
770 unsigned long txcnt;
771
772 if (sport->port.x_char) {
773 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
774 sport->port.icount.tx++;
775 sport->port.x_char = 0;
776 return;
777 }
778
779 if (lpuart_stopped_or_empty(&sport->port)) {
780 lpuart32_stop_tx(&sport->port);
781 return;
782 }
783
784 txcnt = lpuart32_read(&sport->port, UARTWATER);
785 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
786 txcnt &= UARTWATER_COUNT_MASK;
787 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
788 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
789 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
790 sport->port.icount.tx++;
791 txcnt = lpuart32_read(&sport->port, UARTWATER);
792 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
793 txcnt &= UARTWATER_COUNT_MASK;
794 }
795
796 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
797 uart_write_wakeup(&sport->port);
798
799 if (uart_circ_empty(xmit))
800 lpuart32_stop_tx(&sport->port);
801}
802
803static void lpuart_start_tx(struct uart_port *port)
804{
805 struct lpuart_port *sport = container_of(port,
806 struct lpuart_port, port);
807 unsigned char temp;
808
809 temp = readb(port->membase + UARTCR2);
810 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
811
812 if (sport->lpuart_dma_tx_use) {
813 if (!lpuart_stopped_or_empty(port))
814 lpuart_dma_tx(sport);
815 } else {
816 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
817 lpuart_transmit_buffer(sport);
818 }
819}
820
821static void lpuart32_start_tx(struct uart_port *port)
822{
823 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
824 unsigned long temp;
825
826 if (sport->lpuart_dma_tx_use) {
827 if (!lpuart_stopped_or_empty(port))
828 lpuart_dma_tx(sport);
829 } else {
830 temp = lpuart32_read(port, UARTCTRL);
831 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
832
833 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
834 lpuart32_transmit_buffer(sport);
835 }
836}
837
838
839static unsigned int lpuart_tx_empty(struct uart_port *port)
840{
841 struct lpuart_port *sport = container_of(port,
842 struct lpuart_port, port);
843 unsigned char sr1 = readb(port->membase + UARTSR1);
844 unsigned char sfifo = readb(port->membase + UARTSFIFO);
845
846 if (sport->dma_tx_in_progress)
847 return 0;
848
849 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
850 return TIOCSER_TEMT;
851
852 return 0;
853}
854
855static unsigned int lpuart32_tx_empty(struct uart_port *port)
856{
857 struct lpuart_port *sport = container_of(port,
858 struct lpuart_port, port);
859 unsigned long stat = lpuart32_read(port, UARTSTAT);
860 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
861
862 if (sport->dma_tx_in_progress)
863 return 0;
864
865 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
866 return TIOCSER_TEMT;
867
868 return 0;
869}
870
871static void lpuart_txint(struct lpuart_port *sport)
872{
873 spin_lock(&sport->port.lock);
874 lpuart_transmit_buffer(sport);
875 spin_unlock(&sport->port.lock);
876}
877
878static void lpuart_rxint(struct lpuart_port *sport)
879{
880 unsigned int flg, ignored = 0, overrun = 0;
881 struct tty_port *port = &sport->port.state->port;
882 unsigned char rx, sr;
883
884 spin_lock(&sport->port.lock);
885
886 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
887 flg = TTY_NORMAL;
888 sport->port.icount.rx++;
889
890
891
892
893 sr = readb(sport->port.membase + UARTSR1);
894 rx = readb(sport->port.membase + UARTDR);
895
896 if (uart_prepare_sysrq_char(&sport->port, rx))
897 continue;
898
899 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
900 if (sr & UARTSR1_PE)
901 sport->port.icount.parity++;
902 else if (sr & UARTSR1_FE)
903 sport->port.icount.frame++;
904
905 if (sr & UARTSR1_OR)
906 overrun++;
907
908 if (sr & sport->port.ignore_status_mask) {
909 if (++ignored > 100)
910 goto out;
911 continue;
912 }
913
914 sr &= sport->port.read_status_mask;
915
916 if (sr & UARTSR1_PE)
917 flg = TTY_PARITY;
918 else if (sr & UARTSR1_FE)
919 flg = TTY_FRAME;
920
921 if (sr & UARTSR1_OR)
922 flg = TTY_OVERRUN;
923
924 sport->port.sysrq = 0;
925 }
926
927 tty_insert_flip_char(port, rx, flg);
928 }
929
930out:
931 if (overrun) {
932 sport->port.icount.overrun += overrun;
933
934
935
936
937
938 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
939 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
940 }
941
942 uart_unlock_and_check_sysrq(&sport->port);
943
944 tty_flip_buffer_push(port);
945}
946
947static void lpuart32_txint(struct lpuart_port *sport)
948{
949 spin_lock(&sport->port.lock);
950 lpuart32_transmit_buffer(sport);
951 spin_unlock(&sport->port.lock);
952}
953
954static void lpuart32_rxint(struct lpuart_port *sport)
955{
956 unsigned int flg, ignored = 0;
957 struct tty_port *port = &sport->port.state->port;
958 unsigned long rx, sr;
959 bool is_break;
960
961 spin_lock(&sport->port.lock);
962
963 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
964 flg = TTY_NORMAL;
965 sport->port.icount.rx++;
966
967
968
969
970 sr = lpuart32_read(&sport->port, UARTSTAT);
971 rx = lpuart32_read(&sport->port, UARTDATA);
972 rx &= UARTDATA_MASK;
973
974
975
976
977
978 is_break = (sr & UARTSTAT_FE) && !rx;
979
980 if (is_break && uart_handle_break(&sport->port))
981 continue;
982
983 if (uart_prepare_sysrq_char(&sport->port, rx))
984 continue;
985
986 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
987 if (sr & UARTSTAT_PE) {
988 if (is_break)
989 sport->port.icount.brk++;
990 else
991 sport->port.icount.parity++;
992 } else if (sr & UARTSTAT_FE) {
993 sport->port.icount.frame++;
994 }
995
996 if (sr & UARTSTAT_OR)
997 sport->port.icount.overrun++;
998
999 if (sr & sport->port.ignore_status_mask) {
1000 if (++ignored > 100)
1001 goto out;
1002 continue;
1003 }
1004
1005 sr &= sport->port.read_status_mask;
1006
1007 if (sr & UARTSTAT_PE) {
1008 if (is_break)
1009 flg = TTY_BREAK;
1010 else
1011 flg = TTY_PARITY;
1012 } else if (sr & UARTSTAT_FE) {
1013 flg = TTY_FRAME;
1014 }
1015
1016 if (sr & UARTSTAT_OR)
1017 flg = TTY_OVERRUN;
1018 }
1019
1020 tty_insert_flip_char(port, rx, flg);
1021 }
1022
1023out:
1024 uart_unlock_and_check_sysrq(&sport->port);
1025
1026 tty_flip_buffer_push(port);
1027}
1028
1029static irqreturn_t lpuart_int(int irq, void *dev_id)
1030{
1031 struct lpuart_port *sport = dev_id;
1032 unsigned char sts;
1033
1034 sts = readb(sport->port.membase + UARTSR1);
1035
1036
1037 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1038 readb(sport->port.membase + UARTDR);
1039 uart_handle_break(&sport->port);
1040
1041 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1042 return IRQ_HANDLED;
1043 }
1044
1045 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1046 lpuart_rxint(sport);
1047
1048 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1049 lpuart_txint(sport);
1050
1051 return IRQ_HANDLED;
1052}
1053
1054static irqreturn_t lpuart32_int(int irq, void *dev_id)
1055{
1056 struct lpuart_port *sport = dev_id;
1057 unsigned long sts, rxcount;
1058
1059 sts = lpuart32_read(&sport->port, UARTSTAT);
1060 rxcount = lpuart32_read(&sport->port, UARTWATER);
1061 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1062
1063 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1064 lpuart32_rxint(sport);
1065
1066 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1067 lpuart32_txint(sport);
1068
1069 lpuart32_write(&sport->port, sts, UARTSTAT);
1070 return IRQ_HANDLED;
1071}
1072
1073
1074static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1075 unsigned char *p, int count)
1076{
1077 while (count--) {
1078 if (*p && uart_handle_sysrq_char(port, *p))
1079 return;
1080 p++;
1081 }
1082}
1083
1084static void lpuart_handle_sysrq(struct lpuart_port *sport)
1085{
1086 struct circ_buf *ring = &sport->rx_ring;
1087 int count;
1088
1089 if (ring->head < ring->tail) {
1090 count = sport->rx_sgl.length - ring->tail;
1091 lpuart_handle_sysrq_chars(&sport->port,
1092 ring->buf + ring->tail, count);
1093 ring->tail = 0;
1094 }
1095
1096 if (ring->head > ring->tail) {
1097 count = ring->head - ring->tail;
1098 lpuart_handle_sysrq_chars(&sport->port,
1099 ring->buf + ring->tail, count);
1100 ring->tail = ring->head;
1101 }
1102}
1103
1104static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1105{
1106 struct tty_port *port = &sport->port.state->port;
1107 struct dma_tx_state state;
1108 enum dma_status dmastat;
1109 struct dma_chan *chan = sport->dma_rx_chan;
1110 struct circ_buf *ring = &sport->rx_ring;
1111 unsigned long flags;
1112 int count = 0;
1113
1114 if (lpuart_is_32(sport)) {
1115 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1116
1117 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1118
1119 lpuart32_read(&sport->port, UARTDATA);
1120
1121 if (sr & UARTSTAT_PE)
1122 sport->port.icount.parity++;
1123 else if (sr & UARTSTAT_FE)
1124 sport->port.icount.frame++;
1125 }
1126 } else {
1127 unsigned char sr = readb(sport->port.membase + UARTSR1);
1128
1129 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1130 unsigned char cr2;
1131
1132
1133 cr2 = readb(sport->port.membase + UARTCR2);
1134 cr2 &= ~UARTCR2_RE;
1135 writeb(cr2, sport->port.membase + UARTCR2);
1136
1137
1138 readb(sport->port.membase + UARTDR);
1139
1140 if (sr & UARTSR1_PE)
1141 sport->port.icount.parity++;
1142 else if (sr & UARTSR1_FE)
1143 sport->port.icount.frame++;
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153 if (readb(sport->port.membase + UARTSFIFO) &
1154 UARTSFIFO_RXUF) {
1155 writeb(UARTSFIFO_RXUF,
1156 sport->port.membase + UARTSFIFO);
1157 writeb(UARTCFIFO_RXFLUSH,
1158 sport->port.membase + UARTCFIFO);
1159 }
1160
1161 cr2 |= UARTCR2_RE;
1162 writeb(cr2, sport->port.membase + UARTCR2);
1163 }
1164 }
1165
1166 async_tx_ack(sport->dma_rx_desc);
1167
1168 spin_lock_irqsave(&sport->port.lock, flags);
1169
1170 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1171 if (dmastat == DMA_ERROR) {
1172 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1173 spin_unlock_irqrestore(&sport->port.lock, flags);
1174 return;
1175 }
1176
1177
1178 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1179 DMA_FROM_DEVICE);
1180
1181
1182
1183
1184
1185
1186
1187
1188 ring->head = sport->rx_sgl.length - state.residue;
1189 BUG_ON(ring->head > sport->rx_sgl.length);
1190
1191
1192
1193
1194 if (sport->port.sysrq) {
1195 lpuart_handle_sysrq(sport);
1196 goto exit;
1197 }
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211 if (ring->head < ring->tail) {
1212 count = sport->rx_sgl.length - ring->tail;
1213
1214 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1215 ring->tail = 0;
1216 sport->port.icount.rx += count;
1217 }
1218
1219
1220 if (ring->tail < ring->head) {
1221 count = ring->head - ring->tail;
1222 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1223
1224 if (ring->head >= sport->rx_sgl.length)
1225 ring->head = 0;
1226 ring->tail = ring->head;
1227 sport->port.icount.rx += count;
1228 }
1229
1230exit:
1231 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1232 DMA_FROM_DEVICE);
1233
1234 spin_unlock_irqrestore(&sport->port.lock, flags);
1235
1236 tty_flip_buffer_push(port);
1237 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1238}
1239
1240static void lpuart_dma_rx_complete(void *arg)
1241{
1242 struct lpuart_port *sport = arg;
1243
1244 lpuart_copy_rx_to_tty(sport);
1245}
1246
1247static void lpuart_timer_func(struct timer_list *t)
1248{
1249 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1250
1251 lpuart_copy_rx_to_tty(sport);
1252}
1253
1254static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1255{
1256 struct dma_slave_config dma_rx_sconfig = {};
1257 struct circ_buf *ring = &sport->rx_ring;
1258 int ret, nent;
1259 int bits, baud;
1260 struct tty_port *port = &sport->port.state->port;
1261 struct tty_struct *tty = port->tty;
1262 struct ktermios *termios = &tty->termios;
1263 struct dma_chan *chan = sport->dma_rx_chan;
1264
1265 baud = tty_get_baud_rate(tty);
1266
1267 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1268 if (termios->c_cflag & PARENB)
1269 bits++;
1270
1271
1272
1273
1274
1275 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1276 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1277 if (sport->rx_dma_rng_buf_len < 16)
1278 sport->rx_dma_rng_buf_len = 16;
1279
1280 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1281 if (!ring->buf)
1282 return -ENOMEM;
1283
1284 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1285 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1286 DMA_FROM_DEVICE);
1287
1288 if (!nent) {
1289 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1290 return -EINVAL;
1291 }
1292
1293 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1294 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1295 dma_rx_sconfig.src_maxburst = 1;
1296 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1297 ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1298
1299 if (ret < 0) {
1300 dev_err(sport->port.dev,
1301 "DMA Rx slave config failed, err = %d\n", ret);
1302 return ret;
1303 }
1304
1305 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1306 sg_dma_address(&sport->rx_sgl),
1307 sport->rx_sgl.length,
1308 sport->rx_sgl.length / 2,
1309 DMA_DEV_TO_MEM,
1310 DMA_PREP_INTERRUPT);
1311 if (!sport->dma_rx_desc) {
1312 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1313 return -EFAULT;
1314 }
1315
1316 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1317 sport->dma_rx_desc->callback_param = sport;
1318 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1319 dma_async_issue_pending(chan);
1320
1321 if (lpuart_is_32(sport)) {
1322 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1323
1324 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1325 } else {
1326 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1327 sport->port.membase + UARTCR5);
1328 }
1329
1330 return 0;
1331}
1332
1333static void lpuart_dma_rx_free(struct uart_port *port)
1334{
1335 struct lpuart_port *sport = container_of(port,
1336 struct lpuart_port, port);
1337 struct dma_chan *chan = sport->dma_rx_chan;
1338
1339 dmaengine_terminate_all(chan);
1340 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1341 kfree(sport->rx_ring.buf);
1342 sport->rx_ring.tail = 0;
1343 sport->rx_ring.head = 0;
1344 sport->dma_rx_desc = NULL;
1345 sport->dma_rx_cookie = -EINVAL;
1346}
1347
1348static int lpuart_config_rs485(struct uart_port *port,
1349 struct serial_rs485 *rs485)
1350{
1351 struct lpuart_port *sport = container_of(port,
1352 struct lpuart_port, port);
1353
1354 u8 modem = readb(sport->port.membase + UARTMODEM) &
1355 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1356 writeb(modem, sport->port.membase + UARTMODEM);
1357
1358
1359 rs485->delay_rts_before_send = 0;
1360 rs485->delay_rts_after_send = 0;
1361 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1362
1363 if (rs485->flags & SER_RS485_ENABLED) {
1364
1365 modem |= UARTMODEM_TXRTSE;
1366
1367
1368
1369
1370
1371
1372 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1373 SER_RS485_RTS_AFTER_SEND)))
1374 rs485->flags |= SER_RS485_RTS_ON_SEND;
1375
1376 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1377 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1378 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1379
1380
1381
1382
1383
1384
1385
1386 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1387 modem &= ~UARTMODEM_TXRTSPOL;
1388 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1389 modem |= UARTMODEM_TXRTSPOL;
1390 }
1391
1392
1393 sport->port.rs485 = *rs485;
1394
1395 writeb(modem, sport->port.membase + UARTMODEM);
1396 return 0;
1397}
1398
1399static int lpuart32_config_rs485(struct uart_port *port,
1400 struct serial_rs485 *rs485)
1401{
1402 struct lpuart_port *sport = container_of(port,
1403 struct lpuart_port, port);
1404
1405 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1406 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1407 lpuart32_write(&sport->port, modem, UARTMODIR);
1408
1409
1410 rs485->delay_rts_before_send = 0;
1411 rs485->delay_rts_after_send = 0;
1412 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1413
1414 if (rs485->flags & SER_RS485_ENABLED) {
1415
1416 modem |= UARTMODEM_TXRTSE;
1417
1418
1419
1420
1421
1422
1423 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1424 SER_RS485_RTS_AFTER_SEND)))
1425 rs485->flags |= SER_RS485_RTS_ON_SEND;
1426
1427 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1428 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1429 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1430
1431
1432
1433
1434
1435
1436
1437 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1438 modem &= ~UARTMODEM_TXRTSPOL;
1439 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1440 modem |= UARTMODEM_TXRTSPOL;
1441 }
1442
1443
1444 sport->port.rs485 = *rs485;
1445
1446 lpuart32_write(&sport->port, modem, UARTMODIR);
1447 return 0;
1448}
1449
1450static unsigned int lpuart_get_mctrl(struct uart_port *port)
1451{
1452 unsigned int mctrl = 0;
1453 u8 reg;
1454
1455 reg = readb(port->membase + UARTCR1);
1456 if (reg & UARTCR1_LOOPS)
1457 mctrl |= TIOCM_LOOP;
1458
1459 return mctrl;
1460}
1461
1462static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1463{
1464 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1465 u32 reg;
1466
1467 reg = lpuart32_read(port, UARTCTRL);
1468 if (reg & UARTCTRL_LOOPS)
1469 mctrl |= TIOCM_LOOP;
1470
1471 return mctrl;
1472}
1473
1474static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1475{
1476 u8 reg;
1477
1478 reg = readb(port->membase + UARTCR1);
1479
1480
1481 reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1482 if (mctrl & TIOCM_LOOP)
1483 reg |= UARTCR1_LOOPS;
1484
1485 writeb(reg, port->membase + UARTCR1);
1486}
1487
1488static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1489{
1490 u32 reg;
1491
1492 reg = lpuart32_read(port, UARTCTRL);
1493
1494
1495 reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1496 if (mctrl & TIOCM_LOOP)
1497 reg |= UARTCTRL_LOOPS;
1498
1499 lpuart32_write(port, reg, UARTCTRL);
1500}
1501
1502static void lpuart_break_ctl(struct uart_port *port, int break_state)
1503{
1504 unsigned char temp;
1505
1506 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1507
1508 if (break_state != 0)
1509 temp |= UARTCR2_SBK;
1510
1511 writeb(temp, port->membase + UARTCR2);
1512}
1513
1514static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1515{
1516 unsigned long temp;
1517
1518 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1519
1520 if (break_state != 0)
1521 temp |= UARTCTRL_SBK;
1522
1523 lpuart32_write(port, temp, UARTCTRL);
1524}
1525
1526static void lpuart_setup_watermark(struct lpuart_port *sport)
1527{
1528 unsigned char val, cr2;
1529 unsigned char cr2_saved;
1530
1531 cr2 = readb(sport->port.membase + UARTCR2);
1532 cr2_saved = cr2;
1533 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1534 UARTCR2_RIE | UARTCR2_RE);
1535 writeb(cr2, sport->port.membase + UARTCR2);
1536
1537 val = readb(sport->port.membase + UARTPFIFO);
1538 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1539 sport->port.membase + UARTPFIFO);
1540
1541
1542 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1543 sport->port.membase + UARTCFIFO);
1544
1545
1546 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1547 readb(sport->port.membase + UARTDR);
1548 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1549 }
1550
1551 writeb(0, sport->port.membase + UARTTWFIFO);
1552 writeb(1, sport->port.membase + UARTRWFIFO);
1553
1554
1555 writeb(cr2_saved, sport->port.membase + UARTCR2);
1556}
1557
1558static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1559{
1560 unsigned char cr2;
1561
1562 lpuart_setup_watermark(sport);
1563
1564 cr2 = readb(sport->port.membase + UARTCR2);
1565 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1566 writeb(cr2, sport->port.membase + UARTCR2);
1567}
1568
1569static void lpuart32_setup_watermark(struct lpuart_port *sport)
1570{
1571 unsigned long val, ctrl;
1572 unsigned long ctrl_saved;
1573
1574 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1575 ctrl_saved = ctrl;
1576 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1577 UARTCTRL_RIE | UARTCTRL_RE);
1578 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1579
1580
1581 val = lpuart32_read(&sport->port, UARTFIFO);
1582 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1583 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1584 lpuart32_write(&sport->port, val, UARTFIFO);
1585
1586
1587 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1588 lpuart32_write(&sport->port, val, UARTWATER);
1589
1590
1591 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1592}
1593
1594static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1595{
1596 u32 temp;
1597
1598 lpuart32_setup_watermark(sport);
1599
1600 temp = lpuart32_read(&sport->port, UARTCTRL);
1601 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1602 lpuart32_write(&sport->port, temp, UARTCTRL);
1603}
1604
1605static void rx_dma_timer_init(struct lpuart_port *sport)
1606{
1607 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1608 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1609 add_timer(&sport->lpuart_timer);
1610}
1611
1612static void lpuart_request_dma(struct lpuart_port *sport)
1613{
1614 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1615 if (IS_ERR(sport->dma_tx_chan)) {
1616 dev_dbg_once(sport->port.dev,
1617 "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1618 PTR_ERR(sport->dma_tx_chan));
1619 sport->dma_tx_chan = NULL;
1620 }
1621
1622 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1623 if (IS_ERR(sport->dma_rx_chan)) {
1624 dev_dbg_once(sport->port.dev,
1625 "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1626 PTR_ERR(sport->dma_rx_chan));
1627 sport->dma_rx_chan = NULL;
1628 }
1629}
1630
1631static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1632{
1633 u32 uartbaud;
1634 int ret;
1635
1636 if (uart_console(&sport->port))
1637 goto err;
1638
1639 if (!sport->dma_tx_chan)
1640 goto err;
1641
1642 ret = lpuart_dma_tx_request(&sport->port);
1643 if (ret)
1644 goto err;
1645
1646 init_waitqueue_head(&sport->dma_wait);
1647 sport->lpuart_dma_tx_use = true;
1648 if (lpuart_is_32(sport)) {
1649 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1650 lpuart32_write(&sport->port,
1651 uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1652 } else {
1653 writeb(readb(sport->port.membase + UARTCR5) |
1654 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1655 }
1656
1657 return;
1658
1659err:
1660 sport->lpuart_dma_tx_use = false;
1661}
1662
1663static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1664{
1665 int ret;
1666 unsigned char cr3;
1667
1668 if (uart_console(&sport->port))
1669 goto err;
1670
1671 if (!sport->dma_rx_chan)
1672 goto err;
1673
1674 ret = lpuart_start_rx_dma(sport);
1675 if (ret)
1676 goto err;
1677
1678
1679 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1680 if (!sport->dma_rx_timeout)
1681 sport->dma_rx_timeout = 1;
1682
1683 sport->lpuart_dma_rx_use = true;
1684 rx_dma_timer_init(sport);
1685
1686 if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1687 cr3 = readb(sport->port.membase + UARTCR3);
1688 cr3 |= UARTCR3_FEIE;
1689 writeb(cr3, sport->port.membase + UARTCR3);
1690 }
1691
1692 return;
1693
1694err:
1695 sport->lpuart_dma_rx_use = false;
1696}
1697
1698static int lpuart_startup(struct uart_port *port)
1699{
1700 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1701 unsigned long flags;
1702 unsigned char temp;
1703
1704
1705 temp = readb(sport->port.membase + UARTPFIFO);
1706
1707 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1708 UARTPFIFO_FIFOSIZE_MASK);
1709 sport->port.fifosize = sport->txfifo_size;
1710
1711 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1712 UARTPFIFO_FIFOSIZE_MASK);
1713
1714 lpuart_request_dma(sport);
1715
1716 spin_lock_irqsave(&sport->port.lock, flags);
1717
1718 lpuart_setup_watermark_enable(sport);
1719
1720 lpuart_rx_dma_startup(sport);
1721 lpuart_tx_dma_startup(sport);
1722
1723 spin_unlock_irqrestore(&sport->port.lock, flags);
1724
1725 return 0;
1726}
1727
1728static void lpuart32_configure(struct lpuart_port *sport)
1729{
1730 unsigned long temp;
1731
1732 if (sport->lpuart_dma_rx_use) {
1733
1734 temp = lpuart32_read(&sport->port, UARTWATER);
1735 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1736 lpuart32_write(&sport->port, temp, UARTWATER);
1737 }
1738 temp = lpuart32_read(&sport->port, UARTCTRL);
1739 if (!sport->lpuart_dma_rx_use)
1740 temp |= UARTCTRL_RIE;
1741 if (!sport->lpuart_dma_tx_use)
1742 temp |= UARTCTRL_TIE;
1743 lpuart32_write(&sport->port, temp, UARTCTRL);
1744}
1745
1746static int lpuart32_startup(struct uart_port *port)
1747{
1748 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1749 unsigned long flags;
1750 unsigned long temp;
1751
1752
1753 temp = lpuart32_read(&sport->port, UARTFIFO);
1754
1755 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1756 UARTFIFO_FIFOSIZE_MASK);
1757 sport->port.fifosize = sport->txfifo_size;
1758
1759 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1760 UARTFIFO_FIFOSIZE_MASK);
1761
1762
1763
1764
1765
1766
1767 if (is_layerscape_lpuart(sport)) {
1768 sport->rxfifo_size = 16;
1769 sport->txfifo_size = 16;
1770 sport->port.fifosize = sport->txfifo_size;
1771 }
1772
1773 lpuart_request_dma(sport);
1774
1775 spin_lock_irqsave(&sport->port.lock, flags);
1776
1777 lpuart32_setup_watermark_enable(sport);
1778
1779 lpuart_rx_dma_startup(sport);
1780 lpuart_tx_dma_startup(sport);
1781
1782 lpuart32_configure(sport);
1783
1784 spin_unlock_irqrestore(&sport->port.lock, flags);
1785 return 0;
1786}
1787
1788static void lpuart_dma_shutdown(struct lpuart_port *sport)
1789{
1790 if (sport->lpuart_dma_rx_use) {
1791 del_timer_sync(&sport->lpuart_timer);
1792 lpuart_dma_rx_free(&sport->port);
1793 }
1794
1795 if (sport->lpuart_dma_tx_use) {
1796 if (wait_event_interruptible(sport->dma_wait,
1797 !sport->dma_tx_in_progress) != false) {
1798 sport->dma_tx_in_progress = false;
1799 dmaengine_terminate_all(sport->dma_tx_chan);
1800 }
1801 }
1802
1803 if (sport->dma_tx_chan)
1804 dma_release_channel(sport->dma_tx_chan);
1805 if (sport->dma_rx_chan)
1806 dma_release_channel(sport->dma_rx_chan);
1807}
1808
1809static void lpuart_shutdown(struct uart_port *port)
1810{
1811 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1812 unsigned char temp;
1813 unsigned long flags;
1814
1815 spin_lock_irqsave(&port->lock, flags);
1816
1817
1818 temp = readb(port->membase + UARTCR2);
1819 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1820 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1821 writeb(temp, port->membase + UARTCR2);
1822
1823 spin_unlock_irqrestore(&port->lock, flags);
1824
1825 lpuart_dma_shutdown(sport);
1826}
1827
1828static void lpuart32_shutdown(struct uart_port *port)
1829{
1830 struct lpuart_port *sport =
1831 container_of(port, struct lpuart_port, port);
1832 unsigned long temp;
1833 unsigned long flags;
1834
1835 spin_lock_irqsave(&port->lock, flags);
1836
1837
1838 temp = lpuart32_read(port, UARTCTRL);
1839 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1840 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1841 lpuart32_write(port, temp, UARTCTRL);
1842
1843 spin_unlock_irqrestore(&port->lock, flags);
1844
1845 lpuart_dma_shutdown(sport);
1846}
1847
1848static void
1849lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1850 struct ktermios *old)
1851{
1852 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1853 unsigned long flags;
1854 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1855 unsigned int baud;
1856 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1857 unsigned int sbr, brfa;
1858
1859 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1860 old_cr2 = readb(sport->port.membase + UARTCR2);
1861 cr3 = readb(sport->port.membase + UARTCR3);
1862 cr4 = readb(sport->port.membase + UARTCR4);
1863 bdh = readb(sport->port.membase + UARTBDH);
1864 modem = readb(sport->port.membase + UARTMODEM);
1865
1866
1867
1868
1869
1870
1871
1872
1873 while ((termios->c_cflag & CSIZE) != CS8 &&
1874 (termios->c_cflag & CSIZE) != CS7) {
1875 termios->c_cflag &= ~CSIZE;
1876 termios->c_cflag |= old_csize;
1877 old_csize = CS8;
1878 }
1879
1880 if ((termios->c_cflag & CSIZE) == CS8 ||
1881 (termios->c_cflag & CSIZE) == CS7)
1882 cr1 = old_cr1 & ~UARTCR1_M;
1883
1884 if (termios->c_cflag & CMSPAR) {
1885 if ((termios->c_cflag & CSIZE) != CS8) {
1886 termios->c_cflag &= ~CSIZE;
1887 termios->c_cflag |= CS8;
1888 }
1889 cr1 |= UARTCR1_M;
1890 }
1891
1892
1893
1894
1895
1896 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1897 termios->c_cflag &= ~CRTSCTS;
1898
1899 if (termios->c_cflag & CRTSCTS)
1900 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1901 else
1902 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1903
1904 termios->c_cflag &= ~CSTOPB;
1905
1906
1907 if ((termios->c_cflag & CSIZE) == CS7)
1908 termios->c_cflag |= PARENB;
1909
1910 if (termios->c_cflag & PARENB) {
1911 if (termios->c_cflag & CMSPAR) {
1912 cr1 &= ~UARTCR1_PE;
1913 if (termios->c_cflag & PARODD)
1914 cr3 |= UARTCR3_T8;
1915 else
1916 cr3 &= ~UARTCR3_T8;
1917 } else {
1918 cr1 |= UARTCR1_PE;
1919 if ((termios->c_cflag & CSIZE) == CS8)
1920 cr1 |= UARTCR1_M;
1921 if (termios->c_cflag & PARODD)
1922 cr1 |= UARTCR1_PT;
1923 else
1924 cr1 &= ~UARTCR1_PT;
1925 }
1926 } else {
1927 cr1 &= ~UARTCR1_PE;
1928 }
1929
1930
1931 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1932
1933
1934
1935
1936
1937
1938
1939
1940 if (old && sport->lpuart_dma_rx_use) {
1941 del_timer_sync(&sport->lpuart_timer);
1942 lpuart_dma_rx_free(&sport->port);
1943 }
1944
1945 spin_lock_irqsave(&sport->port.lock, flags);
1946
1947 sport->port.read_status_mask = 0;
1948 if (termios->c_iflag & INPCK)
1949 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1950 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1951 sport->port.read_status_mask |= UARTSR1_FE;
1952
1953
1954 sport->port.ignore_status_mask = 0;
1955 if (termios->c_iflag & IGNPAR)
1956 sport->port.ignore_status_mask |= UARTSR1_PE;
1957 if (termios->c_iflag & IGNBRK) {
1958 sport->port.ignore_status_mask |= UARTSR1_FE;
1959
1960
1961
1962
1963 if (termios->c_iflag & IGNPAR)
1964 sport->port.ignore_status_mask |= UARTSR1_OR;
1965 }
1966
1967
1968 uart_update_timeout(port, termios->c_cflag, baud);
1969
1970
1971 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1972
1973
1974 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1975 sport->port.membase + UARTCR2);
1976
1977 sbr = sport->port.uartclk / (16 * baud);
1978 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1979 bdh &= ~UARTBDH_SBR_MASK;
1980 bdh |= (sbr >> 8) & 0x1F;
1981 cr4 &= ~UARTCR4_BRFA_MASK;
1982 brfa &= UARTCR4_BRFA_MASK;
1983 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1984 writeb(bdh, sport->port.membase + UARTBDH);
1985 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1986 writeb(cr3, sport->port.membase + UARTCR3);
1987 writeb(cr1, sport->port.membase + UARTCR1);
1988 writeb(modem, sport->port.membase + UARTMODEM);
1989
1990
1991 writeb(old_cr2, sport->port.membase + UARTCR2);
1992
1993 if (old && sport->lpuart_dma_rx_use) {
1994 if (!lpuart_start_rx_dma(sport))
1995 rx_dma_timer_init(sport);
1996 else
1997 sport->lpuart_dma_rx_use = false;
1998 }
1999
2000 spin_unlock_irqrestore(&sport->port.lock, flags);
2001}
2002
2003static void __lpuart32_serial_setbrg(struct uart_port *port,
2004 unsigned int baudrate, bool use_rx_dma,
2005 bool use_tx_dma)
2006{
2007 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
2008 u32 clk = port->uartclk;
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019 baud_diff = baudrate;
2020 osr = 0;
2021 sbr = 0;
2022
2023 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
2024
2025 tmp_sbr = (clk / (baudrate * tmp_osr));
2026 if (tmp_sbr == 0)
2027 tmp_sbr = 1;
2028
2029
2030
2031
2032
2033 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
2034
2035
2036 tmp = clk / (tmp_osr * (tmp_sbr + 1));
2037 if (tmp_diff > (baudrate - tmp)) {
2038 tmp_diff = baudrate - tmp;
2039 tmp_sbr++;
2040 }
2041
2042 if (tmp_sbr > UARTBAUD_SBR_MASK)
2043 continue;
2044
2045 if (tmp_diff <= baud_diff) {
2046 baud_diff = tmp_diff;
2047 osr = tmp_osr;
2048 sbr = tmp_sbr;
2049
2050 if (!baud_diff)
2051 break;
2052 }
2053 }
2054
2055
2056 if (baud_diff > ((baudrate / 100) * 3))
2057 dev_warn(port->dev,
2058 "unacceptable baud rate difference of more than 3%%\n");
2059
2060 tmp = lpuart32_read(port, UARTBAUD);
2061
2062 if ((osr > 3) && (osr < 8))
2063 tmp |= UARTBAUD_BOTHEDGE;
2064
2065 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2066 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2067
2068 tmp &= ~UARTBAUD_SBR_MASK;
2069 tmp |= sbr & UARTBAUD_SBR_MASK;
2070
2071 if (!use_rx_dma)
2072 tmp &= ~UARTBAUD_RDMAE;
2073 if (!use_tx_dma)
2074 tmp &= ~UARTBAUD_TDMAE;
2075
2076 lpuart32_write(port, tmp, UARTBAUD);
2077}
2078
2079static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2080 unsigned int baudrate)
2081{
2082 __lpuart32_serial_setbrg(&sport->port, baudrate,
2083 sport->lpuart_dma_rx_use,
2084 sport->lpuart_dma_tx_use);
2085}
2086
2087
2088static void
2089lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2090 struct ktermios *old)
2091{
2092 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2093 unsigned long flags;
2094 unsigned long ctrl, old_ctrl, bd, modem;
2095 unsigned int baud;
2096 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2097
2098 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2099 bd = lpuart32_read(&sport->port, UARTBAUD);
2100 modem = lpuart32_read(&sport->port, UARTMODIR);
2101
2102
2103
2104
2105
2106
2107
2108
2109 while ((termios->c_cflag & CSIZE) != CS8 &&
2110 (termios->c_cflag & CSIZE) != CS7) {
2111 termios->c_cflag &= ~CSIZE;
2112 termios->c_cflag |= old_csize;
2113 old_csize = CS8;
2114 }
2115
2116 if ((termios->c_cflag & CSIZE) == CS8 ||
2117 (termios->c_cflag & CSIZE) == CS7)
2118 ctrl = old_ctrl & ~UARTCTRL_M;
2119
2120 if (termios->c_cflag & CMSPAR) {
2121 if ((termios->c_cflag & CSIZE) != CS8) {
2122 termios->c_cflag &= ~CSIZE;
2123 termios->c_cflag |= CS8;
2124 }
2125 ctrl |= UARTCTRL_M;
2126 }
2127
2128
2129
2130
2131
2132 if (sport->port.rs485.flags & SER_RS485_ENABLED)
2133 termios->c_cflag &= ~CRTSCTS;
2134
2135 if (termios->c_cflag & CRTSCTS) {
2136 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2137 } else {
2138 termios->c_cflag &= ~CRTSCTS;
2139 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2140 }
2141
2142 if (termios->c_cflag & CSTOPB)
2143 bd |= UARTBAUD_SBNS;
2144 else
2145 bd &= ~UARTBAUD_SBNS;
2146
2147
2148 if ((termios->c_cflag & CSIZE) == CS7)
2149 termios->c_cflag |= PARENB;
2150
2151 if ((termios->c_cflag & PARENB)) {
2152 if (termios->c_cflag & CMSPAR) {
2153 ctrl &= ~UARTCTRL_PE;
2154 ctrl |= UARTCTRL_M;
2155 } else {
2156 ctrl |= UARTCTRL_PE;
2157 if ((termios->c_cflag & CSIZE) == CS8)
2158 ctrl |= UARTCTRL_M;
2159 if (termios->c_cflag & PARODD)
2160 ctrl |= UARTCTRL_PT;
2161 else
2162 ctrl &= ~UARTCTRL_PT;
2163 }
2164 } else {
2165 ctrl &= ~UARTCTRL_PE;
2166 }
2167
2168
2169 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2170
2171
2172
2173
2174
2175
2176
2177
2178 if (old && sport->lpuart_dma_rx_use) {
2179 del_timer_sync(&sport->lpuart_timer);
2180 lpuart_dma_rx_free(&sport->port);
2181 }
2182
2183 spin_lock_irqsave(&sport->port.lock, flags);
2184
2185 sport->port.read_status_mask = 0;
2186 if (termios->c_iflag & INPCK)
2187 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2188 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2189 sport->port.read_status_mask |= UARTSTAT_FE;
2190
2191
2192 sport->port.ignore_status_mask = 0;
2193 if (termios->c_iflag & IGNPAR)
2194 sport->port.ignore_status_mask |= UARTSTAT_PE;
2195 if (termios->c_iflag & IGNBRK) {
2196 sport->port.ignore_status_mask |= UARTSTAT_FE;
2197
2198
2199
2200
2201 if (termios->c_iflag & IGNPAR)
2202 sport->port.ignore_status_mask |= UARTSTAT_OR;
2203 }
2204
2205
2206 uart_update_timeout(port, termios->c_cflag, baud);
2207
2208
2209 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2210
2211
2212 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2213 UARTCTRL);
2214
2215 lpuart32_write(&sport->port, bd, UARTBAUD);
2216 lpuart32_serial_setbrg(sport, baud);
2217 lpuart32_write(&sport->port, modem, UARTMODIR);
2218 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2219
2220
2221 if (old && sport->lpuart_dma_rx_use) {
2222 if (!lpuart_start_rx_dma(sport))
2223 rx_dma_timer_init(sport);
2224 else
2225 sport->lpuart_dma_rx_use = false;
2226 }
2227
2228 spin_unlock_irqrestore(&sport->port.lock, flags);
2229}
2230
2231static const char *lpuart_type(struct uart_port *port)
2232{
2233 return "FSL_LPUART";
2234}
2235
2236static void lpuart_release_port(struct uart_port *port)
2237{
2238
2239}
2240
2241static int lpuart_request_port(struct uart_port *port)
2242{
2243 return 0;
2244}
2245
2246
2247static void lpuart_config_port(struct uart_port *port, int flags)
2248{
2249 if (flags & UART_CONFIG_TYPE)
2250 port->type = PORT_LPUART;
2251}
2252
2253static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2254{
2255 int ret = 0;
2256
2257 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2258 ret = -EINVAL;
2259 if (port->irq != ser->irq)
2260 ret = -EINVAL;
2261 if (ser->io_type != UPIO_MEM)
2262 ret = -EINVAL;
2263 if (port->uartclk / 16 != ser->baud_base)
2264 ret = -EINVAL;
2265 if (port->iobase != ser->port)
2266 ret = -EINVAL;
2267 if (ser->hub6 != 0)
2268 ret = -EINVAL;
2269 return ret;
2270}
2271
2272static const struct uart_ops lpuart_pops = {
2273 .tx_empty = lpuart_tx_empty,
2274 .set_mctrl = lpuart_set_mctrl,
2275 .get_mctrl = lpuart_get_mctrl,
2276 .stop_tx = lpuart_stop_tx,
2277 .start_tx = lpuart_start_tx,
2278 .stop_rx = lpuart_stop_rx,
2279 .break_ctl = lpuart_break_ctl,
2280 .startup = lpuart_startup,
2281 .shutdown = lpuart_shutdown,
2282 .set_termios = lpuart_set_termios,
2283 .type = lpuart_type,
2284 .request_port = lpuart_request_port,
2285 .release_port = lpuart_release_port,
2286 .config_port = lpuart_config_port,
2287 .verify_port = lpuart_verify_port,
2288 .flush_buffer = lpuart_flush_buffer,
2289#if defined(CONFIG_CONSOLE_POLL)
2290 .poll_init = lpuart_poll_init,
2291 .poll_get_char = lpuart_poll_get_char,
2292 .poll_put_char = lpuart_poll_put_char,
2293#endif
2294};
2295
2296static const struct uart_ops lpuart32_pops = {
2297 .tx_empty = lpuart32_tx_empty,
2298 .set_mctrl = lpuart32_set_mctrl,
2299 .get_mctrl = lpuart32_get_mctrl,
2300 .stop_tx = lpuart32_stop_tx,
2301 .start_tx = lpuart32_start_tx,
2302 .stop_rx = lpuart32_stop_rx,
2303 .break_ctl = lpuart32_break_ctl,
2304 .startup = lpuart32_startup,
2305 .shutdown = lpuart32_shutdown,
2306 .set_termios = lpuart32_set_termios,
2307 .type = lpuart_type,
2308 .request_port = lpuart_request_port,
2309 .release_port = lpuart_release_port,
2310 .config_port = lpuart_config_port,
2311 .verify_port = lpuart_verify_port,
2312 .flush_buffer = lpuart_flush_buffer,
2313#if defined(CONFIG_CONSOLE_POLL)
2314 .poll_init = lpuart32_poll_init,
2315 .poll_get_char = lpuart32_poll_get_char,
2316 .poll_put_char = lpuart32_poll_put_char,
2317#endif
2318};
2319
2320static struct lpuart_port *lpuart_ports[UART_NR];
2321
2322#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2323static void lpuart_console_putchar(struct uart_port *port, int ch)
2324{
2325 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2326 writeb(ch, port->membase + UARTDR);
2327}
2328
2329static void lpuart32_console_putchar(struct uart_port *port, int ch)
2330{
2331 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2332 lpuart32_write(port, ch, UARTDATA);
2333}
2334
2335static void
2336lpuart_console_write(struct console *co, const char *s, unsigned int count)
2337{
2338 struct lpuart_port *sport = lpuart_ports[co->index];
2339 unsigned char old_cr2, cr2;
2340 unsigned long flags;
2341 int locked = 1;
2342
2343 if (oops_in_progress)
2344 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2345 else
2346 spin_lock_irqsave(&sport->port.lock, flags);
2347
2348
2349 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2350 cr2 |= UARTCR2_TE | UARTCR2_RE;
2351 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2352 writeb(cr2, sport->port.membase + UARTCR2);
2353
2354 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2355
2356
2357 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2358
2359 writeb(old_cr2, sport->port.membase + UARTCR2);
2360
2361 if (locked)
2362 spin_unlock_irqrestore(&sport->port.lock, flags);
2363}
2364
2365static void
2366lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2367{
2368 struct lpuart_port *sport = lpuart_ports[co->index];
2369 unsigned long old_cr, cr;
2370 unsigned long flags;
2371 int locked = 1;
2372
2373 if (oops_in_progress)
2374 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2375 else
2376 spin_lock_irqsave(&sport->port.lock, flags);
2377
2378
2379 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2380 cr |= UARTCTRL_TE | UARTCTRL_RE;
2381 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2382 lpuart32_write(&sport->port, cr, UARTCTRL);
2383
2384 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2385
2386
2387 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2388
2389 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2390
2391 if (locked)
2392 spin_unlock_irqrestore(&sport->port.lock, flags);
2393}
2394
2395
2396
2397
2398
2399static void __init
2400lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2401 int *parity, int *bits)
2402{
2403 unsigned char cr, bdh, bdl, brfa;
2404 unsigned int sbr, uartclk, baud_raw;
2405
2406 cr = readb(sport->port.membase + UARTCR2);
2407 cr &= UARTCR2_TE | UARTCR2_RE;
2408 if (!cr)
2409 return;
2410
2411
2412
2413 cr = readb(sport->port.membase + UARTCR1);
2414
2415 *parity = 'n';
2416 if (cr & UARTCR1_PE) {
2417 if (cr & UARTCR1_PT)
2418 *parity = 'o';
2419 else
2420 *parity = 'e';
2421 }
2422
2423 if (cr & UARTCR1_M)
2424 *bits = 9;
2425 else
2426 *bits = 8;
2427
2428 bdh = readb(sport->port.membase + UARTBDH);
2429 bdh &= UARTBDH_SBR_MASK;
2430 bdl = readb(sport->port.membase + UARTBDL);
2431 sbr = bdh;
2432 sbr <<= 8;
2433 sbr |= bdl;
2434 brfa = readb(sport->port.membase + UARTCR4);
2435 brfa &= UARTCR4_BRFA_MASK;
2436
2437 uartclk = lpuart_get_baud_clk_rate(sport);
2438
2439
2440
2441 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2442
2443 if (*baud != baud_raw)
2444 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2445 "from %d to %d\n", baud_raw, *baud);
2446}
2447
2448static void __init
2449lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2450 int *parity, int *bits)
2451{
2452 unsigned long cr, bd;
2453 unsigned int sbr, uartclk, baud_raw;
2454
2455 cr = lpuart32_read(&sport->port, UARTCTRL);
2456 cr &= UARTCTRL_TE | UARTCTRL_RE;
2457 if (!cr)
2458 return;
2459
2460
2461
2462 cr = lpuart32_read(&sport->port, UARTCTRL);
2463
2464 *parity = 'n';
2465 if (cr & UARTCTRL_PE) {
2466 if (cr & UARTCTRL_PT)
2467 *parity = 'o';
2468 else
2469 *parity = 'e';
2470 }
2471
2472 if (cr & UARTCTRL_M)
2473 *bits = 9;
2474 else
2475 *bits = 8;
2476
2477 bd = lpuart32_read(&sport->port, UARTBAUD);
2478 bd &= UARTBAUD_SBR_MASK;
2479 if (!bd)
2480 return;
2481
2482 sbr = bd;
2483 uartclk = lpuart_get_baud_clk_rate(sport);
2484
2485
2486
2487 baud_raw = uartclk / (16 * sbr);
2488
2489 if (*baud != baud_raw)
2490 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2491 "from %d to %d\n", baud_raw, *baud);
2492}
2493
2494static int __init lpuart_console_setup(struct console *co, char *options)
2495{
2496 struct lpuart_port *sport;
2497 int baud = 115200;
2498 int bits = 8;
2499 int parity = 'n';
2500 int flow = 'n';
2501
2502
2503
2504
2505
2506
2507 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2508 co->index = 0;
2509
2510 sport = lpuart_ports[co->index];
2511 if (sport == NULL)
2512 return -ENODEV;
2513
2514 if (options)
2515 uart_parse_options(options, &baud, &parity, &bits, &flow);
2516 else
2517 if (lpuart_is_32(sport))
2518 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2519 else
2520 lpuart_console_get_options(sport, &baud, &parity, &bits);
2521
2522 if (lpuart_is_32(sport))
2523 lpuart32_setup_watermark(sport);
2524 else
2525 lpuart_setup_watermark(sport);
2526
2527 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2528}
2529
2530static struct uart_driver lpuart_reg;
2531static struct console lpuart_console = {
2532 .name = DEV_NAME,
2533 .write = lpuart_console_write,
2534 .device = uart_console_device,
2535 .setup = lpuart_console_setup,
2536 .flags = CON_PRINTBUFFER,
2537 .index = -1,
2538 .data = &lpuart_reg,
2539};
2540
2541static struct console lpuart32_console = {
2542 .name = DEV_NAME,
2543 .write = lpuart32_console_write,
2544 .device = uart_console_device,
2545 .setup = lpuart_console_setup,
2546 .flags = CON_PRINTBUFFER,
2547 .index = -1,
2548 .data = &lpuart_reg,
2549};
2550
2551static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2552{
2553 struct earlycon_device *dev = con->data;
2554
2555 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2556}
2557
2558static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2559{
2560 struct earlycon_device *dev = con->data;
2561
2562 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2563}
2564
2565static int __init lpuart_early_console_setup(struct earlycon_device *device,
2566 const char *opt)
2567{
2568 if (!device->port.membase)
2569 return -ENODEV;
2570
2571 device->con->write = lpuart_early_write;
2572 return 0;
2573}
2574
2575static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2576 const char *opt)
2577{
2578 if (!device->port.membase)
2579 return -ENODEV;
2580
2581 if (device->port.iotype != UPIO_MEM32)
2582 device->port.iotype = UPIO_MEM32BE;
2583
2584 device->con->write = lpuart32_early_write;
2585 return 0;
2586}
2587
2588static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2589 const char *opt)
2590{
2591 u32 cr;
2592
2593 if (!device->port.membase)
2594 return -ENODEV;
2595
2596 device->port.iotype = UPIO_MEM32;
2597 device->con->write = lpuart32_early_write;
2598
2599
2600 if (device->port.uartclk && device->baud)
2601 __lpuart32_serial_setbrg(&device->port, device->baud,
2602 false, false);
2603
2604
2605 cr = lpuart32_read(&device->port, UARTCTRL);
2606 cr |= UARTCTRL_TE;
2607 lpuart32_write(&device->port, cr, UARTCTRL);
2608
2609 return 0;
2610}
2611
2612static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2613 const char *opt)
2614{
2615 if (!device->port.membase)
2616 return -ENODEV;
2617
2618 device->port.iotype = UPIO_MEM32;
2619 device->port.membase += IMX_REG_OFF;
2620 device->con->write = lpuart32_early_write;
2621
2622 return 0;
2623}
2624OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2625OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2626OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2627OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2628EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2629EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2630
2631#define LPUART_CONSOLE (&lpuart_console)
2632#define LPUART32_CONSOLE (&lpuart32_console)
2633#else
2634#define LPUART_CONSOLE NULL
2635#define LPUART32_CONSOLE NULL
2636#endif
2637
2638static struct uart_driver lpuart_reg = {
2639 .owner = THIS_MODULE,
2640 .driver_name = DRIVER_NAME,
2641 .dev_name = DEV_NAME,
2642 .nr = ARRAY_SIZE(lpuart_ports),
2643 .cons = LPUART_CONSOLE,
2644};
2645
2646static int lpuart_probe(struct platform_device *pdev)
2647{
2648 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2649 struct device_node *np = pdev->dev.of_node;
2650 struct lpuart_port *sport;
2651 struct resource *res;
2652 int ret;
2653
2654 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2655 if (!sport)
2656 return -ENOMEM;
2657
2658 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2659 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2660 if (IS_ERR(sport->port.membase))
2661 return PTR_ERR(sport->port.membase);
2662
2663 sport->port.membase += sdata->reg_off;
2664 sport->port.mapbase = res->start + sdata->reg_off;
2665 sport->port.dev = &pdev->dev;
2666 sport->port.type = PORT_LPUART;
2667 sport->devtype = sdata->devtype;
2668 ret = platform_get_irq(pdev, 0);
2669 if (ret < 0)
2670 return ret;
2671 sport->port.irq = ret;
2672 sport->port.iotype = sdata->iotype;
2673 if (lpuart_is_32(sport))
2674 sport->port.ops = &lpuart32_pops;
2675 else
2676 sport->port.ops = &lpuart_pops;
2677 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2678 sport->port.flags = UPF_BOOT_AUTOCONF;
2679
2680 if (lpuart_is_32(sport))
2681 sport->port.rs485_config = lpuart32_config_rs485;
2682 else
2683 sport->port.rs485_config = lpuart_config_rs485;
2684
2685 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2686 if (IS_ERR(sport->ipg_clk)) {
2687 ret = PTR_ERR(sport->ipg_clk);
2688 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2689 return ret;
2690 }
2691
2692 sport->baud_clk = NULL;
2693 if (is_imx8qxp_lpuart(sport)) {
2694 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2695 if (IS_ERR(sport->baud_clk)) {
2696 ret = PTR_ERR(sport->baud_clk);
2697 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2698 return ret;
2699 }
2700 }
2701
2702 ret = of_alias_get_id(np, "serial");
2703 if (ret < 0) {
2704 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2705 if (ret < 0) {
2706 dev_err(&pdev->dev, "port line is full, add device failed\n");
2707 return ret;
2708 }
2709 sport->id_allocated = true;
2710 }
2711 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2712 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2713 ret = -EINVAL;
2714 goto failed_out_of_range;
2715 }
2716 sport->port.line = ret;
2717
2718 ret = lpuart_enable_clks(sport);
2719 if (ret)
2720 goto failed_clock_enable;
2721 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2722
2723 lpuart_ports[sport->port.line] = sport;
2724
2725 platform_set_drvdata(pdev, &sport->port);
2726
2727 if (lpuart_is_32(sport)) {
2728 lpuart_reg.cons = LPUART32_CONSOLE;
2729 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2730 DRIVER_NAME, sport);
2731 } else {
2732 lpuart_reg.cons = LPUART_CONSOLE;
2733 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2734 DRIVER_NAME, sport);
2735 }
2736
2737 if (ret)
2738 goto failed_irq_request;
2739
2740 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2741 if (ret)
2742 goto failed_attach_port;
2743
2744 ret = lpuart_global_reset(sport);
2745 if (ret)
2746 goto failed_reset;
2747
2748 ret = uart_get_rs485_mode(&sport->port);
2749 if (ret)
2750 goto failed_get_rs485;
2751
2752 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2753 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2754
2755 if (sport->port.rs485.delay_rts_before_send ||
2756 sport->port.rs485.delay_rts_after_send)
2757 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2758
2759 sport->port.rs485_config(&sport->port, &sport->port.rs485);
2760
2761 return 0;
2762
2763failed_get_rs485:
2764failed_reset:
2765 uart_remove_one_port(&lpuart_reg, &sport->port);
2766failed_attach_port:
2767failed_irq_request:
2768 lpuart_disable_clks(sport);
2769failed_clock_enable:
2770failed_out_of_range:
2771 if (sport->id_allocated)
2772 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2773 return ret;
2774}
2775
2776static int lpuart_remove(struct platform_device *pdev)
2777{
2778 struct lpuart_port *sport = platform_get_drvdata(pdev);
2779
2780 uart_remove_one_port(&lpuart_reg, &sport->port);
2781
2782 if (sport->id_allocated)
2783 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2784
2785 lpuart_disable_clks(sport);
2786
2787 if (sport->dma_tx_chan)
2788 dma_release_channel(sport->dma_tx_chan);
2789
2790 if (sport->dma_rx_chan)
2791 dma_release_channel(sport->dma_rx_chan);
2792
2793 return 0;
2794}
2795
2796static int __maybe_unused lpuart_suspend(struct device *dev)
2797{
2798 struct lpuart_port *sport = dev_get_drvdata(dev);
2799 unsigned long temp;
2800 bool irq_wake;
2801
2802 if (lpuart_is_32(sport)) {
2803
2804 temp = lpuart32_read(&sport->port, UARTCTRL);
2805 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2806 lpuart32_write(&sport->port, temp, UARTCTRL);
2807 } else {
2808
2809 temp = readb(sport->port.membase + UARTCR2);
2810 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2811 writeb(temp, sport->port.membase + UARTCR2);
2812 }
2813
2814 uart_suspend_port(&lpuart_reg, &sport->port);
2815
2816
2817 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2818
2819 if (sport->lpuart_dma_rx_use) {
2820
2821
2822
2823
2824
2825
2826
2827 if (irq_wake) {
2828 del_timer_sync(&sport->lpuart_timer);
2829 lpuart_dma_rx_free(&sport->port);
2830 }
2831
2832
2833 if (lpuart_is_32(sport)) {
2834 temp = lpuart32_read(&sport->port, UARTBAUD);
2835 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2836 UARTBAUD);
2837 } else {
2838 writeb(readb(sport->port.membase + UARTCR5) &
2839 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2840 }
2841 }
2842
2843 if (sport->lpuart_dma_tx_use) {
2844 sport->dma_tx_in_progress = false;
2845 dmaengine_terminate_all(sport->dma_tx_chan);
2846 }
2847
2848 if (sport->port.suspended && !irq_wake)
2849 lpuart_disable_clks(sport);
2850
2851 return 0;
2852}
2853
2854static int __maybe_unused lpuart_resume(struct device *dev)
2855{
2856 struct lpuart_port *sport = dev_get_drvdata(dev);
2857 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2858
2859 if (sport->port.suspended && !irq_wake)
2860 lpuart_enable_clks(sport);
2861
2862 if (lpuart_is_32(sport))
2863 lpuart32_setup_watermark_enable(sport);
2864 else
2865 lpuart_setup_watermark_enable(sport);
2866
2867 if (sport->lpuart_dma_rx_use) {
2868 if (irq_wake) {
2869 if (!lpuart_start_rx_dma(sport))
2870 rx_dma_timer_init(sport);
2871 else
2872 sport->lpuart_dma_rx_use = false;
2873 }
2874 }
2875
2876 lpuart_tx_dma_startup(sport);
2877
2878 if (lpuart_is_32(sport))
2879 lpuart32_configure(sport);
2880
2881 uart_resume_port(&lpuart_reg, &sport->port);
2882
2883 return 0;
2884}
2885
2886static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2887
2888static struct platform_driver lpuart_driver = {
2889 .probe = lpuart_probe,
2890 .remove = lpuart_remove,
2891 .driver = {
2892 .name = "fsl-lpuart",
2893 .of_match_table = lpuart_dt_ids,
2894 .pm = &lpuart_pm_ops,
2895 },
2896};
2897
2898static int __init lpuart_serial_init(void)
2899{
2900 int ret = uart_register_driver(&lpuart_reg);
2901
2902 if (ret)
2903 return ret;
2904
2905 ret = platform_driver_register(&lpuart_driver);
2906 if (ret)
2907 uart_unregister_driver(&lpuart_reg);
2908
2909 return ret;
2910}
2911
2912static void __exit lpuart_serial_exit(void)
2913{
2914 ida_destroy(&fsl_lpuart_ida);
2915 platform_driver_unregister(&lpuart_driver);
2916 uart_unregister_driver(&lpuart_reg);
2917}
2918
2919module_init(lpuart_serial_init);
2920module_exit(lpuart_serial_exit);
2921
2922MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2923MODULE_LICENSE("GPL v2");
2924