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12#include <linux/delay.h>
13#include <linux/serial_reg.h>
14#include <linux/tty.h>
15#include <linux/pci.h>
16#include <asm/io.h>
17
18#include "jsm.h"
19
20static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
21
22
23
24
25
26
27
28
29
30static inline void neo_pci_posting_flush(struct jsm_board *bd)
31{
32 readb(bd->re_map_membase + 0x8D);
33}
34
35static void neo_set_cts_flow_control(struct jsm_channel *ch)
36{
37 u8 ier, efr;
38 ier = readb(&ch->ch_neo_uart->ier);
39 efr = readb(&ch->ch_neo_uart->efr);
40
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
42
43
44 ier |= (UART_17158_IER_CTSDSR);
45 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
46
47
48 efr &= ~(UART_17158_EFR_IXON);
49
50
51 writeb(0, &ch->ch_neo_uart->efr);
52
53
54 writeb(efr, &ch->ch_neo_uart->efr);
55
56
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
58
59
60 writeb(8, &ch->ch_neo_uart->tfifo);
61 ch->ch_t_tlevel = 8;
62
63 writeb(ier, &ch->ch_neo_uart->ier);
64}
65
66static void neo_set_rts_flow_control(struct jsm_channel *ch)
67{
68 u8 ier, efr;
69 ier = readb(&ch->ch_neo_uart->ier);
70 efr = readb(&ch->ch_neo_uart->efr);
71
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
73
74
75 ier |= (UART_17158_IER_RTSDTR);
76 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
77
78
79 ier &= ~(UART_17158_IER_XOFF);
80 efr &= ~(UART_17158_EFR_IXOFF);
81
82
83 writeb(0, &ch->ch_neo_uart->efr);
84
85
86 writeb(efr, &ch->ch_neo_uart->efr);
87
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
89 ch->ch_r_watermark = 4;
90
91 writeb(56, &ch->ch_neo_uart->rfifo);
92 ch->ch_r_tlevel = 56;
93
94 writeb(ier, &ch->ch_neo_uart->ier);
95
96
97
98
99
100
101
102 ch->ch_mostat |= (UART_MCR_RTS);
103}
104
105
106static void neo_set_ixon_flow_control(struct jsm_channel *ch)
107{
108 u8 ier, efr;
109 ier = readb(&ch->ch_neo_uart->ier);
110 efr = readb(&ch->ch_neo_uart->efr);
111
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
113
114
115 ier &= ~(UART_17158_IER_CTSDSR);
116 efr &= ~(UART_17158_EFR_CTSDSR);
117
118
119 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
120
121
122 writeb(0, &ch->ch_neo_uart->efr);
123
124
125 writeb(efr, &ch->ch_neo_uart->efr);
126
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
128 ch->ch_r_watermark = 4;
129
130 writeb(32, &ch->ch_neo_uart->rfifo);
131 ch->ch_r_tlevel = 32;
132
133
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
135 writeb(0, &ch->ch_neo_uart->xonchar2);
136
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
138 writeb(0, &ch->ch_neo_uart->xoffchar2);
139
140 writeb(ier, &ch->ch_neo_uart->ier);
141}
142
143static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
144{
145 u8 ier, efr;
146 ier = readb(&ch->ch_neo_uart->ier);
147 efr = readb(&ch->ch_neo_uart->efr);
148
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
150
151
152 ier &= ~(UART_17158_IER_RTSDTR);
153 efr &= ~(UART_17158_EFR_RTSDTR);
154
155
156 ier |= (UART_17158_IER_XOFF);
157 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
158
159
160 writeb(0, &ch->ch_neo_uart->efr);
161
162
163 writeb(efr, &ch->ch_neo_uart->efr);
164
165
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
167
168 writeb(8, &ch->ch_neo_uart->tfifo);
169 ch->ch_t_tlevel = 8;
170
171
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
173 writeb(0, &ch->ch_neo_uart->xonchar2);
174
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
176 writeb(0, &ch->ch_neo_uart->xoffchar2);
177
178 writeb(ier, &ch->ch_neo_uart->ier);
179}
180
181static void neo_set_no_input_flow_control(struct jsm_channel *ch)
182{
183 u8 ier, efr;
184 ier = readb(&ch->ch_neo_uart->ier);
185 efr = readb(&ch->ch_neo_uart->efr);
186
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
188
189
190 ier &= ~(UART_17158_IER_RTSDTR);
191 efr &= ~(UART_17158_EFR_RTSDTR);
192
193
194 ier &= ~(UART_17158_IER_XOFF);
195 if (ch->ch_c_iflag & IXON)
196 efr &= ~(UART_17158_EFR_IXOFF);
197 else
198 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
199
200
201 writeb(0, &ch->ch_neo_uart->efr);
202
203
204 writeb(efr, &ch->ch_neo_uart->efr);
205
206
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
208
209 ch->ch_r_watermark = 0;
210
211 writeb(16, &ch->ch_neo_uart->tfifo);
212 ch->ch_t_tlevel = 16;
213
214 writeb(16, &ch->ch_neo_uart->rfifo);
215 ch->ch_r_tlevel = 16;
216
217 writeb(ier, &ch->ch_neo_uart->ier);
218}
219
220static void neo_set_no_output_flow_control(struct jsm_channel *ch)
221{
222 u8 ier, efr;
223 ier = readb(&ch->ch_neo_uart->ier);
224 efr = readb(&ch->ch_neo_uart->efr);
225
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
227
228
229 ier &= ~(UART_17158_IER_CTSDSR);
230 efr &= ~(UART_17158_EFR_CTSDSR);
231
232
233 if (ch->ch_c_iflag & IXOFF)
234 efr &= ~(UART_17158_EFR_IXON);
235 else
236 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
237
238
239 writeb(0, &ch->ch_neo_uart->efr);
240
241
242 writeb(efr, &ch->ch_neo_uart->efr);
243
244
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
246
247 ch->ch_r_watermark = 0;
248
249 writeb(16, &ch->ch_neo_uart->tfifo);
250 ch->ch_t_tlevel = 16;
251
252 writeb(16, &ch->ch_neo_uart->rfifo);
253 ch->ch_r_tlevel = 16;
254
255 writeb(ier, &ch->ch_neo_uart->ier);
256}
257
258static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
259{
260
261
262 if (ch->ch_c_cflag & CRTSCTS)
263 return;
264
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
266
267
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
269 writeb(0, &ch->ch_neo_uart->xonchar2);
270
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
272 writeb(0, &ch->ch_neo_uart->xoffchar2);
273}
274
275static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
276{
277 int qleft = 0;
278 u8 linestatus = 0;
279 u8 error_mask = 0;
280 int n = 0;
281 int total = 0;
282 u16 head;
283 u16 tail;
284
285
286 head = ch->ch_r_head & RQUEUEMASK;
287 tail = ch->ch_r_tail & RQUEUEMASK;
288
289
290 linestatus = ch->ch_cached_lsr;
291 ch->ch_cached_lsr = 0;
292
293
294 if ((qleft = tail - head - 1) < 0)
295 qleft += RQUEUEMASK + 1;
296
297
298
299
300
301
302
303
304 if (!(ch->ch_flags & CH_FIFO_ENABLED))
305 total = 0;
306 else {
307 total = readb(&ch->ch_neo_uart->rfifo);
308
309
310
311
312
313
314
315
316
317 total -= 3;
318 }
319
320
321
322
323
324
325
326 total = min(total, qleft);
327
328 while (total > 0) {
329
330
331
332
333 linestatus = readb(&ch->ch_neo_uart->lsr);
334
335
336
337
338
339
340 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
341 break;
342
343
344 n = min(((u32) total), (RQUEUESIZE - (u32) head));
345
346
347
348
349
350
351
352 n = min((u32) n, (u32) 12);
353
354
355
356
357
358
359 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
360 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
361
362 linestatus = 0;
363
364
365 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
366
367
368
369
370
371 memset(ch->ch_equeue + head, 0, n);
372
373
374 head = (head + n) & RQUEUEMASK;
375 total -= n;
376 qleft -= n;
377 ch->ch_rxcount += n;
378 }
379
380
381
382
383
384 if (ch->ch_c_iflag & IGNBRK)
385 error_mask |= UART_LSR_BI;
386
387
388
389
390
391 while (1) {
392
393
394
395
396
397 linestatus |= readb(&ch->ch_neo_uart->lsr);
398
399
400
401
402
403
404 if (!(linestatus & UART_LSR_DR)) {
405 ch->ch_cached_lsr = linestatus;
406 break;
407 }
408
409
410 linestatus &= ~UART_LSR_DR;
411
412
413
414
415
416
417 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
418 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
419 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
420 }
421
422
423
424
425 if (linestatus & error_mask) {
426 u8 discard;
427 linestatus = 0;
428 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
429 continue;
430 }
431
432
433
434
435
436
437
438
439
440 while (qleft < 1) {
441 jsm_dbg(READ, &ch->ch_bd->pci_dev,
442 "Queue full, dropping DATA:%x LSR:%x\n",
443 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
444
445 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
446 ch->ch_err_overrun++;
447 qleft++;
448 }
449
450 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
451 ch->ch_equeue[head] = (u8) linestatus;
452
453 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
454 ch->ch_rqueue[head], ch->ch_equeue[head]);
455
456
457 linestatus = 0;
458
459
460 head = (head + 1) & RQUEUEMASK;
461
462 qleft--;
463 ch->ch_rxcount++;
464 }
465
466
467
468
469 ch->ch_r_head = head & RQUEUEMASK;
470 ch->ch_e_head = head & EQUEUEMASK;
471 jsm_input(ch);
472}
473
474static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
475{
476 u16 head;
477 u16 tail;
478 int n;
479 int s;
480 int qlen;
481 u32 len_written = 0;
482 struct circ_buf *circ;
483
484 if (!ch)
485 return;
486
487 circ = &ch->uart_port.state->xmit;
488
489
490 if (uart_circ_empty(circ))
491 return;
492
493
494 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
495 return;
496
497
498
499 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
500 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
501
502 ch->ch_cached_lsr |= lsrbits;
503 if (ch->ch_cached_lsr & UART_LSR_THRE) {
504 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
505
506 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
507 jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
508 "Tx data: %x\n", circ->buf[circ->tail]);
509 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1);
510 ch->ch_txcount++;
511 }
512 return;
513 }
514
515
516
517
518 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
519 return;
520
521 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
522
523
524 head = circ->head & (UART_XMIT_SIZE - 1);
525 tail = circ->tail & (UART_XMIT_SIZE - 1);
526 qlen = uart_circ_chars_pending(circ);
527
528
529 n = min(n, qlen);
530
531 while (n > 0) {
532
533 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
534 s = min(s, n);
535
536 if (s <= 0)
537 break;
538
539 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
540
541 tail = (tail + s) & (UART_XMIT_SIZE - 1);
542 n -= s;
543 ch->ch_txcount += s;
544 len_written += s;
545 }
546
547
548 circ->tail = tail & (UART_XMIT_SIZE - 1);
549
550 if (len_written >= ch->ch_t_tlevel)
551 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
552
553 if (uart_circ_empty(circ))
554 uart_write_wakeup(&ch->uart_port);
555}
556
557static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
558{
559 u8 msignals = signals;
560
561 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
562 "neo_parse_modem: port: %d msignals: %x\n",
563 ch->ch_portnum, msignals);
564
565
566
567 msignals &= 0xf8;
568
569 if (msignals & UART_MSR_DDCD)
570 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
571 if (msignals & UART_MSR_DDSR)
572 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
573 if (msignals & UART_MSR_DCD)
574 ch->ch_mistat |= UART_MSR_DCD;
575 else
576 ch->ch_mistat &= ~UART_MSR_DCD;
577
578 if (msignals & UART_MSR_DSR)
579 ch->ch_mistat |= UART_MSR_DSR;
580 else
581 ch->ch_mistat &= ~UART_MSR_DSR;
582
583 if (msignals & UART_MSR_RI)
584 ch->ch_mistat |= UART_MSR_RI;
585 else
586 ch->ch_mistat &= ~UART_MSR_RI;
587
588 if (msignals & UART_MSR_CTS)
589 ch->ch_mistat |= UART_MSR_CTS;
590 else
591 ch->ch_mistat &= ~UART_MSR_CTS;
592
593 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
594 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
595 ch->ch_portnum,
596 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
597 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
598 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
602}
603
604
605static void neo_assert_modem_signals(struct jsm_channel *ch)
606{
607 if (!ch)
608 return;
609
610 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
611
612
613 neo_pci_posting_flush(ch->ch_bd);
614}
615
616
617
618
619
620
621static void neo_flush_uart_write(struct jsm_channel *ch)
622{
623 u8 tmp = 0;
624 int i = 0;
625
626 if (!ch)
627 return;
628
629 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
630
631 for (i = 0; i < 10; i++) {
632
633
634 tmp = readb(&ch->ch_neo_uart->isr_fcr);
635 if (tmp & UART_FCR_CLEAR_XMIT) {
636 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
637 "Still flushing TX UART... i: %d\n", i);
638 udelay(10);
639 }
640 else
641 break;
642 }
643
644 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
645}
646
647
648
649
650
651
652
653static void neo_flush_uart_read(struct jsm_channel *ch)
654{
655 u8 tmp = 0;
656 int i = 0;
657
658 if (!ch)
659 return;
660
661 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
662
663 for (i = 0; i < 10; i++) {
664
665
666 tmp = readb(&ch->ch_neo_uart->isr_fcr);
667 if (tmp & 2) {
668 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
669 "Still flushing RX UART... i: %d\n", i);
670 udelay(10);
671 }
672 else
673 break;
674 }
675}
676
677
678
679
680static void neo_clear_break(struct jsm_channel *ch)
681{
682 unsigned long lock_flags;
683
684 spin_lock_irqsave(&ch->ch_lock, lock_flags);
685
686
687 if (ch->ch_flags & CH_BREAK_SENDING) {
688 u8 temp = readb(&ch->ch_neo_uart->lcr);
689 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
690
691 ch->ch_flags &= ~(CH_BREAK_SENDING);
692 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
693 "clear break Finishing UART_LCR_SBC! finished: %lx\n",
694 jiffies);
695
696
697 neo_pci_posting_flush(ch->ch_bd);
698 }
699 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
700}
701
702
703
704
705static void neo_parse_isr(struct jsm_board *brd, u32 port)
706{
707 struct jsm_channel *ch;
708 u8 isr;
709 u8 cause;
710 unsigned long lock_flags;
711
712 if (!brd)
713 return;
714
715 if (port >= brd->maxports)
716 return;
717
718 ch = brd->channels[port];
719 if (!ch)
720 return;
721
722
723 while (1) {
724
725 isr = readb(&ch->ch_neo_uart->isr_fcr);
726
727
728 if (isr & UART_IIR_NO_INT)
729 break;
730
731
732
733
734 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
735
736 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
737 __FILE__, __LINE__, isr);
738
739 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
740
741 neo_copy_data_from_uart_to_queue(ch);
742
743
744 spin_lock_irqsave(&ch->ch_lock, lock_flags);
745 jsm_check_queue_flow_control(ch);
746 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
747 }
748
749 if (isr & UART_IIR_THRI) {
750
751 spin_lock_irqsave(&ch->ch_lock, lock_flags);
752 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
753 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
754 neo_copy_data_from_queue_to_uart(ch);
755 }
756
757 if (isr & UART_17158_IIR_XONXOFF) {
758 cause = readb(&ch->ch_neo_uart->xoffchar1);
759
760 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
761 "Port %d. Got ISR_XONXOFF: cause:%x\n",
762 port, cause);
763
764
765
766
767
768
769 spin_lock_irqsave(&ch->ch_lock, lock_flags);
770 if (cause == UART_17158_XON_DETECT) {
771
772 if (brd->channels[port]->ch_flags & CH_STOP) {
773 ch->ch_flags &= ~(CH_STOP);
774 }
775 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
776 "Port %d. XON detected in incoming data\n",
777 port);
778 }
779 else if (cause == UART_17158_XOFF_DETECT) {
780 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
781 ch->ch_flags |= CH_STOP;
782 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
783 "Setting CH_STOP\n");
784 }
785 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
786 "Port: %d. XOFF detected in incoming data\n",
787 port);
788 }
789 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
790 }
791
792 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
793
794
795
796
797 cause = readb(&ch->ch_neo_uart->mcr);
798
799
800 spin_lock_irqsave(&ch->ch_lock, lock_flags);
801 if ((cause & 0x4) == 0) {
802 if (cause & UART_MCR_RTS)
803 ch->ch_mostat |= UART_MCR_RTS;
804 else
805 ch->ch_mostat &= ~(UART_MCR_RTS);
806 } else {
807 if (cause & UART_MCR_DTR)
808 ch->ch_mostat |= UART_MCR_DTR;
809 else
810 ch->ch_mostat &= ~(UART_MCR_DTR);
811 }
812 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
813 }
814
815
816 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
817 "MOD_STAT: sending to parse_modem_sigs\n");
818 spin_lock_irqsave(&ch->uart_port.lock, lock_flags);
819 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
820 spin_unlock_irqrestore(&ch->uart_port.lock, lock_flags);
821 }
822}
823
824static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
825{
826 struct jsm_channel *ch;
827 int linestatus;
828 unsigned long lock_flags;
829
830 if (!brd)
831 return;
832
833 if (port >= brd->maxports)
834 return;
835
836 ch = brd->channels[port];
837 if (!ch)
838 return;
839
840 linestatus = readb(&ch->ch_neo_uart->lsr);
841
842 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
843 __FILE__, __LINE__, port, linestatus);
844
845 ch->ch_cached_lsr |= linestatus;
846
847 if (ch->ch_cached_lsr & UART_LSR_DR) {
848
849 neo_copy_data_from_uart_to_queue(ch);
850 spin_lock_irqsave(&ch->ch_lock, lock_flags);
851 jsm_check_queue_flow_control(ch);
852 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
853 }
854
855
856
857
858
859
860
861 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
862 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
863 "%s:%d Port: %d Got an RX error, need to parse LSR\n",
864 __FILE__, __LINE__, port);
865
866
867
868
869
870
871 if (linestatus & UART_LSR_PE) {
872 ch->ch_err_parity++;
873 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
874 __FILE__, __LINE__, port);
875 }
876
877 if (linestatus & UART_LSR_FE) {
878 ch->ch_err_frame++;
879 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
880 __FILE__, __LINE__, port);
881 }
882
883 if (linestatus & UART_LSR_BI) {
884 ch->ch_err_break++;
885 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
886 "%s:%d Port: %d. BRK INTR!\n",
887 __FILE__, __LINE__, port);
888 }
889
890 if (linestatus & UART_LSR_OE) {
891
892
893
894
895
896
897 ch->ch_err_overrun++;
898 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
899 "%s:%d Port: %d. Rx Overrun!\n",
900 __FILE__, __LINE__, port);
901 }
902
903 if (linestatus & UART_LSR_THRE) {
904 spin_lock_irqsave(&ch->ch_lock, lock_flags);
905 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
906 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
907
908
909 neo_copy_data_from_queue_to_uart(ch);
910 }
911 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
912 spin_lock_irqsave(&ch->ch_lock, lock_flags);
913 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
914 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
915
916
917 neo_copy_data_from_queue_to_uart(ch);
918 }
919}
920
921
922
923
924
925static void neo_param(struct jsm_channel *ch)
926{
927 u8 lcr = 0;
928 u8 uart_lcr, ier;
929 u32 baud;
930 int quot;
931 struct jsm_board *bd;
932
933 bd = ch->ch_bd;
934 if (!bd)
935 return;
936
937
938
939
940 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
941 ch->ch_r_head = ch->ch_r_tail = 0;
942 ch->ch_e_head = ch->ch_e_tail = 0;
943
944 neo_flush_uart_write(ch);
945 neo_flush_uart_read(ch);
946
947 ch->ch_flags |= (CH_BAUD0);
948 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
949 neo_assert_modem_signals(ch);
950 return;
951
952 } else {
953 int i;
954 unsigned int cflag;
955 static struct {
956 unsigned int rate;
957 unsigned int cflag;
958 } baud_rates[] = {
959 { 921600, B921600 },
960 { 460800, B460800 },
961 { 230400, B230400 },
962 { 115200, B115200 },
963 { 57600, B57600 },
964 { 38400, B38400 },
965 { 19200, B19200 },
966 { 9600, B9600 },
967 { 4800, B4800 },
968 { 2400, B2400 },
969 { 1200, B1200 },
970 { 600, B600 },
971 { 300, B300 },
972 { 200, B200 },
973 { 150, B150 },
974 { 134, B134 },
975 { 110, B110 },
976 { 75, B75 },
977 { 50, B50 },
978 };
979
980 cflag = C_BAUD(ch->uart_port.state->port.tty);
981 baud = 9600;
982 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
983 if (baud_rates[i].cflag == cflag) {
984 baud = baud_rates[i].rate;
985 break;
986 }
987 }
988
989 if (ch->ch_flags & CH_BAUD0)
990 ch->ch_flags &= ~(CH_BAUD0);
991 }
992
993 if (ch->ch_c_cflag & PARENB)
994 lcr |= UART_LCR_PARITY;
995
996 if (!(ch->ch_c_cflag & PARODD))
997 lcr |= UART_LCR_EPAR;
998
999
1000
1001
1002
1003#ifdef CMSPAR
1004 if (ch->ch_c_cflag & CMSPAR)
1005 lcr |= UART_LCR_SPAR;
1006#endif
1007
1008 if (ch->ch_c_cflag & CSTOPB)
1009 lcr |= UART_LCR_STOP;
1010
1011 switch (ch->ch_c_cflag & CSIZE) {
1012 case CS5:
1013 lcr |= UART_LCR_WLEN5;
1014 break;
1015 case CS6:
1016 lcr |= UART_LCR_WLEN6;
1017 break;
1018 case CS7:
1019 lcr |= UART_LCR_WLEN7;
1020 break;
1021 case CS8:
1022 default:
1023 lcr |= UART_LCR_WLEN8;
1024 break;
1025 }
1026
1027 ier = readb(&ch->ch_neo_uart->ier);
1028 uart_lcr = readb(&ch->ch_neo_uart->lcr);
1029
1030 quot = ch->ch_bd->bd_dividend / baud;
1031
1032 if (quot != 0) {
1033 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1034 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1035 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1036 writeb(lcr, &ch->ch_neo_uart->lcr);
1037 }
1038
1039 if (uart_lcr != lcr)
1040 writeb(lcr, &ch->ch_neo_uart->lcr);
1041
1042 if (ch->ch_c_cflag & CREAD)
1043 ier |= (UART_IER_RDI | UART_IER_RLSI);
1044
1045 ier |= (UART_IER_THRI | UART_IER_MSI);
1046
1047 writeb(ier, &ch->ch_neo_uart->ier);
1048
1049
1050 neo_set_new_start_stop_chars(ch);
1051
1052 if (ch->ch_c_cflag & CRTSCTS)
1053 neo_set_cts_flow_control(ch);
1054 else if (ch->ch_c_iflag & IXON) {
1055
1056 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1057 neo_set_no_output_flow_control(ch);
1058 else
1059 neo_set_ixon_flow_control(ch);
1060 }
1061 else
1062 neo_set_no_output_flow_control(ch);
1063
1064 if (ch->ch_c_cflag & CRTSCTS)
1065 neo_set_rts_flow_control(ch);
1066 else if (ch->ch_c_iflag & IXOFF) {
1067
1068 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1069 neo_set_no_input_flow_control(ch);
1070 else
1071 neo_set_ixoff_flow_control(ch);
1072 }
1073 else
1074 neo_set_no_input_flow_control(ch);
1075
1076
1077
1078
1079
1080 if (baud < 9600) {
1081 writeb(1, &ch->ch_neo_uart->rfifo);
1082 ch->ch_r_tlevel = 1;
1083 }
1084
1085 neo_assert_modem_signals(ch);
1086
1087
1088 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1089 return;
1090}
1091
1092
1093
1094
1095
1096
1097static irqreturn_t neo_intr(int irq, void *voidbrd)
1098{
1099 struct jsm_board *brd = voidbrd;
1100 struct jsm_channel *ch;
1101 int port = 0;
1102 int type = 0;
1103 int current_port;
1104 u32 tmp;
1105 u32 uart_poll;
1106 unsigned long lock_flags;
1107 unsigned long lock_flags2;
1108 int outofloop_count = 0;
1109
1110
1111 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1112
1113
1114
1115
1116
1117
1118 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1119
1120 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
1121 __FILE__, __LINE__, uart_poll);
1122
1123 if (!uart_poll) {
1124 jsm_dbg(INTR, &brd->pci_dev,
1125 "Kernel interrupted to me, but no pending interrupts...\n");
1126 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1127 return IRQ_NONE;
1128 }
1129
1130
1131
1132 current_port = 0;
1133
1134
1135 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1136
1137 tmp = uart_poll;
1138 outofloop_count++;
1139
1140
1141 if ((tmp & jsm_offset_table[current_port]) != 0) {
1142 port = current_port;
1143 type = tmp >> (8 + (port * 3));
1144 type &= 0x7;
1145 } else {
1146 current_port++;
1147 continue;
1148 }
1149
1150 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n",
1151 __FILE__, __LINE__, port, type);
1152
1153
1154 uart_poll &= ~(jsm_offset_table[port]);
1155
1156 if (!type) {
1157
1158 jsm_dbg(INTR, &brd->pci_dev,
1159 "Interrupt with no type! port: %d\n", port);
1160 continue;
1161 }
1162
1163
1164 switch (type) {
1165
1166 case UART_17158_RXRDY_TIMEOUT:
1167
1168
1169
1170
1171
1172
1173 if (port >= brd->nasync)
1174 continue;
1175
1176 ch = brd->channels[port];
1177 if (!ch)
1178 continue;
1179
1180 neo_copy_data_from_uart_to_queue(ch);
1181
1182
1183 spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1184 jsm_check_queue_flow_control(ch);
1185 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1186
1187 continue;
1188
1189 case UART_17158_RX_LINE_STATUS:
1190
1191
1192
1193 neo_parse_lsr(brd, port);
1194 continue;
1195
1196 case UART_17158_TXRDY:
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209 neo_parse_isr(brd, port);
1210 continue;
1211
1212 case UART_17158_MSR:
1213
1214
1215
1216 neo_parse_isr(brd, port);
1217 continue;
1218
1219 default:
1220
1221
1222
1223
1224
1225
1226 jsm_dbg(INTR, &brd->pci_dev,
1227 "%s:%d Unknown Interrupt type: %x\n",
1228 __FILE__, __LINE__, type);
1229 continue;
1230 }
1231 }
1232
1233 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1234
1235 jsm_dbg(INTR, &brd->pci_dev, "finish\n");
1236 return IRQ_HANDLED;
1237}
1238
1239
1240
1241
1242
1243
1244static void neo_disable_receiver(struct jsm_channel *ch)
1245{
1246 u8 tmp = readb(&ch->ch_neo_uart->ier);
1247 tmp &= ~(UART_IER_RDI);
1248 writeb(tmp, &ch->ch_neo_uart->ier);
1249
1250
1251 neo_pci_posting_flush(ch->ch_bd);
1252}
1253
1254
1255
1256
1257
1258
1259
1260static void neo_enable_receiver(struct jsm_channel *ch)
1261{
1262 u8 tmp = readb(&ch->ch_neo_uart->ier);
1263 tmp |= (UART_IER_RDI);
1264 writeb(tmp, &ch->ch_neo_uart->ier);
1265
1266
1267 neo_pci_posting_flush(ch->ch_bd);
1268}
1269
1270static void neo_send_start_character(struct jsm_channel *ch)
1271{
1272 if (!ch)
1273 return;
1274
1275 if (ch->ch_startc != __DISABLED_CHAR) {
1276 ch->ch_xon_sends++;
1277 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1278
1279
1280 neo_pci_posting_flush(ch->ch_bd);
1281 }
1282}
1283
1284static void neo_send_stop_character(struct jsm_channel *ch)
1285{
1286 if (!ch)
1287 return;
1288
1289 if (ch->ch_stopc != __DISABLED_CHAR) {
1290 ch->ch_xoff_sends++;
1291 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1292
1293
1294 neo_pci_posting_flush(ch->ch_bd);
1295 }
1296}
1297
1298
1299
1300
1301static void neo_uart_init(struct jsm_channel *ch)
1302{
1303 writeb(0, &ch->ch_neo_uart->ier);
1304 writeb(0, &ch->ch_neo_uart->efr);
1305 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1306
1307
1308 readb(&ch->ch_neo_uart->txrx);
1309 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1310 readb(&ch->ch_neo_uart->lsr);
1311 readb(&ch->ch_neo_uart->msr);
1312
1313 ch->ch_flags |= CH_FIFO_ENABLED;
1314
1315
1316 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1317}
1318
1319
1320
1321
1322static void neo_uart_off(struct jsm_channel *ch)
1323{
1324
1325 writeb(0, &ch->ch_neo_uart->efr);
1326
1327
1328 writeb(0, &ch->ch_neo_uart->ier);
1329}
1330
1331static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1332{
1333 u8 left = 0;
1334 u8 lsr = readb(&ch->ch_neo_uart->lsr);
1335
1336
1337 ch->ch_cached_lsr |= lsr;
1338
1339
1340 if (!(lsr & UART_LSR_TEMT))
1341 left = 1;
1342 else {
1343 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1344 left = 0;
1345 }
1346
1347 return left;
1348}
1349
1350
1351static void neo_send_break(struct jsm_channel *ch)
1352{
1353
1354
1355
1356
1357
1358
1359
1360 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1361 u8 temp = readb(&ch->ch_neo_uart->lcr);
1362 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1363 ch->ch_flags |= (CH_BREAK_SENDING);
1364
1365
1366 neo_pci_posting_flush(ch->ch_bd);
1367 }
1368}
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1379{
1380 if (!ch)
1381 return;
1382
1383 writeb(c, &ch->ch_neo_uart->txrx);
1384
1385
1386 neo_pci_posting_flush(ch->ch_bd);
1387}
1388
1389struct board_ops jsm_neo_ops = {
1390 .intr = neo_intr,
1391 .uart_init = neo_uart_init,
1392 .uart_off = neo_uart_off,
1393 .param = neo_param,
1394 .assert_modem_signals = neo_assert_modem_signals,
1395 .flush_uart_write = neo_flush_uart_write,
1396 .flush_uart_read = neo_flush_uart_read,
1397 .disable_receiver = neo_disable_receiver,
1398 .enable_receiver = neo_enable_receiver,
1399 .send_break = neo_send_break,
1400 .clear_break = neo_clear_break,
1401 .send_start_character = neo_send_start_character,
1402 .send_stop_character = neo_send_stop_character,
1403 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
1404 .get_uart_bytes_left = neo_get_uart_bytes_left,
1405 .send_immediate_char = neo_send_immediate_char
1406};
1407