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19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/console.h>
22#include <linux/serial_reg.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/serial_core.h>
31#include <linux/irq.h>
32#include <linux/pm_runtime.h>
33#include <linux/pm_wakeirq.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/gpio/consumer.h>
37#include <linux/platform_data/serial-omap.h>
38
39#define OMAP_MAX_HSUART_PORTS 10
40
41#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
42
43#define OMAP_UART_REV_42 0x0402
44#define OMAP_UART_REV_46 0x0406
45#define OMAP_UART_REV_52 0x0502
46#define OMAP_UART_REV_63 0x0603
47
48#define OMAP_UART_TX_WAKEUP_EN BIT(7)
49
50
51#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
52
53#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
54#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
55
56#define DEFAULT_CLK_SPEED 48000000
57
58
59#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
60#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
61#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
62
63
64#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
65#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
66
67
68#define OMAP_UART_MVR_SCHEME_SHIFT 30
69
70#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
71#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
72#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
73
74#define OMAP_UART_MVR_MAJ_MASK 0x700
75#define OMAP_UART_MVR_MAJ_SHIFT 8
76#define OMAP_UART_MVR_MIN_MASK 0x3f
77
78#define OMAP_UART_DMA_CH_FREE -1
79
80#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
81#define OMAP_MODE13X_SPEED 230400
82
83
84
85
86#define OMAP_UART_WER_MOD_WKUP 0x7F
87
88
89#define OMAP_UART_SW_TX 0x08
90
91
92#define OMAP_UART_SW_RX 0x02
93
94#define OMAP_UART_SW_CLR 0xF0
95
96#define OMAP_UART_TCR_TRIG 0x0F
97
98struct uart_omap_dma {
99 u8 uart_dma_tx;
100 u8 uart_dma_rx;
101 int rx_dma_channel;
102 int tx_dma_channel;
103 dma_addr_t rx_buf_dma_phys;
104 dma_addr_t tx_buf_dma_phys;
105 unsigned int uart_base;
106
107
108
109
110 unsigned char *rx_buf;
111 unsigned int prev_rx_dma_pos;
112 int tx_buf_size;
113 int tx_dma_used;
114 int rx_dma_used;
115 spinlock_t tx_lock;
116 spinlock_t rx_lock;
117
118 struct timer_list rx_timer;
119 unsigned int rx_buf_size;
120 unsigned int rx_poll_rate;
121 unsigned int rx_timeout;
122};
123
124struct uart_omap_port {
125 struct uart_port port;
126 struct uart_omap_dma uart_dma;
127 struct device *dev;
128 int wakeirq;
129
130 unsigned char ier;
131 unsigned char lcr;
132 unsigned char mcr;
133 unsigned char fcr;
134 unsigned char efr;
135 unsigned char dll;
136 unsigned char dlh;
137 unsigned char mdr1;
138 unsigned char scr;
139 unsigned char wer;
140
141 int use_dma;
142
143
144
145
146
147 unsigned int lsr_break_flag;
148 unsigned char msr_saved_flags;
149 char name[20];
150 unsigned long port_activity;
151 int context_loss_cnt;
152 u32 errata;
153 u32 features;
154
155 struct gpio_desc *rts_gpiod;
156
157 struct pm_qos_request pm_qos_request;
158 u32 latency;
159 u32 calc_latency;
160 struct work_struct qos_work;
161 bool is_suspending;
162
163 unsigned int rs485_tx_filter_count;
164};
165
166#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
167
168static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
169
170
171static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
172
173static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
174{
175 offset <<= up->port.regshift;
176 return readw(up->port.membase + offset);
177}
178
179static inline void serial_out(struct uart_omap_port *up, int offset, int value)
180{
181 offset <<= up->port.regshift;
182 writew(value, up->port.membase + offset);
183}
184
185static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
186{
187 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
189 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
190 serial_out(up, UART_FCR, 0);
191}
192
193#ifdef CONFIG_PM
194static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
195{
196 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
197
198 if (!pdata || !pdata->get_context_loss_count)
199 return -EINVAL;
200
201 return pdata->get_context_loss_count(up->dev);
202}
203
204
205static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
206{
207 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
208
209 if (!pdata || !pdata->enable_wakeup)
210 return;
211
212 pdata->enable_wakeup(up->dev, enable);
213}
214#endif
215
216
217
218
219
220static inline int calculate_baud_abs_diff(struct uart_port *port,
221 unsigned int baud, unsigned int mode)
222{
223 unsigned int n = port->uartclk / (mode * baud);
224 int abs_diff;
225
226 if (n == 0)
227 n = 1;
228
229 abs_diff = baud - (port->uartclk / (mode * n));
230 if (abs_diff < 0)
231 abs_diff = -abs_diff;
232
233 return abs_diff;
234}
235
236
237
238
239
240
241
242
243
244
245
246
247static bool
248serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
249{
250 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
251 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
252
253 return (abs_diff_13 >= abs_diff_16);
254}
255
256
257
258
259
260
261static unsigned int
262serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
263{
264 unsigned int mode;
265
266 if (!serial_omap_baud_is_mode16(port, baud))
267 mode = 13;
268 else
269 mode = 16;
270 return port->uartclk/(mode * baud);
271}
272
273static void serial_omap_enable_ms(struct uart_port *port)
274{
275 struct uart_omap_port *up = to_uart_omap_port(port);
276
277 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
278
279 up->ier |= UART_IER_MSI;
280 serial_out(up, UART_IER, up->ier);
281}
282
283static void serial_omap_stop_tx(struct uart_port *port)
284{
285 struct uart_omap_port *up = to_uart_omap_port(port);
286 int res;
287
288
289 if (port->rs485.flags & SER_RS485_ENABLED) {
290 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
291
292
293
294
295
296
297
298 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
299 serial_out(up, UART_OMAP_SCR, up->scr);
300 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
301 1 : 0;
302 if (up->rts_gpiod &&
303 gpiod_get_value(up->rts_gpiod) != res) {
304 if (port->rs485.delay_rts_after_send > 0)
305 mdelay(
306 port->rs485.delay_rts_after_send);
307 gpiod_set_value(up->rts_gpiod, res);
308 }
309 } else {
310
311
312
313
314
315
316
317
318 up->scr |= OMAP_UART_SCR_TX_EMPTY;
319 serial_out(up, UART_OMAP_SCR, up->scr);
320 return;
321 }
322 }
323
324 if (up->ier & UART_IER_THRI) {
325 up->ier &= ~UART_IER_THRI;
326 serial_out(up, UART_IER, up->ier);
327 }
328}
329
330static void serial_omap_stop_rx(struct uart_port *port)
331{
332 struct uart_omap_port *up = to_uart_omap_port(port);
333
334 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
335 up->port.read_status_mask &= ~UART_LSR_DR;
336 serial_out(up, UART_IER, up->ier);
337}
338
339static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
340{
341 struct circ_buf *xmit = &up->port.state->xmit;
342 int count;
343
344 if (up->port.x_char) {
345 serial_out(up, UART_TX, up->port.x_char);
346 up->port.icount.tx++;
347 up->port.x_char = 0;
348 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
349 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
350 up->rs485_tx_filter_count++;
351
352 return;
353 }
354 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
355 serial_omap_stop_tx(&up->port);
356 return;
357 }
358 count = up->port.fifosize / 4;
359 do {
360 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
361 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
362 up->port.icount.tx++;
363 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
364 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
365 up->rs485_tx_filter_count++;
366
367 if (uart_circ_empty(xmit))
368 break;
369 } while (--count > 0);
370
371 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
372 uart_write_wakeup(&up->port);
373
374 if (uart_circ_empty(xmit))
375 serial_omap_stop_tx(&up->port);
376}
377
378static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
379{
380 if (!(up->ier & UART_IER_THRI)) {
381 up->ier |= UART_IER_THRI;
382 serial_out(up, UART_IER, up->ier);
383 }
384}
385
386static void serial_omap_start_tx(struct uart_port *port)
387{
388 struct uart_omap_port *up = to_uart_omap_port(port);
389 int res;
390
391
392 if (port->rs485.flags & SER_RS485_ENABLED) {
393
394 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
395 serial_out(up, UART_OMAP_SCR, up->scr);
396
397
398 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
399 if (up->rts_gpiod && gpiod_get_value(up->rts_gpiod) != res) {
400 gpiod_set_value(up->rts_gpiod, res);
401 if (port->rs485.delay_rts_before_send > 0)
402 mdelay(port->rs485.delay_rts_before_send);
403 }
404 }
405
406 if ((port->rs485.flags & SER_RS485_ENABLED) &&
407 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
408 up->rs485_tx_filter_count = 0;
409
410 serial_omap_enable_ier_thri(up);
411}
412
413static void serial_omap_throttle(struct uart_port *port)
414{
415 struct uart_omap_port *up = to_uart_omap_port(port);
416 unsigned long flags;
417
418 spin_lock_irqsave(&up->port.lock, flags);
419 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
420 serial_out(up, UART_IER, up->ier);
421 spin_unlock_irqrestore(&up->port.lock, flags);
422}
423
424static void serial_omap_unthrottle(struct uart_port *port)
425{
426 struct uart_omap_port *up = to_uart_omap_port(port);
427 unsigned long flags;
428
429 spin_lock_irqsave(&up->port.lock, flags);
430 up->ier |= UART_IER_RLSI | UART_IER_RDI;
431 serial_out(up, UART_IER, up->ier);
432 spin_unlock_irqrestore(&up->port.lock, flags);
433}
434
435static unsigned int check_modem_status(struct uart_omap_port *up)
436{
437 unsigned int status;
438
439 status = serial_in(up, UART_MSR);
440 status |= up->msr_saved_flags;
441 up->msr_saved_flags = 0;
442 if ((status & UART_MSR_ANY_DELTA) == 0)
443 return status;
444
445 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
446 up->port.state != NULL) {
447 if (status & UART_MSR_TERI)
448 up->port.icount.rng++;
449 if (status & UART_MSR_DDSR)
450 up->port.icount.dsr++;
451 if (status & UART_MSR_DDCD)
452 uart_handle_dcd_change
453 (&up->port, status & UART_MSR_DCD);
454 if (status & UART_MSR_DCTS)
455 uart_handle_cts_change
456 (&up->port, status & UART_MSR_CTS);
457 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
458 }
459
460 return status;
461}
462
463static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
464{
465 unsigned int flag;
466
467
468
469
470
471 if (likely(lsr & UART_LSR_DR)) {
472 serial_in(up, UART_RX);
473 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
474 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
475 up->rs485_tx_filter_count)
476 up->rs485_tx_filter_count--;
477 }
478
479 up->port.icount.rx++;
480 flag = TTY_NORMAL;
481
482 if (lsr & UART_LSR_BI) {
483 flag = TTY_BREAK;
484 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
485 up->port.icount.brk++;
486
487
488
489
490
491
492 if (uart_handle_break(&up->port))
493 return;
494
495 }
496
497 if (lsr & UART_LSR_PE) {
498 flag = TTY_PARITY;
499 up->port.icount.parity++;
500 }
501
502 if (lsr & UART_LSR_FE) {
503 flag = TTY_FRAME;
504 up->port.icount.frame++;
505 }
506
507 if (lsr & UART_LSR_OE)
508 up->port.icount.overrun++;
509
510#ifdef CONFIG_SERIAL_OMAP_CONSOLE
511 if (up->port.line == up->port.cons->index) {
512
513 lsr |= up->lsr_break_flag;
514 }
515#endif
516 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
517}
518
519static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
520{
521 unsigned char ch = 0;
522 unsigned int flag;
523
524 if (!(lsr & UART_LSR_DR))
525 return;
526
527 ch = serial_in(up, UART_RX);
528 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
529 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
530 up->rs485_tx_filter_count) {
531 up->rs485_tx_filter_count--;
532 return;
533 }
534
535 flag = TTY_NORMAL;
536 up->port.icount.rx++;
537
538 if (uart_handle_sysrq_char(&up->port, ch))
539 return;
540
541 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
542}
543
544
545
546
547
548
549static irqreturn_t serial_omap_irq(int irq, void *dev_id)
550{
551 struct uart_omap_port *up = dev_id;
552 unsigned int iir, lsr;
553 unsigned int type;
554 irqreturn_t ret = IRQ_NONE;
555 int max_count = 256;
556
557 spin_lock(&up->port.lock);
558
559 do {
560 iir = serial_in(up, UART_IIR);
561 if (iir & UART_IIR_NO_INT)
562 break;
563
564 ret = IRQ_HANDLED;
565 lsr = serial_in(up, UART_LSR);
566
567
568 type = iir & 0x3e;
569
570 switch (type) {
571 case UART_IIR_MSI:
572 check_modem_status(up);
573 break;
574 case UART_IIR_THRI:
575 transmit_chars(up, lsr);
576 break;
577 case UART_IIR_RX_TIMEOUT:
578 case UART_IIR_RDI:
579 serial_omap_rdi(up, lsr);
580 break;
581 case UART_IIR_RLSI:
582 serial_omap_rlsi(up, lsr);
583 break;
584 case UART_IIR_CTS_RTS_DSR:
585
586 break;
587 case UART_IIR_XOFF:
588 default:
589 break;
590 }
591 } while (max_count--);
592
593 spin_unlock(&up->port.lock);
594
595 tty_flip_buffer_push(&up->port.state->port);
596
597 up->port_activity = jiffies;
598
599 return ret;
600}
601
602static unsigned int serial_omap_tx_empty(struct uart_port *port)
603{
604 struct uart_omap_port *up = to_uart_omap_port(port);
605 unsigned long flags;
606 unsigned int ret = 0;
607
608 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
609 spin_lock_irqsave(&up->port.lock, flags);
610 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
611 spin_unlock_irqrestore(&up->port.lock, flags);
612
613 return ret;
614}
615
616static unsigned int serial_omap_get_mctrl(struct uart_port *port)
617{
618 struct uart_omap_port *up = to_uart_omap_port(port);
619 unsigned int status;
620 unsigned int ret = 0;
621
622 status = check_modem_status(up);
623
624 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
625
626 if (status & UART_MSR_DCD)
627 ret |= TIOCM_CAR;
628 if (status & UART_MSR_RI)
629 ret |= TIOCM_RNG;
630 if (status & UART_MSR_DSR)
631 ret |= TIOCM_DSR;
632 if (status & UART_MSR_CTS)
633 ret |= TIOCM_CTS;
634 return ret;
635}
636
637static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
638{
639 struct uart_omap_port *up = to_uart_omap_port(port);
640 unsigned char mcr = 0, old_mcr, lcr;
641
642 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
643 if (mctrl & TIOCM_RTS)
644 mcr |= UART_MCR_RTS;
645 if (mctrl & TIOCM_DTR)
646 mcr |= UART_MCR_DTR;
647 if (mctrl & TIOCM_OUT1)
648 mcr |= UART_MCR_OUT1;
649 if (mctrl & TIOCM_OUT2)
650 mcr |= UART_MCR_OUT2;
651 if (mctrl & TIOCM_LOOP)
652 mcr |= UART_MCR_LOOP;
653
654 old_mcr = serial_in(up, UART_MCR);
655 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
656 UART_MCR_DTR | UART_MCR_RTS);
657 up->mcr = old_mcr | mcr;
658 serial_out(up, UART_MCR, up->mcr);
659
660
661 lcr = serial_in(up, UART_LCR);
662 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
663 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
664 up->efr |= UART_EFR_RTS;
665 else
666 up->efr &= ~UART_EFR_RTS;
667 serial_out(up, UART_EFR, up->efr);
668 serial_out(up, UART_LCR, lcr);
669}
670
671static void serial_omap_break_ctl(struct uart_port *port, int break_state)
672{
673 struct uart_omap_port *up = to_uart_omap_port(port);
674 unsigned long flags;
675
676 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
677 spin_lock_irqsave(&up->port.lock, flags);
678 if (break_state == -1)
679 up->lcr |= UART_LCR_SBC;
680 else
681 up->lcr &= ~UART_LCR_SBC;
682 serial_out(up, UART_LCR, up->lcr);
683 spin_unlock_irqrestore(&up->port.lock, flags);
684}
685
686static int serial_omap_startup(struct uart_port *port)
687{
688 struct uart_omap_port *up = to_uart_omap_port(port);
689 unsigned long flags;
690 int retval;
691
692
693
694
695 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
696 up->name, up);
697 if (retval)
698 return retval;
699
700
701 if (up->wakeirq) {
702 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
703 if (retval) {
704 free_irq(up->port.irq, up);
705 return retval;
706 }
707 }
708
709 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
710
711 pm_runtime_get_sync(up->dev);
712
713
714
715
716 serial_omap_clear_fifos(up);
717
718
719
720
721 (void) serial_in(up, UART_LSR);
722 if (serial_in(up, UART_LSR) & UART_LSR_DR)
723 (void) serial_in(up, UART_RX);
724 (void) serial_in(up, UART_IIR);
725 (void) serial_in(up, UART_MSR);
726
727
728
729
730 serial_out(up, UART_LCR, UART_LCR_WLEN8);
731 spin_lock_irqsave(&up->port.lock, flags);
732
733
734
735 up->port.mctrl |= TIOCM_OUT2;
736 serial_omap_set_mctrl(&up->port, up->port.mctrl);
737 spin_unlock_irqrestore(&up->port.lock, flags);
738
739 up->msr_saved_flags = 0;
740
741
742
743
744
745 up->ier = UART_IER_RLSI | UART_IER_RDI;
746 serial_out(up, UART_IER, up->ier);
747
748
749 up->wer = OMAP_UART_WER_MOD_WKUP;
750 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
751 up->wer |= OMAP_UART_TX_WAKEUP_EN;
752
753 serial_out(up, UART_OMAP_WER, up->wer);
754
755 up->port_activity = jiffies;
756 return 0;
757}
758
759static void serial_omap_shutdown(struct uart_port *port)
760{
761 struct uart_omap_port *up = to_uart_omap_port(port);
762 unsigned long flags;
763
764 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
765
766
767
768
769 up->ier = 0;
770 serial_out(up, UART_IER, 0);
771
772 spin_lock_irqsave(&up->port.lock, flags);
773 up->port.mctrl &= ~TIOCM_OUT2;
774 serial_omap_set_mctrl(&up->port, up->port.mctrl);
775 spin_unlock_irqrestore(&up->port.lock, flags);
776
777
778
779
780 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
781 serial_omap_clear_fifos(up);
782
783
784
785
786 if (serial_in(up, UART_LSR) & UART_LSR_DR)
787 (void) serial_in(up, UART_RX);
788
789 pm_runtime_put_sync(up->dev);
790 free_irq(up->port.irq, up);
791 dev_pm_clear_wake_irq(up->dev);
792}
793
794static void serial_omap_uart_qos_work(struct work_struct *work)
795{
796 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
797 qos_work);
798
799 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
800}
801
802static void
803serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
804 struct ktermios *old)
805{
806 struct uart_omap_port *up = to_uart_omap_port(port);
807 unsigned char cval = 0;
808 unsigned long flags;
809 unsigned int baud, quot;
810
811 switch (termios->c_cflag & CSIZE) {
812 case CS5:
813 cval = UART_LCR_WLEN5;
814 break;
815 case CS6:
816 cval = UART_LCR_WLEN6;
817 break;
818 case CS7:
819 cval = UART_LCR_WLEN7;
820 break;
821 default:
822 case CS8:
823 cval = UART_LCR_WLEN8;
824 break;
825 }
826
827 if (termios->c_cflag & CSTOPB)
828 cval |= UART_LCR_STOP;
829 if (termios->c_cflag & PARENB)
830 cval |= UART_LCR_PARITY;
831 if (!(termios->c_cflag & PARODD))
832 cval |= UART_LCR_EPAR;
833 if (termios->c_cflag & CMSPAR)
834 cval |= UART_LCR_SPAR;
835
836
837
838
839
840 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
841 quot = serial_omap_get_divisor(port, baud);
842
843
844 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
845 up->latency = up->calc_latency;
846 schedule_work(&up->qos_work);
847
848 up->dll = quot & 0xff;
849 up->dlh = quot >> 8;
850 up->mdr1 = UART_OMAP_MDR1_DISABLE;
851
852 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
853 UART_FCR_ENABLE_FIFO;
854
855
856
857
858
859 spin_lock_irqsave(&up->port.lock, flags);
860
861
862
863
864 uart_update_timeout(port, termios->c_cflag, baud);
865
866 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
867 if (termios->c_iflag & INPCK)
868 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
869 if (termios->c_iflag & (BRKINT | PARMRK))
870 up->port.read_status_mask |= UART_LSR_BI;
871
872
873
874
875 up->port.ignore_status_mask = 0;
876 if (termios->c_iflag & IGNPAR)
877 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
878 if (termios->c_iflag & IGNBRK) {
879 up->port.ignore_status_mask |= UART_LSR_BI;
880
881
882
883
884 if (termios->c_iflag & IGNPAR)
885 up->port.ignore_status_mask |= UART_LSR_OE;
886 }
887
888
889
890
891 if ((termios->c_cflag & CREAD) == 0)
892 up->port.ignore_status_mask |= UART_LSR_DR;
893
894
895
896
897 up->ier &= ~UART_IER_MSI;
898 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
899 up->ier |= UART_IER_MSI;
900 serial_out(up, UART_IER, up->ier);
901 serial_out(up, UART_LCR, cval);
902 up->lcr = cval;
903 up->scr = 0;
904
905
906
907
908
909
910
911 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
912 serial_out(up, UART_DLL, 0);
913 serial_out(up, UART_DLM, 0);
914 serial_out(up, UART_LCR, 0);
915
916 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
917
918 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
919 up->efr &= ~UART_EFR_SCD;
920 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
921
922 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
923 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
924 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
925
926
927 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
928
929
930
931
932
933
934
935
936
937
938
939
940
941 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
942 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
943 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
944 UART_FCR_ENABLE_FIFO;
945
946 serial_out(up, UART_FCR, up->fcr);
947 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
948
949 serial_out(up, UART_OMAP_SCR, up->scr);
950
951
952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
953 serial_out(up, UART_MCR, up->mcr);
954 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
955 serial_out(up, UART_EFR, up->efr);
956 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
957
958
959
960 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
961 serial_omap_mdr1_errataset(up, up->mdr1);
962 else
963 serial_out(up, UART_OMAP_MDR1, up->mdr1);
964
965 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
966 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
967
968 serial_out(up, UART_LCR, 0);
969 serial_out(up, UART_IER, 0);
970 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
971
972 serial_out(up, UART_DLL, up->dll);
973 serial_out(up, UART_DLM, up->dlh);
974
975 serial_out(up, UART_LCR, 0);
976 serial_out(up, UART_IER, up->ier);
977 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
978
979 serial_out(up, UART_EFR, up->efr);
980 serial_out(up, UART_LCR, cval);
981
982 if (!serial_omap_baud_is_mode16(port, baud))
983 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
984 else
985 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
986
987 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
988 serial_omap_mdr1_errataset(up, up->mdr1);
989 else
990 serial_out(up, UART_OMAP_MDR1, up->mdr1);
991
992
993 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
994
995
996 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
997 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
998
999
1000 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1001 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1002 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1003
1004 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1005
1006 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1007
1008 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1009
1010 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1011 up->efr |= UART_EFR_CTS;
1012 } else {
1013
1014 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1015 }
1016
1017 if (up->port.flags & UPF_SOFT_FLOW) {
1018
1019 up->efr &= OMAP_UART_SW_CLR;
1020
1021
1022
1023
1024
1025
1026 if (termios->c_iflag & IXON)
1027 up->efr |= OMAP_UART_SW_RX;
1028
1029
1030
1031
1032
1033
1034 if (termios->c_iflag & IXOFF) {
1035 up->port.status |= UPSTAT_AUTOXOFF;
1036 up->efr |= OMAP_UART_SW_TX;
1037 }
1038
1039
1040
1041
1042
1043
1044
1045 if (termios->c_iflag & IXANY)
1046 up->mcr |= UART_MCR_XONANY;
1047 else
1048 up->mcr &= ~UART_MCR_XONANY;
1049 }
1050 serial_out(up, UART_MCR, up->mcr);
1051 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1052 serial_out(up, UART_EFR, up->efr);
1053 serial_out(up, UART_LCR, up->lcr);
1054
1055 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1056
1057 spin_unlock_irqrestore(&up->port.lock, flags);
1058 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1059}
1060
1061static void
1062serial_omap_pm(struct uart_port *port, unsigned int state,
1063 unsigned int oldstate)
1064{
1065 struct uart_omap_port *up = to_uart_omap_port(port);
1066 unsigned char efr;
1067
1068 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1069
1070 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1071 efr = serial_in(up, UART_EFR);
1072 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1073 serial_out(up, UART_LCR, 0);
1074
1075 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1076 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1077 serial_out(up, UART_EFR, efr);
1078 serial_out(up, UART_LCR, 0);
1079}
1080
1081static void serial_omap_release_port(struct uart_port *port)
1082{
1083 dev_dbg(port->dev, "serial_omap_release_port+\n");
1084}
1085
1086static int serial_omap_request_port(struct uart_port *port)
1087{
1088 dev_dbg(port->dev, "serial_omap_request_port+\n");
1089 return 0;
1090}
1091
1092static void serial_omap_config_port(struct uart_port *port, int flags)
1093{
1094 struct uart_omap_port *up = to_uart_omap_port(port);
1095
1096 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1097 up->port.line);
1098 up->port.type = PORT_OMAP;
1099 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1100}
1101
1102static int
1103serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1104{
1105
1106 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1107 return -EINVAL;
1108}
1109
1110static const char *
1111serial_omap_type(struct uart_port *port)
1112{
1113 struct uart_omap_port *up = to_uart_omap_port(port);
1114
1115 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1116 return up->name;
1117}
1118
1119#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1120
1121static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1122{
1123 unsigned int status, tmout = 10000;
1124
1125
1126 do {
1127 status = serial_in(up, UART_LSR);
1128
1129 if (status & UART_LSR_BI)
1130 up->lsr_break_flag = UART_LSR_BI;
1131
1132 if (--tmout == 0)
1133 break;
1134 udelay(1);
1135 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1136
1137
1138 if (up->port.flags & UPF_CONS_FLOW) {
1139 tmout = 1000000;
1140 for (tmout = 1000000; tmout; tmout--) {
1141 unsigned int msr = serial_in(up, UART_MSR);
1142
1143 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1144 if (msr & UART_MSR_CTS)
1145 break;
1146
1147 udelay(1);
1148 }
1149 }
1150}
1151
1152#ifdef CONFIG_CONSOLE_POLL
1153
1154static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1155{
1156 struct uart_omap_port *up = to_uart_omap_port(port);
1157
1158 wait_for_xmitr(up);
1159 serial_out(up, UART_TX, ch);
1160}
1161
1162static int serial_omap_poll_get_char(struct uart_port *port)
1163{
1164 struct uart_omap_port *up = to_uart_omap_port(port);
1165 unsigned int status;
1166
1167 status = serial_in(up, UART_LSR);
1168 if (!(status & UART_LSR_DR)) {
1169 status = NO_POLL_CHAR;
1170 goto out;
1171 }
1172
1173 status = serial_in(up, UART_RX);
1174
1175out:
1176 return status;
1177}
1178
1179#endif
1180
1181#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1182
1183#ifdef CONFIG_SERIAL_EARLYCON
1184static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1185{
1186 offset <<= port->regshift;
1187 return readw(port->membase + offset);
1188}
1189
1190static void omap_serial_early_out(struct uart_port *port, int offset,
1191 int value)
1192{
1193 offset <<= port->regshift;
1194 writew(value, port->membase + offset);
1195}
1196
1197static void omap_serial_early_putc(struct uart_port *port, int c)
1198{
1199 unsigned int status;
1200
1201 for (;;) {
1202 status = omap_serial_early_in(port, UART_LSR);
1203 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1204 break;
1205 cpu_relax();
1206 }
1207 omap_serial_early_out(port, UART_TX, c);
1208}
1209
1210static void early_omap_serial_write(struct console *console, const char *s,
1211 unsigned int count)
1212{
1213 struct earlycon_device *device = console->data;
1214 struct uart_port *port = &device->port;
1215
1216 uart_console_write(port, s, count, omap_serial_early_putc);
1217}
1218
1219static int __init early_omap_serial_setup(struct earlycon_device *device,
1220 const char *options)
1221{
1222 struct uart_port *port = &device->port;
1223
1224 if (!(device->port.membase || device->port.iobase))
1225 return -ENODEV;
1226
1227 port->regshift = 2;
1228 device->con->write = early_omap_serial_write;
1229 return 0;
1230}
1231
1232OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1233OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1234OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1235#endif
1236
1237static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1238
1239static struct uart_driver serial_omap_reg;
1240
1241static void serial_omap_console_putchar(struct uart_port *port, int ch)
1242{
1243 struct uart_omap_port *up = to_uart_omap_port(port);
1244
1245 wait_for_xmitr(up);
1246 serial_out(up, UART_TX, ch);
1247}
1248
1249static void
1250serial_omap_console_write(struct console *co, const char *s,
1251 unsigned int count)
1252{
1253 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1254 unsigned long flags;
1255 unsigned int ier;
1256 int locked = 1;
1257
1258 local_irq_save(flags);
1259 if (up->port.sysrq)
1260 locked = 0;
1261 else if (oops_in_progress)
1262 locked = spin_trylock(&up->port.lock);
1263 else
1264 spin_lock(&up->port.lock);
1265
1266
1267
1268
1269 ier = serial_in(up, UART_IER);
1270 serial_out(up, UART_IER, 0);
1271
1272 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1273
1274
1275
1276
1277
1278 wait_for_xmitr(up);
1279 serial_out(up, UART_IER, ier);
1280
1281
1282
1283
1284
1285
1286
1287 if (up->msr_saved_flags)
1288 check_modem_status(up);
1289
1290 if (locked)
1291 spin_unlock(&up->port.lock);
1292 local_irq_restore(flags);
1293}
1294
1295static int __init
1296serial_omap_console_setup(struct console *co, char *options)
1297{
1298 struct uart_omap_port *up;
1299 int baud = 115200;
1300 int bits = 8;
1301 int parity = 'n';
1302 int flow = 'n';
1303
1304 if (serial_omap_console_ports[co->index] == NULL)
1305 return -ENODEV;
1306 up = serial_omap_console_ports[co->index];
1307
1308 if (options)
1309 uart_parse_options(options, &baud, &parity, &bits, &flow);
1310
1311 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1312}
1313
1314static struct console serial_omap_console = {
1315 .name = OMAP_SERIAL_NAME,
1316 .write = serial_omap_console_write,
1317 .device = uart_console_device,
1318 .setup = serial_omap_console_setup,
1319 .flags = CON_PRINTBUFFER,
1320 .index = -1,
1321 .data = &serial_omap_reg,
1322};
1323
1324static void serial_omap_add_console_port(struct uart_omap_port *up)
1325{
1326 serial_omap_console_ports[up->port.line] = up;
1327}
1328
1329#define OMAP_CONSOLE (&serial_omap_console)
1330
1331#else
1332
1333#define OMAP_CONSOLE NULL
1334
1335static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1336{}
1337
1338#endif
1339
1340
1341static int
1342serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1343{
1344 struct uart_omap_port *up = to_uart_omap_port(port);
1345 unsigned int mode;
1346 int val;
1347
1348
1349 mode = up->ier;
1350 up->ier = 0;
1351 serial_out(up, UART_IER, 0);
1352
1353
1354 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1355 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1356
1357
1358 port->rs485 = *rs485;
1359
1360 if (up->rts_gpiod) {
1361
1362 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1363 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1364 val = (port->rs485.flags & val) ? 1 : 0;
1365 gpiod_set_value(up->rts_gpiod, val);
1366 }
1367
1368
1369 up->ier = mode;
1370 serial_out(up, UART_IER, up->ier);
1371
1372
1373
1374
1375 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1376 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1377 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1378 serial_out(up, UART_OMAP_SCR, up->scr);
1379 }
1380
1381 return 0;
1382}
1383
1384static const struct uart_ops serial_omap_pops = {
1385 .tx_empty = serial_omap_tx_empty,
1386 .set_mctrl = serial_omap_set_mctrl,
1387 .get_mctrl = serial_omap_get_mctrl,
1388 .stop_tx = serial_omap_stop_tx,
1389 .start_tx = serial_omap_start_tx,
1390 .throttle = serial_omap_throttle,
1391 .unthrottle = serial_omap_unthrottle,
1392 .stop_rx = serial_omap_stop_rx,
1393 .enable_ms = serial_omap_enable_ms,
1394 .break_ctl = serial_omap_break_ctl,
1395 .startup = serial_omap_startup,
1396 .shutdown = serial_omap_shutdown,
1397 .set_termios = serial_omap_set_termios,
1398 .pm = serial_omap_pm,
1399 .type = serial_omap_type,
1400 .release_port = serial_omap_release_port,
1401 .request_port = serial_omap_request_port,
1402 .config_port = serial_omap_config_port,
1403 .verify_port = serial_omap_verify_port,
1404#ifdef CONFIG_CONSOLE_POLL
1405 .poll_put_char = serial_omap_poll_put_char,
1406 .poll_get_char = serial_omap_poll_get_char,
1407#endif
1408};
1409
1410static struct uart_driver serial_omap_reg = {
1411 .owner = THIS_MODULE,
1412 .driver_name = "OMAP-SERIAL",
1413 .dev_name = OMAP_SERIAL_NAME,
1414 .nr = OMAP_MAX_HSUART_PORTS,
1415 .cons = OMAP_CONSOLE,
1416};
1417
1418#ifdef CONFIG_PM_SLEEP
1419static int serial_omap_prepare(struct device *dev)
1420{
1421 struct uart_omap_port *up = dev_get_drvdata(dev);
1422
1423 up->is_suspending = true;
1424
1425 return 0;
1426}
1427
1428static void serial_omap_complete(struct device *dev)
1429{
1430 struct uart_omap_port *up = dev_get_drvdata(dev);
1431
1432 up->is_suspending = false;
1433}
1434
1435static int serial_omap_suspend(struct device *dev)
1436{
1437 struct uart_omap_port *up = dev_get_drvdata(dev);
1438
1439 uart_suspend_port(&serial_omap_reg, &up->port);
1440 flush_work(&up->qos_work);
1441
1442 if (device_may_wakeup(dev))
1443 serial_omap_enable_wakeup(up, true);
1444 else
1445 serial_omap_enable_wakeup(up, false);
1446
1447 return 0;
1448}
1449
1450static int serial_omap_resume(struct device *dev)
1451{
1452 struct uart_omap_port *up = dev_get_drvdata(dev);
1453
1454 if (device_may_wakeup(dev))
1455 serial_omap_enable_wakeup(up, false);
1456
1457 uart_resume_port(&serial_omap_reg, &up->port);
1458
1459 return 0;
1460}
1461#else
1462#define serial_omap_prepare NULL
1463#define serial_omap_complete NULL
1464#endif
1465
1466static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1467{
1468 u32 mvr, scheme;
1469 u16 revision, major, minor;
1470
1471 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1472
1473
1474 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1475
1476 switch (scheme) {
1477 case 0:
1478
1479 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1480 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1481 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1482 break;
1483 case 1:
1484
1485
1486 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1487 OMAP_UART_MVR_MAJ_SHIFT;
1488 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1489 break;
1490 default:
1491 dev_warn(up->dev,
1492 "Unknown %s revision, defaulting to highest\n",
1493 up->name);
1494
1495 major = 0xff;
1496 minor = 0xff;
1497 }
1498
1499
1500 revision = UART_BUILD_REVISION(major, minor);
1501
1502 switch (revision) {
1503 case OMAP_UART_REV_46:
1504 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1505 UART_ERRATA_i291_DMA_FORCEIDLE);
1506 break;
1507 case OMAP_UART_REV_52:
1508 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1509 UART_ERRATA_i291_DMA_FORCEIDLE);
1510 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1511 break;
1512 case OMAP_UART_REV_63:
1513 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1514 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1515 break;
1516 default:
1517 break;
1518 }
1519}
1520
1521static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1522{
1523 struct omap_uart_port_info *omap_up_info;
1524
1525 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1526 if (!omap_up_info)
1527 return NULL;
1528
1529 of_property_read_u32(dev->of_node, "clock-frequency",
1530 &omap_up_info->uartclk);
1531
1532 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1533
1534 return omap_up_info;
1535}
1536
1537static int serial_omap_probe_rs485(struct uart_omap_port *up,
1538 struct device *dev)
1539{
1540 struct serial_rs485 *rs485conf = &up->port.rs485;
1541 struct device_node *np = dev->of_node;
1542 enum gpiod_flags gflags;
1543 int ret;
1544
1545 rs485conf->flags = 0;
1546 up->rts_gpiod = NULL;
1547
1548 if (!np)
1549 return 0;
1550
1551 ret = uart_get_rs485_mode(&up->port);
1552 if (ret)
1553 return ret;
1554
1555 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1556 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1557 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1558 } else {
1559 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1560 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1561 }
1562
1563
1564 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1565 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1566 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1567 if (IS_ERR(up->rts_gpiod)) {
1568 ret = PTR_ERR(up->rts_gpiod);
1569 if (ret == -EPROBE_DEFER)
1570 return ret;
1571
1572
1573
1574
1575 up->rts_gpiod = NULL;
1576 } else {
1577 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1578 }
1579
1580 return 0;
1581}
1582
1583static int serial_omap_probe(struct platform_device *pdev)
1584{
1585 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1586 struct uart_omap_port *up;
1587 struct resource *mem;
1588 void __iomem *base;
1589 int uartirq = 0;
1590 int wakeirq = 0;
1591 int ret;
1592
1593
1594 if (pdev->dev.of_node) {
1595 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1596 if (!uartirq)
1597 return -EPROBE_DEFER;
1598 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1599 omap_up_info = of_get_uart_port_info(&pdev->dev);
1600 pdev->dev.platform_data = omap_up_info;
1601 } else {
1602 uartirq = platform_get_irq(pdev, 0);
1603 if (uartirq < 0)
1604 return -EPROBE_DEFER;
1605 }
1606
1607 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1608 if (!up)
1609 return -ENOMEM;
1610
1611 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1612 base = devm_ioremap_resource(&pdev->dev, mem);
1613 if (IS_ERR(base))
1614 return PTR_ERR(base);
1615
1616 up->dev = &pdev->dev;
1617 up->port.dev = &pdev->dev;
1618 up->port.type = PORT_OMAP;
1619 up->port.iotype = UPIO_MEM;
1620 up->port.irq = uartirq;
1621 up->port.regshift = 2;
1622 up->port.fifosize = 64;
1623 up->port.ops = &serial_omap_pops;
1624 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1625
1626 if (pdev->dev.of_node)
1627 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1628 else
1629 ret = pdev->id;
1630
1631 if (ret < 0) {
1632 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1633 ret);
1634 goto err_port_line;
1635 }
1636 up->port.line = ret;
1637
1638 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1639 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1640 OMAP_MAX_HSUART_PORTS);
1641 ret = -ENXIO;
1642 goto err_port_line;
1643 }
1644
1645 up->wakeirq = wakeirq;
1646 if (!up->wakeirq)
1647 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1648 up->port.line);
1649
1650 ret = serial_omap_probe_rs485(up, &pdev->dev);
1651 if (ret < 0)
1652 goto err_rs485;
1653
1654 sprintf(up->name, "OMAP UART%d", up->port.line);
1655 up->port.mapbase = mem->start;
1656 up->port.membase = base;
1657 up->port.flags = omap_up_info->flags;
1658 up->port.uartclk = omap_up_info->uartclk;
1659 up->port.rs485_config = serial_omap_config_rs485;
1660 if (!up->port.uartclk) {
1661 up->port.uartclk = DEFAULT_CLK_SPEED;
1662 dev_warn(&pdev->dev,
1663 "No clock speed specified: using default: %d\n",
1664 DEFAULT_CLK_SPEED);
1665 }
1666
1667 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1668 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1669 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1670 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1671
1672 platform_set_drvdata(pdev, up);
1673 if (omap_up_info->autosuspend_timeout == 0)
1674 omap_up_info->autosuspend_timeout = -1;
1675
1676 device_init_wakeup(up->dev, true);
1677
1678 pm_runtime_enable(&pdev->dev);
1679
1680 pm_runtime_get_sync(&pdev->dev);
1681
1682 omap_serial_fill_features_erratas(up);
1683
1684 ui[up->port.line] = up;
1685 serial_omap_add_console_port(up);
1686
1687 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1688 if (ret != 0)
1689 goto err_add_port;
1690
1691 return 0;
1692
1693err_add_port:
1694 pm_runtime_put_sync(&pdev->dev);
1695 pm_runtime_disable(&pdev->dev);
1696 cpu_latency_qos_remove_request(&up->pm_qos_request);
1697 device_init_wakeup(up->dev, false);
1698err_rs485:
1699err_port_line:
1700 return ret;
1701}
1702
1703static int serial_omap_remove(struct platform_device *dev)
1704{
1705 struct uart_omap_port *up = platform_get_drvdata(dev);
1706
1707 pm_runtime_get_sync(up->dev);
1708
1709 uart_remove_one_port(&serial_omap_reg, &up->port);
1710
1711 pm_runtime_put_sync(up->dev);
1712 pm_runtime_disable(up->dev);
1713 cpu_latency_qos_remove_request(&up->pm_qos_request);
1714 device_init_wakeup(&dev->dev, false);
1715
1716 return 0;
1717}
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1729{
1730 u8 timeout = 255;
1731
1732 serial_out(up, UART_OMAP_MDR1, mdr1);
1733 udelay(2);
1734 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1735 UART_FCR_CLEAR_RCVR);
1736
1737
1738
1739
1740 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1741 (UART_LSR_THRE | UART_LSR_DR))) {
1742 timeout--;
1743 if (!timeout) {
1744
1745 dev_crit(up->dev, "Errata i202: timedout %x\n",
1746 serial_in(up, UART_LSR));
1747 break;
1748 }
1749 udelay(1);
1750 }
1751}
1752
1753#ifdef CONFIG_PM
1754static void serial_omap_restore_context(struct uart_omap_port *up)
1755{
1756 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1757 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1758 else
1759 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1760
1761 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1762 serial_out(up, UART_EFR, UART_EFR_ECB);
1763 serial_out(up, UART_LCR, 0x0);
1764 serial_out(up, UART_IER, 0x0);
1765 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1766 serial_out(up, UART_DLL, up->dll);
1767 serial_out(up, UART_DLM, up->dlh);
1768 serial_out(up, UART_LCR, 0x0);
1769 serial_out(up, UART_IER, up->ier);
1770 serial_out(up, UART_FCR, up->fcr);
1771 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1772 serial_out(up, UART_MCR, up->mcr);
1773 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1774 serial_out(up, UART_OMAP_SCR, up->scr);
1775 serial_out(up, UART_EFR, up->efr);
1776 serial_out(up, UART_LCR, up->lcr);
1777 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1778 serial_omap_mdr1_errataset(up, up->mdr1);
1779 else
1780 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1781 serial_out(up, UART_OMAP_WER, up->wer);
1782}
1783
1784static int serial_omap_runtime_suspend(struct device *dev)
1785{
1786 struct uart_omap_port *up = dev_get_drvdata(dev);
1787
1788 if (!up)
1789 return -EINVAL;
1790
1791
1792
1793
1794
1795
1796
1797 if (up->is_suspending && !console_suspend_enabled &&
1798 uart_console(&up->port))
1799 return -EBUSY;
1800
1801 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1802
1803 serial_omap_enable_wakeup(up, true);
1804
1805 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1806 schedule_work(&up->qos_work);
1807
1808 return 0;
1809}
1810
1811static int serial_omap_runtime_resume(struct device *dev)
1812{
1813 struct uart_omap_port *up = dev_get_drvdata(dev);
1814
1815 int loss_cnt = serial_omap_get_context_loss_count(up);
1816
1817 serial_omap_enable_wakeup(up, false);
1818
1819 if (loss_cnt < 0) {
1820 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1821 loss_cnt);
1822 serial_omap_restore_context(up);
1823 } else if (up->context_loss_cnt != loss_cnt) {
1824 serial_omap_restore_context(up);
1825 }
1826 up->latency = up->calc_latency;
1827 schedule_work(&up->qos_work);
1828
1829 return 0;
1830}
1831#endif
1832
1833static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1834 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1835 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1836 serial_omap_runtime_resume, NULL)
1837 .prepare = serial_omap_prepare,
1838 .complete = serial_omap_complete,
1839};
1840
1841#if defined(CONFIG_OF)
1842static const struct of_device_id omap_serial_of_match[] = {
1843 { .compatible = "ti,omap2-uart" },
1844 { .compatible = "ti,omap3-uart" },
1845 { .compatible = "ti,omap4-uart" },
1846 {},
1847};
1848MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1849#endif
1850
1851static struct platform_driver serial_omap_driver = {
1852 .probe = serial_omap_probe,
1853 .remove = serial_omap_remove,
1854 .driver = {
1855 .name = OMAP_SERIAL_DRIVER_NAME,
1856 .pm = &serial_omap_dev_pm_ops,
1857 .of_match_table = of_match_ptr(omap_serial_of_match),
1858 },
1859};
1860
1861static int __init serial_omap_init(void)
1862{
1863 int ret;
1864
1865 ret = uart_register_driver(&serial_omap_reg);
1866 if (ret != 0)
1867 return ret;
1868 ret = platform_driver_register(&serial_omap_driver);
1869 if (ret != 0)
1870 uart_unregister_driver(&serial_omap_reg);
1871 return ret;
1872}
1873
1874static void __exit serial_omap_exit(void)
1875{
1876 platform_driver_unregister(&serial_omap_driver);
1877 uart_unregister_driver(&serial_omap_reg);
1878}
1879
1880module_init(serial_omap_init);
1881module_exit(serial_omap_exit);
1882
1883MODULE_DESCRIPTION("OMAP High Speed UART driver");
1884MODULE_LICENSE("GPL");
1885MODULE_AUTHOR("Texas Instruments Inc");
1886