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16#include <linux/bitops.h>
17#include <linux/compiler.h>
18#include <linux/completion.h>
19#include <linux/console.h>
20#include <linux/delay.h>
21#include <linux/firmware.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/kernel.h>
27#include <linux/log2.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/slab.h>
33#include <linux/sysrq.h>
34#include <linux/tty.h>
35#include <linux/tty_flip.h>
36#include <linux/types.h>
37
38#define DRV_NAME "rp2"
39
40#define RP2_FW_NAME "rp2.fw"
41#define RP2_UCODE_BYTES 0x3f
42
43#define PORTS_PER_ASIC 16
44#define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
45
46#define UART_CLOCK 44236800
47#define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
48#define FIFO_SIZE 512
49
50
51#define RP2_FPGA_CTL0 0x110
52#define RP2_FPGA_CTL1 0x11c
53#define RP2_IRQ_MASK 0x1ec
54#define RP2_IRQ_MASK_EN_m BIT(0)
55#define RP2_IRQ_STATUS 0x1f0
56
57
58#define RP2_ASIC_SPACING 0x1000
59#define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
60
61#define RP2_PORT_BASE 0x000
62#define RP2_PORT_SPACING 0x040
63
64#define RP2_UCODE_BASE 0x400
65#define RP2_UCODE_SPACING 0x80
66
67#define RP2_CLK_PRESCALER 0xc00
68#define RP2_CH_IRQ_STAT 0xc04
69#define RP2_CH_IRQ_MASK 0xc08
70#define RP2_ASIC_IRQ 0xd00
71#define RP2_ASIC_IRQ_EN_m BIT(20)
72#define RP2_GLOBAL_CMD 0xd0c
73#define RP2_ASIC_CFG 0xd04
74
75
76#define RP2_DATA_DWORD 0x000
77
78#define RP2_DATA_BYTE 0x008
79#define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
80#define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
81#define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
82#define RP2_DATA_BYTE_BREAK_m BIT(11)
83
84
85#define RP2_DUMMY_READ BIT(16)
86
87#define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
88 RP2_DATA_BYTE_ERR_OVERRUN_m | \
89 RP2_DATA_BYTE_ERR_FRAMING_m | \
90 RP2_DATA_BYTE_BREAK_m)
91
92#define RP2_RX_FIFO_COUNT 0x00c
93#define RP2_TX_FIFO_COUNT 0x00e
94
95#define RP2_CHAN_STAT 0x010
96#define RP2_CHAN_STAT_RXDATA_m BIT(0)
97#define RP2_CHAN_STAT_DCD_m BIT(3)
98#define RP2_CHAN_STAT_DSR_m BIT(4)
99#define RP2_CHAN_STAT_CTS_m BIT(5)
100#define RP2_CHAN_STAT_RI_m BIT(6)
101#define RP2_CHAN_STAT_OVERRUN_m BIT(13)
102#define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
103#define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
104#define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
105#define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
106#define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
107
108#define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
109 RP2_CHAN_STAT_CTS_CHANGED_m | \
110 RP2_CHAN_STAT_CD_CHANGED_m | \
111 RP2_CHAN_STAT_RI_CHANGED_m)
112
113#define RP2_TXRX_CTL 0x014
114#define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
115#define RP2_TXRX_CTL_RXIRQ_m BIT(2)
116#define RP2_TXRX_CTL_RX_TRIG_s 3
117#define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
118#define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
119#define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
120#define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
121#define RP2_TXRX_CTL_RX_EN_m BIT(5)
122#define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
123#define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
124#define RP2_TXRX_CTL_TX_TRIG_s 16
125#define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
126#define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
127#define RP2_TXRX_CTL_TXIRQ_m BIT(19)
128#define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
129#define RP2_TXRX_CTL_TX_EN_m BIT(24)
130#define RP2_TXRX_CTL_RTS_m BIT(25)
131#define RP2_TXRX_CTL_DTR_m BIT(26)
132#define RP2_TXRX_CTL_LOOP_m BIT(27)
133#define RP2_TXRX_CTL_BREAK_m BIT(28)
134#define RP2_TXRX_CTL_CMSPAR_m BIT(29)
135#define RP2_TXRX_CTL_nPARODD_m BIT(30)
136#define RP2_TXRX_CTL_PARENB_m BIT(31)
137
138#define RP2_UART_CTL 0x018
139#define RP2_UART_CTL_MODE_s 0
140#define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
141#define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
142#define RP2_UART_CTL_FLUSH_RX_m BIT(3)
143#define RP2_UART_CTL_FLUSH_TX_m BIT(4)
144#define RP2_UART_CTL_RESET_CH_m BIT(5)
145#define RP2_UART_CTL_XMIT_EN_m BIT(6)
146#define RP2_UART_CTL_DATABITS_s 8
147#define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
148#define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
149#define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
150#define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
151#define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
152#define RP2_UART_CTL_STOPBITS_m BIT(10)
153
154#define RP2_BAUD 0x01c
155
156
157#define RP2_TX_SWFLOW 0x02
158#define RP2_TX_SWFLOW_ena 0x81
159#define RP2_TX_SWFLOW_dis 0x9d
160
161#define RP2_RX_SWFLOW 0x0c
162#define RP2_RX_SWFLOW_ena 0x81
163#define RP2_RX_SWFLOW_dis 0x8d
164
165#define RP2_RX_FIFO 0x37
166#define RP2_RX_FIFO_ena 0x08
167#define RP2_RX_FIFO_dis 0x81
168
169static struct uart_driver rp2_uart_driver = {
170 .owner = THIS_MODULE,
171 .driver_name = DRV_NAME,
172 .dev_name = "ttyRP",
173 .nr = CONFIG_SERIAL_RP2_NR_UARTS,
174};
175
176struct rp2_card;
177
178struct rp2_uart_port {
179 struct uart_port port;
180 int idx;
181 int ignore_rx;
182 struct rp2_card *card;
183 void __iomem *asic_base;
184 void __iomem *base;
185 void __iomem *ucode;
186};
187
188struct rp2_card {
189 struct pci_dev *pdev;
190 struct rp2_uart_port *ports;
191 int n_ports;
192 int initialized_ports;
193 int minor_start;
194 int smpte;
195 void __iomem *bar0;
196 void __iomem *bar1;
197 spinlock_t card_lock;
198};
199
200#define RP_ID(prod) PCI_VDEVICE(RP, (prod))
201#define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
202
203static inline void rp2_decode_cap(const struct pci_device_id *id,
204 int *ports, int *smpte)
205{
206 *ports = id->driver_data >> 8;
207 *smpte = id->driver_data & 0xff;
208}
209
210static DEFINE_SPINLOCK(rp2_minor_lock);
211static int rp2_minor_next;
212
213static int rp2_alloc_ports(int n_ports)
214{
215 int ret = -ENOSPC;
216
217 spin_lock(&rp2_minor_lock);
218 if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
219
220 ret = rp2_minor_next;
221 rp2_minor_next += n_ports;
222 }
223 spin_unlock(&rp2_minor_lock);
224
225 return ret;
226}
227
228static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
229{
230 return container_of(port, struct rp2_uart_port, port);
231}
232
233static void rp2_rmw(struct rp2_uart_port *up, int reg,
234 u32 clr_bits, u32 set_bits)
235{
236 u32 tmp = readl(up->base + reg);
237 tmp &= ~clr_bits;
238 tmp |= set_bits;
239 writel(tmp, up->base + reg);
240}
241
242static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
243{
244 rp2_rmw(up, reg, val, 0);
245}
246
247static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
248{
249 rp2_rmw(up, reg, 0, val);
250}
251
252static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
253 int is_enabled)
254{
255 unsigned long flags, irq_mask;
256
257 spin_lock_irqsave(&up->card->card_lock, flags);
258
259 irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
260 if (is_enabled)
261 irq_mask &= ~BIT(ch_num);
262 else
263 irq_mask |= BIT(ch_num);
264 writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
265
266 spin_unlock_irqrestore(&up->card->card_lock, flags);
267}
268
269static unsigned int rp2_uart_tx_empty(struct uart_port *port)
270{
271 struct rp2_uart_port *up = port_to_up(port);
272 unsigned long tx_fifo_bytes, flags;
273
274
275
276
277
278
279 spin_lock_irqsave(&up->port.lock, flags);
280 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
281 spin_unlock_irqrestore(&up->port.lock, flags);
282
283 return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
284}
285
286static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
287{
288 struct rp2_uart_port *up = port_to_up(port);
289 u32 status;
290
291 status = readl(up->base + RP2_CHAN_STAT);
292 return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
293 ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
294 ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
295 ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
296}
297
298static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
299{
300 rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
301 RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
302 ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
303 ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
304 ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
305}
306
307static void rp2_uart_start_tx(struct uart_port *port)
308{
309 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
310}
311
312static void rp2_uart_stop_tx(struct uart_port *port)
313{
314 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
315}
316
317static void rp2_uart_stop_rx(struct uart_port *port)
318{
319 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
320}
321
322static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
323{
324 unsigned long flags;
325
326 spin_lock_irqsave(&port->lock, flags);
327 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
328 break_state ? RP2_TXRX_CTL_BREAK_m : 0);
329 spin_unlock_irqrestore(&port->lock, flags);
330}
331
332static void rp2_uart_enable_ms(struct uart_port *port)
333{
334 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
335}
336
337static void __rp2_uart_set_termios(struct rp2_uart_port *up,
338 unsigned long cfl,
339 unsigned long ifl,
340 unsigned int baud_div)
341{
342
343 writew(baud_div - 1, up->base + RP2_BAUD);
344
345
346 rp2_rmw(up, RP2_UART_CTL,
347 RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
348 ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
349 (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
350 (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
351 (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
352 (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
353
354
355 rp2_rmw(up, RP2_TXRX_CTL,
356 RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
357 RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
358 RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
359 RP2_TXRX_CTL_CTSFLOW_m,
360 ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
361 ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
362 ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
363 ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
364 RP2_TXRX_CTL_CTSFLOW_m) : 0));
365
366
367 writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
368 up->ucode + RP2_TX_SWFLOW);
369 writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
370 up->ucode + RP2_RX_SWFLOW);
371}
372
373static void rp2_uart_set_termios(struct uart_port *port,
374 struct ktermios *new,
375 struct ktermios *old)
376{
377 struct rp2_uart_port *up = port_to_up(port);
378 unsigned long flags;
379 unsigned int baud, baud_div;
380
381 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
382 baud_div = uart_get_divisor(port, baud);
383
384 if (tty_termios_baud_rate(new))
385 tty_termios_encode_baud_rate(new, baud, baud);
386
387 spin_lock_irqsave(&port->lock, flags);
388
389
390 port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
391
392 __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
393 uart_update_timeout(port, new->c_cflag, baud);
394
395 spin_unlock_irqrestore(&port->lock, flags);
396}
397
398static void rp2_rx_chars(struct rp2_uart_port *up)
399{
400 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
401 struct tty_port *port = &up->port.state->port;
402
403 for (; bytes != 0; bytes--) {
404 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
405 char ch = byte & 0xff;
406
407 if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
408 if (!uart_handle_sysrq_char(&up->port, ch))
409 uart_insert_char(&up->port, byte, 0, ch,
410 TTY_NORMAL);
411 } else {
412 char flag = TTY_NORMAL;
413
414 if (byte & RP2_DATA_BYTE_BREAK_m)
415 flag = TTY_BREAK;
416 else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
417 flag = TTY_FRAME;
418 else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
419 flag = TTY_PARITY;
420 uart_insert_char(&up->port, byte,
421 RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
422 }
423 up->port.icount.rx++;
424 }
425
426 tty_flip_buffer_push(port);
427}
428
429static void rp2_tx_chars(struct rp2_uart_port *up)
430{
431 u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);
432 struct circ_buf *xmit = &up->port.state->xmit;
433
434 if (uart_tx_stopped(&up->port)) {
435 rp2_uart_stop_tx(&up->port);
436 return;
437 }
438
439 for (; max_tx != 0; max_tx--) {
440 if (up->port.x_char) {
441 writeb(up->port.x_char, up->base + RP2_DATA_BYTE);
442 up->port.x_char = 0;
443 up->port.icount.tx++;
444 continue;
445 }
446 if (uart_circ_empty(xmit)) {
447 rp2_uart_stop_tx(&up->port);
448 break;
449 }
450 writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);
451 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
452 up->port.icount.tx++;
453 }
454
455 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456 uart_write_wakeup(&up->port);
457}
458
459static void rp2_ch_interrupt(struct rp2_uart_port *up)
460{
461 u32 status;
462
463 spin_lock(&up->port.lock);
464
465
466
467
468
469 status = readl(up->base + RP2_CHAN_STAT);
470 writel(status, up->base + RP2_CHAN_STAT);
471
472 if (status & RP2_CHAN_STAT_RXDATA_m)
473 rp2_rx_chars(up);
474 if (status & RP2_CHAN_STAT_TXEMPTY_m)
475 rp2_tx_chars(up);
476 if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
477 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
478
479 spin_unlock(&up->port.lock);
480}
481
482static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
483{
484 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
485 int ch, handled = 0;
486 unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
487 ~readl(base + RP2_CH_IRQ_MASK);
488
489 for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
490 rp2_ch_interrupt(&card->ports[ch]);
491 handled++;
492 }
493 return handled;
494}
495
496static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
497{
498 struct rp2_card *card = dev_id;
499 int handled;
500
501 handled = rp2_asic_interrupt(card, 0);
502 if (card->n_ports >= PORTS_PER_ASIC)
503 handled += rp2_asic_interrupt(card, 1);
504
505 return handled ? IRQ_HANDLED : IRQ_NONE;
506}
507
508static inline void rp2_flush_fifos(struct rp2_uart_port *up)
509{
510 rp2_rmw_set(up, RP2_UART_CTL,
511 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
512 readl(up->base + RP2_UART_CTL);
513 udelay(10);
514 rp2_rmw_clr(up, RP2_UART_CTL,
515 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
516}
517
518static int rp2_uart_startup(struct uart_port *port)
519{
520 struct rp2_uart_port *up = port_to_up(port);
521
522 rp2_flush_fifos(up);
523 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
524 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
525 RP2_TXRX_CTL_RX_TRIG_1);
526 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
527 rp2_mask_ch_irq(up, up->idx, 1);
528
529 return 0;
530}
531
532static void rp2_uart_shutdown(struct uart_port *port)
533{
534 struct rp2_uart_port *up = port_to_up(port);
535 unsigned long flags;
536
537 rp2_uart_break_ctl(port, 0);
538
539 spin_lock_irqsave(&port->lock, flags);
540 rp2_mask_ch_irq(up, up->idx, 0);
541 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
542 spin_unlock_irqrestore(&port->lock, flags);
543}
544
545static const char *rp2_uart_type(struct uart_port *port)
546{
547 return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
548}
549
550static void rp2_uart_release_port(struct uart_port *port)
551{
552
553}
554
555static int rp2_uart_request_port(struct uart_port *port)
556{
557
558 return 0;
559}
560
561static void rp2_uart_config_port(struct uart_port *port, int flags)
562{
563 if (flags & UART_CONFIG_TYPE)
564 port->type = PORT_RP2;
565}
566
567static int rp2_uart_verify_port(struct uart_port *port,
568 struct serial_struct *ser)
569{
570 if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
571 return -EINVAL;
572
573 return 0;
574}
575
576static const struct uart_ops rp2_uart_ops = {
577 .tx_empty = rp2_uart_tx_empty,
578 .set_mctrl = rp2_uart_set_mctrl,
579 .get_mctrl = rp2_uart_get_mctrl,
580 .stop_tx = rp2_uart_stop_tx,
581 .start_tx = rp2_uart_start_tx,
582 .stop_rx = rp2_uart_stop_rx,
583 .enable_ms = rp2_uart_enable_ms,
584 .break_ctl = rp2_uart_break_ctl,
585 .startup = rp2_uart_startup,
586 .shutdown = rp2_uart_shutdown,
587 .set_termios = rp2_uart_set_termios,
588 .type = rp2_uart_type,
589 .release_port = rp2_uart_release_port,
590 .request_port = rp2_uart_request_port,
591 .config_port = rp2_uart_config_port,
592 .verify_port = rp2_uart_verify_port,
593};
594
595static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
596{
597 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
598 u32 clk_cfg;
599
600 writew(1, base + RP2_GLOBAL_CMD);
601 readw(base + RP2_GLOBAL_CMD);
602 msleep(100);
603 writel(0, base + RP2_CLK_PRESCALER);
604
605
606 clk_cfg = readw(base + RP2_ASIC_CFG);
607 clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
608 writew(clk_cfg, base + RP2_ASIC_CFG);
609
610
611 writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
612 writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
613}
614
615static void rp2_init_card(struct rp2_card *card)
616{
617 writel(4, card->bar0 + RP2_FPGA_CTL0);
618 writel(0, card->bar0 + RP2_FPGA_CTL1);
619
620 rp2_reset_asic(card, 0);
621 if (card->n_ports >= PORTS_PER_ASIC)
622 rp2_reset_asic(card, 1);
623
624 writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
625}
626
627static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
628{
629 int i;
630
631 writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
632 readl(up->base + RP2_UART_CTL);
633 udelay(1);
634
635 writel(0, up->base + RP2_TXRX_CTL);
636 writel(0, up->base + RP2_UART_CTL);
637 readl(up->base + RP2_UART_CTL);
638 udelay(1);
639
640 rp2_flush_fifos(up);
641
642 for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
643 writeb(fw->data[i], up->ucode + i);
644
645 __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
646 rp2_uart_set_mctrl(&up->port, 0);
647
648 writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
649 rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
650 RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
651 rp2_rmw_set(up, RP2_TXRX_CTL,
652 RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
653}
654
655static void rp2_remove_ports(struct rp2_card *card)
656{
657 int i;
658
659 for (i = 0; i < card->initialized_ports; i++)
660 uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
661 card->initialized_ports = 0;
662}
663
664static int rp2_load_firmware(struct rp2_card *card, const struct firmware *fw)
665{
666 resource_size_t phys_base;
667 int i, rc = 0;
668
669 phys_base = pci_resource_start(card->pdev, 1);
670
671 for (i = 0; i < card->n_ports; i++) {
672 struct rp2_uart_port *rp = &card->ports[i];
673 struct uart_port *p;
674 int j = (unsigned)i % PORTS_PER_ASIC;
675
676 rp->asic_base = card->bar1;
677 rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
678 rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
679 rp->card = card;
680 rp->idx = j;
681
682 p = &rp->port;
683 p->line = card->minor_start + i;
684 p->dev = &card->pdev->dev;
685 p->type = PORT_RP2;
686 p->iotype = UPIO_MEM32;
687 p->uartclk = UART_CLOCK;
688 p->regshift = 2;
689 p->fifosize = FIFO_SIZE;
690 p->ops = &rp2_uart_ops;
691 p->irq = card->pdev->irq;
692 p->membase = rp->base;
693 p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
694
695 if (i >= PORTS_PER_ASIC) {
696 rp->asic_base += RP2_ASIC_SPACING;
697 rp->base += RP2_ASIC_SPACING;
698 rp->ucode += RP2_ASIC_SPACING;
699 p->mapbase += RP2_ASIC_SPACING;
700 }
701
702 rp2_init_port(rp, fw);
703 rc = uart_add_one_port(&rp2_uart_driver, p);
704 if (rc) {
705 dev_err(&card->pdev->dev,
706 "error registering port %d: %d\n", i, rc);
707 rp2_remove_ports(card);
708 break;
709 }
710 card->initialized_ports++;
711 }
712
713 return rc;
714}
715
716static int rp2_probe(struct pci_dev *pdev,
717 const struct pci_device_id *id)
718{
719 const struct firmware *fw;
720 struct rp2_card *card;
721 struct rp2_uart_port *ports;
722 void __iomem * const *bars;
723 int rc;
724
725 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
726 if (!card)
727 return -ENOMEM;
728 pci_set_drvdata(pdev, card);
729 spin_lock_init(&card->card_lock);
730
731 rc = pcim_enable_device(pdev);
732 if (rc)
733 return rc;
734
735 rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
736 if (rc)
737 return rc;
738
739 bars = pcim_iomap_table(pdev);
740 card->bar0 = bars[0];
741 card->bar1 = bars[1];
742 card->pdev = pdev;
743
744 rp2_decode_cap(id, &card->n_ports, &card->smpte);
745 dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
746
747 card->minor_start = rp2_alloc_ports(card->n_ports);
748 if (card->minor_start < 0) {
749 dev_err(&pdev->dev,
750 "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
751 return -EINVAL;
752 }
753
754 rp2_init_card(card);
755
756 ports = devm_kcalloc(&pdev->dev, card->n_ports, sizeof(*ports),
757 GFP_KERNEL);
758 if (!ports)
759 return -ENOMEM;
760 card->ports = ports;
761
762 rc = request_firmware(&fw, RP2_FW_NAME, &pdev->dev);
763 if (rc < 0) {
764 dev_err(&pdev->dev, "cannot find '%s' firmware image\n",
765 RP2_FW_NAME);
766 return rc;
767 }
768
769 rc = rp2_load_firmware(card, fw);
770
771 release_firmware(fw);
772 if (rc < 0)
773 return rc;
774
775 rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
776 IRQF_SHARED, DRV_NAME, card);
777 if (rc)
778 return rc;
779
780 return 0;
781}
782
783static void rp2_remove(struct pci_dev *pdev)
784{
785 struct rp2_card *card = pci_get_drvdata(pdev);
786
787 rp2_remove_ports(card);
788}
789
790static const struct pci_device_id rp2_pci_tbl[] = {
791
792
793
794 { RP_ID(0x0040), RP_CAP(8, 0) },
795 { RP_ID(0x0041), RP_CAP(32, 0) },
796 { RP_ID(0x0042), RP_CAP(8, 0) },
797 { RP_ID(0x0043), RP_CAP(16, 0) },
798 { RP_ID(0x0044), RP_CAP(4, 0) },
799 { RP_ID(0x0045), RP_CAP(8, 0) },
800 { RP_ID(0x0046), RP_CAP(4, 0) },
801 { RP_ID(0x0047), RP_CAP(4, 0) },
802 { RP_ID(0x004a), RP_CAP(4, 0) },
803 { RP_ID(0x004b), RP_CAP(8, 0) },
804 { RP_ID(0x004c), RP_CAP(8, 0) },
805 { RP_ID(0x004d), RP_CAP(4, 0) },
806 { RP_ID(0x004e), RP_CAP(2, 0) },
807 { RP_ID(0x004f), RP_CAP(2, 1) },
808 { RP_ID(0x0050), RP_CAP(4, 0) },
809 { RP_ID(0x0051), RP_CAP(8, 0) },
810 { RP_ID(0x0052), RP_CAP(8, 1) },
811
812
813
814 { RP_ID(0x0060), RP_CAP(8, 0) },
815 { RP_ID(0x0061), RP_CAP(32, 0) },
816 { RP_ID(0x0062), RP_CAP(8, 0) },
817 { RP_ID(0x0063), RP_CAP(16, 0) },
818 { RP_ID(0x0064), RP_CAP(4, 0) },
819 { RP_ID(0x0065), RP_CAP(8, 0) },
820 { RP_ID(0x0066), RP_CAP(4, 0) },
821 { RP_ID(0x0067), RP_CAP(4, 0) },
822 { RP_ID(0x0068), RP_CAP(8, 0) },
823 { RP_ID(0x0072), RP_CAP(8, 1) },
824 { }
825};
826MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
827
828static struct pci_driver rp2_pci_driver = {
829 .name = DRV_NAME,
830 .id_table = rp2_pci_tbl,
831 .probe = rp2_probe,
832 .remove = rp2_remove,
833};
834
835static int __init rp2_uart_init(void)
836{
837 int rc;
838
839 rc = uart_register_driver(&rp2_uart_driver);
840 if (rc)
841 return rc;
842
843 rc = pci_register_driver(&rp2_pci_driver);
844 if (rc) {
845 uart_unregister_driver(&rp2_uart_driver);
846 return rc;
847 }
848
849 return 0;
850}
851
852static void __exit rp2_uart_exit(void)
853{
854 pci_unregister_driver(&rp2_pci_driver);
855 uart_unregister_driver(&rp2_uart_driver);
856}
857
858module_init(rp2_uart_init);
859module_exit(rp2_uart_exit);
860
861MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
862MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
863MODULE_LICENSE("GPL v2");
864MODULE_FIRMWARE(RP2_FW_NAME);
865
