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12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/dma-direction.h>
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_platform.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27#include <linux/pm_wakeirq.h>
28#include <linux/serial_core.h>
29#include <linux/serial.h>
30#include <linux/spinlock.h>
31#include <linux/sysrq.h>
32#include <linux/tty_flip.h>
33#include <linux/tty.h>
34
35#include "serial_mctrl_gpio.h"
36#include "stm32-usart.h"
37
38static void stm32_usart_stop_tx(struct uart_port *port);
39static void stm32_usart_transmit_chars(struct uart_port *port);
40
41static inline struct stm32_port *to_stm32_port(struct uart_port *port)
42{
43 return container_of(port, struct stm32_port, port);
44}
45
46static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
47{
48 u32 val;
49
50 val = readl_relaxed(port->membase + reg);
51 val |= bits;
52 writel_relaxed(val, port->membase + reg);
53}
54
55static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
56{
57 u32 val;
58
59 val = readl_relaxed(port->membase + reg);
60 val &= ~bits;
61 writel_relaxed(val, port->membase + reg);
62}
63
64static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
65 u32 delay_DDE, u32 baud)
66{
67 u32 rs485_deat_dedt;
68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
69 bool over8;
70
71 *cr3 |= USART_CR3_DEM;
72 over8 = *cr1 & USART_CR1_OVER8;
73
74 if (over8)
75 rs485_deat_dedt = delay_ADE * baud * 8;
76 else
77 rs485_deat_dedt = delay_ADE * baud * 16;
78
79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
81 rs485_deat_dedt_max : rs485_deat_dedt;
82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
83 USART_CR1_DEAT_MASK;
84 *cr1 |= rs485_deat_dedt;
85
86 if (over8)
87 rs485_deat_dedt = delay_DDE * baud * 8;
88 else
89 rs485_deat_dedt = delay_DDE * baud * 16;
90
91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
93 rs485_deat_dedt_max : rs485_deat_dedt;
94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
95 USART_CR1_DEDT_MASK;
96 *cr1 |= rs485_deat_dedt;
97}
98
99static int stm32_usart_config_rs485(struct uart_port *port,
100 struct serial_rs485 *rs485conf)
101{
102 struct stm32_port *stm32_port = to_stm32_port(port);
103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
105 u32 usartdiv, baud, cr1, cr3;
106 bool over8;
107
108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
109
110 port->rs485 = *rs485conf;
111
112 rs485conf->flags |= SER_RS485_RX_DURING_TX;
113
114 if (rs485conf->flags & SER_RS485_ENABLED) {
115 cr1 = readl_relaxed(port->membase + ofs->cr1);
116 cr3 = readl_relaxed(port->membase + ofs->cr3);
117 usartdiv = readl_relaxed(port->membase + ofs->brr);
118 usartdiv = usartdiv & GENMASK(15, 0);
119 over8 = cr1 & USART_CR1_OVER8;
120
121 if (over8)
122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
123 << USART_BRR_04_R_SHIFT;
124
125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
126 stm32_usart_config_reg_rs485(&cr1, &cr3,
127 rs485conf->delay_rts_before_send,
128 rs485conf->delay_rts_after_send,
129 baud);
130
131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
132 cr3 &= ~USART_CR3_DEP;
133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
134 } else {
135 cr3 |= USART_CR3_DEP;
136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
137 }
138
139 writel_relaxed(cr3, port->membase + ofs->cr3);
140 writel_relaxed(cr1, port->membase + ofs->cr1);
141 } else {
142 stm32_usart_clr_bits(port, ofs->cr3,
143 USART_CR3_DEM | USART_CR3_DEP);
144 stm32_usart_clr_bits(port, ofs->cr1,
145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
146 }
147
148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
149
150 return 0;
151}
152
153static int stm32_usart_init_rs485(struct uart_port *port,
154 struct platform_device *pdev)
155{
156 struct serial_rs485 *rs485conf = &port->rs485;
157
158 rs485conf->flags = 0;
159 rs485conf->delay_rts_before_send = 0;
160 rs485conf->delay_rts_after_send = 0;
161
162 if (!pdev->dev.of_node)
163 return -ENODEV;
164
165 return uart_get_rs485_mode(port);
166}
167
168static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr,
169 int *last_res, bool threaded)
170{
171 struct stm32_port *stm32_port = to_stm32_port(port);
172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
173 enum dma_status status;
174 struct dma_tx_state state;
175
176 *sr = readl_relaxed(port->membase + ofs->isr);
177
178 if (threaded && stm32_port->rx_ch) {
179 status = dmaengine_tx_status(stm32_port->rx_ch,
180 stm32_port->rx_ch->cookie,
181 &state);
182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue))
183 return 1;
184 else
185 return 0;
186 } else if (*sr & USART_SR_RXNE) {
187 return 1;
188 }
189 return 0;
190}
191
192static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr,
193 int *last_res)
194{
195 struct stm32_port *stm32_port = to_stm32_port(port);
196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
197 unsigned long c;
198
199 if (stm32_port->rx_ch) {
200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
201 if ((*last_res) == 0)
202 *last_res = RX_BUF_L;
203 } else {
204 c = readl_relaxed(port->membase + ofs->rdr);
205
206 c &= stm32_port->rdr_mask;
207 }
208
209 return c;
210}
211
212static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
213{
214 struct tty_port *tport = &port->state->port;
215 struct stm32_port *stm32_port = to_stm32_port(port);
216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
217 unsigned long c;
218 u32 sr;
219 char flag;
220
221 spin_lock(&port->lock);
222
223 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
224 threaded)) {
225 sr |= USART_SR_DUMMY_RX;
226 flag = TTY_NORMAL;
227
228
229
230
231
232
233
234
235
236
237
238
239 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
240 writel_relaxed(sr & USART_SR_ERR_MASK,
241 port->membase + ofs->icr);
242
243 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res);
244 port->icount.rx++;
245 if (sr & USART_SR_ERR_MASK) {
246 if (sr & USART_SR_ORE) {
247 port->icount.overrun++;
248 } else if (sr & USART_SR_PE) {
249 port->icount.parity++;
250 } else if (sr & USART_SR_FE) {
251
252 if (!c) {
253 port->icount.brk++;
254 if (uart_handle_break(port))
255 continue;
256 } else {
257 port->icount.frame++;
258 }
259 }
260
261 sr &= port->read_status_mask;
262
263 if (sr & USART_SR_PE) {
264 flag = TTY_PARITY;
265 } else if (sr & USART_SR_FE) {
266 if (!c)
267 flag = TTY_BREAK;
268 else
269 flag = TTY_FRAME;
270 }
271 }
272
273 if (uart_prepare_sysrq_char(port, c))
274 continue;
275 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
276 }
277
278 uart_unlock_and_check_sysrq(port);
279
280 tty_flip_buffer_push(tport);
281}
282
283static void stm32_usart_tx_dma_complete(void *arg)
284{
285 struct uart_port *port = arg;
286 struct stm32_port *stm32port = to_stm32_port(port);
287 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
288 unsigned long flags;
289
290 dmaengine_terminate_async(stm32port->tx_ch);
291 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
292 stm32port->tx_dma_busy = false;
293
294
295 spin_lock_irqsave(&port->lock, flags);
296 stm32_usart_transmit_chars(port);
297 spin_unlock_irqrestore(&port->lock, flags);
298}
299
300static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
301{
302 struct stm32_port *stm32_port = to_stm32_port(port);
303 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
304
305
306
307
308
309 if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
310 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
311 else
312 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
313}
314
315static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
316{
317 struct stm32_port *stm32_port = to_stm32_port(port);
318 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
319
320 if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
321 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
322 else
323 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
324}
325
326static void stm32_usart_transmit_chars_pio(struct uart_port *port)
327{
328 struct stm32_port *stm32_port = to_stm32_port(port);
329 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
330 struct circ_buf *xmit = &port->state->xmit;
331
332 if (stm32_port->tx_dma_busy) {
333 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
334 stm32_port->tx_dma_busy = false;
335 }
336
337 while (!uart_circ_empty(xmit)) {
338
339 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
340 break;
341 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
342 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
343 port->icount.tx++;
344 }
345
346
347 if (uart_circ_empty(xmit))
348 stm32_usart_tx_interrupt_disable(port);
349 else
350 stm32_usart_tx_interrupt_enable(port);
351}
352
353static void stm32_usart_transmit_chars_dma(struct uart_port *port)
354{
355 struct stm32_port *stm32port = to_stm32_port(port);
356 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
357 struct circ_buf *xmit = &port->state->xmit;
358 struct dma_async_tx_descriptor *desc = NULL;
359 unsigned int count, i;
360
361 if (stm32port->tx_dma_busy)
362 return;
363
364 stm32port->tx_dma_busy = true;
365
366 count = uart_circ_chars_pending(xmit);
367
368 if (count > TX_BUF_L)
369 count = TX_BUF_L;
370
371 if (xmit->tail < xmit->head) {
372 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
373 } else {
374 size_t one = UART_XMIT_SIZE - xmit->tail;
375 size_t two;
376
377 if (one > count)
378 one = count;
379 two = count - one;
380
381 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
382 if (two)
383 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
384 }
385
386 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
387 stm32port->tx_dma_buf,
388 count,
389 DMA_MEM_TO_DEV,
390 DMA_PREP_INTERRUPT);
391
392 if (!desc)
393 goto fallback_err;
394
395 desc->callback = stm32_usart_tx_dma_complete;
396 desc->callback_param = port;
397
398
399 if (dma_submit_error(dmaengine_submit(desc))) {
400
401 dmaengine_terminate_async(stm32port->tx_ch);
402 goto fallback_err;
403 }
404
405
406 dma_async_issue_pending(stm32port->tx_ch);
407
408 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
409
410 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
411 port->icount.tx += count;
412 return;
413
414fallback_err:
415 for (i = count; i > 0; i--)
416 stm32_usart_transmit_chars_pio(port);
417}
418
419static void stm32_usart_transmit_chars(struct uart_port *port)
420{
421 struct stm32_port *stm32_port = to_stm32_port(port);
422 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
423 struct circ_buf *xmit = &port->state->xmit;
424
425 if (port->x_char) {
426 if (stm32_port->tx_dma_busy)
427 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
428 writel_relaxed(port->x_char, port->membase + ofs->tdr);
429 port->x_char = 0;
430 port->icount.tx++;
431 if (stm32_port->tx_dma_busy)
432 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
433 return;
434 }
435
436 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
437 stm32_usart_tx_interrupt_disable(port);
438 return;
439 }
440
441 if (ofs->icr == UNDEF_REG)
442 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
443 else
444 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
445
446 if (stm32_port->tx_ch)
447 stm32_usart_transmit_chars_dma(port);
448 else
449 stm32_usart_transmit_chars_pio(port);
450
451 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
452 uart_write_wakeup(port);
453
454 if (uart_circ_empty(xmit))
455 stm32_usart_tx_interrupt_disable(port);
456}
457
458static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
459{
460 struct uart_port *port = ptr;
461 struct tty_port *tport = &port->state->port;
462 struct stm32_port *stm32_port = to_stm32_port(port);
463 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
464 u32 sr;
465
466 sr = readl_relaxed(port->membase + ofs->isr);
467
468 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
469 writel_relaxed(USART_ICR_RTOCF,
470 port->membase + ofs->icr);
471
472 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
473
474 writel_relaxed(USART_ICR_WUCF,
475 port->membase + ofs->icr);
476 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
477 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
478 pm_wakeup_event(tport->tty->dev, 0);
479 }
480
481 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
482 stm32_usart_receive_chars(port, false);
483
484 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
485 spin_lock(&port->lock);
486 stm32_usart_transmit_chars(port);
487 spin_unlock(&port->lock);
488 }
489
490 if (stm32_port->rx_ch)
491 return IRQ_WAKE_THREAD;
492 else
493 return IRQ_HANDLED;
494}
495
496static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
497{
498 struct uart_port *port = ptr;
499 struct stm32_port *stm32_port = to_stm32_port(port);
500
501 if (stm32_port->rx_ch)
502 stm32_usart_receive_chars(port, true);
503
504 return IRQ_HANDLED;
505}
506
507static unsigned int stm32_usart_tx_empty(struct uart_port *port)
508{
509 struct stm32_port *stm32_port = to_stm32_port(port);
510 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
511
512 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
513 return TIOCSER_TEMT;
514
515 return 0;
516}
517
518static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
519{
520 struct stm32_port *stm32_port = to_stm32_port(port);
521 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
522
523 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
524 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
525 else
526 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
527
528 mctrl_gpio_set(stm32_port->gpios, mctrl);
529}
530
531static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
532{
533 struct stm32_port *stm32_port = to_stm32_port(port);
534 unsigned int ret;
535
536
537 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
538
539 return mctrl_gpio_get(stm32_port->gpios, &ret);
540}
541
542static void stm32_usart_enable_ms(struct uart_port *port)
543{
544 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
545}
546
547static void stm32_usart_disable_ms(struct uart_port *port)
548{
549 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
550}
551
552
553static void stm32_usart_stop_tx(struct uart_port *port)
554{
555 struct stm32_port *stm32_port = to_stm32_port(port);
556 struct serial_rs485 *rs485conf = &port->rs485;
557
558 stm32_usart_tx_interrupt_disable(port);
559
560 if (rs485conf->flags & SER_RS485_ENABLED) {
561 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
562 mctrl_gpio_set(stm32_port->gpios,
563 stm32_port->port.mctrl & ~TIOCM_RTS);
564 } else {
565 mctrl_gpio_set(stm32_port->gpios,
566 stm32_port->port.mctrl | TIOCM_RTS);
567 }
568 }
569}
570
571
572static void stm32_usart_start_tx(struct uart_port *port)
573{
574 struct stm32_port *stm32_port = to_stm32_port(port);
575 struct serial_rs485 *rs485conf = &port->rs485;
576 struct circ_buf *xmit = &port->state->xmit;
577
578 if (uart_circ_empty(xmit))
579 return;
580
581 if (rs485conf->flags & SER_RS485_ENABLED) {
582 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
583 mctrl_gpio_set(stm32_port->gpios,
584 stm32_port->port.mctrl | TIOCM_RTS);
585 } else {
586 mctrl_gpio_set(stm32_port->gpios,
587 stm32_port->port.mctrl & ~TIOCM_RTS);
588 }
589 }
590
591 stm32_usart_transmit_chars(port);
592}
593
594
595static void stm32_usart_flush_buffer(struct uart_port *port)
596{
597 struct stm32_port *stm32_port = to_stm32_port(port);
598 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
599
600 if (stm32_port->tx_ch) {
601 dmaengine_terminate_async(stm32_port->tx_ch);
602 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
603 stm32_port->tx_dma_busy = false;
604 }
605}
606
607
608static void stm32_usart_throttle(struct uart_port *port)
609{
610 struct stm32_port *stm32_port = to_stm32_port(port);
611 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
612 unsigned long flags;
613
614 spin_lock_irqsave(&port->lock, flags);
615 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
616 if (stm32_port->cr3_irq)
617 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
618
619 spin_unlock_irqrestore(&port->lock, flags);
620}
621
622
623static void stm32_usart_unthrottle(struct uart_port *port)
624{
625 struct stm32_port *stm32_port = to_stm32_port(port);
626 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
627 unsigned long flags;
628
629 spin_lock_irqsave(&port->lock, flags);
630 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
631 if (stm32_port->cr3_irq)
632 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
633
634 spin_unlock_irqrestore(&port->lock, flags);
635}
636
637
638static void stm32_usart_stop_rx(struct uart_port *port)
639{
640 struct stm32_port *stm32_port = to_stm32_port(port);
641 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
642
643 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
644 if (stm32_port->cr3_irq)
645 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
646}
647
648
649static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
650{
651}
652
653static int stm32_usart_startup(struct uart_port *port)
654{
655 struct stm32_port *stm32_port = to_stm32_port(port);
656 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
657 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
658 const char *name = to_platform_device(port->dev)->name;
659 u32 val;
660 int ret;
661
662 ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
663 stm32_usart_threaded_interrupt,
664 IRQF_ONESHOT | IRQF_NO_SUSPEND,
665 name, port);
666 if (ret)
667 return ret;
668
669 if (stm32_port->swap) {
670 val = readl_relaxed(port->membase + ofs->cr2);
671 val |= USART_CR2_SWAP;
672 writel_relaxed(val, port->membase + ofs->cr2);
673 }
674
675
676 if (ofs->rqr != UNDEF_REG)
677 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
678
679
680 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
681 stm32_usart_set_bits(port, ofs->cr1, val);
682
683 return 0;
684}
685
686static void stm32_usart_shutdown(struct uart_port *port)
687{
688 struct stm32_port *stm32_port = to_stm32_port(port);
689 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
690 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
691 u32 val, isr;
692 int ret;
693
694
695 stm32_usart_disable_ms(port);
696
697 val = USART_CR1_TXEIE | USART_CR1_TE;
698 val |= stm32_port->cr1_irq | USART_CR1_RE;
699 val |= BIT(cfg->uart_enable_bit);
700 if (stm32_port->fifoen)
701 val |= USART_CR1_FIFOEN;
702
703 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
704 isr, (isr & USART_SR_TC),
705 10, 100000);
706
707
708 if (ret)
709 dev_err(port->dev, "Transmission is not complete\n");
710
711
712 if (ofs->rqr != UNDEF_REG)
713 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
714 port->membase + ofs->rqr);
715
716 stm32_usart_clr_bits(port, ofs->cr1, val);
717
718 free_irq(port->irq, port);
719}
720
721static void stm32_usart_set_termios(struct uart_port *port,
722 struct ktermios *termios,
723 struct ktermios *old)
724{
725 struct stm32_port *stm32_port = to_stm32_port(port);
726 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
727 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
728 struct serial_rs485 *rs485conf = &port->rs485;
729 unsigned int baud, bits;
730 u32 usartdiv, mantissa, fraction, oversampling;
731 tcflag_t cflag = termios->c_cflag;
732 u32 cr1, cr2, cr3, isr;
733 unsigned long flags;
734 int ret;
735
736 if (!stm32_port->hw_flow_control)
737 cflag &= ~CRTSCTS;
738
739 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
740
741 spin_lock_irqsave(&port->lock, flags);
742
743 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
744 isr,
745 (isr & USART_SR_TC),
746 10, 100000);
747
748
749 if (ret)
750 dev_err(port->dev, "Transmission is not complete\n");
751
752
753 writel_relaxed(0, port->membase + ofs->cr1);
754
755
756 if (ofs->rqr != UNDEF_REG)
757 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
758 port->membase + ofs->rqr);
759
760 cr1 = USART_CR1_TE | USART_CR1_RE;
761 if (stm32_port->fifoen)
762 cr1 |= USART_CR1_FIFOEN;
763 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
764
765
766 cr3 = readl_relaxed(port->membase + ofs->cr3);
767 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
768 if (stm32_port->fifoen) {
769 if (stm32_port->txftcfg >= 0)
770 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT;
771 if (stm32_port->rxftcfg >= 0)
772 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT;
773 }
774
775 if (cflag & CSTOPB)
776 cr2 |= USART_CR2_STOP_2B;
777
778 bits = tty_get_char_size(cflag);
779 stm32_port->rdr_mask = (BIT(bits) - 1);
780
781 if (cflag & PARENB) {
782 bits++;
783 cr1 |= USART_CR1_PCE;
784 }
785
786
787
788
789
790
791
792
793 if (bits == 9)
794 cr1 |= USART_CR1_M0;
795 else if ((bits == 7) && cfg->has_7bits_data)
796 cr1 |= USART_CR1_M1;
797 else if (bits != 8)
798 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
799 , bits);
800
801 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
802 (stm32_port->fifoen &&
803 stm32_port->rxftcfg >= 0))) {
804 if (cflag & CSTOPB)
805 bits = bits + 3;
806 else
807 bits = bits + 2;
808
809
810 stm32_port->cr1_irq = USART_CR1_RTOIE;
811 writel_relaxed(bits, port->membase + ofs->rtor);
812 cr2 |= USART_CR2_RTOEN;
813
814 if (!stm32_port->rx_ch)
815 stm32_port->cr3_irq = USART_CR3_RXFTIE;
816 }
817
818 cr1 |= stm32_port->cr1_irq;
819 cr3 |= stm32_port->cr3_irq;
820
821 if (cflag & PARODD)
822 cr1 |= USART_CR1_PS;
823
824 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
825 if (cflag & CRTSCTS) {
826 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
827 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
828 }
829
830 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
831
832
833
834
835
836
837
838 if (usartdiv < 16) {
839 oversampling = 8;
840 cr1 |= USART_CR1_OVER8;
841 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
842 } else {
843 oversampling = 16;
844 cr1 &= ~USART_CR1_OVER8;
845 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
846 }
847
848 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
849 fraction = usartdiv % oversampling;
850 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
851
852 uart_update_timeout(port, cflag, baud);
853
854 port->read_status_mask = USART_SR_ORE;
855 if (termios->c_iflag & INPCK)
856 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
857 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
858 port->read_status_mask |= USART_SR_FE;
859
860
861 port->ignore_status_mask = 0;
862 if (termios->c_iflag & IGNPAR)
863 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
864 if (termios->c_iflag & IGNBRK) {
865 port->ignore_status_mask |= USART_SR_FE;
866
867
868
869
870 if (termios->c_iflag & IGNPAR)
871 port->ignore_status_mask |= USART_SR_ORE;
872 }
873
874
875 if ((termios->c_cflag & CREAD) == 0)
876 port->ignore_status_mask |= USART_SR_DUMMY_RX;
877
878 if (stm32_port->rx_ch)
879 cr3 |= USART_CR3_DMAR;
880
881 if (rs485conf->flags & SER_RS485_ENABLED) {
882 stm32_usart_config_reg_rs485(&cr1, &cr3,
883 rs485conf->delay_rts_before_send,
884 rs485conf->delay_rts_after_send,
885 baud);
886 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
887 cr3 &= ~USART_CR3_DEP;
888 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
889 } else {
890 cr3 |= USART_CR3_DEP;
891 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
892 }
893
894 } else {
895 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
896 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
897 }
898
899
900 if (stm32_port->wakeup_src) {
901 cr3 &= ~USART_CR3_WUS_MASK;
902 cr3 |= USART_CR3_WUS_START_BIT;
903 }
904
905 writel_relaxed(cr3, port->membase + ofs->cr3);
906 writel_relaxed(cr2, port->membase + ofs->cr2);
907 writel_relaxed(cr1, port->membase + ofs->cr1);
908
909 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
910 spin_unlock_irqrestore(&port->lock, flags);
911
912
913 if (UART_ENABLE_MS(port, termios->c_cflag))
914 stm32_usart_enable_ms(port);
915 else
916 stm32_usart_disable_ms(port);
917}
918
919static const char *stm32_usart_type(struct uart_port *port)
920{
921 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
922}
923
924static void stm32_usart_release_port(struct uart_port *port)
925{
926}
927
928static int stm32_usart_request_port(struct uart_port *port)
929{
930 return 0;
931}
932
933static void stm32_usart_config_port(struct uart_port *port, int flags)
934{
935 if (flags & UART_CONFIG_TYPE)
936 port->type = PORT_STM32;
937}
938
939static int
940stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
941{
942
943 return -EINVAL;
944}
945
946static void stm32_usart_pm(struct uart_port *port, unsigned int state,
947 unsigned int oldstate)
948{
949 struct stm32_port *stm32port = container_of(port,
950 struct stm32_port, port);
951 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
952 const struct stm32_usart_config *cfg = &stm32port->info->cfg;
953 unsigned long flags;
954
955 switch (state) {
956 case UART_PM_STATE_ON:
957 pm_runtime_get_sync(port->dev);
958 break;
959 case UART_PM_STATE_OFF:
960 spin_lock_irqsave(&port->lock, flags);
961 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
962 spin_unlock_irqrestore(&port->lock, flags);
963 pm_runtime_put_sync(port->dev);
964 break;
965 }
966}
967
968static const struct uart_ops stm32_uart_ops = {
969 .tx_empty = stm32_usart_tx_empty,
970 .set_mctrl = stm32_usart_set_mctrl,
971 .get_mctrl = stm32_usart_get_mctrl,
972 .stop_tx = stm32_usart_stop_tx,
973 .start_tx = stm32_usart_start_tx,
974 .throttle = stm32_usart_throttle,
975 .unthrottle = stm32_usart_unthrottle,
976 .stop_rx = stm32_usart_stop_rx,
977 .enable_ms = stm32_usart_enable_ms,
978 .break_ctl = stm32_usart_break_ctl,
979 .startup = stm32_usart_startup,
980 .shutdown = stm32_usart_shutdown,
981 .flush_buffer = stm32_usart_flush_buffer,
982 .set_termios = stm32_usart_set_termios,
983 .pm = stm32_usart_pm,
984 .type = stm32_usart_type,
985 .release_port = stm32_usart_release_port,
986 .request_port = stm32_usart_request_port,
987 .config_port = stm32_usart_config_port,
988 .verify_port = stm32_usart_verify_port,
989};
990
991
992
993
994
995
996
997static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 };
998
999static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p,
1000 int *ftcfg)
1001{
1002 u32 bytes, i;
1003
1004
1005 if (of_property_read_u32(pdev->dev.of_node, p, &bytes))
1006 bytes = 8;
1007
1008 for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++)
1009 if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes)
1010 break;
1011 if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg))
1012 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1;
1013
1014 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p,
1015 stm32h7_usart_fifo_thresh_cfg[i]);
1016
1017
1018 if (i)
1019 *ftcfg = i - 1;
1020 else
1021 *ftcfg = -EINVAL;
1022}
1023
1024static void stm32_usart_deinit_port(struct stm32_port *stm32port)
1025{
1026 clk_disable_unprepare(stm32port->clk);
1027}
1028
1029static int stm32_usart_init_port(struct stm32_port *stm32port,
1030 struct platform_device *pdev)
1031{
1032 struct uart_port *port = &stm32port->port;
1033 struct resource *res;
1034 int ret, irq;
1035
1036 irq = platform_get_irq(pdev, 0);
1037 if (irq < 0)
1038 return irq;
1039
1040 port->iotype = UPIO_MEM;
1041 port->flags = UPF_BOOT_AUTOCONF;
1042 port->ops = &stm32_uart_ops;
1043 port->dev = &pdev->dev;
1044 port->fifosize = stm32port->info->cfg.fifosize;
1045 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1046 port->irq = irq;
1047 port->rs485_config = stm32_usart_config_rs485;
1048
1049 ret = stm32_usart_init_rs485(port, pdev);
1050 if (ret)
1051 return ret;
1052
1053 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
1054 of_property_read_bool(pdev->dev.of_node, "wakeup-source");
1055
1056 stm32port->swap = stm32port->info->cfg.has_swap &&
1057 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
1058
1059 stm32port->fifoen = stm32port->info->cfg.has_fifo;
1060 if (stm32port->fifoen) {
1061 stm32_usart_get_ftcfg(pdev, "rx-threshold",
1062 &stm32port->rxftcfg);
1063 stm32_usart_get_ftcfg(pdev, "tx-threshold",
1064 &stm32port->txftcfg);
1065 }
1066
1067 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1068 if (IS_ERR(port->membase))
1069 return PTR_ERR(port->membase);
1070 port->mapbase = res->start;
1071
1072 spin_lock_init(&port->lock);
1073
1074 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1075 if (IS_ERR(stm32port->clk))
1076 return PTR_ERR(stm32port->clk);
1077
1078
1079 ret = clk_prepare_enable(stm32port->clk);
1080 if (ret)
1081 return ret;
1082
1083 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1084 if (!stm32port->port.uartclk) {
1085 ret = -EINVAL;
1086 goto err_clk;
1087 }
1088
1089 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1090 if (IS_ERR(stm32port->gpios)) {
1091 ret = PTR_ERR(stm32port->gpios);
1092 goto err_clk;
1093 }
1094
1095
1096
1097
1098
1099 if (stm32port->hw_flow_control) {
1100 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1101 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1102 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1103 ret = -EINVAL;
1104 goto err_clk;
1105 }
1106 }
1107
1108 return ret;
1109
1110err_clk:
1111 clk_disable_unprepare(stm32port->clk);
1112
1113 return ret;
1114}
1115
1116static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1117{
1118 struct device_node *np = pdev->dev.of_node;
1119 int id;
1120
1121 if (!np)
1122 return NULL;
1123
1124 id = of_alias_get_id(np, "serial");
1125 if (id < 0) {
1126 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1127 return NULL;
1128 }
1129
1130 if (WARN_ON(id >= STM32_MAX_PORTS))
1131 return NULL;
1132
1133 stm32_ports[id].hw_flow_control =
1134 of_property_read_bool (np, "st,hw-flow-ctrl") ||
1135 of_property_read_bool (np, "uart-has-rtscts");
1136 stm32_ports[id].port.line = id;
1137 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1138 stm32_ports[id].cr3_irq = 0;
1139 stm32_ports[id].last_res = RX_BUF_L;
1140 return &stm32_ports[id];
1141}
1142
1143#ifdef CONFIG_OF
1144static const struct of_device_id stm32_match[] = {
1145 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1146 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1147 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1148 {},
1149};
1150
1151MODULE_DEVICE_TABLE(of, stm32_match);
1152#endif
1153
1154static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port,
1155 struct platform_device *pdev)
1156{
1157 if (stm32port->rx_buf)
1158 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf,
1159 stm32port->rx_dma_buf);
1160}
1161
1162static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1163 struct platform_device *pdev)
1164{
1165 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1166 struct uart_port *port = &stm32port->port;
1167 struct device *dev = &pdev->dev;
1168 struct dma_slave_config config;
1169 struct dma_async_tx_descriptor *desc = NULL;
1170 int ret;
1171
1172
1173
1174
1175
1176 if (uart_console(port))
1177 return -ENODEV;
1178
1179 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L,
1180 &stm32port->rx_dma_buf,
1181 GFP_KERNEL);
1182 if (!stm32port->rx_buf)
1183 return -ENOMEM;
1184
1185
1186 memset(&config, 0, sizeof(config));
1187 config.src_addr = port->mapbase + ofs->rdr;
1188 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1189
1190 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1191 if (ret < 0) {
1192 dev_err(dev, "rx dma channel config failed\n");
1193 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1194 return ret;
1195 }
1196
1197
1198 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1199 stm32port->rx_dma_buf,
1200 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1201 DMA_PREP_INTERRUPT);
1202 if (!desc) {
1203 dev_err(dev, "rx dma prep cyclic failed\n");
1204 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1205 return -ENODEV;
1206 }
1207
1208
1209 desc->callback = NULL;
1210 desc->callback_param = NULL;
1211
1212
1213 ret = dma_submit_error(dmaengine_submit(desc));
1214 if (ret) {
1215 dmaengine_terminate_sync(stm32port->rx_ch);
1216 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1217 return ret;
1218 }
1219
1220
1221 dma_async_issue_pending(stm32port->rx_ch);
1222
1223 return 0;
1224}
1225
1226static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port,
1227 struct platform_device *pdev)
1228{
1229 if (stm32port->tx_buf)
1230 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf,
1231 stm32port->tx_dma_buf);
1232}
1233
1234static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1235 struct platform_device *pdev)
1236{
1237 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1238 struct uart_port *port = &stm32port->port;
1239 struct device *dev = &pdev->dev;
1240 struct dma_slave_config config;
1241 int ret;
1242
1243 stm32port->tx_dma_busy = false;
1244
1245 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
1246 &stm32port->tx_dma_buf,
1247 GFP_KERNEL);
1248 if (!stm32port->tx_buf)
1249 return -ENOMEM;
1250
1251
1252 memset(&config, 0, sizeof(config));
1253 config.dst_addr = port->mapbase + ofs->tdr;
1254 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1255
1256 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1257 if (ret < 0) {
1258 dev_err(dev, "tx dma channel config failed\n");
1259 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1260 return ret;
1261 }
1262
1263 return 0;
1264}
1265
1266static int stm32_usart_serial_probe(struct platform_device *pdev)
1267{
1268 struct stm32_port *stm32port;
1269 int ret;
1270
1271 stm32port = stm32_usart_of_get_port(pdev);
1272 if (!stm32port)
1273 return -ENODEV;
1274
1275 stm32port->info = of_device_get_match_data(&pdev->dev);
1276 if (!stm32port->info)
1277 return -EINVAL;
1278
1279 ret = stm32_usart_init_port(stm32port, pdev);
1280 if (ret)
1281 return ret;
1282
1283 if (stm32port->wakeup_src) {
1284 device_set_wakeup_capable(&pdev->dev, true);
1285 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq);
1286 if (ret)
1287 goto err_deinit_port;
1288 }
1289
1290 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx");
1291 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) {
1292 ret = -EPROBE_DEFER;
1293 goto err_wakeirq;
1294 }
1295
1296 if (IS_ERR(stm32port->rx_ch))
1297 stm32port->rx_ch = NULL;
1298
1299 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx");
1300 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) {
1301 ret = -EPROBE_DEFER;
1302 goto err_dma_rx;
1303 }
1304
1305 if (IS_ERR(stm32port->tx_ch))
1306 stm32port->tx_ch = NULL;
1307
1308 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) {
1309
1310 dma_release_channel(stm32port->rx_ch);
1311 stm32port->rx_ch = NULL;
1312 }
1313
1314 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) {
1315
1316 dma_release_channel(stm32port->tx_ch);
1317 stm32port->tx_ch = NULL;
1318 }
1319
1320 if (!stm32port->rx_ch)
1321 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n");
1322 if (!stm32port->tx_ch)
1323 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n");
1324
1325 platform_set_drvdata(pdev, &stm32port->port);
1326
1327 pm_runtime_get_noresume(&pdev->dev);
1328 pm_runtime_set_active(&pdev->dev);
1329 pm_runtime_enable(&pdev->dev);
1330
1331 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1332 if (ret)
1333 goto err_port;
1334
1335 pm_runtime_put_sync(&pdev->dev);
1336
1337 return 0;
1338
1339err_port:
1340 pm_runtime_disable(&pdev->dev);
1341 pm_runtime_set_suspended(&pdev->dev);
1342 pm_runtime_put_noidle(&pdev->dev);
1343
1344 if (stm32port->tx_ch) {
1345 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1346 dma_release_channel(stm32port->tx_ch);
1347 }
1348
1349 if (stm32port->rx_ch)
1350 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1351
1352err_dma_rx:
1353 if (stm32port->rx_ch)
1354 dma_release_channel(stm32port->rx_ch);
1355
1356err_wakeirq:
1357 if (stm32port->wakeup_src)
1358 dev_pm_clear_wake_irq(&pdev->dev);
1359
1360err_deinit_port:
1361 if (stm32port->wakeup_src)
1362 device_set_wakeup_capable(&pdev->dev, false);
1363
1364 stm32_usart_deinit_port(stm32port);
1365
1366 return ret;
1367}
1368
1369static int stm32_usart_serial_remove(struct platform_device *pdev)
1370{
1371 struct uart_port *port = platform_get_drvdata(pdev);
1372 struct stm32_port *stm32_port = to_stm32_port(port);
1373 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1374 int err;
1375
1376 pm_runtime_get_sync(&pdev->dev);
1377 err = uart_remove_one_port(&stm32_usart_driver, port);
1378 if (err)
1379 return(err);
1380
1381 pm_runtime_disable(&pdev->dev);
1382 pm_runtime_set_suspended(&pdev->dev);
1383 pm_runtime_put_noidle(&pdev->dev);
1384
1385 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1386
1387 if (stm32_port->tx_ch) {
1388 dmaengine_terminate_async(stm32_port->tx_ch);
1389 stm32_usart_of_dma_tx_remove(stm32_port, pdev);
1390 dma_release_channel(stm32_port->tx_ch);
1391 }
1392
1393 if (stm32_port->rx_ch) {
1394 dmaengine_terminate_async(stm32_port->rx_ch);
1395 stm32_usart_of_dma_rx_remove(stm32_port, pdev);
1396 dma_release_channel(stm32_port->rx_ch);
1397 }
1398
1399 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1400
1401 if (stm32_port->wakeup_src) {
1402 dev_pm_clear_wake_irq(&pdev->dev);
1403 device_init_wakeup(&pdev->dev, false);
1404 }
1405
1406 stm32_usart_deinit_port(stm32_port);
1407
1408 return 0;
1409}
1410
1411#ifdef CONFIG_SERIAL_STM32_CONSOLE
1412static void stm32_usart_console_putchar(struct uart_port *port, int ch)
1413{
1414 struct stm32_port *stm32_port = to_stm32_port(port);
1415 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1416
1417 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1418 cpu_relax();
1419
1420 writel_relaxed(ch, port->membase + ofs->tdr);
1421}
1422
1423static void stm32_usart_console_write(struct console *co, const char *s,
1424 unsigned int cnt)
1425{
1426 struct uart_port *port = &stm32_ports[co->index].port;
1427 struct stm32_port *stm32_port = to_stm32_port(port);
1428 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1429 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1430 unsigned long flags;
1431 u32 old_cr1, new_cr1;
1432 int locked = 1;
1433
1434 if (oops_in_progress)
1435 locked = spin_trylock_irqsave(&port->lock, flags);
1436 else
1437 spin_lock_irqsave(&port->lock, flags);
1438
1439
1440 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1441 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1442 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1443 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1444
1445 uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1446
1447
1448 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1449
1450 if (locked)
1451 spin_unlock_irqrestore(&port->lock, flags);
1452}
1453
1454static int stm32_usart_console_setup(struct console *co, char *options)
1455{
1456 struct stm32_port *stm32port;
1457 int baud = 9600;
1458 int bits = 8;
1459 int parity = 'n';
1460 int flow = 'n';
1461
1462 if (co->index >= STM32_MAX_PORTS)
1463 return -ENODEV;
1464
1465 stm32port = &stm32_ports[co->index];
1466
1467
1468
1469
1470
1471
1472
1473 if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1474 return -ENXIO;
1475
1476 if (options)
1477 uart_parse_options(options, &baud, &parity, &bits, &flow);
1478
1479 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1480}
1481
1482static struct console stm32_console = {
1483 .name = STM32_SERIAL_NAME,
1484 .device = uart_console_device,
1485 .write = stm32_usart_console_write,
1486 .setup = stm32_usart_console_setup,
1487 .flags = CON_PRINTBUFFER,
1488 .index = -1,
1489 .data = &stm32_usart_driver,
1490};
1491
1492#define STM32_SERIAL_CONSOLE (&stm32_console)
1493
1494#else
1495#define STM32_SERIAL_CONSOLE NULL
1496#endif
1497
1498static struct uart_driver stm32_usart_driver = {
1499 .driver_name = DRIVER_NAME,
1500 .dev_name = STM32_SERIAL_NAME,
1501 .major = 0,
1502 .minor = 0,
1503 .nr = STM32_MAX_PORTS,
1504 .cons = STM32_SERIAL_CONSOLE,
1505};
1506
1507static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1508 bool enable)
1509{
1510 struct stm32_port *stm32_port = to_stm32_port(port);
1511 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1512
1513 if (!stm32_port->wakeup_src)
1514 return;
1515
1516
1517
1518
1519
1520 if (enable) {
1521 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1522 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
1523 } else {
1524 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1525 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
1526 }
1527}
1528
1529static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
1530{
1531 struct uart_port *port = dev_get_drvdata(dev);
1532
1533 uart_suspend_port(&stm32_usart_driver, port);
1534
1535 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1536 stm32_usart_serial_en_wakeup(port, true);
1537
1538
1539
1540
1541
1542
1543
1544 if (console_suspend_enabled || !uart_console(port)) {
1545 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1546 pinctrl_pm_select_idle_state(dev);
1547 else
1548 pinctrl_pm_select_sleep_state(dev);
1549 }
1550
1551 return 0;
1552}
1553
1554static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
1555{
1556 struct uart_port *port = dev_get_drvdata(dev);
1557
1558 pinctrl_pm_select_default_state(dev);
1559
1560 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1561 stm32_usart_serial_en_wakeup(port, false);
1562
1563 return uart_resume_port(&stm32_usart_driver, port);
1564}
1565
1566static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1567{
1568 struct uart_port *port = dev_get_drvdata(dev);
1569 struct stm32_port *stm32port = container_of(port,
1570 struct stm32_port, port);
1571
1572 clk_disable_unprepare(stm32port->clk);
1573
1574 return 0;
1575}
1576
1577static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
1578{
1579 struct uart_port *port = dev_get_drvdata(dev);
1580 struct stm32_port *stm32port = container_of(port,
1581 struct stm32_port, port);
1582
1583 return clk_prepare_enable(stm32port->clk);
1584}
1585
1586static const struct dev_pm_ops stm32_serial_pm_ops = {
1587 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
1588 stm32_usart_runtime_resume, NULL)
1589 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
1590 stm32_usart_serial_resume)
1591};
1592
1593static struct platform_driver stm32_serial_driver = {
1594 .probe = stm32_usart_serial_probe,
1595 .remove = stm32_usart_serial_remove,
1596 .driver = {
1597 .name = DRIVER_NAME,
1598 .pm = &stm32_serial_pm_ops,
1599 .of_match_table = of_match_ptr(stm32_match),
1600 },
1601};
1602
1603static int __init stm32_usart_init(void)
1604{
1605 static char banner[] __initdata = "STM32 USART driver initialized";
1606 int ret;
1607
1608 pr_info("%s\n", banner);
1609
1610 ret = uart_register_driver(&stm32_usart_driver);
1611 if (ret)
1612 return ret;
1613
1614 ret = platform_driver_register(&stm32_serial_driver);
1615 if (ret)
1616 uart_unregister_driver(&stm32_usart_driver);
1617
1618 return ret;
1619}
1620
1621static void __exit stm32_usart_exit(void)
1622{
1623 platform_driver_unregister(&stm32_serial_driver);
1624 uart_unregister_driver(&stm32_usart_driver);
1625}
1626
1627module_init(stm32_usart_init);
1628module_exit(stm32_usart_exit);
1629
1630MODULE_ALIAS("platform:" DRIVER_NAME);
1631MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1632MODULE_LICENSE("GPL v2");
1633