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12#ifndef __LINUX_CDNS3_GADGET
13#define __LINUX_CDNS3_GADGET
14#include <linux/usb/gadget.h>
15#include <linux/dma-direction.h>
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71struct cdns3_usb_regs {
72 __le32 usb_conf;
73 __le32 usb_sts;
74 __le32 usb_cmd;
75 __le32 usb_itpn;
76 __le32 usb_lpm;
77 __le32 usb_ien;
78 __le32 usb_ists;
79 __le32 ep_sel;
80 __le32 ep_traddr;
81 __le32 ep_cfg;
82 __le32 ep_cmd;
83 __le32 ep_sts;
84 __le32 ep_sts_sid;
85 __le32 ep_sts_en;
86 __le32 drbl;
87 __le32 ep_ien;
88 __le32 ep_ists;
89 __le32 usb_pwr;
90 __le32 usb_conf2;
91 __le32 usb_cap1;
92 __le32 usb_cap2;
93 __le32 usb_cap3;
94 __le32 usb_cap4;
95 __le32 usb_cap5;
96 __le32 usb_cap6;
97 __le32 usb_cpkt1;
98 __le32 usb_cpkt2;
99 __le32 usb_cpkt3;
100 __le32 ep_dma_ext_addr;
101 __le32 buf_addr;
102 __le32 buf_data;
103 __le32 buf_ctrl;
104 __le32 dtrans;
105 __le32 tdl_from_trb;
106 __le32 tdl_beh;
107 __le32 ep_tdl;
108 __le32 tdl_beh2;
109 __le32 dma_adv_td;
110 __le32 reserved1[26];
111 __le32 cfg_reg1;
112 __le32 dbg_link1;
113 __le32 dbg_link2;
114 __le32 cfg_regs[74];
115 __le32 reserved2[51];
116 __le32 dma_axi_ctrl;
117 __le32 dma_axi_id;
118 __le32 dma_axi_cap;
119 __le32 dma_axi_ctrl0;
120 __le32 dma_axi_ctrl1;
121};
122
123
124
125#define USB_CONF_CFGRST BIT(0)
126
127#define USB_CONF_CFGSET BIT(1)
128
129#define USB_CONF_USB3DIS BIT(3)
130
131#define USB_CONF_USB2DIS BIT(4)
132
133#define USB_CONF_LENDIAN BIT(5)
134
135
136
137
138
139#define USB_CONF_BENDIAN BIT(6)
140
141#define USB_CONF_SWRST BIT(7)
142
143#define USB_CONF_DSING BIT(8)
144
145#define USB_CONF_DMULT BIT(9)
146
147#define USB_CONF_DMAOFFEN BIT(10)
148
149#define USB_CONF_DMAOFFDS BIT(11)
150
151#define USB_CONF_CFORCE_FS BIT(12)
152
153#define USB_CONF_SFORCE_FS BIT(13)
154
155#define USB_CONF_DEVEN BIT(14)
156
157#define USB_CONF_DEVDS BIT(15)
158
159#define USB_CONF_L1EN BIT(16)
160
161#define USB_CONF_L1DS BIT(17)
162
163#define USB_CONF_CLK2OFFEN BIT(18)
164
165#define USB_CONF_CLK2OFFDS BIT(19)
166
167#define USB_CONF_LGO_L0 BIT(20)
168
169#define USB_CONF_CLK3OFFEN BIT(21)
170
171#define USB_CONF_CLK3OFFDS BIT(22)
172
173
174#define USB_CONF_U1EN BIT(24)
175
176#define USB_CONF_U1DS BIT(25)
177
178#define USB_CONF_U2EN BIT(26)
179
180#define USB_CONF_U2DS BIT(27)
181
182#define USB_CONF_LGO_U0 BIT(28)
183
184#define USB_CONF_LGO_U1 BIT(29)
185
186#define USB_CONF_LGO_U2 BIT(30)
187
188#define USB_CONF_LGO_SSINACT BIT(31)
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195
196#define USB_STS_CFGSTS_MASK BIT(0)
197#define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK)
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202
203#define USB_STS_OV_MASK BIT(1)
204#define USB_STS_OV(p) ((p) & USB_STS_OV_MASK)
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209
210#define USB_STS_USB3CONS_MASK BIT(2)
211#define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK)
212
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217
218#define USB_STS_DTRANS_MASK BIT(3)
219#define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK)
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227
228#define USB_STS_USBSPEED_MASK GENMASK(6, 4)
229#define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4)
230#define USB_STS_LS (0x1 << 4)
231#define USB_STS_FS (0x2 << 4)
232#define USB_STS_HS (0x3 << 4)
233#define USB_STS_SS (0x4 << 4)
234#define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
235#define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
236#define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
237#define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
238#define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
239
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242
243
244#define USB_STS_ENDIAN_MASK BIT(7)
245#define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK)
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251
252#define USB_STS_CLK2OFF_MASK BIT(8)
253#define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK)
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259
260#define USB_STS_CLK3OFF_MASK BIT(9)
261#define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK)
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266
267#define USB_STS_IN_RST_MASK BIT(10)
268#define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK)
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274
275#define USB_STS_TDL_TRB_ENABLED BIT(11)
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281#define USB_STS_DEVS_MASK BIT(14)
282#define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK)
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287
288#define USB_STS_ADDRESSED_MASK BIT(15)
289#define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK)
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294
295#define USB_STS_L1ENS_MASK BIT(16)
296#define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK)
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301
302#define USB_STS_VBUSS_MASK BIT(17)
303#define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK)
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310
311#define USB_STS_LPMST_MASK GENMASK(19, 18)
312#define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
313#define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
314#define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
315#define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
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320
321#define USB_STS_USB2CONS_MASK BIT(20)
322#define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK)
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327
328#define USB_STS_DISABLE_HS_MASK BIT(21)
329#define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK)
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334
335#define USB_STS_U1ENS_MASK BIT(24)
336#define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK)
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341
342#define USB_STS_U2ENS_MASK BIT(25)
343#define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK)
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347
348#define USB_STS_LST_MASK GENMASK(29, 26)
349#define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
350#define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
351#define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
352#define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
353#define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
354#define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
355#define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
356#define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
357#define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
358#define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
359#define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
360#define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
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365
366#define USB_STS_DMAOFF_MASK BIT(30)
367#define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK)
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371
372
373#define USB_STS_ENDIAN2_MASK BIT(31)
374#define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK)
375
376
377
378#define USB_CMD_SET_ADDR BIT(0)
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385
386#define USB_CMD_FADDR_MASK GENMASK(7, 1)
387#define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
388
389#define USB_CMD_SDNFW BIT(8)
390
391#define USB_CMD_STMODE BIT(9)
392
393#define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
394#define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK)
395
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397
398
399#define USB_CMD_SDNLTM BIT(12)
400
401#define USB_CMD_SPKT BIT(13)
402
403#define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
404#define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK)
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408
409#define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
410#define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
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417
418#define USB_ITPN_MASK GENMASK(13, 0)
419#define USB_ITPN(p) ((p) & USB_ITPN_MASK)
420
421
422
423#define USB_LPM_HIRD_MASK GENMASK(3, 0)
424#define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK)
425
426#define USB_LPM_BRW BIT(4)
427
428
429
430#define USB_IEN_CONIEN BIT(0)
431
432#define USB_IEN_DISIEN BIT(1)
433
434#define USB_IEN_UWRESIEN BIT(2)
435
436#define USB_IEN_UHRESIEN BIT(3)
437
438#define USB_IEN_U3ENTIEN BIT(4)
439
440#define USB_IEN_U3EXTIEN BIT(5)
441
442#define USB_IEN_U2ENTIEN BIT(6)
443
444#define USB_IEN_U2EXTIEN BIT(7)
445
446#define USB_IEN_U1ENTIEN BIT(8)
447
448#define USB_IEN_U1EXTIEN BIT(9)
449
450#define USB_IEN_ITPIEN BIT(10)
451
452#define USB_IEN_WAKEIEN BIT(11)
453
454#define USB_IEN_SPKTIEN BIT(12)
455
456#define USB_IEN_CON2IEN BIT(16)
457
458#define USB_IEN_DIS2IEN BIT(17)
459
460#define USB_IEN_U2RESIEN BIT(18)
461
462#define USB_IEN_L2ENTIEN BIT(20)
463
464#define USB_IEN_L2EXTIEN BIT(21)
465
466#define USB_IEN_L1ENTIEN BIT(24)
467
468#define USB_IEN_L1EXTIEN BIT(25)
469
470#define USB_IEN_CFGRESIEN BIT(26)
471
472#define USB_IEN_UWRESSIEN BIT(28)
473
474#define USB_IEN_UWRESEIEN BIT(29)
475
476#define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
477 | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
478 | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
479 | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
480
481
482
483#define USB_ISTS_CONI BIT(0)
484
485#define USB_ISTS_DISI BIT(1)
486
487#define USB_ISTS_UWRESI BIT(2)
488
489#define USB_ISTS_UHRESI BIT(3)
490
491#define USB_ISTS_U3ENTI BIT(4)
492
493#define USB_ISTS_U3EXTI BIT(5)
494
495#define USB_ISTS_U2ENTI BIT(6)
496
497#define USB_ISTS_U2EXTI BIT(7)
498
499#define USB_ISTS_U1ENTI BIT(8)
500
501#define USB_ISTS_U1EXTI BIT(9)
502
503#define USB_ISTS_ITPI BIT(10)
504
505#define USB_ISTS_WAKEI BIT(11)
506
507#define USB_ISTS_SPKTI BIT(12)
508
509#define USB_ISTS_CON2I BIT(16)
510
511#define USB_ISTS_DIS2I BIT(17)
512
513#define USB_ISTS_U2RESI BIT(18)
514
515#define USB_ISTS_L2ENTI BIT(20)
516
517#define USB_ISTS_L2EXTI BIT(21)
518
519#define USB_ISTS_L1ENTI BIT(24)
520
521#define USB_ISTS_L1EXTI BIT(25)
522
523#define USB_ISTS_CFGRESI BIT(26)
524
525#define USB_ISTS_UWRESSI BIT(28)
526
527#define USB_ISTS_UWRESEI BIT(29)
528
529
530#define EP_SEL_EPNO_MASK GENMASK(3, 0)
531
532#define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK)
533
534#define EP_SEL_DIR BIT(7)
535
536#define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
537#define select_ep_out (EP_SEL_EPNO(p))
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540
541#define EP_TRADDR_TRADDR(p) ((p))
542
543
544
545#define EP_CFG_ENABLE BIT(0)
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551
552#define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
553#define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
554
555#define EP_CFG_STREAM_EN BIT(3)
556
557#define EP_CFG_TDL_CHK BIT(4)
558
559#define EP_CFG_SID_CHK BIT(5)
560
561#define EP_CFG_EPENDIAN BIT(7)
562
563#define EP_CFG_MAXBURST_MASK GENMASK(11, 8)
564#define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK)
565
566#define EP_CFG_MULT_MASK GENMASK(15, 14)
567#define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK)
568
569#define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16)
570#define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
571
572#define EP_CFG_BUFFERING_MASK GENMASK(31, 27)
573#define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK)
574
575
576
577#define EP_CMD_EPRST BIT(0)
578
579#define EP_CMD_SSTALL BIT(1)
580
581#define EP_CMD_CSTALL BIT(2)
582
583#define EP_CMD_ERDY BIT(3)
584
585#define EP_CMD_REQ_CMPL BIT(5)
586
587#define EP_CMD_DRDY BIT(6)
588
589#define EP_CMD_DFLUSH BIT(7)
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593
594
595#define EP_CMD_STDL BIT(8)
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599
600#define EP_CMD_TDL_MASK GENMASK(15, 9)
601#define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK)
602#define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9)
603#define EP_CMD_TDL_MAX (EP_CMD_TDL_MASK >> 9)
604
605
606#define EP_CMD_ERDY_SID_MASK GENMASK(31, 16)
607#define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK)
608
609
610
611#define EP_STS_SETUP BIT(0)
612
613#define EP_STS_STALL(p) ((p) & BIT(1))
614
615#define EP_STS_IOC BIT(2)
616
617#define EP_STS_ISP BIT(3)
618
619#define EP_STS_DESCMIS BIT(4)
620
621#define EP_STS_STREAMR BIT(5)
622
623#define EP_STS_MD_EXIT BIT(6)
624
625#define EP_STS_TRBERR BIT(7)
626
627#define EP_STS_NRDY BIT(8)
628
629#define EP_STS_DBUSY BIT(9)
630
631#define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
632
633#define EP_STS_CCS(p) ((p) & BIT(11))
634
635#define EP_STS_PRIME BIT(12)
636
637#define EP_STS_SIDERR BIT(13)
638
639#define EP_STS_OUTSMM BIT(14)
640
641#define EP_STS_ISOERR BIT(15)
642
643#define EP_STS_HOSTPP(p) ((p) & BIT(16))
644
645#define EP_STS_SPSMST_MASK GENMASK(18, 17)
646#define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
647#define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
648#define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
649#define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
650
651#define EP_STS_IOT BIT(19)
652
653#define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)
654#define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
655
656#define EP_STS_OUTQ_VAL_MASK BIT(28)
657#define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK)
658
659#define EP_STS_STPWAIT BIT(31)
660
661
662
663#define EP_STS_SID_MASK GENMASK(15, 0)
664#define EP_STS_SID(p) ((p) & EP_STS_SID_MASK)
665
666
667
668#define EP_STS_EN_SETUPEN BIT(0)
669
670#define EP_STS_EN_DESCMISEN BIT(4)
671
672#define EP_STS_EN_STREAMREN BIT(5)
673
674#define EP_STS_EN_MD_EXITEN BIT(6)
675
676#define EP_STS_EN_TRBERREN BIT(7)
677
678#define EP_STS_EN_NRDYEN BIT(8)
679
680#define EP_STS_EN_PRIMEEEN BIT(12)
681
682#define EP_STS_EN_SIDERREN BIT(13)
683
684#define EP_STS_EN_OUTSMMEN BIT(14)
685
686#define EP_STS_EN_ISOERREN BIT(15)
687
688#define EP_STS_EN_IOTEN BIT(19)
689
690#define EP_STS_EN_STPWAITEN BIT(31)
691
692
693#define DB_VALUE_BY_INDEX(index) (1 << (index))
694#define DB_VALUE_EP0_OUT BIT(0)
695#define DB_VALUE_EP0_IN BIT(16)
696
697
698#define EP_IEN(index) (1 << (index))
699#define EP_IEN_EP_OUT0 BIT(0)
700#define EP_IEN_EP_IN0 BIT(16)
701
702
703#define EP_ISTS(index) (1 << (index))
704#define EP_ISTS_EP_OUT0 BIT(0)
705#define EP_ISTS_EP_IN0 BIT(16)
706
707
708
709#define PUSB_PWR_PSO_EN BIT(0)
710
711#define PUSB_PWR_PSO_DS BIT(1)
712
713
714
715
716
717#define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8)
718
719
720
721
722#define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9)
723
724#define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30)
725
726#define PUSB_PWR_FST_REG_ACCESS BIT(31)
727
728
729
730
731
732
733
734#define USB_CONF2_DIS_TDL_TRB BIT(1)
735
736
737
738
739
740#define USB_CONF2_EN_TDL_TRB BIT(2)
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750
751
752#define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0)
753#define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
754#define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
755#define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
756#define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
757
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764
765
766#define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
767#define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
768#define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
769#define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
770#define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
771
772
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778
779
780#define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8)
781#define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
782#define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
783#define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
784#define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
785
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792
793
794#define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
795#define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
796#define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
797
798
799
800
801
802
803
804#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
805#define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
806#define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
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817
818#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
819#define DEV_U3PHY_WIDTH_8(p) \
820 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
821#define DEV_U3PHY_WIDTH_16(p) \
822 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
823#define DEV_U3PHY_WIDTH_32(p) \
824 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
825#define DEV_U3PHY_WIDTH_64(p) \
826 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
827
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833
834#define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24))
835
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838
839
840
841#define DEV_U2PHY_ULPI(p) ((p) & BIT(25))
842
843
844
845
846
847
848
849#define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26))
850
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853
854
855#define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
856
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859
860
861
862#define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
863
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868
869
870#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
871
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883
884
885#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
886
887
888#define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
889
890
891#define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
892
893
894#define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
895
896
897
898#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
899
900#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
901
902#define DEV_VER_NXP_V1 0x00024502
903#define DEV_VER_TI_V1 0x00024509
904#define DEV_VER_V2 0x0002450C
905#define DEV_VER_V3 0x0002450d
906
907
908
909
910
911
912#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0))
913
914
915
916
917#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)
918#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8))
919
920
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922
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925
926
927#define DBG_LINK1_RXDET_BREAK_DIS BIT(16)
928
929#define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17))
930
931
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933
934
935#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24)
936
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939
940
941#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25)
942
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944
945
946
947#define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26)
948
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950
951
952
953#define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
954
955
956
957#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
958
959#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
960#define DMA_AXI_CTRL_NON_SECURE 0x02
961
962#define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
963
964#define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
965
966
967
968
969
970#define TRBS_PER_SEGMENT 600
971
972#define ISO_MAX_INTERVAL 10
973
974#define MAX_TRB_LENGTH BIT(16)
975
976#if TRBS_PER_SEGMENT < 2
977#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
978#endif
979
980#define TRBS_PER_STREAM_SEGMENT 2
981
982#if TRBS_PER_STREAM_SEGMENT < 2
983#error "Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2."
984#endif
985
986
987
988
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991
992
993#define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8)
994
995#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
996 TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
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1004
1005struct cdns3_trb {
1006 __le32 buffer;
1007 __le32 length;
1008 __le32 control;
1009};
1010
1011#define TRB_SIZE (sizeof(struct cdns3_trb))
1012#define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT)
1013#define TRB_STREAM_RING_SIZE (TRB_SIZE * TRBS_PER_STREAM_SEGMENT)
1014#define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
1015#define TRB_CTRL_RING_SIZE (TRB_SIZE * 2)
1016
1017
1018#define TRB_TYPE_BITMASK GENMASK(15, 10)
1019#define TRB_TYPE(p) ((p) << 10)
1020#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1021
1022
1023
1024#define TRB_NORMAL 1
1025
1026#define TRB_LINK 6
1027
1028
1029#define TRB_CYCLE BIT(0)
1030
1031
1032
1033#define TRB_TOGGLE BIT(1)
1034
1035
1036
1037
1038#define TRB_SMM BIT(1)
1039
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1046
1047
1048#define TRB_SP BIT(1)
1049
1050
1051#define TRB_ISP BIT(2)
1052
1053#define TRB_FIFO_MODE BIT(3)
1054
1055#define TRB_CHAIN BIT(4)
1056
1057#define TRB_IOC BIT(5)
1058
1059
1060#define TRB_STREAM_ID_BITMASK GENMASK(31, 16)
1061#define TRB_STREAM_ID(p) ((p) << 16)
1062#define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16)
1063
1064
1065#define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16))
1066#define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16)
1067
1068
1069#define TRB_LEN(p) ((p) & GENMASK(16, 0))
1070
1071
1072#define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17))
1073#define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17)
1074
1075
1076#define TRB_BURST_LEN(p) ((unsigned int)((p) << 24) & GENMASK(31, 24))
1077#define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24)
1078
1079
1080#define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
1081
1082
1083
1084
1085
1086#define USB_DEVICE_MAX_ADDRESS 127
1087
1088
1089#define CDNS3_EP_MAX_PACKET_LIMIT 1024
1090#define CDNS3_EP_MAX_STREAMS 15
1091#define CDNS3_EP0_MAX_PACKET_LIMIT 512
1092
1093
1094#define CDNS3_ENDPOINTS_MAX_COUNT 32
1095#define CDNS3_EP_ZLP_BUF_SIZE 1024
1096
1097#define CDNS3_EP_BUF_SIZE 4
1098#define CDNS3_EP_ISO_HS_MULT 3
1099#define CDNS3_EP_ISO_SS_BURST 3
1100#define CDNS3_MAX_NUM_DESCMISS_BUF 32
1101#define CDNS3_DESCMIS_BUF_SIZE 2048
1102#define CDNS3_WA2_NUM_BUFFERS 128
1103
1104
1105
1106struct cdns3_device;
1107
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1134
1135struct cdns3_endpoint {
1136 struct usb_ep endpoint;
1137 struct list_head pending_req_list;
1138 struct list_head deferred_req_list;
1139 struct list_head wa2_descmiss_req_list;
1140 int wa2_counter;
1141
1142 struct cdns3_trb *trb_pool;
1143 dma_addr_t trb_pool_dma;
1144
1145 struct cdns3_device *cdns3_dev;
1146 char name[20];
1147
1148#define EP_ENABLED BIT(0)
1149#define EP_STALLED BIT(1)
1150#define EP_STALL_PENDING BIT(2)
1151#define EP_WEDGE BIT(3)
1152#define EP_TRANSFER_STARTED BIT(4)
1153#define EP_UPDATE_EP_TRBADDR BIT(5)
1154#define EP_PENDING_REQUEST BIT(6)
1155#define EP_RING_FULL BIT(7)
1156#define EP_CLAIMED BIT(8)
1157#define EP_DEFERRED_DRDY BIT(9)
1158#define EP_QUIRK_ISO_OUT_EN BIT(10)
1159#define EP_QUIRK_END_TRANSFER BIT(11)
1160#define EP_QUIRK_EXTRA_BUF_DET BIT(12)
1161#define EP_QUIRK_EXTRA_BUF_EN BIT(13)
1162#define EP_TDLCHK_EN BIT(15)
1163#define EP_CONFIGURED BIT(16)
1164 u32 flags;
1165
1166 struct cdns3_request *descmis_req;
1167
1168 u8 dir;
1169 u8 num;
1170 u8 type;
1171 int interval;
1172
1173 int free_trbs;
1174 int num_trbs;
1175 int alloc_ring_size;
1176 u8 pcs;
1177 u8 ccs;
1178 int enqueue;
1179 int dequeue;
1180 u8 trb_burst_size;
1181
1182 unsigned int wa1_set:1;
1183 struct cdns3_trb *wa1_trb;
1184 unsigned int wa1_trb_index;
1185 unsigned int wa1_cycle_bit:1;
1186
1187
1188 unsigned int use_streams:1;
1189 unsigned int prime_flag:1;
1190 u32 ep_sts_pending;
1191 u16 last_stream_id;
1192 u16 pending_tdl;
1193 unsigned int stream_sg_idx;
1194};
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205struct cdns3_aligned_buf {
1206 void *buf;
1207 dma_addr_t dma;
1208 u32 size;
1209 enum dma_data_direction dir;
1210 unsigned in_use:1;
1211 struct list_head list;
1212};
1213
1214
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1221
1222
1223
1224
1225
1226
1227
1228
1229struct cdns3_request {
1230 struct usb_request request;
1231 struct cdns3_endpoint *priv_ep;
1232 struct cdns3_trb *trb;
1233 int start_trb;
1234 int end_trb;
1235 struct cdns3_aligned_buf *aligned_buf;
1236#define REQUEST_PENDING BIT(0)
1237#define REQUEST_INTERNAL BIT(1)
1238#define REQUEST_INTERNAL_CH BIT(2)
1239#define REQUEST_ZLP BIT(3)
1240#define REQUEST_UNALIGNED BIT(4)
1241 u32 flags;
1242 struct list_head list;
1243 int finished_trb;
1244 int num_of_trb;
1245};
1246
1247#define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
1248
1249
1250#define CDNS3_SETUP_STAGE 0x0
1251#define CDNS3_DATA_STAGE 0x1
1252#define CDNS3_STATUS_STAGE 0x2
1253
1254
1255
1256
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1261
1262
1263
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1281
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1285
1286
1287struct cdns3_device {
1288 struct device *dev;
1289 struct device *sysdev;
1290
1291 struct usb_gadget gadget;
1292 struct usb_gadget_driver *gadget_driver;
1293
1294#define CDNS_REVISION_V0 0x00024501
1295#define CDNS_REVISION_V1 0x00024509
1296 u32 dev_ver;
1297
1298
1299 spinlock_t lock;
1300
1301 struct cdns3_usb_regs __iomem *regs;
1302
1303 struct dma_pool *eps_dma_pool;
1304 struct usb_ctrlrequest *setup_buf;
1305 dma_addr_t setup_dma;
1306 void *zlp_buf;
1307
1308 u8 ep0_stage;
1309 int ep0_data_dir;
1310
1311 struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT];
1312
1313 struct list_head aligned_buf_list;
1314 struct work_struct aligned_buf_wq;
1315
1316 u32 selected_ep;
1317 u16 isoch_delay;
1318
1319 unsigned wait_for_setup:1;
1320 unsigned u1_allowed:1;
1321 unsigned u2_allowed:1;
1322 unsigned is_selfpowered:1;
1323 unsigned setup_pending:1;
1324 unsigned hw_configured_flag:1;
1325 unsigned wake_up_flag:1;
1326 unsigned status_completion_no_call:1;
1327 unsigned using_streams:1;
1328 int out_mem_is_allocated;
1329
1330 struct work_struct pending_status_wq;
1331 struct usb_request *pending_status_request;
1332
1333
1334 u16 onchip_buffers;
1335 u16 onchip_used_size;
1336};
1337
1338void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
1339dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
1340 struct cdns3_trb *trb);
1341enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
1342void cdns3_pending_setup_status_handler(struct work_struct *work);
1343void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
1344void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
1345void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
1346void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
1347struct usb_request *cdns3_next_request(struct list_head *list);
1348void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
1349int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
1350u8 cdns3_ep_addr_to_index(u8 ep_addr);
1351int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
1352int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
1353void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
1354int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
1355struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1356 gfp_t gfp_flags);
1357void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1358 struct usb_request *request);
1359int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
1360void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
1361 struct cdns3_request *priv_req,
1362 int status);
1363
1364int cdns3_init_ep0(struct cdns3_device *priv_dev,
1365 struct cdns3_endpoint *priv_ep);
1366void cdns3_ep0_config(struct cdns3_device *priv_dev);
1367int cdns3_ep_config(struct cdns3_endpoint *priv_ep, bool enable);
1368void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
1369int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
1370
1371#endif
1372