1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2/* 3 * core.h - DesignWare HS OTG Controller common declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef __DWC2_CORE_H__ 39#define __DWC2_CORE_H__ 40 41#include <linux/acpi.h> 42#include <linux/phy/phy.h> 43#include <linux/regulator/consumer.h> 44#include <linux/usb/gadget.h> 45#include <linux/usb/otg.h> 46#include <linux/usb/phy.h> 47#include "hw.h" 48 49/* 50 * Suggested defines for tracers: 51 * - no_printk: Disable tracing 52 * - pr_info: Print this info to the console 53 * - trace_printk: Print this info to trace buffer (good for verbose logging) 54 */ 55 56#define DWC2_TRACE_SCHEDULER no_printk 57#define DWC2_TRACE_SCHEDULER_VB no_printk 58 59/* Detailed scheduler tracing, but won't overwhelm console */ 60#define dwc2_sch_dbg(hsotg, fmt, ...) \ 61 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 62 dev_name(hsotg->dev), ##__VA_ARGS__) 63 64/* Verbose scheduler tracing */ 65#define dwc2_sch_vdbg(hsotg, fmt, ...) \ 66 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 67 dev_name(hsotg->dev), ##__VA_ARGS__) 68 69/* Maximum number of Endpoints/HostChannels */ 70#define MAX_EPS_CHANNELS 16 71 72/* dwc2-hsotg declarations */ 73static const char * const dwc2_hsotg_supply_names[] = { 74 "vusb_d", /* digital USB supply, 1.2V */ 75 "vusb_a", /* analog USB supply, 1.1V */ 76}; 77 78#define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names) 79 80/* 81 * EP0_MPS_LIMIT 82 * 83 * Unfortunately there seems to be a limit of the amount of data that can 84 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 85 * packets (which practically means 1 packet and 63 bytes of data) when the 86 * MPS is set to 64. 87 * 88 * This means if we are wanting to move >127 bytes of data, we need to 89 * split the transactions up, but just doing one packet at a time does 90 * not work (this may be an implicit DATA0 PID on first packet of the 91 * transaction) and doing 2 packets is outside the controller's limits. 92 * 93 * If we try to lower the MPS size for EP0, then no transfers work properly 94 * for EP0, and the system will fail basic enumeration. As no cause for this 95 * has currently been found, we cannot support any large IN transfers for 96 * EP0. 97 */ 98#define EP0_MPS_LIMIT 64 99 100struct dwc2_hsotg; 101struct dwc2_hsotg_req; 102 103/** 104 * struct dwc2_hsotg_ep - driver endpoint definition. 105 * @ep: The gadget layer representation of the endpoint. 106 * @name: The driver generated name for the endpoint. 107 * @queue: Queue of requests for this endpoint. 108 * @parent: Reference back to the parent device structure. 109 * @req: The current request that the endpoint is processing. This is 110 * used to indicate an request has been loaded onto the endpoint 111 * and has yet to be completed (maybe due to data move, or simply 112 * awaiting an ack from the core all the data has been completed). 113 * @debugfs: File entry for debugfs file for this endpoint. 114 * @dir_in: Set to true if this endpoint is of the IN direction, which 115 * means that it is sending data to the Host. 116 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped. 117 * @index: The index for the endpoint registers. 118 * @mc: Multi Count - number of transactions per microframe 119 * @interval: Interval for periodic endpoints, in frames or microframes. 120 * @name: The name array passed to the USB core. 121 * @halted: Set if the endpoint has been halted. 122 * @periodic: Set if this is a periodic ep, such as Interrupt 123 * @isochronous: Set if this is a isochronous ep 124 * @send_zlp: Set if we need to send a zero-length packet. 125 * @wedged: Set if ep is wedged. 126 * @desc_list_dma: The DMA address of descriptor chain currently in use. 127 * @desc_list: Pointer to descriptor DMA chain head currently in use. 128 * @desc_count: Count of entries within the DMA descriptor chain of EP. 129 * @next_desc: index of next free descriptor in the ISOC chain under SW control. 130 * @compl_desc: index of next descriptor to be completed by xFerComplete 131 * @total_data: The total number of data bytes done. 132 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 133 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0. 134 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 135 * @last_load: The offset of data for the last start of request. 136 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 137 * @target_frame: Targeted frame num to setup next ISOC transfer 138 * @frame_overrun: Indicates SOF number overrun in DSTS 139 * 140 * This is the driver's state for each registered endpoint, allowing it 141 * to keep track of transactions that need doing. Each endpoint has a 142 * lock to protect the state, to try and avoid using an overall lock 143 * for the host controller as much as possible. 144 * 145 * For periodic IN endpoints, we have fifo_size and fifo_load to try 146 * and keep track of the amount of data in the periodic FIFO for each 147 * of these as we don't have a status register that tells us how much 148 * is in each of them. (note, this may actually be useless information 149 * as in shared-fifo mode periodic in acts like a single-frame packet 150 * buffer than a fifo) 151 */ 152struct dwc2_hsotg_ep { 153 struct usb_ep ep; 154 struct list_head queue; 155 struct dwc2_hsotg *parent; 156 struct dwc2_hsotg_req *req; 157 struct dentry *debugfs; 158 159 unsigned long total_data; 160 unsigned int size_loaded; 161 unsigned int last_load; 162 unsigned int fifo_load; 163 unsigned short fifo_size; 164 unsigned short fifo_index; 165 166 unsigned char dir_in; 167 unsigned char map_dir; 168 unsigned char index; 169 unsigned char mc; 170 u16 interval; 171 172 unsigned int halted:1; 173 unsigned int periodic:1; 174 unsigned int isochronous:1; 175 unsigned int send_zlp:1; 176 unsigned int wedged:1; 177 unsigned int target_frame; 178#define TARGET_FRAME_INITIAL 0xFFFFFFFF 179 bool frame_overrun; 180 181 dma_addr_t desc_list_dma; 182 struct dwc2_dma_desc *desc_list; 183 u8 desc_count; 184 185 unsigned int next_desc; 186 unsigned int compl_desc; 187 188 char name[10]; 189}; 190 191/** 192 * struct dwc2_hsotg_req - data transfer request 193 * @req: The USB gadget request 194 * @queue: The list of requests for the endpoint this is queued for. 195 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 196 */ 197struct dwc2_hsotg_req { 198 struct usb_request req; 199 struct list_head queue; 200 void *saved_req_buf; 201}; 202 203#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 204 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 205#define call_gadget(_hs, _entry) \ 206do { \ 207 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 208 (_hs)->driver && (_hs)->driver->_entry) { \ 209 spin_unlock(&_hs->lock); \ 210 (_hs)->driver->_entry(&(_hs)->gadget); \ 211 spin_lock(&_hs->lock); \ 212 } \ 213} while (0) 214#else 215#define call_gadget(_hs, _entry) do {} while (0) 216#endif 217 218struct dwc2_hsotg; 219struct dwc2_host_chan; 220 221/* Device States */ 222enum dwc2_lx_state { 223 DWC2_L0, /* On state */ 224 DWC2_L1, /* LPM sleep state */ 225 DWC2_L2, /* USB suspend state */ 226 DWC2_L3, /* Off state */ 227}; 228 229/* Gadget ep0 states */ 230enum dwc2_ep0_state { 231 DWC2_EP0_SETUP, 232 DWC2_EP0_DATA_IN, 233 DWC2_EP0_DATA_OUT, 234 DWC2_EP0_STATUS_IN, 235 DWC2_EP0_STATUS_OUT, 236}; 237 238/** 239 * struct dwc2_core_params - Parameters for configuring the core 240 * 241 * @otg_cap: Specifies the OTG capabilities. 242 * 0 - HNP and SRP capable 243 * 1 - SRP Only capable 244 * 2 - No HNP/SRP capable (always available) 245 * Defaults to best available option (0, 1, then 2) 246 * @host_dma: Specifies whether to use slave or DMA mode for accessing 247 * the data FIFOs. The driver will automatically detect the 248 * value for this parameter if none is specified. 249 * 0 - Slave (always available) 250 * 1 - DMA (default, if available) 251 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 252 * address DMA mode or descriptor DMA mode for accessing 253 * the data FIFOs. The driver will automatically detect the 254 * value for this if none is specified. 255 * 0 - Address DMA 256 * 1 - Descriptor DMA (default, if available) 257 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 258 * address DMA mode or descriptor DMA mode for accessing 259 * the data FIFOs in Full Speed mode only. The driver 260 * will automatically detect the value for this if none is 261 * specified. 262 * 0 - Address DMA 263 * 1 - Descriptor DMA in FS (default, if available) 264 * @speed: Specifies the maximum speed of operation in host and 265 * device mode. The actual speed depends on the speed of 266 * the attached device and the value of phy_type. 267 * 0 - High Speed 268 * (default when phy_type is UTMI+ or ULPI) 269 * 1 - Full Speed 270 * (default when phy_type is Full Speed) 271 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 272 * 1 - Allow dynamic FIFO sizing (default, if available) 273 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 274 * are enabled for non-periodic IN endpoints in device 275 * mode. 276 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 277 * dynamic FIFO sizing is enabled 278 * 16 to 32768 279 * Actual maximum value is autodetected and also 280 * the default. 281 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 282 * in host mode when dynamic FIFO sizing is enabled 283 * 16 to 32768 284 * Actual maximum value is autodetected and also 285 * the default. 286 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 287 * host mode when dynamic FIFO sizing is enabled 288 * 16 to 32768 289 * Actual maximum value is autodetected and also 290 * the default. 291 * @max_transfer_size: The maximum transfer size supported, in bytes 292 * 2047 to 65,535 293 * Actual maximum value is autodetected and also 294 * the default. 295 * @max_packet_count: The maximum number of packets in a transfer 296 * 15 to 511 297 * Actual maximum value is autodetected and also 298 * the default. 299 * @host_channels: The number of host channel registers to use 300 * 1 to 16 301 * Actual maximum value is autodetected and also 302 * the default. 303 * @phy_type: Specifies the type of PHY interface to use. By default, 304 * the driver will automatically detect the phy_type. 305 * 0 - Full Speed Phy 306 * 1 - UTMI+ Phy 307 * 2 - ULPI Phy 308 * Defaults to best available option (2, 1, then 0) 309 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 310 * is applicable for a phy_type of UTMI+ or ULPI. (For a 311 * ULPI phy_type, this parameter indicates the data width 312 * between the MAC and the ULPI Wrapper.) Also, this 313 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 314 * parameter was set to "8 and 16 bits", meaning that the 315 * core has been configured to work at either data path 316 * width. 317 * 8 or 16 (default 16 if available) 318 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 319 * data rate. This parameter is only applicable if phy_type 320 * is ULPI. 321 * 0 - single data rate ULPI interface with 8 bit wide 322 * data bus (default) 323 * 1 - double data rate ULPI interface with 4 bit wide 324 * data bus 325 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 326 * external supply to drive the VBus 327 * 0 - Internal supply (default) 328 * 1 - External supply 329 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 330 * speed PHY. This parameter is only applicable if phy_type 331 * is FS. 332 * 0 - No (default) 333 * 1 - Yes 334 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled. 335 * 0 - Disable (default) 336 * 1 - Enable 337 * @acg_enable: For enabling Active Clock Gating in the controller 338 * 0 - No 339 * 1 - Yes 340 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 341 * 0 - No (default) 342 * 1 - Yes 343 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 344 * when attached to a Full Speed or Low Speed device in 345 * host mode. 346 * 0 - Don't support low power mode (default) 347 * 1 - Support low power mode 348 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 349 * when connected to a Low Speed device in host 350 * mode. This parameter is applicable only if 351 * host_support_fs_ls_low_power is enabled. 352 * 0 - 48 MHz 353 * (default when phy_type is UTMI+ or ULPI) 354 * 1 - 6 MHz 355 * (default when phy_type is Full Speed) 356 * @oc_disable: Flag to disable overcurrent condition. 357 * 0 - Allow overcurrent condition to get detected 358 * 1 - Disable overcurrent condtion to get detected 359 * @ts_dline: Enable Term Select Dline pulsing 360 * 0 - No (default) 361 * 1 - Yes 362 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 363 * 0 - No (default for core < 2.92a) 364 * 1 - Yes (default for core >= 2.92a) 365 * @ahbcfg: This field allows the default value of the GAHBCFG 366 * register to be overridden 367 * -1 - GAHBCFG value will be set to 0x06 368 * (INCR, default) 369 * all others - GAHBCFG value will be overridden with 370 * this value 371 * Not all bits can be controlled like this, the 372 * bits defined by GAHBCFG_CTRL_MASK are controlled 373 * by the driver and are ignored in this 374 * configuration value. 375 * @uframe_sched: True to enable the microframe scheduler 376 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 377 * Disable CONIDSTSCHNG controller interrupt in such 378 * case. 379 * 0 - No (default) 380 * 1 - Yes 381 * @power_down: Specifies whether the controller support power_down. 382 * If power_down is enabled, the controller will enter 383 * power_down in both peripheral and host mode when 384 * needed. 385 * 0 - No (default) 386 * 1 - Partial power down 387 * 2 - Hibernation 388 * @no_clock_gating: Specifies whether to avoid clock gating feature. 389 * 0 - No (use clock gating) 390 * 1 - Yes (avoid it) 391 * @lpm: Enable LPM support. 392 * 0 - No 393 * 1 - Yes 394 * @lpm_clock_gating: Enable core PHY clock gating. 395 * 0 - No 396 * 1 - Yes 397 * @besl: Enable LPM Errata support. 398 * 0 - No 399 * 1 - Yes 400 * @hird_threshold_en: HIRD or HIRD Threshold enable. 401 * 0 - No 402 * 1 - Yes 403 * @hird_threshold: Value of BESL or HIRD Threshold. 404 * @ref_clk_per: Indicates in terms of pico seconds the period 405 * of ref_clk. 406 * 62500 - 16MHz 407 * 58823 - 17MHz 408 * 52083 - 19.2MHz 409 * 50000 - 20MHz 410 * 41666 - 24MHz 411 * 33333 - 30MHz (default) 412 * 25000 - 40MHz 413 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which 414 * the controller should generate an interrupt if the 415 * device had been in L1 state until that period. 416 * This is used by SW to initiate Remote WakeUp in the 417 * controller so as to sync to the uF number from the host. 418 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO 419 * register. 420 * 0 - Deactivate the transceiver (default) 421 * 1 - Activate the transceiver 422 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level 423 * detection using GGPIO register. 424 * 0 - Deactivate the external level detection (default) 425 * 1 - Activate the external level detection 426 * @g_dma: Enables gadget dma usage (default: autodetect). 427 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect). 428 * @g_rx_fifo_size: The periodic rx fifo size for the device, in 429 * DWORDS from 16-32768 (default: 2048 if 430 * possible, otherwise autodetect). 431 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in 432 * DWORDS from 16-32768 (default: 1024 if 433 * possible, otherwise autodetect). 434 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo 435 * mode. Each value corresponds to one EP 436 * starting from EP1 (max 15 values). Sizes are 437 * in DWORDS with possible values from 438 * 16-32768 (default: 256, 256, 256, 256, 768, 439 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0). 440 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL 441 * while full&low speed device connect. And change speed 442 * back to DWC2_SPEED_PARAM_HIGH while device is gone. 443 * 0 - No (default) 444 * 1 - Yes 445 * @service_interval: Enable service interval based scheduling. 446 * 0 - No 447 * 1 - Yes 448 * 449 * The following parameters may be specified when starting the module. These 450 * parameters define how the DWC_otg controller should be configured. A 451 * value of -1 (or any other out of range value) for any parameter means 452 * to read the value from hardware (if possible) or use the builtin 453 * default described above. 454 */ 455struct dwc2_core_params { 456 u8 otg_cap; 457#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 458#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 459#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 460 461 u8 phy_type; 462#define DWC2_PHY_TYPE_PARAM_FS 0 463#define DWC2_PHY_TYPE_PARAM_UTMI 1 464#define DWC2_PHY_TYPE_PARAM_ULPI 2 465 466 u8 speed; 467#define DWC2_SPEED_PARAM_HIGH 0 468#define DWC2_SPEED_PARAM_FULL 1 469#define DWC2_SPEED_PARAM_LOW 2 470 471 u8 phy_utmi_width; 472 bool phy_ulpi_ddr; 473 bool phy_ulpi_ext_vbus; 474 bool enable_dynamic_fifo; 475 bool en_multiple_tx_fifo; 476 bool i2c_enable; 477 bool acg_enable; 478 bool ulpi_fs_ls; 479 bool ts_dline; 480 bool reload_ctl; 481 bool uframe_sched; 482 bool external_id_pin_ctl; 483 484 int power_down; 485#define DWC2_POWER_DOWN_PARAM_NONE 0 486#define DWC2_POWER_DOWN_PARAM_PARTIAL 1 487#define DWC2_POWER_DOWN_PARAM_HIBERNATION 2 488 bool no_clock_gating; 489 490 bool lpm; 491 bool lpm_clock_gating; 492 bool besl; 493 bool hird_threshold_en; 494 bool service_interval; 495 u8 hird_threshold; 496 bool activate_stm_fs_transceiver; 497 bool activate_stm_id_vb_detection; 498 bool ipg_isoc_en; 499 u16 max_packet_count; 500 u32 max_transfer_size; 501 u32 ahbcfg; 502 503 /* GREFCLK parameters */ 504 u32 ref_clk_per; 505 u16 sof_cnt_wkup_alert; 506 507 /* Host parameters */ 508 bool host_dma; 509 bool dma_desc_enable; 510 bool dma_desc_fs_enable; 511 bool host_support_fs_ls_low_power; 512 bool host_ls_low_power_phy_clk; 513 bool oc_disable; 514 515 u8 host_channels; 516 u16 host_rx_fifo_size; 517 u16 host_nperio_tx_fifo_size; 518 u16 host_perio_tx_fifo_size; 519 520 /* Gadget parameters */ 521 bool g_dma; 522 bool g_dma_desc; 523 u32 g_rx_fifo_size; 524 u32 g_np_tx_fifo_size; 525 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 526 527 bool change_speed_quirk; 528}; 529 530/** 531 * struct dwc2_hw_params - Autodetected parameters. 532 * 533 * These parameters are the various parameters read from hardware 534 * registers during initialization. They typically contain the best 535 * supported or maximum value that can be configured in the 536 * corresponding dwc2_core_params value. 537 * 538 * The values that are not in dwc2_core_params are documented below. 539 * 540 * @op_mode: Mode of Operation 541 * 0 - HNP- and SRP-Capable OTG (Host & Device) 542 * 1 - SRP-Capable OTG (Host & Device) 543 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 544 * 3 - SRP-Capable Device 545 * 4 - Non-OTG Device 546 * 5 - SRP-Capable Host 547 * 6 - Non-OTG Host 548 * @arch: Architecture 549 * 0 - Slave only 550 * 1 - External DMA 551 * 2 - Internal DMA 552 * @ipg_isoc_en: This feature indicates that the controller supports 553 * the worst-case scenario of Rx followed by Rx 554 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi 555 * specification for any token following ISOC OUT token. 556 * 0 - Don't support 557 * 1 - Support 558 * @power_optimized: Are power optimizations enabled? 559 * @num_dev_ep: Number of device endpoints available 560 * @num_dev_in_eps: Number of device IN endpoints available 561 * @num_dev_perio_in_ep: Number of device periodic IN endpoints 562 * available 563 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue 564 * Depth 565 * 0 to 30 566 * @host_perio_tx_q_depth: 567 * Host Mode Periodic Request Queue Depth 568 * 2, 4 or 8 569 * @nperio_tx_q_depth: 570 * Non-Periodic Request Queue Depth 571 * 2, 4 or 8 572 * @hs_phy_type: High-speed PHY interface type 573 * 0 - High-speed interface not supported 574 * 1 - UTMI+ 575 * 2 - ULPI 576 * 3 - UTMI+ and ULPI 577 * @fs_phy_type: Full-speed PHY interface type 578 * 0 - Full speed interface not supported 579 * 1 - Dedicated full speed interface 580 * 2 - FS pins shared with UTMI+ pins 581 * 3 - FS pins shared with ULPI pins 582 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 583 * @hibernation: Is hibernation enabled? 584 * @utmi_phy_data_width: UTMI+ PHY data width 585 * 0 - 8 bits 586 * 1 - 16 bits 587 * 2 - 8 or 16 bits 588 * @snpsid: Value from SNPSID register 589 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 590 * @g_tx_fifo_size: Power-on values of TxFIFO sizes 591 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 592 * address DMA mode or descriptor DMA mode for accessing 593 * the data FIFOs. The driver will automatically detect the 594 * value for this if none is specified. 595 * 0 - Address DMA 596 * 1 - Descriptor DMA (default, if available) 597 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 598 * 1 - Allow dynamic FIFO sizing (default, if available) 599 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 600 * are enabled for non-periodic IN endpoints in device 601 * mode. 602 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 603 * in host mode when dynamic FIFO sizing is enabled 604 * 16 to 32768 605 * Actual maximum value is autodetected and also 606 * the default. 607 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 608 * host mode when dynamic FIFO sizing is enabled 609 * 16 to 32768 610 * Actual maximum value is autodetected and also 611 * the default. 612 * @max_transfer_size: The maximum transfer size supported, in bytes 613 * 2047 to 65,535 614 * Actual maximum value is autodetected and also 615 * the default. 616 * @max_packet_count: The maximum number of packets in a transfer 617 * 15 to 511 618 * Actual maximum value is autodetected and also 619 * the default. 620 * @host_channels: The number of host channel registers to use 621 * 1 to 16 622 * Actual maximum value is autodetected and also 623 * the default. 624 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 625 * in device mode when dynamic FIFO sizing is enabled 626 * 16 to 32768 627 * Actual maximum value is autodetected and also 628 * the default. 629 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 630 * speed PHY. This parameter is only applicable if phy_type 631 * is FS. 632 * 0 - No (default) 633 * 1 - Yes 634 * @acg_enable: For enabling Active Clock Gating in the controller 635 * 0 - Disable 636 * 1 - Enable 637 * @lpm_mode: For enabling Link Power Management in the controller 638 * 0 - Disable 639 * 1 - Enable 640 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic 641 * FIFO sizing is enabled 16 to 32768 642 * Actual maximum value is autodetected and also 643 * the default. 644 * @service_interval_mode: For enabling service interval based scheduling in the 645 * controller. 646 * 0 - Disable 647 * 1 - Enable 648 */ 649struct dwc2_hw_params { 650 unsigned op_mode:3; 651 unsigned arch:2; 652 unsigned dma_desc_enable:1; 653 unsigned enable_dynamic_fifo:1; 654 unsigned en_multiple_tx_fifo:1; 655 unsigned rx_fifo_size:16; 656 unsigned host_nperio_tx_fifo_size:16; 657 unsigned dev_nperio_tx_fifo_size:16; 658 unsigned host_perio_tx_fifo_size:16; 659 unsigned nperio_tx_q_depth:3; 660 unsigned host_perio_tx_q_depth:3; 661 unsigned dev_token_q_depth:5; 662 unsigned max_transfer_size:26; 663 unsigned max_packet_count:11; 664 unsigned host_channels:5; 665 unsigned hs_phy_type:2; 666 unsigned fs_phy_type:2; 667 unsigned i2c_enable:1; 668 unsigned acg_enable:1; 669 unsigned num_dev_ep:4; 670 unsigned num_dev_in_eps : 4; 671 unsigned num_dev_perio_in_ep:4; 672 unsigned total_fifo_size:16; 673 unsigned power_optimized:1; 674 unsigned hibernation:1; 675 unsigned utmi_phy_data_width:2; 676 unsigned lpm_mode:1; 677 unsigned ipg_isoc_en:1; 678 unsigned service_interval_mode:1; 679 u32 snpsid; 680 u32 dev_ep_dirs; 681 u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; 682}; 683 684/* Size of control and EP0 buffers */ 685#define DWC2_CTRL_BUFF_SIZE 8 686 687/** 688 * struct dwc2_gregs_backup - Holds global registers state before 689 * entering partial power down 690 * @gotgctl: Backup of GOTGCTL register 691 * @gintmsk: Backup of GINTMSK register 692 * @gahbcfg: Backup of GAHBCFG register 693 * @gusbcfg: Backup of GUSBCFG register 694 * @grxfsiz: Backup of GRXFSIZ register 695 * @gnptxfsiz: Backup of GNPTXFSIZ register 696 * @gi2cctl: Backup of GI2CCTL register 697 * @glpmcfg: Backup of GLPMCFG register 698 * @gdfifocfg: Backup of GDFIFOCFG register 699 * @pcgcctl: Backup of PCGCCTL register 700 * @pcgcctl1: Backup of PCGCCTL1 register 701 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 702 * @gpwrdn: Backup of GPWRDN register 703 * @valid: True if registers values backuped. 704 */ 705struct dwc2_gregs_backup { 706 u32 gotgctl; 707 u32 gintmsk; 708 u32 gahbcfg; 709 u32 gusbcfg; 710 u32 grxfsiz; 711 u32 gnptxfsiz; 712 u32 gi2cctl; 713 u32 glpmcfg; 714 u32 pcgcctl; 715 u32 pcgcctl1; 716 u32 gdfifocfg; 717 u32 gpwrdn; 718 bool valid; 719}; 720 721/** 722 * struct dwc2_dregs_backup - Holds device registers state before 723 * entering partial power down 724 * @dcfg: Backup of DCFG register 725 * @dctl: Backup of DCTL register 726 * @daintmsk: Backup of DAINTMSK register 727 * @diepmsk: Backup of DIEPMSK register 728 * @doepmsk: Backup of DOEPMSK register 729 * @diepctl: Backup of DIEPCTL register 730 * @dieptsiz: Backup of DIEPTSIZ register 731 * @diepdma: Backup of DIEPDMA register 732 * @doepctl: Backup of DOEPCTL register 733 * @doeptsiz: Backup of DOEPTSIZ register 734 * @doepdma: Backup of DOEPDMA register 735 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 736 * @valid: True if registers values backuped. 737 */ 738struct dwc2_dregs_backup { 739 u32 dcfg; 740 u32 dctl; 741 u32 daintmsk; 742 u32 diepmsk; 743 u32 doepmsk; 744 u32 diepctl[MAX_EPS_CHANNELS]; 745 u32 dieptsiz[MAX_EPS_CHANNELS]; 746 u32 diepdma[MAX_EPS_CHANNELS]; 747 u32 doepctl[MAX_EPS_CHANNELS]; 748 u32 doeptsiz[MAX_EPS_CHANNELS]; 749 u32 doepdma[MAX_EPS_CHANNELS]; 750 u32 dtxfsiz[MAX_EPS_CHANNELS]; 751 bool valid; 752}; 753 754/** 755 * struct dwc2_hregs_backup - Holds host registers state before 756 * entering partial power down 757 * @hcfg: Backup of HCFG register 758 * @haintmsk: Backup of HAINTMSK register 759 * @hcintmsk: Backup of HCINTMSK register 760 * @hprt0: Backup of HPTR0 register 761 * @hfir: Backup of HFIR register 762 * @hptxfsiz: Backup of HPTXFSIZ register 763 * @valid: True if registers values backuped. 764 */ 765struct dwc2_hregs_backup { 766 u32 hcfg; 767 u32 haintmsk; 768 u32 hcintmsk[MAX_EPS_CHANNELS]; 769 u32 hprt0; 770 u32 hfir; 771 u32 hptxfsiz; 772 bool valid; 773}; 774 775/* 776 * Constants related to high speed periodic scheduling 777 * 778 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 779 * reservation point of view it's assumed that the schedule goes right back to 780 * the beginning after the end of the schedule. 781 * 782 * What does that mean for scheduling things with a long interval? It means 783 * we'll reserve time for them in every possible microframe that they could 784 * ever be scheduled in. ...but we'll still only actually schedule them as 785 * often as they were requested. 786 * 787 * We keep our schedule in a "bitmap" structure. This simplifies having 788 * to keep track of and merge intervals: we just let the bitmap code do most 789 * of the heavy lifting. In a way scheduling is much like memory allocation. 790 * 791 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 792 * supposed to schedule for periodic transfers). That's according to spec. 793 * 794 * Note that though we only schedule 80% of each microframe, the bitmap that we 795 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 796 * space for each uFrame). 797 * 798 * Requirements: 799 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 800 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 801 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 802 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 803 */ 804#define DWC2_US_PER_UFRAME 125 805#define DWC2_HS_PERIODIC_US_PER_UFRAME 100 806 807#define DWC2_HS_SCHEDULE_UFRAMES 8 808#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 809 DWC2_HS_PERIODIC_US_PER_UFRAME) 810 811/* 812 * Constants related to low speed scheduling 813 * 814 * For high speed we schedule every 1us. For low speed that's a bit overkill, 815 * so we make up a unit called a "slice" that's worth 25us. There are 40 816 * slices in a full frame and we can schedule 36 of those (90%) for periodic 817 * transfers. 818 * 819 * Our low speed schedule can be as short as 1 frame or could be longer. When 820 * we only schedule 1 frame it means that we'll need to reserve a time every 821 * frame even for things that only transfer very rarely, so something that runs 822 * every 2048 frames will get time reserved in every frame. Our low speed 823 * schedule can be longer and we'll be able to handle more overlap, but that 824 * will come at increased memory cost and increased time to schedule. 825 * 826 * Note: one other advantage of a short low speed schedule is that if we mess 827 * up and miss scheduling we can jump in and use any of the slots that we 828 * happened to reserve. 829 * 830 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 831 * the schedule. There will be one schedule per TT. 832 * 833 * Requirements: 834 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 835 */ 836#define DWC2_US_PER_SLICE 25 837#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 838 839#define DWC2_ROUND_US_TO_SLICE(us) \ 840 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 841 DWC2_US_PER_SLICE) 842 843#define DWC2_LS_PERIODIC_US_PER_FRAME \ 844 900 845#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 846 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 847 DWC2_US_PER_SLICE) 848 849#define DWC2_LS_SCHEDULE_FRAMES 1 850#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 851 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 852 853/** 854 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 855 * and periodic schedules 856 * 857 * These are common for both host and peripheral modes: 858 * 859 * @dev: The struct device pointer 860 * @regs: Pointer to controller regs 861 * @hw_params: Parameters that were autodetected from the 862 * hardware registers 863 * @params: Parameters that define how the core should be configured 864 * @op_state: The operational State, during transitions (a_host=> 865 * a_peripheral and b_device=>b_host) this may not match 866 * the core, but allows the software to determine 867 * transitions 868 * @dr_mode: Requested mode of operation, one of following: 869 * - USB_DR_MODE_PERIPHERAL 870 * - USB_DR_MODE_HOST 871 * - USB_DR_MODE_OTG 872 * @role_sw: usb_role_switch handle 873 * @hcd_enabled: Host mode sub-driver initialization indicator. 874 * @gadget_enabled: Peripheral mode sub-driver initialization indicator. 875 * @ll_hw_enabled: Status of low-level hardware resources. 876 * @hibernated: True if core is hibernated 877 * @in_ppd: True if core is partial power down mode. 878 * @bus_suspended: True if bus is suspended 879 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a 880 * remote wakeup. 881 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend. 882 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at 883 * suspend if we need USB to wake us up. 884 * @frame_number: Frame number read from the core. For both device 885 * and host modes. The value ranges are from 0 886 * to HFNUM_MAX_FRNUM. 887 * @phy: The otg phy transceiver structure for phy control. 888 * @uphy: The otg phy transceiver structure for old USB phy 889 * control. 890 * @plat: The platform specific configuration data. This can be 891 * removed once all SoCs support usb transceiver. 892 * @supplies: Definition of USB power supplies 893 * @vbus_supply: Regulator supplying vbus. 894 * @usb33d: Optional 3.3v regulator used on some stm32 devices to 895 * supply ID and VBUS detection hardware. 896 * @lock: Spinlock that protects all the driver data structures 897 * @priv: Stores a pointer to the struct usb_hcd 898 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 899 * transfer are in process of being queued 900 * @srp_success: Stores status of SRP request in the case of a FS PHY 901 * with an I2C interface 902 * @wq_otg: Workqueue object used for handling of some interrupts 903 * @wf_otg: Work object for handling Connector ID Status Change 904 * interrupt 905 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 906 * @lx_state: Lx state of connected device 907 * @gr_backup: Backup of global registers during suspend 908 * @dr_backup: Backup of device registers during suspend 909 * @hr_backup: Backup of host registers during suspend 910 * @needs_byte_swap: Specifies whether the opposite endianness. 911 * 912 * These are for host mode: 913 * 914 * @flags: Flags for handling root port state changes 915 * @flags.d32: Contain all root port flags 916 * @flags.b: Separate root port flags from each other 917 * @flags.b.port_connect_status_change: True if root port connect status 918 * changed 919 * @flags.b.port_connect_status: True if device connected to root port 920 * @flags.b.port_reset_change: True if root port reset status changed 921 * @flags.b.port_enable_change: True if root port enable status changed 922 * @flags.b.port_suspend_change: True if root port suspend status changed 923 * @flags.b.port_over_current_change: True if root port over current state 924 * changed. 925 * @flags.b.port_l1_change: True if root port l1 status changed 926 * @flags.b.reserved: Reserved bits of root port register 927 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 928 * Transfers associated with these QHs are not currently 929 * assigned to a host channel. 930 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 931 * Transfers associated with these QHs are currently 932 * assigned to a host channel. 933 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 934 * non-periodic schedule 935 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule. 936 * Transfers associated with these QHs are not currently 937 * assigned to a host channel. 938 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 939 * list of QHs for periodic transfers that are _not_ 940 * scheduled for the next frame. Each QH in the list has an 941 * interval counter that determines when it needs to be 942 * scheduled for execution. This scheduling mechanism 943 * allows only a simple calculation for periodic bandwidth 944 * used (i.e. must assume that all periodic transfers may 945 * need to execute in the same frame). However, it greatly 946 * simplifies scheduling and should be sufficient for the 947 * vast majority of OTG hosts, which need to connect to a 948 * small number of peripherals at one time. Items move from 949 * this list to periodic_sched_ready when the QH interval 950 * counter is 0 at SOF. 951 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 952 * the next frame, but have not yet been assigned to host 953 * channels. Items move from this list to 954 * periodic_sched_assigned as host channels become 955 * available during the current frame. 956 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 957 * frame that are assigned to host channels. Items move 958 * from this list to periodic_sched_queued as the 959 * transactions for the QH are queued to the DWC_otg 960 * controller. 961 * @periodic_sched_queued: List of periodic QHs that have been queued for 962 * execution. Items move from this list to either 963 * periodic_sched_inactive or periodic_sched_ready when the 964 * channel associated with the transfer is released. If the 965 * interval for the QH is 1, the item moves to 966 * periodic_sched_ready because it must be rescheduled for 967 * the next frame. Otherwise, the item moves to 968 * periodic_sched_inactive. 969 * @split_order: List keeping track of channels doing splits, in order. 970 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 971 * This value is in microseconds per (micro)frame. The 972 * assumption is that all periodic transfers may occur in 973 * the same (micro)frame. 974 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 975 * host is in high speed mode; low speed schedules are 976 * stored elsewhere since we need one per TT. 977 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 978 * SOF enable/disable. 979 * @free_hc_list: Free host channels in the controller. This is a list of 980 * struct dwc2_host_chan items. 981 * @periodic_channels: Number of host channels assigned to periodic transfers. 982 * Currently assuming that there is a dedicated host 983 * channel for each periodic transaction and at least one 984 * host channel is available for non-periodic transactions. 985 * @non_periodic_channels: Number of host channels assigned to non-periodic 986 * transfers 987 * @available_host_channels: Number of host channels available for the 988 * microframe scheduler to use 989 * @hc_ptr_array: Array of pointers to the host channel descriptors. 990 * Allows accessing a host channel descriptor given the 991 * host channel number. This is useful in interrupt 992 * handlers. 993 * @status_buf: Buffer used for data received during the status phase of 994 * a control transfer. 995 * @status_buf_dma: DMA address for status_buf 996 * @start_work: Delayed work for handling host A-cable connection 997 * @reset_work: Delayed work for handling a port reset 998 * @phy_reset_work: Work structure for doing a PHY reset 999 * @otg_port: OTG port number 1000 * @frame_list: Frame list
1001 * @frame_list_dma: Frame list DMA address 1002 * @frame_list_sz: Frame list size 1003 * @desc_gen_cache: Kmem cache for generic descriptors 1004 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 1005 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf 1006 * 1007 * These are for peripheral mode: 1008 * 1009 * @driver: USB gadget driver 1010 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 1011 * @num_of_eps: Number of available EPs (excluding EP0) 1012 * @debug_root: Root directrory for debugfs. 1013 * @ep0_reply: Request used for ep0 reply. 1014 * @ep0_buff: Buffer for EP0 reply data, if needed. 1015 * @ctrl_buff: Buffer for EP0 control requests. 1016 * @ctrl_req: Request for EP0 control packets. 1017 * @ep0_state: EP0 control transfers state 1018 * @delayed_status: true when gadget driver asks for delayed status 1019 * @test_mode: USB test mode requested by the host 1020 * @remote_wakeup_allowed: True if device is allowed to wake-up host by 1021 * remote-wakeup signalling 1022 * @setup_desc_dma: EP0 setup stage desc chain DMA address 1023 * @setup_desc: EP0 setup stage desc chain pointer 1024 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address 1025 * @ctrl_in_desc: EP0 IN data phase desc chain pointer 1026 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address 1027 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer 1028 * @irq: Interrupt request line number 1029 * @clk: Pointer to otg clock 1030 * @reset: Pointer to dwc2 reset controller 1031 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10. 1032 * @regset: A pointer to a struct debugfs_regset32, which contains 1033 * a pointer to an array of register definitions, the 1034 * array size and the base address where the register bank 1035 * is to be found. 1036 * @last_frame_num: Number of last frame. Range from 0 to 32768 1037 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1038 * defined, for missed SOFs tracking. Array holds that 1039 * frame numbers, which not equal to last_frame_num +1 1040 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is 1041 * defined, for missed SOFs tracking. 1042 * If current_frame_number != last_frame_num+1 1043 * then last_frame_num added to this array 1044 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array 1045 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed 1046 * 0 - if missed SOFs frame numbers not dumbed 1047 * @fifo_mem: Total internal RAM for FIFOs (bytes) 1048 * @fifo_map: Each bit intend for concrete fifo. If that bit is set, 1049 * then that fifo is used 1050 * @gadget: Represents a usb gadget device 1051 * @connected: Used in slave mode. True if device connected with host 1052 * @eps_in: The IN endpoints being supplied to the gadget framework 1053 * @eps_out: The OUT endpoints being supplied to the gadget framework 1054 * @new_connection: Used in host mode. True if there are new connected 1055 * device 1056 * @enabled: Indicates the enabling state of controller 1057 * 1058 */ 1059struct dwc2_hsotg { 1060 struct device *dev; 1061 void __iomem *regs; 1062 /** Params detected from hardware */ 1063 struct dwc2_hw_params hw_params; 1064 /** Params to actually use */ 1065 struct dwc2_core_params params; 1066 enum usb_otg_state op_state; 1067 enum usb_dr_mode dr_mode; 1068 struct usb_role_switch *role_sw; 1069 unsigned int hcd_enabled:1; 1070 unsigned int gadget_enabled:1; 1071 unsigned int ll_hw_enabled:1; 1072 unsigned int hibernated:1; 1073 unsigned int in_ppd:1; 1074 bool bus_suspended; 1075 unsigned int reset_phy_on_wake:1; 1076 unsigned int need_phy_for_wake:1; 1077 unsigned int phy_off_for_suspend:1; 1078 u16 frame_number; 1079 1080 struct phy *phy; 1081 struct usb_phy *uphy; 1082 struct dwc2_hsotg_plat *plat; 1083 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES]; 1084 struct regulator *vbus_supply; 1085 struct regulator *usb33d; 1086 1087 spinlock_t lock; 1088 void *priv; 1089 int irq; 1090 struct clk *clk; 1091 struct reset_control *reset; 1092 struct reset_control *reset_ecc; 1093 1094 unsigned int queuing_high_bandwidth:1; 1095 unsigned int srp_success:1; 1096 1097 struct workqueue_struct *wq_otg; 1098 struct work_struct wf_otg; 1099 struct timer_list wkp_timer; 1100 enum dwc2_lx_state lx_state; 1101 struct dwc2_gregs_backup gr_backup; 1102 struct dwc2_dregs_backup dr_backup; 1103 struct dwc2_hregs_backup hr_backup; 1104 1105 struct dentry *debug_root; 1106 struct debugfs_regset32 *regset; 1107 bool needs_byte_swap; 1108 1109 /* DWC OTG HW Release versions */ 1110#define DWC2_CORE_REV_2_71a 0x4f54271a 1111#define DWC2_CORE_REV_2_72a 0x4f54272a 1112#define DWC2_CORE_REV_2_80a 0x4f54280a 1113#define DWC2_CORE_REV_2_90a 0x4f54290a 1114#define DWC2_CORE_REV_2_91a 0x4f54291a 1115#define DWC2_CORE_REV_2_92a 0x4f54292a 1116#define DWC2_CORE_REV_2_94a 0x4f54294a 1117#define DWC2_CORE_REV_3_00a 0x4f54300a 1118#define DWC2_CORE_REV_3_10a 0x4f54310a 1119#define DWC2_CORE_REV_4_00a 0x4f54400a 1120#define DWC2_CORE_REV_4_20a 0x4f54420a 1121#define DWC2_FS_IOT_REV_1_00a 0x5531100a 1122#define DWC2_HS_IOT_REV_1_00a 0x5532100a 1123#define DWC2_CORE_REV_MASK 0x0000ffff 1124 1125 /* DWC OTG HW Core ID */ 1126#define DWC2_OTG_ID 0x4f540000 1127#define DWC2_FS_IOT_ID 0x55310000 1128#define DWC2_HS_IOT_ID 0x55320000 1129 1130#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1131 union dwc2_hcd_internal_flags { 1132 u32 d32; 1133 struct { 1134 unsigned port_connect_status_change:1; 1135 unsigned port_connect_status:1; 1136 unsigned port_reset_change:1; 1137 unsigned port_enable_change:1; 1138 unsigned port_suspend_change:1; 1139 unsigned port_over_current_change:1; 1140 unsigned port_l1_change:1; 1141 unsigned reserved:25; 1142 } b; 1143 } flags; 1144 1145 struct list_head non_periodic_sched_inactive; 1146 struct list_head non_periodic_sched_waiting; 1147 struct list_head non_periodic_sched_active; 1148 struct list_head *non_periodic_qh_ptr; 1149 struct list_head periodic_sched_inactive; 1150 struct list_head periodic_sched_ready; 1151 struct list_head periodic_sched_assigned; 1152 struct list_head periodic_sched_queued; 1153 struct list_head split_order; 1154 u16 periodic_usecs; 1155 unsigned long hs_periodic_bitmap[ 1156 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 1157 u16 periodic_qh_count; 1158 bool new_connection; 1159 1160 u16 last_frame_num; 1161 1162#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 1163#define FRAME_NUM_ARRAY_SIZE 1000 1164 u16 *frame_num_array; 1165 u16 *last_frame_num_array; 1166 int frame_num_idx; 1167 int dumped_frame_num_array; 1168#endif 1169 1170 struct list_head free_hc_list; 1171 int periodic_channels; 1172 int non_periodic_channels; 1173 int available_host_channels; 1174 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 1175 u8 *status_buf; 1176 dma_addr_t status_buf_dma; 1177#define DWC2_HCD_STATUS_BUF_SIZE 64 1178 1179 struct delayed_work start_work; 1180 struct delayed_work reset_work; 1181 struct work_struct phy_reset_work; 1182 u8 otg_port; 1183 u32 *frame_list; 1184 dma_addr_t frame_list_dma; 1185 u32 frame_list_sz; 1186 struct kmem_cache *desc_gen_cache; 1187 struct kmem_cache *desc_hsisoc_cache; 1188 struct kmem_cache *unaligned_cache; 1189#define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024 1190 1191#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 1192 1193#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1194 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1195 /* Gadget structures */ 1196 struct usb_gadget_driver *driver; 1197 int fifo_mem; 1198 unsigned int dedicated_fifos:1; 1199 unsigned char num_of_eps; 1200 u32 fifo_map; 1201 1202 struct usb_request *ep0_reply; 1203 struct usb_request *ctrl_req; 1204 void *ep0_buff; 1205 void *ctrl_buff; 1206 enum dwc2_ep0_state ep0_state; 1207 unsigned delayed_status : 1; 1208 u8 test_mode; 1209 1210 dma_addr_t setup_desc_dma[2]; 1211 struct dwc2_dma_desc *setup_desc[2]; 1212 dma_addr_t ctrl_in_desc_dma; 1213 struct dwc2_dma_desc *ctrl_in_desc; 1214 dma_addr_t ctrl_out_desc_dma; 1215 struct dwc2_dma_desc *ctrl_out_desc; 1216 1217 struct usb_gadget gadget; 1218 unsigned int enabled:1; 1219 unsigned int connected:1; 1220 unsigned int remote_wakeup_allowed:1; 1221 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 1222 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 1223#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 1224}; 1225 1226/* Normal architectures just use readl/write */ 1227static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) 1228{ 1229 u32 val; 1230 1231 val = readl(hsotg->regs + offset); 1232 if (hsotg->needs_byte_swap) 1233 return swab32(val); 1234 else 1235 return val; 1236} 1237 1238static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) 1239{ 1240 if (hsotg->needs_byte_swap) 1241 writel(swab32(value), hsotg->regs + offset); 1242 else 1243 writel(value, hsotg->regs + offset); 1244 1245#ifdef DWC2_LOG_WRITES 1246 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); 1247#endif 1248} 1249 1250static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, 1251 void *buffer, unsigned int count) 1252{ 1253 if (count) { 1254 u32 *buf = buffer; 1255 1256 do { 1257 u32 x = dwc2_readl(hsotg, offset); 1258 *buf++ = x; 1259 } while (--count); 1260 } 1261} 1262 1263static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, 1264 const void *buffer, unsigned int count) 1265{ 1266 if (count) { 1267 const u32 *buf = buffer; 1268 1269 do { 1270 dwc2_writel(hsotg, *buf++, offset); 1271 } while (--count); 1272 } 1273} 1274 1275/* Reasons for halting a host channel */ 1276enum dwc2_halt_status { 1277 DWC2_HC_XFER_NO_HALT_STATUS, 1278 DWC2_HC_XFER_COMPLETE, 1279 DWC2_HC_XFER_URB_COMPLETE, 1280 DWC2_HC_XFER_ACK, 1281 DWC2_HC_XFER_NAK, 1282 DWC2_HC_XFER_NYET, 1283 DWC2_HC_XFER_STALL, 1284 DWC2_HC_XFER_XACT_ERR, 1285 DWC2_HC_XFER_FRAME_OVERRUN, 1286 DWC2_HC_XFER_BABBLE_ERR, 1287 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1288 DWC2_HC_XFER_AHB_ERR, 1289 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1290 DWC2_HC_XFER_URB_DEQUEUE, 1291}; 1292 1293/* Core version information */ 1294static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg) 1295{ 1296 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000; 1297} 1298 1299static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg) 1300{ 1301 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000; 1302} 1303 1304static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg) 1305{ 1306 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000; 1307} 1308 1309/* 1310 * The following functions support initialization of the core driver component 1311 * and the DWC_otg controller 1312 */ 1313int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait); 1314int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1315int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 1316 bool restore); 1317int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host); 1318int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 1319 int reset, int is_host); 1320void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg); 1321int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy); 1322 1323void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host); 1324void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1325 1326bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1327 1328int dwc2_check_core_version(struct dwc2_hsotg *hsotg); 1329 1330/* 1331 * Common core Functions. 1332 * The following functions support managing the DWC_otg controller in either 1333 * device or host mode. 1334 */ 1335void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1336void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1337void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1338 1339void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1340void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1341 1342void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 1343 int is_host); 1344int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg); 1345int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg); 1346 1347void dwc2_enable_acg(struct dwc2_hsotg *hsotg); 1348 1349/* This function should be called on every hardware interrupt. */ 1350irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1351 1352/* The device ID match table */ 1353extern const struct of_device_id dwc2_of_match_table[]; 1354extern const struct acpi_device_id dwc2_acpi_match[]; 1355 1356int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1357int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1358 1359/* Common polling functions */ 1360int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1361 u32 timeout); 1362int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit, 1363 u32 timeout); 1364/* Parameters */ 1365int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1366int dwc2_init_params(struct dwc2_hsotg *hsotg); 1367 1368/* 1369 * The following functions check the controller's OTG operation mode 1370 * capability (GHWCFG2.OTG_MODE). 1371 * 1372 * These functions can be used before the internal hsotg->hw_params 1373 * are read in and cached so they always read directly from the 1374 * GHWCFG2 register. 1375 */ 1376unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg); 1377bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1378bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1379bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1380 1381/* 1382 * Returns the mode of operation, host or device 1383 */ 1384static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1385{ 1386 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1387} 1388 1389static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1390{ 1391 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1392} 1393 1394int dwc2_drd_init(struct dwc2_hsotg *hsotg); 1395void dwc2_drd_suspend(struct dwc2_hsotg *hsotg); 1396void dwc2_drd_resume(struct dwc2_hsotg *hsotg); 1397void dwc2_drd_exit(struct dwc2_hsotg *hsotg); 1398 1399/* 1400 * Dump core registers and SPRAM 1401 */ 1402void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1403void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1404void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1405 1406/* Gadget defines */ 1407#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 1408 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1409int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1410int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1411int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1412int dwc2_gadget_init(struct dwc2_hsotg *hsotg); 1413void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1414 bool reset); 1415void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg); 1416void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1417void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1418int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1419#define dwc2_is_device_connected(hsotg) (hsotg->connected) 1420int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1421int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup); 1422int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg); 1423int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1424 int rem_wakeup, int reset); 1425int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1426int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1427 bool restore); 1428void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg); 1429void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1430 int rem_wakeup); 1431int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg); 1432int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg); 1433int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg); 1434void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg); 1435void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg); 1436static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) 1437{ hsotg->fifo_map = 0; } 1438#else 1439static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1440{ return 0; } 1441static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1442{ return 0; } 1443static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1444{ return 0; } 1445static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg) 1446{ return 0; } 1447static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1448 bool reset) {} 1449static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {} 1450static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1451static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1452static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1453 int testmode) 1454{ return 0; } 1455#define dwc2_is_device_connected(hsotg) (0) 1456static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1457{ return 0; } 1458static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, 1459 int remote_wakeup) 1460{ return 0; } 1461static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) 1462{ return 0; } 1463static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, 1464 int rem_wakeup, int reset) 1465{ return 0; } 1466static inline int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1467{ return 0; } 1468static inline int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1469 bool restore) 1470{ return 0; } 1471static inline void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1472static inline void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, 1473 int rem_wakeup) {} 1474static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg) 1475{ return 0; } 1476static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg) 1477{ return 0; } 1478static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg) 1479{ return 0; } 1480static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {} 1481static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {} 1482static inline void dwc2_clear_fifo_map(struct dwc2_hsotg *hsotg) {} 1483#endif 1484 1485#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1486int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1487int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1488void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1489void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1490void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1491int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup); 1492int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex); 1493int dwc2_port_resume(struct dwc2_hsotg *hsotg); 1494int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1495int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1496int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg); 1497int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1498 int rem_wakeup, int reset); 1499int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg); 1500int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1501 int rem_wakeup, bool restore); 1502void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg); 1503void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup); 1504bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2); 1505static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) 1506{ schedule_work(&hsotg->phy_reset_work); } 1507#else 1508static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1509{ return 0; } 1510static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1511 int us) 1512{ return 0; } 1513static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1514static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1515static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1516static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1517static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 1518{ return 0; } 1519static inline int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1520{ return 0; } 1521static inline int dwc2_port_resume(struct dwc2_hsotg *hsotg) 1522{ return 0; } 1523static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 1524{ return 0; } 1525static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1526{ return 0; } 1527static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1528{ return 0; } 1529static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 1530{ return 0; } 1531static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, 1532 int rem_wakeup, int reset) 1533{ return 0; } 1534static inline int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) 1535{ return 0; } 1536static inline int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 1537 int rem_wakeup, bool restore) 1538{ return 0; } 1539static inline void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) {} 1540static inline void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, 1541 int rem_wakeup) {} 1542static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) 1543{ return false; } 1544static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {} 1545 1546#endif 1547 1548#endif /* __DWC2_CORE_H__ */ 1549