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42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/spinlock.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/delay.h>
49#include <linux/io.h>
50#include <linux/slab.h>
51#include <linux/usb.h>
52
53#include <linux/usb/hcd.h>
54#include <linux/usb/ch11.h>
55
56#include "core.h"
57#include "hcd.h"
58
59
60
61
62
63
64
65
66
67
68
69
70
71static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
72{
73 u32 intmsk;
74
75
76 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
77
78
79 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
80
81
82 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
83
84 if (!hsotg->params.host_dma)
85 intmsk |= GINTSTS_RXFLVL;
86 if (!hsotg->params.external_id_pin_ctl)
87 intmsk |= GINTSTS_CONIDSTSCHNG;
88
89 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
90 GINTSTS_SESSREQINT;
91
92 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
93 intmsk |= GINTSTS_LPMTRANRCVD;
94
95 dwc2_writel(hsotg, intmsk, GINTMSK);
96}
97
98static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
99{
100 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
101
102 switch (hsotg->hw_params.arch) {
103 case GHWCFG2_EXT_DMA_ARCH:
104 dev_err(hsotg->dev, "External DMA Mode not supported\n");
105 return -EINVAL;
106
107 case GHWCFG2_INT_DMA_ARCH:
108 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
109 if (hsotg->params.ahbcfg != -1) {
110 ahbcfg &= GAHBCFG_CTRL_MASK;
111 ahbcfg |= hsotg->params.ahbcfg &
112 ~GAHBCFG_CTRL_MASK;
113 }
114 break;
115
116 case GHWCFG2_SLAVE_ONLY_ARCH:
117 default:
118 dev_dbg(hsotg->dev, "Slave Only Mode\n");
119 break;
120 }
121
122 if (hsotg->params.host_dma)
123 ahbcfg |= GAHBCFG_DMA_EN;
124 else
125 hsotg->params.dma_desc_enable = false;
126
127 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
128
129 return 0;
130}
131
132static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
133{
134 u32 usbcfg;
135
136 usbcfg = dwc2_readl(hsotg, GUSBCFG);
137 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
138
139 switch (hsotg->hw_params.op_mode) {
140 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
141 if (hsotg->params.otg_cap ==
142 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
143 usbcfg |= GUSBCFG_HNPCAP;
144 if (hsotg->params.otg_cap !=
145 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
146 usbcfg |= GUSBCFG_SRPCAP;
147 break;
148
149 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
150 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
151 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
152 if (hsotg->params.otg_cap !=
153 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
154 usbcfg |= GUSBCFG_SRPCAP;
155 break;
156
157 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
158 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
159 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
160 default:
161 break;
162 }
163
164 dwc2_writel(hsotg, usbcfg, GUSBCFG);
165}
166
167static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
168{
169 if (hsotg->vbus_supply)
170 return regulator_enable(hsotg->vbus_supply);
171
172 return 0;
173}
174
175static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
176{
177 if (hsotg->vbus_supply)
178 return regulator_disable(hsotg->vbus_supply);
179
180 return 0;
181}
182
183
184
185
186
187
188static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
189{
190 u32 intmsk;
191
192 dev_dbg(hsotg->dev, "%s()\n", __func__);
193
194
195 dwc2_writel(hsotg, 0, GINTMSK);
196 dwc2_writel(hsotg, 0, HAINTMSK);
197
198
199 dwc2_enable_common_interrupts(hsotg);
200
201
202 intmsk = dwc2_readl(hsotg, GINTMSK);
203 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
204 dwc2_writel(hsotg, intmsk, GINTMSK);
205}
206
207
208
209
210
211
212static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
213{
214 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
215
216
217 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
218 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
219 dwc2_writel(hsotg, intmsk, GINTMSK);
220}
221
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223
224
225
226
227
228
229static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
230{
231 struct dwc2_core_params *params = &hsotg->params;
232 struct dwc2_hw_params *hw = &hsotg->hw_params;
233 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
234
235 total_fifo_size = hw->total_fifo_size;
236 rxfsiz = params->host_rx_fifo_size;
237 nptxfsiz = params->host_nperio_tx_fifo_size;
238 ptxfsiz = params->host_perio_tx_fifo_size;
239
240
241
242
243
244
245
246 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
247
248
249
250
251
252
253 rxfsiz = 516 + hw->host_channels;
254
255
256
257
258
259
260 nptxfsiz = 256;
261
262
263
264
265
266
267 ptxfsiz = 768;
268
269 params->host_rx_fifo_size = rxfsiz;
270 params->host_nperio_tx_fifo_size = nptxfsiz;
271 params->host_perio_tx_fifo_size = ptxfsiz;
272 }
273
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280
281
282
283
284 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
285 dev_err(hsotg->dev, "invalid fifo sizes\n");
286}
287
288static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
289{
290 struct dwc2_core_params *params = &hsotg->params;
291 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
292
293 if (!params->enable_dynamic_fifo)
294 return;
295
296 dwc2_calculate_dynamic_fifo(hsotg);
297
298
299 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
300 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
301 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
302 grxfsiz |= params->host_rx_fifo_size <<
303 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
304 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
305 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
306 dwc2_readl(hsotg, GRXFSIZ));
307
308
309 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
310 dwc2_readl(hsotg, GNPTXFSIZ));
311 nptxfsiz = params->host_nperio_tx_fifo_size <<
312 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
313 nptxfsiz |= params->host_rx_fifo_size <<
314 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
315 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
316 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
317 dwc2_readl(hsotg, GNPTXFSIZ));
318
319
320 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
321 dwc2_readl(hsotg, HPTXFSIZ));
322 hptxfsiz = params->host_perio_tx_fifo_size <<
323 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
324 hptxfsiz |= (params->host_rx_fifo_size +
325 params->host_nperio_tx_fifo_size) <<
326 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
327 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
328 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
329 dwc2_readl(hsotg, HPTXFSIZ));
330
331 if (hsotg->params.en_multiple_tx_fifo &&
332 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
333
334
335
336
337
338 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
339 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
340 dfifocfg |= (params->host_rx_fifo_size +
341 params->host_nperio_tx_fifo_size +
342 params->host_perio_tx_fifo_size) <<
343 GDFIFOCFG_EPINFOBASE_SHIFT &
344 GDFIFOCFG_EPINFOBASE_MASK;
345 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
346 }
347}
348
349
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351
352
353
354
355
356
357
358
359u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
360{
361 u32 usbcfg;
362 u32 hprt0;
363 int clock = 60;
364
365 usbcfg = dwc2_readl(hsotg, GUSBCFG);
366 hprt0 = dwc2_readl(hsotg, HPRT0);
367
368 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
369 !(usbcfg & GUSBCFG_PHYIF16))
370 clock = 60;
371 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
372 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
373 clock = 48;
374 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
375 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
376 clock = 30;
377 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
378 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
379 clock = 60;
380 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
381 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
382 clock = 48;
383 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
384 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
385 clock = 48;
386 if ((usbcfg & GUSBCFG_PHYSEL) &&
387 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
388 clock = 48;
389
390 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
391
392 return 125 * clock - 1;
393
394
395 return 1000 * clock - 1;
396}
397
398
399
400
401
402
403
404
405
406void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
407{
408 u32 *data_buf = (u32 *)dest;
409 int word_count = (bytes + 3) / 4;
410 int i;
411
412
413
414
415
416
417
418 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
419
420 for (i = 0; i < word_count; i++, data_buf++)
421 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
422}
423
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425
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430
431
432
433
434
435static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
436 struct dwc2_host_chan *chan)
437{
438#ifdef VERBOSE_DEBUG
439 int num_channels = hsotg->params.host_channels;
440 struct dwc2_qh *qh;
441 u32 hcchar;
442 u32 hcsplt;
443 u32 hctsiz;
444 u32 hc_dma;
445 int i;
446
447 if (!chan)
448 return;
449
450 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
451 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
452 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
453 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
454
455 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
456 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
457 hcchar, hcsplt);
458 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
459 hctsiz, hc_dma);
460 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
461 chan->dev_addr, chan->ep_num, chan->ep_is_in);
462 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
463 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
464 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
465 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
466 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
467 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
468 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
469 (unsigned long)chan->xfer_dma);
470 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
471 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
472 dev_dbg(hsotg->dev, " NP inactive sched:\n");
473 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
474 qh_list_entry)
475 dev_dbg(hsotg->dev, " %p\n", qh);
476 dev_dbg(hsotg->dev, " NP waiting sched:\n");
477 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
478 qh_list_entry)
479 dev_dbg(hsotg->dev, " %p\n", qh);
480 dev_dbg(hsotg->dev, " NP active sched:\n");
481 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
482 qh_list_entry)
483 dev_dbg(hsotg->dev, " %p\n", qh);
484 dev_dbg(hsotg->dev, " Channels:\n");
485 for (i = 0; i < num_channels; i++) {
486 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
487
488 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
489 }
490#endif
491}
492
493static int _dwc2_hcd_start(struct usb_hcd *hcd);
494
495static void dwc2_host_start(struct dwc2_hsotg *hsotg)
496{
497 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
498
499 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
500 _dwc2_hcd_start(hcd);
501}
502
503static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
504{
505 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
506
507 hcd->self.is_b_host = 0;
508}
509
510static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
511 int *hub_addr, int *hub_port)
512{
513 struct urb *urb = context;
514
515 if (urb->dev->tt)
516 *hub_addr = urb->dev->tt->hub->devnum;
517 else
518 *hub_addr = 0;
519 *hub_port = urb->dev->ttport;
520}
521
522
523
524
525
526
527
528static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
529 struct dwc2_host_chan *chan)
530{
531 u32 hcintmsk = HCINTMSK_CHHLTD;
532
533 switch (chan->ep_type) {
534 case USB_ENDPOINT_XFER_CONTROL:
535 case USB_ENDPOINT_XFER_BULK:
536 dev_vdbg(hsotg->dev, "control/bulk\n");
537 hcintmsk |= HCINTMSK_XFERCOMPL;
538 hcintmsk |= HCINTMSK_STALL;
539 hcintmsk |= HCINTMSK_XACTERR;
540 hcintmsk |= HCINTMSK_DATATGLERR;
541 if (chan->ep_is_in) {
542 hcintmsk |= HCINTMSK_BBLERR;
543 } else {
544 hcintmsk |= HCINTMSK_NAK;
545 hcintmsk |= HCINTMSK_NYET;
546 if (chan->do_ping)
547 hcintmsk |= HCINTMSK_ACK;
548 }
549
550 if (chan->do_split) {
551 hcintmsk |= HCINTMSK_NAK;
552 if (chan->complete_split)
553 hcintmsk |= HCINTMSK_NYET;
554 else
555 hcintmsk |= HCINTMSK_ACK;
556 }
557
558 if (chan->error_state)
559 hcintmsk |= HCINTMSK_ACK;
560 break;
561
562 case USB_ENDPOINT_XFER_INT:
563 if (dbg_perio())
564 dev_vdbg(hsotg->dev, "intr\n");
565 hcintmsk |= HCINTMSK_XFERCOMPL;
566 hcintmsk |= HCINTMSK_NAK;
567 hcintmsk |= HCINTMSK_STALL;
568 hcintmsk |= HCINTMSK_XACTERR;
569 hcintmsk |= HCINTMSK_DATATGLERR;
570 hcintmsk |= HCINTMSK_FRMOVRUN;
571
572 if (chan->ep_is_in)
573 hcintmsk |= HCINTMSK_BBLERR;
574 if (chan->error_state)
575 hcintmsk |= HCINTMSK_ACK;
576 if (chan->do_split) {
577 if (chan->complete_split)
578 hcintmsk |= HCINTMSK_NYET;
579 else
580 hcintmsk |= HCINTMSK_ACK;
581 }
582 break;
583
584 case USB_ENDPOINT_XFER_ISOC:
585 if (dbg_perio())
586 dev_vdbg(hsotg->dev, "isoc\n");
587 hcintmsk |= HCINTMSK_XFERCOMPL;
588 hcintmsk |= HCINTMSK_FRMOVRUN;
589 hcintmsk |= HCINTMSK_ACK;
590
591 if (chan->ep_is_in) {
592 hcintmsk |= HCINTMSK_XACTERR;
593 hcintmsk |= HCINTMSK_BBLERR;
594 }
595 break;
596 default:
597 dev_err(hsotg->dev, "## Unknown EP type ##\n");
598 break;
599 }
600
601 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
602 if (dbg_hc(chan))
603 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
604}
605
606static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
607 struct dwc2_host_chan *chan)
608{
609 u32 hcintmsk = HCINTMSK_CHHLTD;
610
611
612
613
614
615 if (!hsotg->params.dma_desc_enable) {
616 if (dbg_hc(chan))
617 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
618 hcintmsk |= HCINTMSK_AHBERR;
619 } else {
620 if (dbg_hc(chan))
621 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
622 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
623 hcintmsk |= HCINTMSK_XFERCOMPL;
624 }
625
626 if (chan->error_state && !chan->do_split &&
627 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
628 if (dbg_hc(chan))
629 dev_vdbg(hsotg->dev, "setting ACK\n");
630 hcintmsk |= HCINTMSK_ACK;
631 if (chan->ep_is_in) {
632 hcintmsk |= HCINTMSK_DATATGLERR;
633 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
634 hcintmsk |= HCINTMSK_NAK;
635 }
636 }
637
638 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
639 if (dbg_hc(chan))
640 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
641}
642
643static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
644 struct dwc2_host_chan *chan)
645{
646 u32 intmsk;
647
648 if (hsotg->params.host_dma) {
649 if (dbg_hc(chan))
650 dev_vdbg(hsotg->dev, "DMA enabled\n");
651 dwc2_hc_enable_dma_ints(hsotg, chan);
652 } else {
653 if (dbg_hc(chan))
654 dev_vdbg(hsotg->dev, "DMA disabled\n");
655 dwc2_hc_enable_slave_ints(hsotg, chan);
656 }
657
658
659 intmsk = dwc2_readl(hsotg, HAINTMSK);
660 intmsk |= 1 << chan->hc_num;
661 dwc2_writel(hsotg, intmsk, HAINTMSK);
662 if (dbg_hc(chan))
663 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
664
665
666 intmsk = dwc2_readl(hsotg, GINTMSK);
667 intmsk |= GINTSTS_HCHINT;
668 dwc2_writel(hsotg, intmsk, GINTMSK);
669 if (dbg_hc(chan))
670 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
671}
672
673
674
675
676
677
678
679
680
681
682
683
684static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
685{
686 u8 hc_num = chan->hc_num;
687 u32 hcintmsk;
688 u32 hcchar;
689 u32 hcsplt = 0;
690
691 if (dbg_hc(chan))
692 dev_vdbg(hsotg->dev, "%s()\n", __func__);
693
694
695 hcintmsk = 0xffffffff;
696 hcintmsk &= ~HCINTMSK_RESERVED14_31;
697 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
698
699
700 dwc2_hc_enable_ints(hsotg, chan);
701
702
703
704
705
706 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
707 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
708 if (chan->ep_is_in)
709 hcchar |= HCCHAR_EPDIR;
710 if (chan->speed == USB_SPEED_LOW)
711 hcchar |= HCCHAR_LSPDDEV;
712 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
713 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
714 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
715 if (dbg_hc(chan)) {
716 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
717 hc_num, hcchar);
718
719 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
720 __func__, hc_num);
721 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
722 chan->dev_addr);
723 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
724 chan->ep_num);
725 dev_vdbg(hsotg->dev, " Is In: %d\n",
726 chan->ep_is_in);
727 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
728 chan->speed == USB_SPEED_LOW);
729 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
730 chan->ep_type);
731 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
732 chan->max_packet);
733 }
734
735
736 if (chan->do_split) {
737 if (dbg_hc(chan))
738 dev_vdbg(hsotg->dev,
739 "Programming HC %d with split --> %s\n",
740 hc_num,
741 chan->complete_split ? "CSPLIT" : "SSPLIT");
742 if (chan->complete_split)
743 hcsplt |= HCSPLT_COMPSPLT;
744 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
745 HCSPLT_XACTPOS_MASK;
746 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
747 HCSPLT_HUBADDR_MASK;
748 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
749 HCSPLT_PRTADDR_MASK;
750 if (dbg_hc(chan)) {
751 dev_vdbg(hsotg->dev, " comp split %d\n",
752 chan->complete_split);
753 dev_vdbg(hsotg->dev, " xact pos %d\n",
754 chan->xact_pos);
755 dev_vdbg(hsotg->dev, " hub addr %d\n",
756 chan->hub_addr);
757 dev_vdbg(hsotg->dev, " hub port %d\n",
758 chan->hub_port);
759 dev_vdbg(hsotg->dev, " is_in %d\n",
760 chan->ep_is_in);
761 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
762 chan->max_packet);
763 dev_vdbg(hsotg->dev, " xferlen %d\n",
764 chan->xfer_len);
765 }
766 }
767
768 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
769}
770
771
772
773
774
775
776
777
778
779
780
781
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784
785
786
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795
796
797
798
799void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
800 enum dwc2_halt_status halt_status)
801{
802 u32 nptxsts, hptxsts, hcchar;
803
804 if (dbg_hc(chan))
805 dev_vdbg(hsotg->dev, "%s()\n", __func__);
806
807
808
809
810
811
812
813 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
814 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
815 if (!chan->do_split &&
816 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
817 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
818 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
819 __func__);
820 return;
821 }
822 }
823
824 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
825 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
826
827 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
828 halt_status == DWC2_HC_XFER_AHB_ERR) {
829
830
831
832
833
834
835 u32 hcintmsk = HCINTMSK_CHHLTD;
836
837 dev_vdbg(hsotg->dev, "dequeue/error\n");
838 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
839
840
841
842
843
844
845 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
846
847
848
849
850
851
852 chan->halt_status = halt_status;
853
854 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
855 if (!(hcchar & HCCHAR_CHENA)) {
856
857
858
859
860
861
862
863
864
865
866
867 return;
868 }
869 }
870 if (chan->halt_pending) {
871
872
873
874
875
876 dev_vdbg(hsotg->dev,
877 "*** %s: Channel %d, chan->halt_pending already set ***\n",
878 __func__, chan->hc_num);
879 return;
880 }
881
882 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
883
884
885
886 if (!hsotg->params.dma_desc_enable) {
887 if (dbg_hc(chan))
888 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
889 hcchar |= HCCHAR_CHENA;
890 } else {
891 if (dbg_hc(chan))
892 dev_dbg(hsotg->dev, "desc DMA enabled\n");
893 }
894 hcchar |= HCCHAR_CHDIS;
895
896 if (!hsotg->params.host_dma) {
897 if (dbg_hc(chan))
898 dev_vdbg(hsotg->dev, "DMA not enabled\n");
899 hcchar |= HCCHAR_CHENA;
900
901
902 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
903 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
904 dev_vdbg(hsotg->dev, "control/bulk\n");
905 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
906 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
907 dev_vdbg(hsotg->dev, "Disabling channel\n");
908 hcchar &= ~HCCHAR_CHENA;
909 }
910 } else {
911 if (dbg_perio())
912 dev_vdbg(hsotg->dev, "isoc/intr\n");
913 hptxsts = dwc2_readl(hsotg, HPTXSTS);
914 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
915 hsotg->queuing_high_bandwidth) {
916 if (dbg_perio())
917 dev_vdbg(hsotg->dev, "Disabling channel\n");
918 hcchar &= ~HCCHAR_CHENA;
919 }
920 }
921 } else {
922 if (dbg_hc(chan))
923 dev_vdbg(hsotg->dev, "DMA enabled\n");
924 }
925
926 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
927 chan->halt_status = halt_status;
928
929 if (hcchar & HCCHAR_CHENA) {
930 if (dbg_hc(chan))
931 dev_vdbg(hsotg->dev, "Channel enabled\n");
932 chan->halt_pending = 1;
933 chan->halt_on_queue = 0;
934 } else {
935 if (dbg_hc(chan))
936 dev_vdbg(hsotg->dev, "Channel disabled\n");
937 chan->halt_on_queue = 1;
938 }
939
940 if (dbg_hc(chan)) {
941 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
942 chan->hc_num);
943 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
944 hcchar);
945 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
946 chan->halt_pending);
947 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
948 chan->halt_on_queue);
949 dev_vdbg(hsotg->dev, " halt_status: %d\n",
950 chan->halt_status);
951 }
952}
953
954
955
956
957
958
959
960
961
962
963void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
964{
965 u32 hcintmsk;
966
967 chan->xfer_started = 0;
968
969 list_del_init(&chan->split_order_list_entry);
970
971
972
973
974
975 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
976 hcintmsk = 0xffffffff;
977 hcintmsk &= ~HCINTMSK_RESERVED14_31;
978 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
979}
980
981
982
983
984
985
986
987
988
989
990
991static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
992 struct dwc2_host_chan *chan, u32 *hcchar)
993{
994 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
995 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
996 int host_speed;
997 int xfer_ns;
998 int xfer_us;
999 int bytes_in_fifo;
1000 u16 fifo_space;
1001 u16 frame_number;
1002 u16 wire_frame;
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028 host_speed = (chan->speed != USB_SPEED_HIGH &&
1029 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1030
1031
1032 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1033 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1034 bytes_in_fifo = sizeof(u32) *
1035 (hsotg->params.host_perio_tx_fifo_size -
1036 fifo_space);
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1047 chan->xfer_len + bytes_in_fifo);
1048 xfer_us = NS_TO_US(xfer_ns);
1049
1050
1051 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1052
1053
1054 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1055
1056
1057
1058
1059
1060
1061
1062
1063 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1064 dwc2_sch_vdbg(hsotg,
1065 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1066 chan->qh, wire_frame, frame_number,
1067 dwc2_frame_num_dec(frame_number,
1068 wire_frame));
1069 wire_frame = frame_number;
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079 chan->qh->next_active_frame =
1080 dwc2_frame_num_dec(frame_number, 1);
1081 }
1082
1083 if (wire_frame & 1)
1084 *hcchar |= HCCHAR_ODDFRM;
1085 else
1086 *hcchar &= ~HCCHAR_ODDFRM;
1087 }
1088}
1089
1090static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1091{
1092
1093 if (chan->speed == USB_SPEED_HIGH) {
1094 if (chan->ep_is_in) {
1095 if (chan->multi_count == 1)
1096 chan->data_pid_start = DWC2_HC_PID_DATA0;
1097 else if (chan->multi_count == 2)
1098 chan->data_pid_start = DWC2_HC_PID_DATA1;
1099 else
1100 chan->data_pid_start = DWC2_HC_PID_DATA2;
1101 } else {
1102 if (chan->multi_count == 1)
1103 chan->data_pid_start = DWC2_HC_PID_DATA0;
1104 else
1105 chan->data_pid_start = DWC2_HC_PID_MDATA;
1106 }
1107 } else {
1108 chan->data_pid_start = DWC2_HC_PID_DATA0;
1109 }
1110}
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1127 struct dwc2_host_chan *chan)
1128{
1129 u32 i;
1130 u32 remaining_count;
1131 u32 byte_count;
1132 u32 dword_count;
1133 u32 *data_buf = (u32 *)chan->xfer_buf;
1134
1135 if (dbg_hc(chan))
1136 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1137
1138 remaining_count = chan->xfer_len - chan->xfer_count;
1139 if (remaining_count > chan->max_packet)
1140 byte_count = chan->max_packet;
1141 else
1142 byte_count = remaining_count;
1143
1144 dword_count = (byte_count + 3) / 4;
1145
1146 if (((unsigned long)data_buf & 0x3) == 0) {
1147
1148 for (i = 0; i < dword_count; i++, data_buf++)
1149 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1150 } else {
1151
1152 for (i = 0; i < dword_count; i++, data_buf++) {
1153 u32 data = data_buf[0] | data_buf[1] << 8 |
1154 data_buf[2] << 16 | data_buf[3] << 24;
1155 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1156 }
1157 }
1158
1159 chan->xfer_count += byte_count;
1160 chan->xfer_buf += byte_count;
1161}
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1173 struct dwc2_host_chan *chan)
1174{
1175 u32 hcchar;
1176 u32 hctsiz;
1177
1178 if (dbg_hc(chan))
1179 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1180 chan->hc_num);
1181
1182 hctsiz = TSIZ_DOPNG;
1183 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1184 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1185
1186 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1187 hcchar |= HCCHAR_CHENA;
1188 hcchar &= ~HCCHAR_CHDIS;
1189 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1190}
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1226 struct dwc2_host_chan *chan)
1227{
1228 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1229 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1230 u32 hcchar;
1231 u32 hctsiz = 0;
1232 u16 num_packets;
1233 u32 ec_mc;
1234
1235 if (dbg_hc(chan))
1236 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1237
1238 if (chan->do_ping) {
1239 if (!hsotg->params.host_dma) {
1240 if (dbg_hc(chan))
1241 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1242 dwc2_hc_do_ping(hsotg, chan);
1243 chan->xfer_started = 1;
1244 return;
1245 }
1246
1247 if (dbg_hc(chan))
1248 dev_vdbg(hsotg->dev, "ping, DMA\n");
1249
1250 hctsiz |= TSIZ_DOPNG;
1251 }
1252
1253 if (chan->do_split) {
1254 if (dbg_hc(chan))
1255 dev_vdbg(hsotg->dev, "split\n");
1256 num_packets = 1;
1257
1258 if (chan->complete_split && !chan->ep_is_in)
1259
1260
1261
1262
1263 chan->xfer_len = 0;
1264 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1265 chan->xfer_len = chan->max_packet;
1266 else if (!chan->ep_is_in && chan->xfer_len > 188)
1267 chan->xfer_len = 188;
1268
1269 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1270 TSIZ_XFERSIZE_MASK;
1271
1272
1273 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1274 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1275 ec_mc = 3;
1276 else
1277 ec_mc = 1;
1278 } else {
1279 if (dbg_hc(chan))
1280 dev_vdbg(hsotg->dev, "no split\n");
1281
1282
1283
1284
1285 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1286 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1287
1288
1289
1290
1291
1292
1293
1294 u32 max_periodic_len =
1295 chan->multi_count * chan->max_packet;
1296
1297 if (chan->xfer_len > max_periodic_len)
1298 chan->xfer_len = max_periodic_len;
1299 } else if (chan->xfer_len > max_hc_xfer_size) {
1300
1301
1302
1303
1304 chan->xfer_len =
1305 max_hc_xfer_size - chan->max_packet + 1;
1306 }
1307
1308 if (chan->xfer_len > 0) {
1309 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1310 chan->max_packet;
1311 if (num_packets > max_hc_pkt_count) {
1312 num_packets = max_hc_pkt_count;
1313 chan->xfer_len = num_packets * chan->max_packet;
1314 } else if (chan->ep_is_in) {
1315
1316
1317
1318
1319
1320
1321 chan->xfer_len = num_packets * chan->max_packet;
1322 }
1323 } else {
1324
1325 num_packets = 1;
1326 }
1327
1328 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1329 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1330
1331
1332
1333
1334 chan->multi_count = num_packets;
1335
1336 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1337 dwc2_set_pid_isoc(chan);
1338
1339 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1340 TSIZ_XFERSIZE_MASK;
1341
1342
1343 ec_mc = chan->multi_count;
1344 }
1345
1346 chan->start_pkt_count = num_packets;
1347 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1348 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1349 TSIZ_SC_MC_PID_MASK;
1350 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1351 if (dbg_hc(chan)) {
1352 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1353 hctsiz, chan->hc_num);
1354
1355 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1356 chan->hc_num);
1357 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1358 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1359 TSIZ_XFERSIZE_SHIFT);
1360 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1361 (hctsiz & TSIZ_PKTCNT_MASK) >>
1362 TSIZ_PKTCNT_SHIFT);
1363 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1364 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1365 TSIZ_SC_MC_PID_SHIFT);
1366 }
1367
1368 if (hsotg->params.host_dma) {
1369 dma_addr_t dma_addr;
1370
1371 if (chan->align_buf) {
1372 if (dbg_hc(chan))
1373 dev_vdbg(hsotg->dev, "align_buf\n");
1374 dma_addr = chan->align_buf;
1375 } else {
1376 dma_addr = chan->xfer_dma;
1377 }
1378 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1379
1380 if (dbg_hc(chan))
1381 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1382 (unsigned long)dma_addr, chan->hc_num);
1383 }
1384
1385
1386 if (chan->do_split) {
1387 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1388
1389 hcsplt |= HCSPLT_SPLTENA;
1390 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1391 }
1392
1393 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1394 hcchar &= ~HCCHAR_MULTICNT_MASK;
1395 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1396 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1397
1398 if (hcchar & HCCHAR_CHDIS)
1399 dev_warn(hsotg->dev,
1400 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1401 __func__, chan->hc_num, hcchar);
1402
1403
1404 hcchar |= HCCHAR_CHENA;
1405 hcchar &= ~HCCHAR_CHDIS;
1406
1407 if (dbg_hc(chan))
1408 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1409 (hcchar & HCCHAR_MULTICNT_MASK) >>
1410 HCCHAR_MULTICNT_SHIFT);
1411
1412 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1413 if (dbg_hc(chan))
1414 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1415 chan->hc_num);
1416
1417 chan->xfer_started = 1;
1418 chan->requests++;
1419
1420 if (!hsotg->params.host_dma &&
1421 !chan->ep_is_in && chan->xfer_len > 0)
1422
1423 dwc2_hc_write_packet(hsotg, chan);
1424}
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1441 struct dwc2_host_chan *chan)
1442{
1443 u32 hcchar;
1444 u32 hctsiz = 0;
1445
1446 if (chan->do_ping)
1447 hctsiz |= TSIZ_DOPNG;
1448
1449 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1450 dwc2_set_pid_isoc(chan);
1451
1452
1453 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1454 TSIZ_SC_MC_PID_MASK;
1455
1456
1457 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1458
1459
1460 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1461
1462 if (dbg_hc(chan)) {
1463 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1464 chan->hc_num);
1465 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1466 chan->data_pid_start);
1467 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1468 }
1469
1470 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1471
1472 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1473 chan->desc_list_sz, DMA_TO_DEVICE);
1474
1475 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1476
1477 if (dbg_hc(chan))
1478 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1479 &chan->desc_list_addr, chan->hc_num);
1480
1481 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1482 hcchar &= ~HCCHAR_MULTICNT_MASK;
1483 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1484 HCCHAR_MULTICNT_MASK;
1485
1486 if (hcchar & HCCHAR_CHDIS)
1487 dev_warn(hsotg->dev,
1488 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1489 __func__, chan->hc_num, hcchar);
1490
1491
1492 hcchar |= HCCHAR_CHENA;
1493 hcchar &= ~HCCHAR_CHDIS;
1494
1495 if (dbg_hc(chan))
1496 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1497 (hcchar & HCCHAR_MULTICNT_MASK) >>
1498 HCCHAR_MULTICNT_SHIFT);
1499
1500 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1501 if (dbg_hc(chan))
1502 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1503 chan->hc_num);
1504
1505 chan->xfer_started = 1;
1506 chan->requests++;
1507}
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1530 struct dwc2_host_chan *chan)
1531{
1532 if (dbg_hc(chan))
1533 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1534 chan->hc_num);
1535
1536 if (chan->do_split)
1537
1538 return 0;
1539
1540 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1541
1542 return 0;
1543
1544 if (chan->ep_is_in) {
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1558
1559 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1560 hcchar |= HCCHAR_CHENA;
1561 hcchar &= ~HCCHAR_CHDIS;
1562 if (dbg_hc(chan))
1563 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1564 hcchar);
1565 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1566 chan->requests++;
1567 return 1;
1568 }
1569
1570
1571
1572 if (chan->xfer_count < chan->xfer_len) {
1573 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1574 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1575 u32 hcchar = dwc2_readl(hsotg,
1576 HCCHAR(chan->hc_num));
1577
1578 dwc2_hc_set_even_odd_frame(hsotg, chan,
1579 &hcchar);
1580 }
1581
1582
1583 dwc2_hc_write_packet(hsotg, chan);
1584 chan->requests++;
1585 return 1;
1586 }
1587
1588 return 0;
1589}
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1604 struct list_head *qh_list)
1605{
1606 struct dwc2_qh *qh, *qh_tmp;
1607 struct dwc2_qtd *qtd, *qtd_tmp;
1608
1609 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1610 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1611 qtd_list_entry) {
1612 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1613 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1614 }
1615 }
1616}
1617
1618static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1619 struct list_head *qh_list)
1620{
1621 struct dwc2_qtd *qtd, *qtd_tmp;
1622 struct dwc2_qh *qh, *qh_tmp;
1623 unsigned long flags;
1624
1625 if (!qh_list->next)
1626
1627 return;
1628
1629 spin_lock_irqsave(&hsotg->lock, flags);
1630
1631
1632 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1633
1634 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1635 dwc2_hcd_qh_unlink(hsotg, qh);
1636
1637
1638 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1639 qtd_list_entry)
1640 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1641
1642 if (qh->channel && qh->channel->qh == qh)
1643 qh->channel->qh = NULL;
1644
1645 spin_unlock_irqrestore(&hsotg->lock, flags);
1646 dwc2_hcd_qh_free(hsotg, qh);
1647 spin_lock_irqsave(&hsotg->lock, flags);
1648 }
1649
1650 spin_unlock_irqrestore(&hsotg->lock, flags);
1651}
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1662{
1663 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1664 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1665 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1666 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1667 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1668 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1669 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1670}
1671
1672
1673
1674
1675
1676
1677void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1678{
1679 u32 hprt0;
1680
1681 if (hsotg->op_state == OTG_STATE_B_HOST) {
1682
1683
1684
1685
1686
1687 hprt0 = dwc2_read_hprt0(hsotg);
1688 hprt0 |= HPRT0_RST;
1689 dwc2_writel(hsotg, hprt0, HPRT0);
1690 }
1691
1692 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1693 msecs_to_jiffies(50));
1694}
1695
1696
1697static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1698{
1699 int num_channels = hsotg->params.host_channels;
1700 struct dwc2_host_chan *channel;
1701 u32 hcchar;
1702 int i;
1703
1704 if (!hsotg->params.host_dma) {
1705
1706 for (i = 0; i < num_channels; i++) {
1707 channel = hsotg->hc_ptr_array[i];
1708 if (!list_empty(&channel->hc_list_entry))
1709 continue;
1710 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1711 if (hcchar & HCCHAR_CHENA) {
1712 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1713 hcchar |= HCCHAR_CHDIS;
1714 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1715 }
1716 }
1717 }
1718
1719 for (i = 0; i < num_channels; i++) {
1720 channel = hsotg->hc_ptr_array[i];
1721 if (!list_empty(&channel->hc_list_entry))
1722 continue;
1723 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1724 if (hcchar & HCCHAR_CHENA) {
1725
1726 hcchar |= HCCHAR_CHDIS;
1727 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1728 }
1729
1730 dwc2_hc_cleanup(hsotg, channel);
1731 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1732
1733
1734
1735
1736
1737 channel->qh = NULL;
1738 }
1739
1740 if (hsotg->params.uframe_sched) {
1741 hsotg->available_host_channels =
1742 hsotg->params.host_channels;
1743 } else {
1744 hsotg->non_periodic_channels = 0;
1745 hsotg->periodic_channels = 0;
1746 }
1747}
1748
1749
1750
1751
1752
1753
1754
1755
1756void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1757{
1758 if (hsotg->lx_state != DWC2_L0)
1759 usb_hcd_resume_root_hub(hsotg->priv);
1760
1761 hsotg->flags.b.port_connect_status_change = 1;
1762 hsotg->flags.b.port_connect_status = 1;
1763}
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1774{
1775 u32 intr;
1776 u32 hprt0;
1777
1778
1779 hsotg->flags.b.port_connect_status_change = 1;
1780 hsotg->flags.b.port_connect_status = 0;
1781
1782
1783
1784
1785
1786
1787 intr = dwc2_readl(hsotg, GINTMSK);
1788 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1789 dwc2_writel(hsotg, intr, GINTMSK);
1790 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1791 dwc2_writel(hsotg, intr, GINTSTS);
1792
1793
1794
1795
1796
1797
1798 if (dwc2_is_device_mode(hsotg)) {
1799 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1800 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1801 dwc2_writel(hsotg, 0, HPRT0);
1802 }
1803
1804 dwc2_disable_host_interrupts(hsotg);
1805 }
1806
1807
1808 dwc2_kill_all_urbs(hsotg);
1809
1810 if (dwc2_is_host_mode(hsotg))
1811
1812 dwc2_hcd_cleanup_channels(hsotg);
1813
1814 dwc2_host_disconnect(hsotg);
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828 if (!force) {
1829 hprt0 = dwc2_readl(hsotg, HPRT0);
1830 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
1831 dwc2_hcd_connect(hsotg);
1832 }
1833}
1834
1835
1836
1837
1838
1839
1840static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1841{
1842 if (hsotg->bus_suspended) {
1843 hsotg->flags.b.port_suspend_change = 1;
1844 usb_hcd_resume_root_hub(hsotg->priv);
1845 }
1846
1847 if (hsotg->lx_state == DWC2_L1)
1848 hsotg->flags.b.port_l1_change = 1;
1849}
1850
1851
1852
1853
1854
1855
1856
1857
1858void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1859{
1860 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1861
1862
1863
1864
1865
1866
1867
1868
1869 dwc2_disable_host_interrupts(hsotg);
1870
1871
1872 dev_dbg(hsotg->dev, "PortPower off\n");
1873 dwc2_writel(hsotg, 0, HPRT0);
1874}
1875
1876
1877static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
1878 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
1879 struct dwc2_qtd *qtd)
1880{
1881 u32 intr_mask;
1882 int retval;
1883 int dev_speed;
1884
1885 if (!hsotg->flags.b.port_connect_status) {
1886
1887 dev_err(hsotg->dev, "Not connected\n");
1888 return -ENODEV;
1889 }
1890
1891 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1892
1893
1894 if ((dev_speed == USB_SPEED_LOW) &&
1895 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
1896 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
1897 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
1898 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1899
1900 if (prtspd == HPRT0_SPD_FULL_SPEED)
1901 return -ENODEV;
1902 }
1903
1904 if (!qtd)
1905 return -EINVAL;
1906
1907 dwc2_hcd_qtd_init(qtd, urb);
1908 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
1909 if (retval) {
1910 dev_err(hsotg->dev,
1911 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
1912 retval);
1913 return retval;
1914 }
1915
1916 intr_mask = dwc2_readl(hsotg, GINTMSK);
1917 if (!(intr_mask & GINTSTS_SOF)) {
1918 enum dwc2_transaction_type tr_type;
1919
1920 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
1921 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
1922
1923
1924
1925
1926 return 0;
1927
1928 tr_type = dwc2_hcd_select_transactions(hsotg);
1929 if (tr_type != DWC2_TRANSACTION_NONE)
1930 dwc2_hcd_queue_transactions(hsotg, tr_type);
1931 }
1932
1933 return 0;
1934}
1935
1936
1937static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
1938 struct dwc2_hcd_urb *urb)
1939{
1940 struct dwc2_qh *qh;
1941 struct dwc2_qtd *urb_qtd;
1942
1943 urb_qtd = urb->qtd;
1944 if (!urb_qtd) {
1945 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
1946 return -EINVAL;
1947 }
1948
1949 qh = urb_qtd->qh;
1950 if (!qh) {
1951 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
1952 return -EINVAL;
1953 }
1954
1955 urb->priv = NULL;
1956
1957 if (urb_qtd->in_process && qh->channel) {
1958 dwc2_dump_channel_info(hsotg, qh->channel);
1959
1960
1961 if (hsotg->flags.b.port_connect_status)
1962
1963
1964
1965
1966
1967
1968
1969 dwc2_hc_halt(hsotg, qh->channel,
1970 DWC2_HC_XFER_URB_DEQUEUE);
1971 }
1972
1973
1974
1975
1976
1977 if (!hsotg->params.dma_desc_enable) {
1978 u8 in_process = urb_qtd->in_process;
1979
1980 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1981 if (in_process) {
1982 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
1983 qh->channel = NULL;
1984 } else if (list_empty(&qh->qtd_list)) {
1985 dwc2_hcd_qh_unlink(hsotg, qh);
1986 }
1987 } else {
1988 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1989 }
1990
1991 return 0;
1992}
1993
1994
1995static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
1996 struct usb_host_endpoint *ep, int retry)
1997{
1998 struct dwc2_qtd *qtd, *qtd_tmp;
1999 struct dwc2_qh *qh;
2000 unsigned long flags;
2001 int rc;
2002
2003 spin_lock_irqsave(&hsotg->lock, flags);
2004
2005 qh = ep->hcpriv;
2006 if (!qh) {
2007 rc = -EINVAL;
2008 goto err;
2009 }
2010
2011 while (!list_empty(&qh->qtd_list) && retry--) {
2012 if (retry == 0) {
2013 dev_err(hsotg->dev,
2014 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2015 rc = -EBUSY;
2016 goto err;
2017 }
2018
2019 spin_unlock_irqrestore(&hsotg->lock, flags);
2020 msleep(20);
2021 spin_lock_irqsave(&hsotg->lock, flags);
2022 qh = ep->hcpriv;
2023 if (!qh) {
2024 rc = -EINVAL;
2025 goto err;
2026 }
2027 }
2028
2029 dwc2_hcd_qh_unlink(hsotg, qh);
2030
2031
2032 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2033 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2034
2035 ep->hcpriv = NULL;
2036
2037 if (qh->channel && qh->channel->qh == qh)
2038 qh->channel->qh = NULL;
2039
2040 spin_unlock_irqrestore(&hsotg->lock, flags);
2041
2042 dwc2_hcd_qh_free(hsotg, qh);
2043
2044 return 0;
2045
2046err:
2047 ep->hcpriv = NULL;
2048 spin_unlock_irqrestore(&hsotg->lock, flags);
2049
2050 return rc;
2051}
2052
2053
2054static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2055 struct usb_host_endpoint *ep)
2056{
2057 struct dwc2_qh *qh = ep->hcpriv;
2058
2059 if (!qh)
2060 return -EINVAL;
2061
2062 qh->data_toggle = DWC2_HC_PID_DATA0;
2063
2064 return 0;
2065}
2066
2067
2068
2069
2070
2071
2072
2073
2074int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2075{
2076 u32 usbcfg, otgctl;
2077 int retval;
2078
2079 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2080
2081 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2082
2083
2084 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2085 if (hsotg->params.phy_ulpi_ext_vbus)
2086 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2087
2088
2089 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2090 if (hsotg->params.ts_dline)
2091 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2092
2093 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2094
2095
2096
2097
2098
2099
2100
2101
2102 if (!initial_setup) {
2103 retval = dwc2_core_reset(hsotg, false);
2104 if (retval) {
2105 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2106 __func__);
2107 return retval;
2108 }
2109 }
2110
2111
2112
2113
2114 retval = dwc2_phy_init(hsotg, initial_setup);
2115 if (retval)
2116 return retval;
2117
2118
2119 retval = dwc2_gahbcfg_init(hsotg);
2120 if (retval)
2121 return retval;
2122
2123
2124 dwc2_gusbcfg_init(hsotg);
2125
2126
2127 otgctl = dwc2_readl(hsotg, GOTGCTL);
2128 otgctl &= ~GOTGCTL_OTGVER;
2129 dwc2_writel(hsotg, otgctl, GOTGCTL);
2130
2131
2132 hsotg->srp_success = 0;
2133
2134
2135 dwc2_enable_common_interrupts(hsotg);
2136
2137
2138
2139
2140
2141 if (dwc2_is_host_mode(hsotg)) {
2142 dev_dbg(hsotg->dev, "Host Mode\n");
2143 hsotg->op_state = OTG_STATE_A_HOST;
2144 } else {
2145 dev_dbg(hsotg->dev, "Device Mode\n");
2146 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2147 }
2148
2149 return 0;
2150}
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2163{
2164 u32 hcfg, hfir, otgctl, usbcfg;
2165
2166 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2177 usbcfg |= GUSBCFG_TOUTCAL(7);
2178 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2179
2180
2181 dwc2_writel(hsotg, 0, PCGCTL);
2182
2183
2184 dwc2_init_fs_ls_pclk_sel(hsotg);
2185 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2186 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2187 hcfg = dwc2_readl(hsotg, HCFG);
2188 hcfg |= HCFG_FSLSSUPP;
2189 dwc2_writel(hsotg, hcfg, HCFG);
2190 }
2191
2192
2193
2194
2195
2196
2197 if (hsotg->params.reload_ctl) {
2198 hfir = dwc2_readl(hsotg, HFIR);
2199 hfir |= HFIR_RLDCTRL;
2200 dwc2_writel(hsotg, hfir, HFIR);
2201 }
2202
2203 if (hsotg->params.dma_desc_enable) {
2204 u32 op_mode = hsotg->hw_params.op_mode;
2205
2206 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2207 !hsotg->hw_params.dma_desc_enable ||
2208 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2209 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2210 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2211 dev_err(hsotg->dev,
2212 "Hardware does not support descriptor DMA mode -\n");
2213 dev_err(hsotg->dev,
2214 "falling back to buffer DMA mode.\n");
2215 hsotg->params.dma_desc_enable = false;
2216 } else {
2217 hcfg = dwc2_readl(hsotg, HCFG);
2218 hcfg |= HCFG_DESCDMA;
2219 dwc2_writel(hsotg, hcfg, HCFG);
2220 }
2221 }
2222
2223
2224 dwc2_config_fifos(hsotg);
2225
2226
2227
2228 otgctl = dwc2_readl(hsotg, GOTGCTL);
2229 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2230 dwc2_writel(hsotg, otgctl, GOTGCTL);
2231
2232
2233 dwc2_flush_tx_fifo(hsotg, 0x10 );
2234 dwc2_flush_rx_fifo(hsotg);
2235
2236
2237 otgctl = dwc2_readl(hsotg, GOTGCTL);
2238 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2239 dwc2_writel(hsotg, otgctl, GOTGCTL);
2240
2241 if (!hsotg->params.dma_desc_enable) {
2242 int num_channels, i;
2243 u32 hcchar;
2244
2245
2246 num_channels = hsotg->params.host_channels;
2247 for (i = 0; i < num_channels; i++) {
2248 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2249 if (hcchar & HCCHAR_CHENA) {
2250 hcchar &= ~HCCHAR_CHENA;
2251 hcchar |= HCCHAR_CHDIS;
2252 hcchar &= ~HCCHAR_EPDIR;
2253 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2254 }
2255 }
2256
2257
2258 for (i = 0; i < num_channels; i++) {
2259 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2260 if (hcchar & HCCHAR_CHENA) {
2261 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2262 hcchar &= ~HCCHAR_EPDIR;
2263 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2264 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2265 __func__, i);
2266
2267 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2268 HCCHAR_CHENA,
2269 1000)) {
2270 dev_warn(hsotg->dev,
2271 "Unable to clear enable on channel %d\n",
2272 i);
2273 }
2274 }
2275 }
2276 }
2277
2278
2279 dwc2_enable_acg(hsotg);
2280
2281
2282 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2283 if (hsotg->op_state == OTG_STATE_A_HOST) {
2284 u32 hprt0 = dwc2_read_hprt0(hsotg);
2285
2286 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2287 !!(hprt0 & HPRT0_PWR));
2288 if (!(hprt0 & HPRT0_PWR)) {
2289 hprt0 |= HPRT0_PWR;
2290 dwc2_writel(hsotg, hprt0, HPRT0);
2291 }
2292 }
2293
2294 dwc2_enable_host_interrupts(hsotg);
2295}
2296
2297
2298
2299
2300
2301
2302static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2303{
2304 struct dwc2_host_chan *chan, *chan_tmp;
2305 int num_channels;
2306 int i;
2307
2308 hsotg->flags.d32 = 0;
2309 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2310
2311 if (hsotg->params.uframe_sched) {
2312 hsotg->available_host_channels =
2313 hsotg->params.host_channels;
2314 } else {
2315 hsotg->non_periodic_channels = 0;
2316 hsotg->periodic_channels = 0;
2317 }
2318
2319
2320
2321
2322
2323 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2324 hc_list_entry)
2325 list_del_init(&chan->hc_list_entry);
2326
2327 num_channels = hsotg->params.host_channels;
2328 for (i = 0; i < num_channels; i++) {
2329 chan = hsotg->hc_ptr_array[i];
2330 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2331 dwc2_hc_cleanup(hsotg, chan);
2332 }
2333
2334
2335 dwc2_core_host_init(hsotg);
2336}
2337
2338static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2339 struct dwc2_host_chan *chan,
2340 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2341{
2342 int hub_addr, hub_port;
2343
2344 chan->do_split = 1;
2345 chan->xact_pos = qtd->isoc_split_pos;
2346 chan->complete_split = qtd->complete_split;
2347 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2348 chan->hub_addr = (u8)hub_addr;
2349 chan->hub_port = (u8)hub_port;
2350}
2351
2352static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2353 struct dwc2_host_chan *chan,
2354 struct dwc2_qtd *qtd)
2355{
2356 struct dwc2_hcd_urb *urb = qtd->urb;
2357 struct dwc2_hcd_iso_packet_desc *frame_desc;
2358
2359 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2360 case USB_ENDPOINT_XFER_CONTROL:
2361 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2362
2363 switch (qtd->control_phase) {
2364 case DWC2_CONTROL_SETUP:
2365 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2366 chan->do_ping = 0;
2367 chan->ep_is_in = 0;
2368 chan->data_pid_start = DWC2_HC_PID_SETUP;
2369 if (hsotg->params.host_dma)
2370 chan->xfer_dma = urb->setup_dma;
2371 else
2372 chan->xfer_buf = urb->setup_packet;
2373 chan->xfer_len = 8;
2374 break;
2375
2376 case DWC2_CONTROL_DATA:
2377 dev_vdbg(hsotg->dev, " Control data transaction\n");
2378 chan->data_pid_start = qtd->data_toggle;
2379 break;
2380
2381 case DWC2_CONTROL_STATUS:
2382
2383
2384
2385
2386 dev_vdbg(hsotg->dev, " Control status transaction\n");
2387 if (urb->length == 0)
2388 chan->ep_is_in = 1;
2389 else
2390 chan->ep_is_in =
2391 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2392 if (chan->ep_is_in)
2393 chan->do_ping = 0;
2394 chan->data_pid_start = DWC2_HC_PID_DATA1;
2395 chan->xfer_len = 0;
2396 if (hsotg->params.host_dma)
2397 chan->xfer_dma = hsotg->status_buf_dma;
2398 else
2399 chan->xfer_buf = hsotg->status_buf;
2400 break;
2401 }
2402 break;
2403
2404 case USB_ENDPOINT_XFER_BULK:
2405 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2406 break;
2407
2408 case USB_ENDPOINT_XFER_INT:
2409 chan->ep_type = USB_ENDPOINT_XFER_INT;
2410 break;
2411
2412 case USB_ENDPOINT_XFER_ISOC:
2413 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2414 if (hsotg->params.dma_desc_enable)
2415 break;
2416
2417 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2418 frame_desc->status = 0;
2419
2420 if (hsotg->params.host_dma) {
2421 chan->xfer_dma = urb->dma;
2422 chan->xfer_dma += frame_desc->offset +
2423 qtd->isoc_split_offset;
2424 } else {
2425 chan->xfer_buf = urb->buf;
2426 chan->xfer_buf += frame_desc->offset +
2427 qtd->isoc_split_offset;
2428 }
2429
2430 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2431
2432 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2433 if (chan->xfer_len <= 188)
2434 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2435 else
2436 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2437 }
2438 break;
2439 }
2440}
2441
2442static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2443 struct dwc2_qh *qh,
2444 struct dwc2_host_chan *chan)
2445{
2446 if (!hsotg->unaligned_cache ||
2447 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2448 return -ENOMEM;
2449
2450 if (!qh->dw_align_buf) {
2451 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2452 GFP_ATOMIC | GFP_DMA);
2453 if (!qh->dw_align_buf)
2454 return -ENOMEM;
2455 }
2456
2457 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2458 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2459 DMA_FROM_DEVICE);
2460
2461 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2462 dev_err(hsotg->dev, "can't map align_buf\n");
2463 chan->align_buf = 0;
2464 return -EINVAL;
2465 }
2466
2467 chan->align_buf = qh->dw_align_buf_dma;
2468 return 0;
2469}
2470
2471#define DWC2_USB_DMA_ALIGN 4
2472
2473static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2474{
2475 void *stored_xfer_buffer;
2476 size_t length;
2477
2478 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2479 return;
2480
2481
2482 memcpy(&stored_xfer_buffer,
2483 PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length,
2484 dma_get_cache_alignment()),
2485 sizeof(urb->transfer_buffer));
2486
2487 if (usb_urb_dir_in(urb)) {
2488 if (usb_pipeisoc(urb->pipe))
2489 length = urb->transfer_buffer_length;
2490 else
2491 length = urb->actual_length;
2492
2493 memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
2494 }
2495 kfree(urb->transfer_buffer);
2496 urb->transfer_buffer = stored_xfer_buffer;
2497
2498 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2499}
2500
2501static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2502{
2503 void *kmalloc_ptr;
2504 size_t kmalloc_size;
2505
2506 if (urb->num_sgs || urb->sg ||
2507 urb->transfer_buffer_length == 0 ||
2508 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2509 return 0;
2510
2511
2512
2513
2514
2515
2516 kmalloc_size = urb->transfer_buffer_length +
2517 (dma_get_cache_alignment() - 1) +
2518 sizeof(urb->transfer_buffer);
2519
2520 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2521 if (!kmalloc_ptr)
2522 return -ENOMEM;
2523
2524
2525
2526
2527
2528 memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length,
2529 dma_get_cache_alignment()),
2530 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2531
2532 if (usb_urb_dir_out(urb))
2533 memcpy(kmalloc_ptr, urb->transfer_buffer,
2534 urb->transfer_buffer_length);
2535 urb->transfer_buffer = kmalloc_ptr;
2536
2537 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2538
2539 return 0;
2540}
2541
2542static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2543 gfp_t mem_flags)
2544{
2545 int ret;
2546
2547
2548 WARN_ON_ONCE(urb->setup_dma &&
2549 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2550
2551 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2552 if (ret)
2553 return ret;
2554
2555 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2556 if (ret)
2557 dwc2_free_dma_aligned_buffer(urb);
2558
2559 return ret;
2560}
2561
2562static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2563{
2564 usb_hcd_unmap_urb_for_dma(hcd, urb);
2565 dwc2_free_dma_aligned_buffer(urb);
2566}
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2578{
2579 struct dwc2_host_chan *chan;
2580 struct dwc2_hcd_urb *urb;
2581 struct dwc2_qtd *qtd;
2582
2583 if (dbg_qh(qh))
2584 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2585
2586 if (list_empty(&qh->qtd_list)) {
2587 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2588 return -ENOMEM;
2589 }
2590
2591 if (list_empty(&hsotg->free_hc_list)) {
2592 dev_dbg(hsotg->dev, "No free channel to assign\n");
2593 return -ENOMEM;
2594 }
2595
2596 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2597 hc_list_entry);
2598
2599
2600 list_del_init(&chan->hc_list_entry);
2601
2602 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2603 urb = qtd->urb;
2604 qh->channel = chan;
2605 qtd->in_process = 1;
2606
2607
2608
2609
2610
2611 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2612 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2613 chan->speed = qh->dev_speed;
2614 chan->max_packet = qh->maxp;
2615
2616 chan->xfer_started = 0;
2617 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2618 chan->error_state = (qtd->error_count > 0);
2619 chan->halt_on_queue = 0;
2620 chan->halt_pending = 0;
2621 chan->requests = 0;
2622
2623
2624
2625
2626
2627
2628
2629
2630 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2631 if (chan->ep_is_in)
2632 chan->do_ping = 0;
2633 else
2634 chan->do_ping = qh->ping_state;
2635
2636 chan->data_pid_start = qh->data_toggle;
2637 chan->multi_count = 1;
2638
2639 if (urb->actual_length > urb->length &&
2640 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2641 urb->actual_length = urb->length;
2642
2643 if (hsotg->params.host_dma)
2644 chan->xfer_dma = urb->dma + urb->actual_length;
2645 else
2646 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2647
2648 chan->xfer_len = urb->length - urb->actual_length;
2649 chan->xfer_count = 0;
2650
2651
2652 if (qh->do_split)
2653 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2654 else
2655 chan->do_split = 0;
2656
2657
2658 dwc2_hc_init_xfer(hsotg, chan, qtd);
2659
2660
2661 if (hsotg->params.host_dma && qh->do_split &&
2662 chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2663 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2664 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2665 dev_err(hsotg->dev,
2666 "Failed to allocate memory to handle non-aligned buffer\n");
2667
2668 chan->align_buf = 0;
2669 chan->multi_count = 0;
2670 list_add_tail(&chan->hc_list_entry,
2671 &hsotg->free_hc_list);
2672 qtd->in_process = 0;
2673 qh->channel = NULL;
2674 return -ENOMEM;
2675 }
2676 } else {
2677
2678
2679
2680
2681 WARN_ON_ONCE(hsotg->params.host_dma &&
2682 (chan->xfer_dma & 0x3));
2683 chan->align_buf = 0;
2684 }
2685
2686 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2687 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2688
2689
2690
2691
2692 chan->multi_count = qh->maxp_mult;
2693
2694 if (hsotg->params.dma_desc_enable) {
2695 chan->desc_list_addr = qh->desc_list_dma;
2696 chan->desc_list_sz = qh->desc_list_sz;
2697 }
2698
2699 dwc2_hc_init(hsotg, chan);
2700 chan->qh = qh;
2701
2702 return 0;
2703}
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714enum dwc2_transaction_type dwc2_hcd_select_transactions(
2715 struct dwc2_hsotg *hsotg)
2716{
2717 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2718 struct list_head *qh_ptr;
2719 struct dwc2_qh *qh;
2720 int num_channels;
2721
2722#ifdef DWC2_DEBUG_SOF
2723 dev_vdbg(hsotg->dev, " Select Transactions\n");
2724#endif
2725
2726
2727 qh_ptr = hsotg->periodic_sched_ready.next;
2728 while (qh_ptr != &hsotg->periodic_sched_ready) {
2729 if (list_empty(&hsotg->free_hc_list))
2730 break;
2731 if (hsotg->params.uframe_sched) {
2732 if (hsotg->available_host_channels <= 1)
2733 break;
2734 hsotg->available_host_channels--;
2735 }
2736 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2737 if (dwc2_assign_and_init_hc(hsotg, qh))
2738 break;
2739
2740
2741
2742
2743
2744 qh_ptr = qh_ptr->next;
2745 list_move_tail(&qh->qh_list_entry,
2746 &hsotg->periodic_sched_assigned);
2747 ret_val = DWC2_TRANSACTION_PERIODIC;
2748 }
2749
2750
2751
2752
2753
2754
2755 num_channels = hsotg->params.host_channels;
2756 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2757 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2758 if (!hsotg->params.uframe_sched &&
2759 hsotg->non_periodic_channels >= num_channels -
2760 hsotg->periodic_channels)
2761 break;
2762 if (list_empty(&hsotg->free_hc_list))
2763 break;
2764 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2765 if (hsotg->params.uframe_sched) {
2766 if (hsotg->available_host_channels < 1)
2767 break;
2768 hsotg->available_host_channels--;
2769 }
2770
2771 if (dwc2_assign_and_init_hc(hsotg, qh))
2772 break;
2773
2774
2775
2776
2777
2778 qh_ptr = qh_ptr->next;
2779 list_move_tail(&qh->qh_list_entry,
2780 &hsotg->non_periodic_sched_active);
2781
2782 if (ret_val == DWC2_TRANSACTION_NONE)
2783 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2784 else
2785 ret_val = DWC2_TRANSACTION_ALL;
2786
2787 if (!hsotg->params.uframe_sched)
2788 hsotg->non_periodic_channels++;
2789 }
2790
2791 return ret_val;
2792}
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2816 struct dwc2_host_chan *chan,
2817 u16 fifo_dwords_avail)
2818{
2819 int retval = 0;
2820
2821 if (chan->do_split)
2822
2823 list_move_tail(&chan->split_order_list_entry,
2824 &hsotg->split_order);
2825
2826 if (hsotg->params.host_dma && chan->qh) {
2827 if (hsotg->params.dma_desc_enable) {
2828 if (!chan->xfer_started ||
2829 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2830 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2831 chan->qh->ping_state = 0;
2832 }
2833 } else if (!chan->xfer_started) {
2834 dwc2_hc_start_transfer(hsotg, chan);
2835 chan->qh->ping_state = 0;
2836 }
2837 } else if (chan->halt_pending) {
2838
2839 } else if (chan->halt_on_queue) {
2840 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2841 } else if (chan->do_ping) {
2842 if (!chan->xfer_started)
2843 dwc2_hc_start_transfer(hsotg, chan);
2844 } else if (!chan->ep_is_in ||
2845 chan->data_pid_start == DWC2_HC_PID_SETUP) {
2846 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2847 if (!chan->xfer_started) {
2848 dwc2_hc_start_transfer(hsotg, chan);
2849 retval = 1;
2850 } else {
2851 retval = dwc2_hc_continue_transfer(hsotg, chan);
2852 }
2853 } else {
2854 retval = -1;
2855 }
2856 } else {
2857 if (!chan->xfer_started) {
2858 dwc2_hc_start_transfer(hsotg, chan);
2859 retval = 1;
2860 } else {
2861 retval = dwc2_hc_continue_transfer(hsotg, chan);
2862 }
2863 }
2864
2865 return retval;
2866}
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2878{
2879 struct list_head *qh_ptr;
2880 struct dwc2_qh *qh;
2881 u32 tx_status;
2882 u32 fspcavail;
2883 u32 gintmsk;
2884 int status;
2885 bool no_queue_space = false;
2886 bool no_fifo_space = false;
2887 u32 qspcavail;
2888
2889
2890 if (list_empty(&hsotg->periodic_sched_assigned))
2891 goto exit;
2892
2893 if (dbg_perio())
2894 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2895
2896 tx_status = dwc2_readl(hsotg, HPTXSTS);
2897 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2898 TXSTS_QSPCAVAIL_SHIFT;
2899 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2900 TXSTS_FSPCAVAIL_SHIFT;
2901
2902 if (dbg_perio()) {
2903 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
2904 qspcavail);
2905 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
2906 fspcavail);
2907 }
2908
2909 qh_ptr = hsotg->periodic_sched_assigned.next;
2910 while (qh_ptr != &hsotg->periodic_sched_assigned) {
2911 tx_status = dwc2_readl(hsotg, HPTXSTS);
2912 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2913 TXSTS_QSPCAVAIL_SHIFT;
2914 if (qspcavail == 0) {
2915 no_queue_space = true;
2916 break;
2917 }
2918
2919 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2920 if (!qh->channel) {
2921 qh_ptr = qh_ptr->next;
2922 continue;
2923 }
2924
2925
2926 if (qh->tt_buffer_dirty) {
2927 qh_ptr = qh_ptr->next;
2928 continue;
2929 }
2930
2931
2932
2933
2934
2935
2936 if (!hsotg->params.host_dma &&
2937 qh->channel->multi_count > 1)
2938 hsotg->queuing_high_bandwidth = 1;
2939
2940 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2941 TXSTS_FSPCAVAIL_SHIFT;
2942 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2943 if (status < 0) {
2944 no_fifo_space = true;
2945 break;
2946 }
2947
2948
2949
2950
2951
2952
2953
2954
2955 if (hsotg->params.host_dma || status == 0 ||
2956 qh->channel->requests == qh->channel->multi_count) {
2957 qh_ptr = qh_ptr->next;
2958
2959
2960
2961
2962 list_move_tail(&qh->qh_list_entry,
2963 &hsotg->periodic_sched_queued);
2964
2965
2966 hsotg->queuing_high_bandwidth = 0;
2967 }
2968 }
2969
2970exit:
2971 if (no_queue_space || no_fifo_space ||
2972 (!hsotg->params.host_dma &&
2973 !list_empty(&hsotg->periodic_sched_assigned))) {
2974
2975
2976
2977
2978
2979
2980
2981 gintmsk = dwc2_readl(hsotg, GINTMSK);
2982 if (!(gintmsk & GINTSTS_PTXFEMP)) {
2983 gintmsk |= GINTSTS_PTXFEMP;
2984 dwc2_writel(hsotg, gintmsk, GINTMSK);
2985 }
2986 } else {
2987
2988
2989
2990
2991
2992
2993
2994 gintmsk = dwc2_readl(hsotg, GINTMSK);
2995 if (gintmsk & GINTSTS_PTXFEMP) {
2996 gintmsk &= ~GINTSTS_PTXFEMP;
2997 dwc2_writel(hsotg, gintmsk, GINTMSK);
2998 }
2999 }
3000}
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3012{
3013 struct list_head *orig_qh_ptr;
3014 struct dwc2_qh *qh;
3015 u32 tx_status;
3016 u32 qspcavail;
3017 u32 fspcavail;
3018 u32 gintmsk;
3019 int status;
3020 int no_queue_space = 0;
3021 int no_fifo_space = 0;
3022 int more_to_do = 0;
3023
3024 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3025
3026 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3027 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3028 TXSTS_QSPCAVAIL_SHIFT;
3029 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3030 TXSTS_FSPCAVAIL_SHIFT;
3031 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3032 qspcavail);
3033 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3034 fspcavail);
3035
3036
3037
3038
3039
3040 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3041 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3042 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3043
3044
3045
3046
3047
3048 do {
3049 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3050 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3051 TXSTS_QSPCAVAIL_SHIFT;
3052 if (!hsotg->params.host_dma && qspcavail == 0) {
3053 no_queue_space = 1;
3054 break;
3055 }
3056
3057 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3058 qh_list_entry);
3059 if (!qh->channel)
3060 goto next;
3061
3062
3063 if (qh->tt_buffer_dirty)
3064 goto next;
3065
3066 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3067 TXSTS_FSPCAVAIL_SHIFT;
3068 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3069
3070 if (status > 0) {
3071 more_to_do = 1;
3072 } else if (status < 0) {
3073 no_fifo_space = 1;
3074 break;
3075 }
3076next:
3077
3078 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3079 if (hsotg->non_periodic_qh_ptr ==
3080 &hsotg->non_periodic_sched_active)
3081 hsotg->non_periodic_qh_ptr =
3082 hsotg->non_periodic_qh_ptr->next;
3083 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3084
3085 if (!hsotg->params.host_dma) {
3086 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3087 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3088 TXSTS_QSPCAVAIL_SHIFT;
3089 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3090 TXSTS_FSPCAVAIL_SHIFT;
3091 dev_vdbg(hsotg->dev,
3092 " NP Tx Req Queue Space Avail (after queue): %d\n",
3093 qspcavail);
3094 dev_vdbg(hsotg->dev,
3095 " NP Tx FIFO Space Avail (after queue): %d\n",
3096 fspcavail);
3097
3098 if (more_to_do || no_queue_space || no_fifo_space) {
3099
3100
3101
3102
3103
3104
3105
3106 gintmsk = dwc2_readl(hsotg, GINTMSK);
3107 gintmsk |= GINTSTS_NPTXFEMP;
3108 dwc2_writel(hsotg, gintmsk, GINTMSK);
3109 } else {
3110
3111
3112
3113
3114
3115
3116
3117 gintmsk = dwc2_readl(hsotg, GINTMSK);
3118 gintmsk &= ~GINTSTS_NPTXFEMP;
3119 dwc2_writel(hsotg, gintmsk, GINTMSK);
3120 }
3121 }
3122}
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3136 enum dwc2_transaction_type tr_type)
3137{
3138#ifdef DWC2_DEBUG_SOF
3139 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3140#endif
3141
3142 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3143 tr_type == DWC2_TRANSACTION_ALL)
3144 dwc2_process_periodic_channels(hsotg);
3145
3146
3147 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3148 tr_type == DWC2_TRANSACTION_ALL) {
3149 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3150 dwc2_process_non_periodic_channels(hsotg);
3151 } else {
3152
3153
3154
3155
3156 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3157
3158 gintmsk &= ~GINTSTS_NPTXFEMP;
3159 dwc2_writel(hsotg, gintmsk, GINTMSK);
3160 }
3161 }
3162}
3163
3164static void dwc2_conn_id_status_change(struct work_struct *work)
3165{
3166 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3167 wf_otg);
3168 u32 count = 0;
3169 u32 gotgctl;
3170 unsigned long flags;
3171
3172 dev_dbg(hsotg->dev, "%s()\n", __func__);
3173
3174 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3175 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3176 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3177 !!(gotgctl & GOTGCTL_CONID_B));
3178
3179
3180 if (gotgctl & GOTGCTL_CONID_B) {
3181 dwc2_vbus_supply_exit(hsotg);
3182
3183 dev_dbg(hsotg->dev, "connId B\n");
3184 if (hsotg->bus_suspended) {
3185 dev_info(hsotg->dev,
3186 "Do port resume before switching to device mode\n");
3187 dwc2_port_resume(hsotg);
3188 }
3189 while (!dwc2_is_device_mode(hsotg)) {
3190 dev_info(hsotg->dev,
3191 "Waiting for Peripheral Mode, Mode=%s\n",
3192 dwc2_is_host_mode(hsotg) ? "Host" :
3193 "Peripheral");
3194 msleep(20);
3195
3196
3197
3198
3199
3200 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3201 if (!(gotgctl & GOTGCTL_CONID_B))
3202 goto host;
3203 if (++count > 250)
3204 break;
3205 }
3206 if (count > 250)
3207 dev_err(hsotg->dev,
3208 "Connection id status change timed out\n");
3209
3210
3211
3212
3213
3214
3215 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3216 dwc2_exit_partial_power_down(hsotg, 0, false);
3217
3218 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3219 dwc2_core_init(hsotg, false);
3220 dwc2_enable_global_interrupts(hsotg);
3221 spin_lock_irqsave(&hsotg->lock, flags);
3222 dwc2_hsotg_core_init_disconnected(hsotg, false);
3223 spin_unlock_irqrestore(&hsotg->lock, flags);
3224
3225 dwc2_enable_acg(hsotg);
3226 dwc2_hsotg_core_connect(hsotg);
3227 } else {
3228host:
3229
3230 dev_dbg(hsotg->dev, "connId A\n");
3231 while (!dwc2_is_host_mode(hsotg)) {
3232 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3233 dwc2_is_host_mode(hsotg) ?
3234 "Host" : "Peripheral");
3235 msleep(20);
3236 if (++count > 250)
3237 break;
3238 }
3239 if (count > 250)
3240 dev_err(hsotg->dev,
3241 "Connection id status change timed out\n");
3242
3243 spin_lock_irqsave(&hsotg->lock, flags);
3244 dwc2_hsotg_disconnect(hsotg);
3245 spin_unlock_irqrestore(&hsotg->lock, flags);
3246
3247 hsotg->op_state = OTG_STATE_A_HOST;
3248
3249 dwc2_core_init(hsotg, false);
3250 dwc2_enable_global_interrupts(hsotg);
3251 dwc2_hcd_start(hsotg);
3252 }
3253}
3254
3255static void dwc2_wakeup_detected(struct timer_list *t)
3256{
3257 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3258 u32 hprt0;
3259
3260 dev_dbg(hsotg->dev, "%s()\n", __func__);
3261
3262
3263
3264
3265
3266 hprt0 = dwc2_read_hprt0(hsotg);
3267 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3268 hprt0 &= ~HPRT0_RES;
3269 dwc2_writel(hsotg, hprt0, HPRT0);
3270 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3271 dwc2_readl(hsotg, HPRT0));
3272
3273 dwc2_hcd_rem_wakeup(hsotg);
3274 hsotg->bus_suspended = false;
3275
3276
3277 hsotg->lx_state = DWC2_L0;
3278}
3279
3280static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3281{
3282 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3283
3284 return hcd->self.b_hnp_enable;
3285}
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3299{
3300 unsigned long flags;
3301 u32 pcgctl;
3302 u32 gotgctl;
3303 int ret = 0;
3304
3305 dev_dbg(hsotg->dev, "%s()\n", __func__);
3306
3307 spin_lock_irqsave(&hsotg->lock, flags);
3308
3309 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3310 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3311 gotgctl |= GOTGCTL_HSTSETHNPEN;
3312 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3313 hsotg->op_state = OTG_STATE_A_SUSPEND;
3314 }
3315
3316 switch (hsotg->params.power_down) {
3317 case DWC2_POWER_DOWN_PARAM_PARTIAL:
3318 ret = dwc2_enter_partial_power_down(hsotg);
3319 if (ret)
3320 dev_err(hsotg->dev,
3321 "enter partial_power_down failed.\n");
3322 break;
3323 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
3324
3325
3326
3327
3328
3329
3330 spin_unlock_irqrestore(&hsotg->lock, flags);
3331 ret = dwc2_enter_hibernation(hsotg, 1);
3332 if (ret)
3333 dev_err(hsotg->dev, "enter hibernation failed.\n");
3334 spin_lock_irqsave(&hsotg->lock, flags);
3335 break;
3336 case DWC2_POWER_DOWN_PARAM_NONE:
3337
3338
3339
3340
3341 if (!hsotg->params.no_clock_gating)
3342 dwc2_host_enter_clock_gating(hsotg);
3343 break;
3344 }
3345
3346
3347 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3348 pcgctl = dwc2_readl(hsotg, PCGCTL);
3349 pcgctl &= ~PCGCTL_STOPPCLK;
3350 dwc2_writel(hsotg, pcgctl, PCGCTL);
3351
3352 spin_unlock_irqrestore(&hsotg->lock, flags);
3353
3354 msleep(200);
3355 } else {
3356 spin_unlock_irqrestore(&hsotg->lock, flags);
3357 }
3358
3359 return ret;
3360}
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372int dwc2_port_resume(struct dwc2_hsotg *hsotg)
3373{
3374 unsigned long flags;
3375 int ret = 0;
3376
3377 spin_lock_irqsave(&hsotg->lock, flags);
3378
3379 switch (hsotg->params.power_down) {
3380 case DWC2_POWER_DOWN_PARAM_PARTIAL:
3381 ret = dwc2_exit_partial_power_down(hsotg, 0, true);
3382 if (ret)
3383 dev_err(hsotg->dev,
3384 "exit partial_power_down failed.\n");
3385 break;
3386 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
3387
3388 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
3389 if (ret)
3390 dev_err(hsotg->dev, "exit hibernation failed.\n");
3391 break;
3392 case DWC2_POWER_DOWN_PARAM_NONE:
3393
3394
3395
3396
3397 spin_unlock_irqrestore(&hsotg->lock, flags);
3398 dwc2_host_exit_clock_gating(hsotg, 0);
3399 spin_lock_irqsave(&hsotg->lock, flags);
3400 break;
3401 }
3402
3403 spin_unlock_irqrestore(&hsotg->lock, flags);
3404
3405 return ret;
3406}
3407
3408
3409static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3410 u16 wvalue, u16 windex, char *buf, u16 wlength)
3411{
3412 struct usb_hub_descriptor *hub_desc;
3413 int retval = 0;
3414 u32 hprt0;
3415 u32 port_status;
3416 u32 speed;
3417 u32 pcgctl;
3418 u32 pwr;
3419
3420 switch (typereq) {
3421 case ClearHubFeature:
3422 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3423
3424 switch (wvalue) {
3425 case C_HUB_LOCAL_POWER:
3426 case C_HUB_OVER_CURRENT:
3427
3428 break;
3429
3430 default:
3431 retval = -EINVAL;
3432 dev_err(hsotg->dev,
3433 "ClearHubFeature request %1xh unknown\n",
3434 wvalue);
3435 }
3436 break;
3437
3438 case ClearPortFeature:
3439 if (wvalue != USB_PORT_FEAT_L1)
3440 if (!windex || windex > 1)
3441 goto error;
3442 switch (wvalue) {
3443 case USB_PORT_FEAT_ENABLE:
3444 dev_dbg(hsotg->dev,
3445 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3446 hprt0 = dwc2_read_hprt0(hsotg);
3447 hprt0 |= HPRT0_ENA;
3448 dwc2_writel(hsotg, hprt0, HPRT0);
3449 break;
3450
3451 case USB_PORT_FEAT_SUSPEND:
3452 dev_dbg(hsotg->dev,
3453 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3454
3455 if (hsotg->bus_suspended)
3456 retval = dwc2_port_resume(hsotg);
3457 break;
3458
3459 case USB_PORT_FEAT_POWER:
3460 dev_dbg(hsotg->dev,
3461 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3462 hprt0 = dwc2_read_hprt0(hsotg);
3463 pwr = hprt0 & HPRT0_PWR;
3464 hprt0 &= ~HPRT0_PWR;
3465 dwc2_writel(hsotg, hprt0, HPRT0);
3466 if (pwr)
3467 dwc2_vbus_supply_exit(hsotg);
3468 break;
3469
3470 case USB_PORT_FEAT_INDICATOR:
3471 dev_dbg(hsotg->dev,
3472 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3473
3474 break;
3475
3476 case USB_PORT_FEAT_C_CONNECTION:
3477
3478
3479
3480 dev_dbg(hsotg->dev,
3481 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3482 hsotg->flags.b.port_connect_status_change = 0;
3483 break;
3484
3485 case USB_PORT_FEAT_C_RESET:
3486
3487 dev_dbg(hsotg->dev,
3488 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3489 hsotg->flags.b.port_reset_change = 0;
3490 break;
3491
3492 case USB_PORT_FEAT_C_ENABLE:
3493
3494
3495
3496
3497 dev_dbg(hsotg->dev,
3498 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3499 hsotg->flags.b.port_enable_change = 0;
3500 break;
3501
3502 case USB_PORT_FEAT_C_SUSPEND:
3503
3504
3505
3506
3507
3508 dev_dbg(hsotg->dev,
3509 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3510 hsotg->flags.b.port_suspend_change = 0;
3511 break;
3512
3513 case USB_PORT_FEAT_C_PORT_L1:
3514 dev_dbg(hsotg->dev,
3515 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3516 hsotg->flags.b.port_l1_change = 0;
3517 break;
3518
3519 case USB_PORT_FEAT_C_OVER_CURRENT:
3520 dev_dbg(hsotg->dev,
3521 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3522 hsotg->flags.b.port_over_current_change = 0;
3523 break;
3524
3525 default:
3526 retval = -EINVAL;
3527 dev_err(hsotg->dev,
3528 "ClearPortFeature request %1xh unknown or unsupported\n",
3529 wvalue);
3530 }
3531 break;
3532
3533 case GetHubDescriptor:
3534 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3535 hub_desc = (struct usb_hub_descriptor *)buf;
3536 hub_desc->bDescLength = 9;
3537 hub_desc->bDescriptorType = USB_DT_HUB;
3538 hub_desc->bNbrPorts = 1;
3539 hub_desc->wHubCharacteristics =
3540 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3541 HUB_CHAR_INDV_PORT_OCPM);
3542 hub_desc->bPwrOn2PwrGood = 1;
3543 hub_desc->bHubContrCurrent = 0;
3544 hub_desc->u.hs.DeviceRemovable[0] = 0;
3545 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3546 break;
3547
3548 case GetHubStatus:
3549 dev_dbg(hsotg->dev, "GetHubStatus\n");
3550 memset(buf, 0, 4);
3551 break;
3552
3553 case GetPortStatus:
3554 dev_vdbg(hsotg->dev,
3555 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3556 hsotg->flags.d32);
3557 if (!windex || windex > 1)
3558 goto error;
3559
3560 port_status = 0;
3561 if (hsotg->flags.b.port_connect_status_change)
3562 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3563 if (hsotg->flags.b.port_enable_change)
3564 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3565 if (hsotg->flags.b.port_suspend_change)
3566 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3567 if (hsotg->flags.b.port_l1_change)
3568 port_status |= USB_PORT_STAT_C_L1 << 16;
3569 if (hsotg->flags.b.port_reset_change)
3570 port_status |= USB_PORT_STAT_C_RESET << 16;
3571 if (hsotg->flags.b.port_over_current_change) {
3572 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3573 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3574 }
3575
3576 if (!hsotg->flags.b.port_connect_status) {
3577
3578
3579
3580
3581
3582
3583
3584 *(__le32 *)buf = cpu_to_le32(port_status);
3585 break;
3586 }
3587
3588 hprt0 = dwc2_readl(hsotg, HPRT0);
3589 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3590
3591 if (hprt0 & HPRT0_CONNSTS)
3592 port_status |= USB_PORT_STAT_CONNECTION;
3593 if (hprt0 & HPRT0_ENA)
3594 port_status |= USB_PORT_STAT_ENABLE;
3595 if (hprt0 & HPRT0_SUSP)
3596 port_status |= USB_PORT_STAT_SUSPEND;
3597 if (hprt0 & HPRT0_OVRCURRACT)
3598 port_status |= USB_PORT_STAT_OVERCURRENT;
3599 if (hprt0 & HPRT0_RST)
3600 port_status |= USB_PORT_STAT_RESET;
3601 if (hprt0 & HPRT0_PWR)
3602 port_status |= USB_PORT_STAT_POWER;
3603
3604 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3605 if (speed == HPRT0_SPD_HIGH_SPEED)
3606 port_status |= USB_PORT_STAT_HIGH_SPEED;
3607 else if (speed == HPRT0_SPD_LOW_SPEED)
3608 port_status |= USB_PORT_STAT_LOW_SPEED;
3609
3610 if (hprt0 & HPRT0_TSTCTL_MASK)
3611 port_status |= USB_PORT_STAT_TEST;
3612
3613
3614 if (hsotg->params.dma_desc_fs_enable) {
3615
3616
3617
3618
3619 if (hsotg->new_connection &&
3620 ((port_status &
3621 (USB_PORT_STAT_CONNECTION |
3622 USB_PORT_STAT_HIGH_SPEED |
3623 USB_PORT_STAT_LOW_SPEED)) ==
3624 USB_PORT_STAT_CONNECTION)) {
3625 u32 hcfg;
3626
3627 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3628 hsotg->params.dma_desc_enable = true;
3629 hcfg = dwc2_readl(hsotg, HCFG);
3630 hcfg |= HCFG_DESCDMA;
3631 dwc2_writel(hsotg, hcfg, HCFG);
3632 hsotg->new_connection = false;
3633 }
3634 }
3635
3636 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3637 *(__le32 *)buf = cpu_to_le32(port_status);
3638 break;
3639
3640 case SetHubFeature:
3641 dev_dbg(hsotg->dev, "SetHubFeature\n");
3642
3643 break;
3644
3645 case SetPortFeature:
3646 dev_dbg(hsotg->dev, "SetPortFeature\n");
3647 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3648 goto error;
3649
3650 if (!hsotg->flags.b.port_connect_status) {
3651
3652
3653
3654
3655
3656
3657
3658 break;
3659 }
3660
3661 switch (wvalue) {
3662 case USB_PORT_FEAT_SUSPEND:
3663 dev_dbg(hsotg->dev,
3664 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3665 if (windex != hsotg->otg_port)
3666 goto error;
3667 if (!hsotg->bus_suspended)
3668 retval = dwc2_port_suspend(hsotg, windex);
3669 break;
3670
3671 case USB_PORT_FEAT_POWER:
3672 dev_dbg(hsotg->dev,
3673 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3674 hprt0 = dwc2_read_hprt0(hsotg);
3675 pwr = hprt0 & HPRT0_PWR;
3676 hprt0 |= HPRT0_PWR;
3677 dwc2_writel(hsotg, hprt0, HPRT0);
3678 if (!pwr)
3679 dwc2_vbus_supply_init(hsotg);
3680 break;
3681
3682 case USB_PORT_FEAT_RESET:
3683 dev_dbg(hsotg->dev,
3684 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3685
3686 hprt0 = dwc2_read_hprt0(hsotg);
3687
3688 if (hsotg->hibernated) {
3689 retval = dwc2_exit_hibernation(hsotg, 0, 1, 1);
3690 if (retval)
3691 dev_err(hsotg->dev,
3692 "exit hibernation failed\n");
3693 }
3694
3695 if (hsotg->in_ppd) {
3696 retval = dwc2_exit_partial_power_down(hsotg, 1,
3697 true);
3698 if (retval)
3699 dev_err(hsotg->dev,
3700 "exit partial_power_down failed\n");
3701 }
3702
3703 if (hsotg->params.power_down ==
3704 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
3705 dwc2_host_exit_clock_gating(hsotg, 0);
3706
3707 pcgctl = dwc2_readl(hsotg, PCGCTL);
3708 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3709 dwc2_writel(hsotg, pcgctl, PCGCTL);
3710
3711 dwc2_writel(hsotg, 0, PCGCTL);
3712
3713 hprt0 = dwc2_read_hprt0(hsotg);
3714 pwr = hprt0 & HPRT0_PWR;
3715
3716 hprt0 &= ~HPRT0_SUSP;
3717
3718
3719
3720
3721
3722
3723 if (!dwc2_hcd_is_b_host(hsotg)) {
3724 hprt0 |= HPRT0_PWR | HPRT0_RST;
3725 dev_dbg(hsotg->dev,
3726 "In host mode, hprt0=%08x\n", hprt0);
3727 dwc2_writel(hsotg, hprt0, HPRT0);
3728 if (!pwr)
3729 dwc2_vbus_supply_init(hsotg);
3730 }
3731
3732
3733 msleep(50);
3734 hprt0 &= ~HPRT0_RST;
3735 dwc2_writel(hsotg, hprt0, HPRT0);
3736 hsotg->lx_state = DWC2_L0;
3737 break;
3738
3739 case USB_PORT_FEAT_INDICATOR:
3740 dev_dbg(hsotg->dev,
3741 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3742
3743 break;
3744
3745 case USB_PORT_FEAT_TEST:
3746 hprt0 = dwc2_read_hprt0(hsotg);
3747 dev_dbg(hsotg->dev,
3748 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3749 hprt0 &= ~HPRT0_TSTCTL_MASK;
3750 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3751 dwc2_writel(hsotg, hprt0, HPRT0);
3752 break;
3753
3754 default:
3755 retval = -EINVAL;
3756 dev_err(hsotg->dev,
3757 "SetPortFeature %1xh unknown or unsupported\n",
3758 wvalue);
3759 break;
3760 }
3761 break;
3762
3763 default:
3764error:
3765 retval = -EINVAL;
3766 dev_dbg(hsotg->dev,
3767 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3768 typereq, windex, wvalue);
3769 break;
3770 }
3771
3772 return retval;
3773}
3774
3775static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3776{
3777 int retval;
3778
3779 if (port != 1)
3780 return -EINVAL;
3781
3782 retval = (hsotg->flags.b.port_connect_status_change ||
3783 hsotg->flags.b.port_reset_change ||
3784 hsotg->flags.b.port_enable_change ||
3785 hsotg->flags.b.port_suspend_change ||
3786 hsotg->flags.b.port_over_current_change);
3787
3788 if (retval) {
3789 dev_dbg(hsotg->dev,
3790 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3791 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3792 hsotg->flags.b.port_connect_status_change);
3793 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3794 hsotg->flags.b.port_reset_change);
3795 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3796 hsotg->flags.b.port_enable_change);
3797 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3798 hsotg->flags.b.port_suspend_change);
3799 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3800 hsotg->flags.b.port_over_current_change);
3801 }
3802
3803 return retval;
3804}
3805
3806int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3807{
3808 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3809
3810#ifdef DWC2_DEBUG_SOF
3811 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3812 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3813#endif
3814 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3815}
3816
3817int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3818{
3819 u32 hprt = dwc2_readl(hsotg, HPRT0);
3820 u32 hfir = dwc2_readl(hsotg, HFIR);
3821 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3822 unsigned int us_per_frame;
3823 unsigned int frame_number;
3824 unsigned int remaining;
3825 unsigned int interval;
3826 unsigned int phy_clks;
3827
3828
3829 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3830
3831
3832 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3833 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3834 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3835
3836
3837
3838
3839
3840 phy_clks = (interval - remaining) +
3841 DIV_ROUND_UP(interval * us, us_per_frame);
3842
3843 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3844}
3845
3846int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3847{
3848 return hsotg->op_state == OTG_STATE_B_HOST;
3849}
3850
3851static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3852 int iso_desc_count,
3853 gfp_t mem_flags)
3854{
3855 struct dwc2_hcd_urb *urb;
3856
3857 urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags);
3858 if (urb)
3859 urb->packet_count = iso_desc_count;
3860 return urb;
3861}
3862
3863static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3864 struct dwc2_hcd_urb *urb, u8 dev_addr,
3865 u8 ep_num, u8 ep_type, u8 ep_dir,
3866 u16 maxp, u16 maxp_mult)
3867{
3868 if (dbg_perio() ||
3869 ep_type == USB_ENDPOINT_XFER_BULK ||
3870 ep_type == USB_ENDPOINT_XFER_CONTROL)
3871 dev_vdbg(hsotg->dev,
3872 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, maxp=%d (%d mult)\n",
3873 dev_addr, ep_num, ep_dir, ep_type, maxp, maxp_mult);
3874 urb->pipe_info.dev_addr = dev_addr;
3875 urb->pipe_info.ep_num = ep_num;
3876 urb->pipe_info.pipe_type = ep_type;
3877 urb->pipe_info.pipe_dir = ep_dir;
3878 urb->pipe_info.maxp = maxp;
3879 urb->pipe_info.maxp_mult = maxp_mult;
3880}
3881
3882
3883
3884
3885
3886void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3887{
3888#ifdef DEBUG
3889 struct dwc2_host_chan *chan;
3890 struct dwc2_hcd_urb *urb;
3891 struct dwc2_qtd *qtd;
3892 int num_channels;
3893 u32 np_tx_status;
3894 u32 p_tx_status;
3895 int i;
3896
3897 num_channels = hsotg->params.host_channels;
3898 dev_dbg(hsotg->dev, "\n");
3899 dev_dbg(hsotg->dev,
3900 "************************************************************\n");
3901 dev_dbg(hsotg->dev, "HCD State:\n");
3902 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3903
3904 for (i = 0; i < num_channels; i++) {
3905 chan = hsotg->hc_ptr_array[i];
3906 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3907 dev_dbg(hsotg->dev,
3908 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3909 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3910 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3911 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3912 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3913 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3914 chan->data_pid_start);
3915 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3916 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3917 chan->xfer_started);
3918 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3919 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3920 (unsigned long)chan->xfer_dma);
3921 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3922 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3923 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3924 chan->halt_on_queue);
3925 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3926 chan->halt_pending);
3927 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3928 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3929 dev_dbg(hsotg->dev, " complete_split: %d\n",
3930 chan->complete_split);
3931 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3932 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3933 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3934 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3935 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3936
3937 if (chan->xfer_started) {
3938 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3939
3940 hfnum = dwc2_readl(hsotg, HFNUM);
3941 hcchar = dwc2_readl(hsotg, HCCHAR(i));
3942 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
3943 hcint = dwc2_readl(hsotg, HCINT(i));
3944 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
3945 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3946 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3947 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3948 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
3949 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
3950 }
3951
3952 if (!(chan->xfer_started && chan->qh))
3953 continue;
3954
3955 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3956 if (!qtd->in_process)
3957 break;
3958 urb = qtd->urb;
3959 dev_dbg(hsotg->dev, " URB Info:\n");
3960 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
3961 qtd, urb);
3962 if (urb) {
3963 dev_dbg(hsotg->dev,
3964 " Dev: %d, EP: %d %s\n",
3965 dwc2_hcd_get_dev_addr(&urb->pipe_info),
3966 dwc2_hcd_get_ep_num(&urb->pipe_info),
3967 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3968 "IN" : "OUT");
3969 dev_dbg(hsotg->dev,
3970 " Max packet size: %d (%d mult)\n",
3971 dwc2_hcd_get_maxp(&urb->pipe_info),
3972 dwc2_hcd_get_maxp_mult(&urb->pipe_info));
3973 dev_dbg(hsotg->dev,
3974 " transfer_buffer: %p\n",
3975 urb->buf);
3976 dev_dbg(hsotg->dev,
3977 " transfer_dma: %08lx\n",
3978 (unsigned long)urb->dma);
3979 dev_dbg(hsotg->dev,
3980 " transfer_buffer_length: %d\n",
3981 urb->length);
3982 dev_dbg(hsotg->dev, " actual_length: %d\n",
3983 urb->actual_length);
3984 }
3985 }
3986 }
3987
3988 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
3989 hsotg->non_periodic_channels);
3990 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
3991 hsotg->periodic_channels);
3992 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
3993 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
3994 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
3995 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3996 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
3997 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3998 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
3999 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4000 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4001 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
4002 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4003 dwc2_dump_global_registers(hsotg);
4004 dwc2_dump_host_registers(hsotg);
4005 dev_dbg(hsotg->dev,
4006 "************************************************************\n");
4007 dev_dbg(hsotg->dev, "\n");
4008#endif
4009}
4010
4011struct wrapper_priv_data {
4012 struct dwc2_hsotg *hsotg;
4013};
4014
4015
4016static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4017{
4018 struct wrapper_priv_data *p;
4019
4020 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4021 return p->hsotg;
4022}
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4045 gfp_t mem_flags, int *ttport)
4046{
4047 struct urb *urb = context;
4048 struct dwc2_tt *dwc_tt = NULL;
4049
4050 if (urb->dev->tt) {
4051 *ttport = urb->dev->ttport;
4052
4053 dwc_tt = urb->dev->tt->hcpriv;
4054 if (!dwc_tt) {
4055 size_t bitmap_size;
4056
4057
4058
4059
4060
4061 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4062 sizeof(dwc_tt->periodic_bitmaps[0]);
4063 if (urb->dev->tt->multi)
4064 bitmap_size *= urb->dev->tt->hub->maxchild;
4065
4066 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4067 mem_flags);
4068 if (!dwc_tt)
4069 return NULL;
4070
4071 dwc_tt->usb_tt = urb->dev->tt;
4072 dwc_tt->usb_tt->hcpriv = dwc_tt;
4073 }
4074
4075 dwc_tt->refcount++;
4076 }
4077
4078 return dwc_tt;
4079}
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4093{
4094
4095 if (!dwc_tt)
4096 return;
4097
4098 WARN_ON(dwc_tt->refcount < 1);
4099
4100 dwc_tt->refcount--;
4101 if (!dwc_tt->refcount) {
4102 dwc_tt->usb_tt->hcpriv = NULL;
4103 kfree(dwc_tt);
4104 }
4105}
4106
4107int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4108{
4109 struct urb *urb = context;
4110
4111 return urb->dev->speed;
4112}
4113
4114static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4115 struct urb *urb)
4116{
4117 struct usb_bus *bus = hcd_to_bus(hcd);
4118
4119 if (urb->interval)
4120 bus->bandwidth_allocated += bw / urb->interval;
4121 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4122 bus->bandwidth_isoc_reqs++;
4123 else
4124 bus->bandwidth_int_reqs++;
4125}
4126
4127static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4128 struct urb *urb)
4129{
4130 struct usb_bus *bus = hcd_to_bus(hcd);
4131
4132 if (urb->interval)
4133 bus->bandwidth_allocated -= bw / urb->interval;
4134 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4135 bus->bandwidth_isoc_reqs--;
4136 else
4137 bus->bandwidth_int_reqs--;
4138}
4139
4140
4141
4142
4143
4144
4145
4146void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4147 int status)
4148{
4149 struct urb *urb;
4150 int i;
4151
4152 if (!qtd) {
4153 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4154 return;
4155 }
4156
4157 if (!qtd->urb) {
4158 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4159 return;
4160 }
4161
4162 urb = qtd->urb->priv;
4163 if (!urb) {
4164 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4165 return;
4166 }
4167
4168 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4169
4170 if (dbg_urb(urb))
4171 dev_vdbg(hsotg->dev,
4172 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4173 __func__, urb, usb_pipedevice(urb->pipe),
4174 usb_pipeendpoint(urb->pipe),
4175 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4176 urb->actual_length);
4177
4178 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4179 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4180 for (i = 0; i < urb->number_of_packets; ++i) {
4181 urb->iso_frame_desc[i].actual_length =
4182 dwc2_hcd_urb_get_iso_desc_actual_length(
4183 qtd->urb, i);
4184 urb->iso_frame_desc[i].status =
4185 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4186 }
4187 }
4188
4189 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4190 for (i = 0; i < urb->number_of_packets; i++)
4191 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4192 i, urb->iso_frame_desc[i].status);
4193 }
4194
4195 urb->status = status;
4196 if (!status) {
4197 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4198 urb->actual_length < urb->transfer_buffer_length)
4199 urb->status = -EREMOTEIO;
4200 }
4201
4202 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4203 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4204 struct usb_host_endpoint *ep = urb->ep;
4205
4206 if (ep)
4207 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4208 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4209 urb);
4210 }
4211
4212 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4213 urb->hcpriv = NULL;
4214 kfree(qtd->urb);
4215 qtd->urb = NULL;
4216
4217 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4218}
4219
4220
4221
4222
4223static void dwc2_hcd_start_func(struct work_struct *work)
4224{
4225 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4226 start_work.work);
4227
4228 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4229 dwc2_host_start(hsotg);
4230}
4231
4232
4233
4234
4235static void dwc2_hcd_reset_func(struct work_struct *work)
4236{
4237 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4238 reset_work.work);
4239 unsigned long flags;
4240 u32 hprt0;
4241
4242 dev_dbg(hsotg->dev, "USB RESET function called\n");
4243
4244 spin_lock_irqsave(&hsotg->lock, flags);
4245
4246 hprt0 = dwc2_read_hprt0(hsotg);
4247 hprt0 &= ~HPRT0_RST;
4248 dwc2_writel(hsotg, hprt0, HPRT0);
4249 hsotg->flags.b.port_reset_change = 1;
4250
4251 spin_unlock_irqrestore(&hsotg->lock, flags);
4252}
4253
4254static void dwc2_hcd_phy_reset_func(struct work_struct *work)
4255{
4256 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4257 phy_reset_work);
4258 int ret;
4259
4260 ret = phy_reset(hsotg->phy);
4261 if (ret)
4262 dev_warn(hsotg->dev, "PHY reset failed\n");
4263}
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276static int _dwc2_hcd_start(struct usb_hcd *hcd)
4277{
4278 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4279 struct usb_bus *bus = hcd_to_bus(hcd);
4280 unsigned long flags;
4281 u32 hprt0;
4282 int ret;
4283
4284 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4285
4286 spin_lock_irqsave(&hsotg->lock, flags);
4287 hsotg->lx_state = DWC2_L0;
4288 hcd->state = HC_STATE_RUNNING;
4289 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4290
4291 if (dwc2_is_device_mode(hsotg)) {
4292 spin_unlock_irqrestore(&hsotg->lock, flags);
4293 return 0;
4294 }
4295
4296 dwc2_hcd_reinit(hsotg);
4297
4298 hprt0 = dwc2_read_hprt0(hsotg);
4299
4300 if (hprt0 & HPRT0_PWR) {
4301
4302 spin_unlock_irqrestore(&hsotg->lock, flags);
4303 ret = dwc2_vbus_supply_init(hsotg);
4304 if (ret)
4305 return ret;
4306 spin_lock_irqsave(&hsotg->lock, flags);
4307 }
4308
4309
4310 if (bus->root_hub) {
4311 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4312
4313 usb_hcd_resume_root_hub(hcd);
4314 }
4315
4316 spin_unlock_irqrestore(&hsotg->lock, flags);
4317
4318 return 0;
4319}
4320
4321
4322
4323
4324
4325static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4326{
4327 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4328 unsigned long flags;
4329 u32 hprt0;
4330
4331
4332 dwc2_disable_host_interrupts(hsotg);
4333
4334
4335 synchronize_irq(hcd->irq);
4336
4337 spin_lock_irqsave(&hsotg->lock, flags);
4338 hprt0 = dwc2_read_hprt0(hsotg);
4339
4340 dwc2_hcd_disconnect(hsotg, true);
4341 dwc2_hcd_stop(hsotg);
4342 hsotg->lx_state = DWC2_L3;
4343 hcd->state = HC_STATE_HALT;
4344 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4345 spin_unlock_irqrestore(&hsotg->lock, flags);
4346
4347
4348 if (hprt0 & HPRT0_PWR)
4349 dwc2_vbus_supply_exit(hsotg);
4350
4351 usleep_range(1000, 3000);
4352}
4353
4354static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4355{
4356 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4357 unsigned long flags;
4358 int ret = 0;
4359
4360 spin_lock_irqsave(&hsotg->lock, flags);
4361
4362 if (dwc2_is_device_mode(hsotg))
4363 goto unlock;
4364
4365 if (hsotg->lx_state != DWC2_L0)
4366 goto unlock;
4367
4368 if (!HCD_HW_ACCESSIBLE(hcd))
4369 goto unlock;
4370
4371 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4372 goto unlock;
4373
4374 if (hsotg->bus_suspended)
4375 goto skip_power_saving;
4376
4377 if (hsotg->flags.b.port_connect_status == 0)
4378 goto skip_power_saving;
4379
4380 switch (hsotg->params.power_down) {
4381 case DWC2_POWER_DOWN_PARAM_PARTIAL:
4382
4383 ret = dwc2_enter_partial_power_down(hsotg);
4384 if (ret)
4385 dev_err(hsotg->dev,
4386 "enter partial_power_down failed\n");
4387
4388 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4389 break;
4390 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
4391
4392 spin_unlock_irqrestore(&hsotg->lock, flags);
4393 ret = dwc2_enter_hibernation(hsotg, 1);
4394 if (ret)
4395 dev_err(hsotg->dev, "enter hibernation failed\n");
4396 spin_lock_irqsave(&hsotg->lock, flags);
4397
4398
4399 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4400 break;
4401 case DWC2_POWER_DOWN_PARAM_NONE:
4402
4403
4404
4405
4406 if (!hsotg->params.no_clock_gating)
4407 dwc2_host_enter_clock_gating(hsotg);
4408
4409
4410 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4411 break;
4412 default:
4413 goto skip_power_saving;
4414 }
4415
4416 spin_unlock_irqrestore(&hsotg->lock, flags);
4417 dwc2_vbus_supply_exit(hsotg);
4418 spin_lock_irqsave(&hsotg->lock, flags);
4419
4420
4421 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4422 spin_unlock_irqrestore(&hsotg->lock, flags);
4423 usb_phy_set_suspend(hsotg->uphy, true);
4424 spin_lock_irqsave(&hsotg->lock, flags);
4425 }
4426
4427skip_power_saving:
4428 hsotg->lx_state = DWC2_L2;
4429unlock:
4430 spin_unlock_irqrestore(&hsotg->lock, flags);
4431
4432 return ret;
4433}
4434
4435static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4436{
4437 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4438 unsigned long flags;
4439 u32 hprt0;
4440 int ret = 0;
4441
4442 spin_lock_irqsave(&hsotg->lock, flags);
4443
4444 if (dwc2_is_device_mode(hsotg))
4445 goto unlock;
4446
4447 if (hsotg->lx_state != DWC2_L2)
4448 goto unlock;
4449
4450 hprt0 = dwc2_read_hprt0(hsotg);
4451
4452
4453
4454
4455
4456
4457 if (hprt0 & HPRT0_CONNSTS) {
4458 hsotg->lx_state = DWC2_L0;
4459 goto unlock;
4460 }
4461
4462 switch (hsotg->params.power_down) {
4463 case DWC2_POWER_DOWN_PARAM_PARTIAL:
4464 ret = dwc2_exit_partial_power_down(hsotg, 0, true);
4465 if (ret)
4466 dev_err(hsotg->dev,
4467 "exit partial_power_down failed\n");
4468
4469
4470
4471
4472 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4473 break;
4474 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
4475 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
4476 if (ret)
4477 dev_err(hsotg->dev, "exit hibernation failed.\n");
4478
4479
4480
4481
4482
4483 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4484 break;
4485 case DWC2_POWER_DOWN_PARAM_NONE:
4486
4487
4488
4489
4490 spin_unlock_irqrestore(&hsotg->lock, flags);
4491 dwc2_host_exit_clock_gating(hsotg, 0);
4492
4493
4494
4495
4496
4497 dwc2_core_init(hsotg, false);
4498 dwc2_enable_global_interrupts(hsotg);
4499 dwc2_hcd_reinit(hsotg);
4500 spin_lock_irqsave(&hsotg->lock, flags);
4501
4502
4503
4504
4505
4506 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4507 break;
4508 default:
4509 hsotg->lx_state = DWC2_L0;
4510 goto unlock;
4511 }
4512
4513
4514 hsotg->flags.b.port_suspend_change = 1;
4515
4516
4517
4518
4519
4520
4521 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4522 spin_unlock_irqrestore(&hsotg->lock, flags);
4523 usb_phy_set_suspend(hsotg->uphy, false);
4524 spin_lock_irqsave(&hsotg->lock, flags);
4525 }
4526
4527
4528 spin_unlock_irqrestore(&hsotg->lock, flags);
4529 dwc2_vbus_supply_init(hsotg);
4530
4531
4532 usleep_range(3000, 5000);
4533 spin_lock_irqsave(&hsotg->lock, flags);
4534
4535
4536
4537
4538
4539 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4540 HPRT0_ENACHG, HPRT0);
4541
4542
4543 spin_unlock_irqrestore(&hsotg->lock, flags);
4544 usleep_range(5000, 7000);
4545 spin_lock_irqsave(&hsotg->lock, flags);
4546unlock:
4547 spin_unlock_irqrestore(&hsotg->lock, flags);
4548
4549 return ret;
4550}
4551
4552
4553static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4554{
4555 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4556
4557 return dwc2_hcd_get_frame_number(hsotg);
4558}
4559
4560static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4561 char *fn_name)
4562{
4563#ifdef VERBOSE_DEBUG
4564 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4565 char *pipetype = NULL;
4566 char *speed = NULL;
4567
4568 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4569 dev_vdbg(hsotg->dev, " Device address: %d\n",
4570 usb_pipedevice(urb->pipe));
4571 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4572 usb_pipeendpoint(urb->pipe),
4573 usb_pipein(urb->pipe) ? "IN" : "OUT");
4574
4575 switch (usb_pipetype(urb->pipe)) {
4576 case PIPE_CONTROL:
4577 pipetype = "CONTROL";
4578 break;
4579 case PIPE_BULK:
4580 pipetype = "BULK";
4581 break;
4582 case PIPE_INTERRUPT:
4583 pipetype = "INTERRUPT";
4584 break;
4585 case PIPE_ISOCHRONOUS:
4586 pipetype = "ISOCHRONOUS";
4587 break;
4588 }
4589
4590 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4591 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4592 "IN" : "OUT");
4593
4594 switch (urb->dev->speed) {
4595 case USB_SPEED_HIGH:
4596 speed = "HIGH";
4597 break;
4598 case USB_SPEED_FULL:
4599 speed = "FULL";
4600 break;
4601 case USB_SPEED_LOW:
4602 speed = "LOW";
4603 break;
4604 default:
4605 speed = "UNKNOWN";
4606 break;
4607 }
4608
4609 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4610 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n",
4611 usb_endpoint_maxp(&urb->ep->desc),
4612 usb_endpoint_maxp_mult(&urb->ep->desc));
4613
4614 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4615 urb->transfer_buffer_length);
4616 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4617 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4618 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4619 urb->setup_packet, (unsigned long)urb->setup_dma);
4620 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4621
4622 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4623 int i;
4624
4625 for (i = 0; i < urb->number_of_packets; i++) {
4626 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4627 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4628 urb->iso_frame_desc[i].offset,
4629 urb->iso_frame_desc[i].length);
4630 }
4631 }
4632#endif
4633}
4634
4635
4636
4637
4638
4639
4640static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4641 gfp_t mem_flags)
4642{
4643 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4644 struct usb_host_endpoint *ep = urb->ep;
4645 struct dwc2_hcd_urb *dwc2_urb;
4646 int i;
4647 int retval;
4648 int alloc_bandwidth = 0;
4649 u8 ep_type = 0;
4650 u32 tflags = 0;
4651 void *buf;
4652 unsigned long flags;
4653 struct dwc2_qh *qh;
4654 bool qh_allocated = false;
4655 struct dwc2_qtd *qtd;
4656 struct dwc2_gregs_backup *gr;
4657
4658 gr = &hsotg->gr_backup;
4659
4660 if (dbg_urb(urb)) {
4661 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4662 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4663 }
4664
4665 if (hsotg->hibernated) {
4666 if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
4667 retval = dwc2_exit_hibernation(hsotg, 0, 0, 1);
4668 else
4669 retval = dwc2_exit_hibernation(hsotg, 0, 0, 0);
4670
4671 if (retval)
4672 dev_err(hsotg->dev,
4673 "exit hibernation failed.\n");
4674 }
4675
4676 if (hsotg->in_ppd) {
4677 retval = dwc2_exit_partial_power_down(hsotg, 0, true);
4678 if (retval)
4679 dev_err(hsotg->dev,
4680 "exit partial_power_down failed\n");
4681 }
4682
4683 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE &&
4684 hsotg->bus_suspended) {
4685 if (dwc2_is_device_mode(hsotg))
4686 dwc2_gadget_exit_clock_gating(hsotg, 0);
4687 else
4688 dwc2_host_exit_clock_gating(hsotg, 0);
4689 }
4690
4691 if (!ep)
4692 return -EINVAL;
4693
4694 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4695 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4696 spin_lock_irqsave(&hsotg->lock, flags);
4697 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4698 alloc_bandwidth = 1;
4699 spin_unlock_irqrestore(&hsotg->lock, flags);
4700 }
4701
4702 switch (usb_pipetype(urb->pipe)) {
4703 case PIPE_CONTROL:
4704 ep_type = USB_ENDPOINT_XFER_CONTROL;
4705 break;
4706 case PIPE_ISOCHRONOUS:
4707 ep_type = USB_ENDPOINT_XFER_ISOC;
4708 break;
4709 case PIPE_BULK:
4710 ep_type = USB_ENDPOINT_XFER_BULK;
4711 break;
4712 case PIPE_INTERRUPT:
4713 ep_type = USB_ENDPOINT_XFER_INT;
4714 break;
4715 }
4716
4717 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4718 mem_flags);
4719 if (!dwc2_urb)
4720 return -ENOMEM;
4721
4722 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4723 usb_pipeendpoint(urb->pipe), ep_type,
4724 usb_pipein(urb->pipe),
4725 usb_endpoint_maxp(&ep->desc),
4726 usb_endpoint_maxp_mult(&ep->desc));
4727
4728 buf = urb->transfer_buffer;
4729
4730 if (hcd_uses_dma(hcd)) {
4731 if (!buf && (urb->transfer_dma & 3)) {
4732 dev_err(hsotg->dev,
4733 "%s: unaligned transfer with no transfer_buffer",
4734 __func__);
4735 retval = -EINVAL;
4736 goto fail0;
4737 }
4738 }
4739
4740 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4741 tflags |= URB_GIVEBACK_ASAP;
4742 if (urb->transfer_flags & URB_ZERO_PACKET)
4743 tflags |= URB_SEND_ZERO_PACKET;
4744
4745 dwc2_urb->priv = urb;
4746 dwc2_urb->buf = buf;
4747 dwc2_urb->dma = urb->transfer_dma;
4748 dwc2_urb->length = urb->transfer_buffer_length;
4749 dwc2_urb->setup_packet = urb->setup_packet;
4750 dwc2_urb->setup_dma = urb->setup_dma;
4751 dwc2_urb->flags = tflags;
4752 dwc2_urb->interval = urb->interval;
4753 dwc2_urb->status = -EINPROGRESS;
4754
4755 for (i = 0; i < urb->number_of_packets; ++i)
4756 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4757 urb->iso_frame_desc[i].offset,
4758 urb->iso_frame_desc[i].length);
4759
4760 urb->hcpriv = dwc2_urb;
4761 qh = (struct dwc2_qh *)ep->hcpriv;
4762
4763 if (!qh) {
4764 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4765 if (!qh) {
4766 retval = -ENOMEM;
4767 goto fail0;
4768 }
4769 ep->hcpriv = qh;
4770 qh_allocated = true;
4771 }
4772
4773 qtd = kzalloc(sizeof(*qtd), mem_flags);
4774 if (!qtd) {
4775 retval = -ENOMEM;
4776 goto fail1;
4777 }
4778
4779 spin_lock_irqsave(&hsotg->lock, flags);
4780 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4781 if (retval)
4782 goto fail2;
4783
4784 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4785 if (retval)
4786 goto fail3;
4787
4788 if (alloc_bandwidth) {
4789 dwc2_allocate_bus_bandwidth(hcd,
4790 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4791 urb);
4792 }
4793
4794 spin_unlock_irqrestore(&hsotg->lock, flags);
4795
4796 return 0;
4797
4798fail3:
4799 dwc2_urb->priv = NULL;
4800 usb_hcd_unlink_urb_from_ep(hcd, urb);
4801 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4802 qh->channel->qh = NULL;
4803fail2:
4804 spin_unlock_irqrestore(&hsotg->lock, flags);
4805 urb->hcpriv = NULL;
4806 kfree(qtd);
4807fail1:
4808 if (qh_allocated) {
4809 struct dwc2_qtd *qtd2, *qtd2_tmp;
4810
4811 ep->hcpriv = NULL;
4812 dwc2_hcd_qh_unlink(hsotg, qh);
4813
4814 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4815 qtd_list_entry)
4816 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4817 dwc2_hcd_qh_free(hsotg, qh);
4818 }
4819fail0:
4820 kfree(dwc2_urb);
4821
4822 return retval;
4823}
4824
4825
4826
4827
4828static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4829 int status)
4830{
4831 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4832 int rc;
4833 unsigned long flags;
4834
4835 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4836 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4837
4838 spin_lock_irqsave(&hsotg->lock, flags);
4839
4840 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4841 if (rc)
4842 goto out;
4843
4844 if (!urb->hcpriv) {
4845 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4846 goto out;
4847 }
4848
4849 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4850
4851 usb_hcd_unlink_urb_from_ep(hcd, urb);
4852
4853 kfree(urb->hcpriv);
4854 urb->hcpriv = NULL;
4855
4856
4857 spin_unlock(&hsotg->lock);
4858 usb_hcd_giveback_urb(hcd, urb, status);
4859 spin_lock(&hsotg->lock);
4860
4861 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4862 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4863out:
4864 spin_unlock_irqrestore(&hsotg->lock, flags);
4865
4866 return rc;
4867}
4868
4869
4870
4871
4872
4873
4874static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4875 struct usb_host_endpoint *ep)
4876{
4877 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4878
4879 dev_dbg(hsotg->dev,
4880 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4881 ep->desc.bEndpointAddress, ep->hcpriv);
4882 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4883}
4884
4885
4886
4887
4888
4889
4890static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4891 struct usb_host_endpoint *ep)
4892{
4893 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4894 unsigned long flags;
4895
4896 dev_dbg(hsotg->dev,
4897 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4898 ep->desc.bEndpointAddress);
4899
4900 spin_lock_irqsave(&hsotg->lock, flags);
4901 dwc2_hcd_endpoint_reset(hsotg, ep);
4902 spin_unlock_irqrestore(&hsotg->lock, flags);
4903}
4904
4905
4906
4907
4908
4909
4910
4911
4912static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4913{
4914 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4915
4916 return dwc2_handle_hcd_intr(hsotg);
4917}
4918
4919
4920
4921
4922
4923
4924
4925static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4926{
4927 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4928
4929 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4930 return buf[0] != 0;
4931}
4932
4933
4934static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4935 u16 windex, char *buf, u16 wlength)
4936{
4937 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4938 wvalue, windex, buf, wlength);
4939 return retval;
4940}
4941
4942
4943static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4944 struct usb_host_endpoint *ep)
4945{
4946 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4947 struct dwc2_qh *qh;
4948 unsigned long flags;
4949
4950 qh = ep->hcpriv;
4951 if (!qh)
4952 return;
4953
4954 spin_lock_irqsave(&hsotg->lock, flags);
4955 qh->tt_buffer_dirty = 0;
4956
4957 if (hsotg->flags.b.port_connect_status)
4958 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4959
4960 spin_unlock_irqrestore(&hsotg->lock, flags);
4961}
4962
4963
4964
4965
4966
4967static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4968{
4969 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4970
4971 if (hsotg->params.speed == speed)
4972 return;
4973
4974 hsotg->params.speed = speed;
4975 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4976}
4977
4978static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4979{
4980 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4981
4982 if (!hsotg->params.change_speed_quirk)
4983 return;
4984
4985
4986
4987
4988 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4989 udev->parent->speed < USB_SPEED_HIGH) {
4990 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4991 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4992 }
4993}
4994
4995static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4996{
4997 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4998
4999 if (!hsotg->params.change_speed_quirk)
5000 return 0;
5001
5002 if (udev->speed == USB_SPEED_HIGH) {
5003 dev_info(hsotg->dev, "Set speed to high-speed\n");
5004 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5005 } else if ((udev->speed == USB_SPEED_FULL ||
5006 udev->speed == USB_SPEED_LOW)) {
5007
5008
5009
5010
5011 dev_info(hsotg->dev, "Set speed to full-speed\n");
5012 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
5013 }
5014
5015 return 0;
5016}
5017
5018static struct hc_driver dwc2_hc_driver = {
5019 .description = "dwc2_hsotg",
5020 .product_desc = "DWC OTG Controller",
5021 .hcd_priv_size = sizeof(struct wrapper_priv_data),
5022
5023 .irq = _dwc2_hcd_irq,
5024 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
5025
5026 .start = _dwc2_hcd_start,
5027 .stop = _dwc2_hcd_stop,
5028 .urb_enqueue = _dwc2_hcd_urb_enqueue,
5029 .urb_dequeue = _dwc2_hcd_urb_dequeue,
5030 .endpoint_disable = _dwc2_hcd_endpoint_disable,
5031 .endpoint_reset = _dwc2_hcd_endpoint_reset,
5032 .get_frame_number = _dwc2_hcd_get_frame_number,
5033
5034 .hub_status_data = _dwc2_hcd_hub_status_data,
5035 .hub_control = _dwc2_hcd_hub_control,
5036 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
5037
5038 .bus_suspend = _dwc2_hcd_suspend,
5039 .bus_resume = _dwc2_hcd_resume,
5040
5041 .map_urb_for_dma = dwc2_map_urb_for_dma,
5042 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
5043};
5044
5045
5046
5047
5048
5049static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5050{
5051 u32 ahbcfg;
5052 u32 dctl;
5053 int i;
5054
5055 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5056
5057
5058 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5059 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
5060 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5061 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5062 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5063 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5064 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5065
5066
5067 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5068 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5069
5070 if (chan) {
5071 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5072 i, chan);
5073 hsotg->hc_ptr_array[i] = NULL;
5074 kfree(chan);
5075 }
5076 }
5077
5078 if (hsotg->params.host_dma) {
5079 if (hsotg->status_buf) {
5080 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5081 hsotg->status_buf,
5082 hsotg->status_buf_dma);
5083 hsotg->status_buf = NULL;
5084 }
5085 } else {
5086 kfree(hsotg->status_buf);
5087 hsotg->status_buf = NULL;
5088 }
5089
5090 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
5091
5092
5093 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5094 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
5095 dwc2_writel(hsotg, 0, GINTMSK);
5096
5097 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5098 dctl = dwc2_readl(hsotg, DCTL);
5099 dctl |= DCTL_SFTDISCON;
5100 dwc2_writel(hsotg, dctl, DCTL);
5101 }
5102
5103 if (hsotg->wq_otg) {
5104 if (!cancel_work_sync(&hsotg->wf_otg))
5105 flush_workqueue(hsotg->wq_otg);
5106 destroy_workqueue(hsotg->wq_otg);
5107 }
5108
5109 cancel_work_sync(&hsotg->phy_reset_work);
5110
5111 del_timer(&hsotg->wkp_timer);
5112}
5113
5114static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5115{
5116
5117 dwc2_disable_host_interrupts(hsotg);
5118
5119 dwc2_hcd_free(hsotg);
5120}
5121
5122
5123
5124
5125
5126
5127
5128int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5129{
5130 struct platform_device *pdev = to_platform_device(hsotg->dev);
5131 struct resource *res;
5132 struct usb_hcd *hcd;
5133 struct dwc2_host_chan *channel;
5134 u32 hcfg;
5135 int i, num_channels;
5136 int retval;
5137
5138 if (usb_disabled())
5139 return -ENODEV;
5140
5141 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5142
5143 retval = -ENOMEM;
5144
5145 hcfg = dwc2_readl(hsotg, HCFG);
5146 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5147
5148#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5149 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5150 sizeof(*hsotg->frame_num_array),
5151 GFP_KERNEL);
5152 if (!hsotg->frame_num_array)
5153 goto error1;
5154 hsotg->last_frame_num_array =
5155 kcalloc(FRAME_NUM_ARRAY_SIZE,
5156 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5157 if (!hsotg->last_frame_num_array)
5158 goto error1;
5159#endif
5160 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5161
5162
5163 if (hsotg->params.host_dma &&
5164 !hsotg->dev->dma_mask) {
5165 dev_warn(hsotg->dev,
5166 "dma_mask not set, disabling DMA\n");
5167 hsotg->params.host_dma = false;
5168 hsotg->params.dma_desc_enable = false;
5169 }
5170
5171
5172 if (hsotg->params.host_dma) {
5173 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5174 dev_warn(hsotg->dev, "can't set DMA mask\n");
5175 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5176 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5177 }
5178
5179 if (hsotg->params.change_speed_quirk) {
5180 dwc2_hc_driver.free_dev = dwc2_free_dev;
5181 dwc2_hc_driver.reset_device = dwc2_reset_device;
5182 }
5183
5184 if (hsotg->params.host_dma)
5185 dwc2_hc_driver.flags |= HCD_DMA;
5186
5187 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5188 if (!hcd)
5189 goto error1;
5190
5191 hcd->has_tt = 1;
5192
5193 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5194 if (!res) {
5195 retval = -EINVAL;
5196 goto error1;
5197 }
5198 hcd->rsrc_start = res->start;
5199 hcd->rsrc_len = resource_size(res);
5200
5201 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5202 hsotg->priv = hcd;
5203
5204
5205
5206
5207
5208 dwc2_disable_global_interrupts(hsotg);
5209
5210
5211 retval = dwc2_core_init(hsotg, true);
5212 if (retval)
5213 goto error2;
5214
5215
5216 retval = -ENOMEM;
5217 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5218 if (!hsotg->wq_otg) {
5219 dev_err(hsotg->dev, "Failed to create workqueue\n");
5220 goto error2;
5221 }
5222 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5223
5224 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5225
5226
5227 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5228 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5229 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5230
5231
5232 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5233 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5234 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5235 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5236
5237 INIT_LIST_HEAD(&hsotg->split_order);
5238
5239
5240
5241
5242
5243 INIT_LIST_HEAD(&hsotg->free_hc_list);
5244 num_channels = hsotg->params.host_channels;
5245 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5246
5247 for (i = 0; i < num_channels; i++) {
5248 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5249 if (!channel)
5250 goto error3;
5251 channel->hc_num = i;
5252 INIT_LIST_HEAD(&channel->split_order_list_entry);
5253 hsotg->hc_ptr_array[i] = channel;
5254 }
5255
5256
5257 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5258 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5259 INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
5260
5261
5262
5263
5264
5265
5266
5267 if (hsotg->params.host_dma)
5268 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5269 DWC2_HCD_STATUS_BUF_SIZE,
5270 &hsotg->status_buf_dma, GFP_KERNEL);
5271 else
5272 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5273 GFP_KERNEL);
5274
5275 if (!hsotg->status_buf)
5276 goto error3;
5277
5278
5279
5280
5281
5282
5283 if (hsotg->params.dma_desc_enable ||
5284 hsotg->params.dma_desc_fs_enable) {
5285 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5286 sizeof(struct dwc2_dma_desc) *
5287 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5288 NULL);
5289 if (!hsotg->desc_gen_cache) {
5290 dev_err(hsotg->dev,
5291 "unable to create dwc2 generic desc cache\n");
5292
5293
5294
5295
5296
5297 hsotg->params.dma_desc_enable = false;
5298 hsotg->params.dma_desc_fs_enable = false;
5299 }
5300
5301 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5302 sizeof(struct dwc2_dma_desc) *
5303 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5304 if (!hsotg->desc_hsisoc_cache) {
5305 dev_err(hsotg->dev,
5306 "unable to create dwc2 hs isoc desc cache\n");
5307
5308 kmem_cache_destroy(hsotg->desc_gen_cache);
5309
5310
5311
5312
5313
5314 hsotg->params.dma_desc_enable = false;
5315 hsotg->params.dma_desc_fs_enable = false;
5316 }
5317 }
5318
5319 if (hsotg->params.host_dma) {
5320
5321
5322
5323
5324 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5325 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5326 SLAB_CACHE_DMA, NULL);
5327 if (!hsotg->unaligned_cache)
5328 dev_err(hsotg->dev,
5329 "unable to create dwc2 unaligned cache\n");
5330 }
5331
5332 hsotg->otg_port = 1;
5333 hsotg->frame_list = NULL;
5334 hsotg->frame_list_dma = 0;
5335 hsotg->periodic_qh_count = 0;
5336
5337
5338 hsotg->lx_state = DWC2_L3;
5339
5340 hcd->self.otg_port = hsotg->otg_port;
5341
5342
5343 hcd->self.sg_tablesize = 0;
5344
5345 if (!IS_ERR_OR_NULL(hsotg->uphy))
5346 otg_set_host(hsotg->uphy->otg, &hcd->self);
5347
5348
5349
5350
5351
5352
5353 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5354 if (retval < 0)
5355 goto error4;
5356
5357 device_wakeup_enable(hcd->self.controller);
5358
5359 dwc2_hcd_dump_state(hsotg);
5360
5361 dwc2_enable_global_interrupts(hsotg);
5362
5363 return 0;
5364
5365error4:
5366 kmem_cache_destroy(hsotg->unaligned_cache);
5367 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5368 kmem_cache_destroy(hsotg->desc_gen_cache);
5369error3:
5370 dwc2_hcd_release(hsotg);
5371error2:
5372 usb_put_hcd(hcd);
5373error1:
5374
5375#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5376 kfree(hsotg->last_frame_num_array);
5377 kfree(hsotg->frame_num_array);
5378#endif
5379
5380 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5381 return retval;
5382}
5383
5384
5385
5386
5387
5388void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5389{
5390 struct usb_hcd *hcd;
5391
5392 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5393
5394 hcd = dwc2_hsotg_to_hcd(hsotg);
5395 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5396
5397 if (!hcd) {
5398 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5399 __func__);
5400 return;
5401 }
5402
5403 if (!IS_ERR_OR_NULL(hsotg->uphy))
5404 otg_set_host(hsotg->uphy->otg, NULL);
5405
5406 usb_remove_hcd(hcd);
5407 hsotg->priv = NULL;
5408
5409 kmem_cache_destroy(hsotg->unaligned_cache);
5410 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5411 kmem_cache_destroy(hsotg->desc_gen_cache);
5412
5413 dwc2_hcd_release(hsotg);
5414 usb_put_hcd(hcd);
5415
5416#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5417 kfree(hsotg->last_frame_num_array);
5418 kfree(hsotg->frame_num_array);
5419#endif
5420}
5421
5422
5423
5424
5425
5426
5427
5428
5429int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5430{
5431 struct dwc2_hregs_backup *hr;
5432 int i;
5433
5434 dev_dbg(hsotg->dev, "%s\n", __func__);
5435
5436
5437 hr = &hsotg->hr_backup;
5438 hr->hcfg = dwc2_readl(hsotg, HCFG);
5439 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5440 for (i = 0; i < hsotg->params.host_channels; ++i)
5441 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5442
5443 hr->hprt0 = dwc2_read_hprt0(hsotg);
5444 hr->hfir = dwc2_readl(hsotg, HFIR);
5445 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5446 hr->valid = true;
5447
5448 return 0;
5449}
5450
5451
5452
5453
5454
5455
5456
5457
5458int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5459{
5460 struct dwc2_hregs_backup *hr;
5461 int i;
5462
5463 dev_dbg(hsotg->dev, "%s\n", __func__);
5464
5465
5466 hr = &hsotg->hr_backup;
5467 if (!hr->valid) {
5468 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5469 __func__);
5470 return -EINVAL;
5471 }
5472 hr->valid = false;
5473
5474 dwc2_writel(hsotg, hr->hcfg, HCFG);
5475 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5476
5477 for (i = 0; i < hsotg->params.host_channels; ++i)
5478 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5479
5480 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5481 dwc2_writel(hsotg, hr->hfir, HFIR);
5482 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5483 hsotg->frame_number = 0;
5484
5485 return 0;
5486}
5487
5488
5489
5490
5491
5492
5493int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5494{
5495 unsigned long flags;
5496 int ret = 0;
5497 u32 hprt0;
5498 u32 pcgcctl;
5499 u32 gusbcfg;
5500 u32 gpwrdn;
5501
5502 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5503 ret = dwc2_backup_global_registers(hsotg);
5504 if (ret) {
5505 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5506 __func__);
5507 return ret;
5508 }
5509 ret = dwc2_backup_host_registers(hsotg);
5510 if (ret) {
5511 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5512 __func__);
5513 return ret;
5514 }
5515
5516
5517 hprt0 = dwc2_readl(hsotg, HPRT0);
5518 hprt0 |= HPRT0_SUSP;
5519 hprt0 &= ~HPRT0_ENA;
5520 dwc2_writel(hsotg, hprt0, HPRT0);
5521
5522
5523 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 5000))
5524 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5525
5526
5527
5528
5529
5530 spin_lock_irqsave(&hsotg->lock, flags);
5531 hsotg->lx_state = DWC2_L2;
5532
5533 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5534 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5535
5536
5537 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5538 pcgcctl |= PCGCTL_STOPPCLK;
5539 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5540 udelay(10);
5541
5542 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5543 gpwrdn |= GPWRDN_PMUACTV;
5544 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5545 udelay(10);
5546 } else {
5547
5548 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5549 gpwrdn |= GPWRDN_PMUACTV;
5550 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5551 udelay(10);
5552
5553 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5554 pcgcctl |= PCGCTL_STOPPCLK;
5555 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5556 udelay(10);
5557 }
5558
5559
5560 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5561 gpwrdn |= GPWRDN_PMUINTSEL;
5562 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5563 udelay(10);
5564
5565
5566 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5567 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5568 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5569 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5570 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5571 udelay(10);
5572
5573
5574 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5575 gpwrdn |= GPWRDN_PWRDNCLMP;
5576 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5577 udelay(10);
5578
5579
5580 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5581 gpwrdn |= GPWRDN_PWRDNSWTCH;
5582 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5583
5584 hsotg->hibernated = 1;
5585 hsotg->bus_suspended = 1;
5586 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5587 spin_unlock_irqrestore(&hsotg->lock, flags);
5588 return ret;
5589}
5590
5591
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602
5603int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5604 int reset)
5605{
5606 u32 gpwrdn;
5607 u32 hprt0;
5608 int ret = 0;
5609 struct dwc2_gregs_backup *gr;
5610 struct dwc2_hregs_backup *hr;
5611
5612 gr = &hsotg->gr_backup;
5613 hr = &hsotg->hr_backup;
5614
5615 dev_dbg(hsotg->dev,
5616 "%s: called with rem_wakeup = %d reset = %d\n",
5617 __func__, rem_wakeup, reset);
5618
5619 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5620 hsotg->hibernated = 0;
5621
5622
5623
5624
5625
5626
5627 mdelay(100);
5628
5629
5630 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5631
5632
5633 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5634 gpwrdn &= ~GPWRDN_RESTORE;
5635 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5636 udelay(10);
5637
5638
5639 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5640 dwc2_writel(hsotg, hr->hcfg, HCFG);
5641
5642
5643 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5644 gpwrdn &= ~GPWRDN_PMUACTV;
5645 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5646 udelay(10);
5647
5648 hprt0 = hr->hprt0;
5649 hprt0 |= HPRT0_PWR;
5650 hprt0 &= ~HPRT0_ENA;
5651 hprt0 &= ~HPRT0_SUSP;
5652 dwc2_writel(hsotg, hprt0, HPRT0);
5653
5654 hprt0 = hr->hprt0;
5655 hprt0 |= HPRT0_PWR;
5656 hprt0 &= ~HPRT0_ENA;
5657 hprt0 &= ~HPRT0_SUSP;
5658
5659 if (reset) {
5660 hprt0 |= HPRT0_RST;
5661 dwc2_writel(hsotg, hprt0, HPRT0);
5662
5663
5664 mdelay(60);
5665 hprt0 &= ~HPRT0_RST;
5666 dwc2_writel(hsotg, hprt0, HPRT0);
5667 } else {
5668 hprt0 |= HPRT0_RES;
5669 dwc2_writel(hsotg, hprt0, HPRT0);
5670
5671
5672 mdelay(100);
5673 hprt0 &= ~HPRT0_RES;
5674 dwc2_writel(hsotg, hprt0, HPRT0);
5675 }
5676
5677 hprt0 = dwc2_readl(hsotg, HPRT0);
5678 hprt0 |= HPRT0_CONNDET;
5679 hprt0 |= HPRT0_ENACHG;
5680 hprt0 &= ~HPRT0_ENA;
5681 dwc2_writel(hsotg, hprt0, HPRT0);
5682
5683 hprt0 = dwc2_readl(hsotg, HPRT0);
5684
5685
5686 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5687
5688
5689 ret = dwc2_restore_global_registers(hsotg);
5690 if (ret) {
5691 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5692 __func__);
5693 return ret;
5694 }
5695
5696
5697 ret = dwc2_restore_host_registers(hsotg);
5698 if (ret) {
5699 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5700 __func__);
5701 return ret;
5702 }
5703
5704 if (rem_wakeup) {
5705 dwc2_hcd_rem_wakeup(hsotg);
5706
5707
5708
5709
5710
5711 hsotg->flags.b.port_connect_status_change = 1;
5712 }
5713
5714 hsotg->hibernated = 0;
5715 hsotg->bus_suspended = 0;
5716 hsotg->lx_state = DWC2_L0;
5717 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
5718 return ret;
5719}
5720
5721bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
5722{
5723 struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub;
5724
5725
5726 if (!device_may_wakeup(dwc2->dev))
5727 return true;
5728
5729
5730
5731
5732
5733 if (usb_wakeup_enabled_descendants(root_hub))
5734 return false;
5735
5736
5737 return true;
5738}
5739
5740
5741
5742
5743
5744
5745
5746
5747
5748
5749
5750int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5751{
5752 u32 pcgcctl;
5753 u32 hprt0;
5754 int ret = 0;
5755
5756 dev_dbg(hsotg->dev, "Entering host partial power down started.\n");
5757
5758
5759 hprt0 = dwc2_read_hprt0(hsotg);
5760 hprt0 |= HPRT0_SUSP;
5761 dwc2_writel(hsotg, hprt0, HPRT0);
5762 udelay(5);
5763
5764
5765 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
5766 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5767
5768
5769 ret = dwc2_backup_global_registers(hsotg);
5770 if (ret) {
5771 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5772 __func__);
5773 return ret;
5774 }
5775
5776 ret = dwc2_backup_host_registers(hsotg);
5777 if (ret) {
5778 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5779 __func__);
5780 return ret;
5781 }
5782
5783
5784
5785
5786
5787 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5788
5789
5790 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5791
5792 pcgcctl |= PCGCTL_PWRCLMP;
5793 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5794 udelay(5);
5795
5796 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5797 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5798 udelay(5);
5799
5800 pcgcctl |= PCGCTL_STOPPCLK;
5801 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5802
5803
5804 hsotg->in_ppd = 1;
5805 hsotg->lx_state = DWC2_L2;
5806 hsotg->bus_suspended = true;
5807
5808 dev_dbg(hsotg->dev, "Entering host partial power down completed.\n");
5809
5810 return ret;
5811}
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5826 int rem_wakeup, bool restore)
5827{
5828 u32 pcgcctl;
5829 int ret = 0;
5830 u32 hprt0;
5831
5832 dev_dbg(hsotg->dev, "Exiting host partial power down started.\n");
5833
5834 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5835 pcgcctl &= ~PCGCTL_STOPPCLK;
5836 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5837 udelay(5);
5838
5839 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5840 pcgcctl &= ~PCGCTL_PWRCLMP;
5841 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5842 udelay(5);
5843
5844 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5845 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5846 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5847
5848 udelay(100);
5849 if (restore) {
5850 ret = dwc2_restore_global_registers(hsotg);
5851 if (ret) {
5852 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5853 __func__);
5854 return ret;
5855 }
5856
5857 ret = dwc2_restore_host_registers(hsotg);
5858 if (ret) {
5859 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5860 __func__);
5861 return ret;
5862 }
5863 }
5864
5865
5866 hprt0 = dwc2_read_hprt0(hsotg);
5867 hprt0 |= HPRT0_RES;
5868 hprt0 &= ~HPRT0_SUSP;
5869 dwc2_writel(hsotg, hprt0, HPRT0);
5870 udelay(5);
5871
5872 if (!rem_wakeup) {
5873
5874 hprt0 = dwc2_read_hprt0(hsotg);
5875 hprt0 &= ~HPRT0_RES;
5876 dwc2_writel(hsotg, hprt0, HPRT0);
5877
5878 hsotg->bus_suspended = false;
5879 } else {
5880
5881 hprt0 = dwc2_read_hprt0(hsotg);
5882 hprt0 |= HPRT0_PWR;
5883 dwc2_writel(hsotg, hprt0, HPRT0);
5884
5885
5886 dwc2_hcd_connect(hsotg);
5887
5888 mod_timer(&hsotg->wkp_timer,
5889 jiffies + msecs_to_jiffies(71));
5890 }
5891
5892
5893 hsotg->in_ppd = 0;
5894 hsotg->lx_state = DWC2_L0;
5895
5896 dev_dbg(hsotg->dev, "Exiting host partial power down completed.\n");
5897 return ret;
5898}
5899
5900
5901
5902
5903
5904
5905
5906
5907void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg)
5908{
5909 u32 hprt0;
5910 u32 pcgctl;
5911
5912 dev_dbg(hsotg->dev, "Entering host clock gating.\n");
5913
5914
5915 hprt0 = dwc2_read_hprt0(hsotg);
5916 hprt0 |= HPRT0_SUSP;
5917 dwc2_writel(hsotg, hprt0, HPRT0);
5918
5919
5920 pcgctl = dwc2_readl(hsotg, PCGCTL);
5921 pcgctl |= PCGCTL_STOPPCLK;
5922 dwc2_writel(hsotg, pcgctl, PCGCTL);
5923 udelay(5);
5924
5925
5926 pcgctl = dwc2_readl(hsotg, PCGCTL);
5927 pcgctl |= PCGCTL_GATEHCLK;
5928 dwc2_writel(hsotg, pcgctl, PCGCTL);
5929 udelay(5);
5930
5931 hsotg->bus_suspended = true;
5932 hsotg->lx_state = DWC2_L2;
5933}
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5944{
5945 u32 hprt0;
5946 u32 pcgctl;
5947
5948 dev_dbg(hsotg->dev, "Exiting host clock gating.\n");
5949
5950
5951 pcgctl = dwc2_readl(hsotg, PCGCTL);
5952 pcgctl &= ~PCGCTL_GATEHCLK;
5953 dwc2_writel(hsotg, pcgctl, PCGCTL);
5954 udelay(5);
5955
5956
5957 pcgctl = dwc2_readl(hsotg, PCGCTL);
5958 pcgctl &= ~PCGCTL_STOPPCLK;
5959 dwc2_writel(hsotg, pcgctl, PCGCTL);
5960 udelay(5);
5961
5962
5963 hprt0 = dwc2_read_hprt0(hsotg);
5964 hprt0 |= HPRT0_RES;
5965 hprt0 &= ~HPRT0_SUSP;
5966 dwc2_writel(hsotg, hprt0, HPRT0);
5967 udelay(5);
5968
5969 if (!rem_wakeup) {
5970
5971 msleep(USB_RESUME_TIMEOUT);
5972
5973
5974 hprt0 = dwc2_read_hprt0(hsotg);
5975 hprt0 &= ~HPRT0_RES;
5976 dwc2_writel(hsotg, hprt0, HPRT0);
5977
5978 hsotg->bus_suspended = false;
5979 hsotg->lx_state = DWC2_L0;
5980 } else {
5981 mod_timer(&hsotg->wkp_timer,
5982 jiffies + msecs_to_jiffies(71));
5983 }
5984}
5985