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11#ifndef __DRIVERS_USB_DWC3_CORE_H
12#define __DRIVERS_USB_DWC3_CORE_H
13
14#include <linux/device.h>
15#include <linux/spinlock.h>
16#include <linux/mutex.h>
17#include <linux/ioport.h>
18#include <linux/list.h>
19#include <linux/bitops.h>
20#include <linux/dma-mapping.h>
21#include <linux/mm.h>
22#include <linux/debugfs.h>
23#include <linux/wait.h>
24#include <linux/workqueue.h>
25
26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
28#include <linux/usb/otg.h>
29#include <linux/usb/role.h>
30#include <linux/ulpi/interface.h>
31
32#include <linux/phy/phy.h>
33
34#include <linux/power_supply.h>
35
36#define DWC3_MSG_MAX 500
37
38
39#define DWC3_PULL_UP_TIMEOUT 500
40#define DWC3_BOUNCE_SIZE 1024
41#define DWC3_EP0_SETUP_SIZE 512
42#define DWC3_ENDPOINTS_NUM 32
43#define DWC3_XHCI_RESOURCES_NUM 2
44#define DWC3_ISOC_MAX_RETRIES 5
45
46#define DWC3_SCRATCHBUF_SIZE 4096
47#define DWC3_EVENT_BUFFERS_SIZE 4096
48#define DWC3_EVENT_TYPE_MASK 0xfe
49
50#define DWC3_EVENT_TYPE_DEV 0
51#define DWC3_EVENT_TYPE_CARKIT 3
52#define DWC3_EVENT_TYPE_I2C 4
53
54#define DWC3_DEVICE_EVENT_DISCONNECT 0
55#define DWC3_DEVICE_EVENT_RESET 1
56#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
57#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
58#define DWC3_DEVICE_EVENT_WAKEUP 4
59#define DWC3_DEVICE_EVENT_HIBER_REQ 5
60#define DWC3_DEVICE_EVENT_SUSPEND 6
61#define DWC3_DEVICE_EVENT_SOF 7
62#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
63#define DWC3_DEVICE_EVENT_CMD_CMPL 10
64#define DWC3_DEVICE_EVENT_OVERFLOW 11
65
66
67#define DWC3_OTG_ROLE_IDLE 0
68#define DWC3_OTG_ROLE_HOST 1
69#define DWC3_OTG_ROLE_DEVICE 2
70
71#define DWC3_GEVNTCOUNT_MASK 0xfffc
72#define DWC3_GEVNTCOUNT_EHB BIT(31)
73#define DWC3_GSNPSID_MASK 0xffff0000
74#define DWC3_GSNPSREV_MASK 0xffff
75#define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
76
77
78#define DWC3_XHCI_REGS_START 0x0
79#define DWC3_XHCI_REGS_END 0x7fff
80#define DWC3_GLOBALS_REGS_START 0xc100
81#define DWC3_GLOBALS_REGS_END 0xc6ff
82#define DWC3_DEVICE_REGS_START 0xc700
83#define DWC3_DEVICE_REGS_END 0xcbff
84#define DWC3_OTG_REGS_START 0xcc00
85#define DWC3_OTG_REGS_END 0xccff
86
87
88#define DWC3_GSBUSCFG0 0xc100
89#define DWC3_GSBUSCFG1 0xc104
90#define DWC3_GTXTHRCFG 0xc108
91#define DWC3_GRXTHRCFG 0xc10c
92#define DWC3_GCTL 0xc110
93#define DWC3_GEVTEN 0xc114
94#define DWC3_GSTS 0xc118
95#define DWC3_GUCTL1 0xc11c
96#define DWC3_GSNPSID 0xc120
97#define DWC3_GGPIO 0xc124
98#define DWC3_GUID 0xc128
99#define DWC3_GUCTL 0xc12c
100#define DWC3_GBUSERRADDR0 0xc130
101#define DWC3_GBUSERRADDR1 0xc134
102#define DWC3_GPRTBIMAP0 0xc138
103#define DWC3_GPRTBIMAP1 0xc13c
104#define DWC3_GHWPARAMS0 0xc140
105#define DWC3_GHWPARAMS1 0xc144
106#define DWC3_GHWPARAMS2 0xc148
107#define DWC3_GHWPARAMS3 0xc14c
108#define DWC3_GHWPARAMS4 0xc150
109#define DWC3_GHWPARAMS5 0xc154
110#define DWC3_GHWPARAMS6 0xc158
111#define DWC3_GHWPARAMS7 0xc15c
112#define DWC3_GDBGFIFOSPACE 0xc160
113#define DWC3_GDBGLTSSM 0xc164
114#define DWC3_GDBGBMU 0xc16c
115#define DWC3_GDBGLSPMUX 0xc170
116#define DWC3_GDBGLSP 0xc174
117#define DWC3_GDBGEPINFO0 0xc178
118#define DWC3_GDBGEPINFO1 0xc17c
119#define DWC3_GPRTBIMAP_HS0 0xc180
120#define DWC3_GPRTBIMAP_HS1 0xc184
121#define DWC3_GPRTBIMAP_FS0 0xc188
122#define DWC3_GPRTBIMAP_FS1 0xc18c
123#define DWC3_GUCTL2 0xc19c
124
125#define DWC3_VER_NUMBER 0xc1a0
126#define DWC3_VER_TYPE 0xc1a4
127
128#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
129#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
130
131#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
132
133#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
134
135#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
136#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
137
138#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
139#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
140#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
141#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
142
143#define DWC3_GHWPARAMS8 0xc600
144#define DWC3_GUCTL3 0xc60c
145#define DWC3_GFLADJ 0xc630
146#define DWC3_GHWPARAMS9 0xc680
147
148
149#define DWC3_DCFG 0xc700
150#define DWC3_DCTL 0xc704
151#define DWC3_DEVTEN 0xc708
152#define DWC3_DSTS 0xc70c
153#define DWC3_DGCMDPAR 0xc710
154#define DWC3_DGCMD 0xc714
155#define DWC3_DALEPENA 0xc720
156
157#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
158#define DWC3_DEPCMDPAR2 0x00
159#define DWC3_DEPCMDPAR1 0x04
160#define DWC3_DEPCMDPAR0 0x08
161#define DWC3_DEPCMD 0x0c
162
163#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
164
165
166#define DWC3_OCFG 0xcc00
167#define DWC3_OCTL 0xcc04
168#define DWC3_OEVT 0xcc08
169#define DWC3_OEVTEN 0xcc0C
170#define DWC3_OSTS 0xcc10
171
172
173
174
175#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7)
176#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6)
177#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5)
178#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4)
179#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3)
180#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2)
181#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1)
182#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0)
183#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
184
185
186#define DWC3_GDBGLSPMUX_ENDBC BIT(15)
187#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
188#define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
189#define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
190
191
192#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
193#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
194#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
195
196#define DWC3_TXFIFO 0
197#define DWC3_RXFIFO 1
198#define DWC3_TXREQQ 2
199#define DWC3_RXREQQ 3
200#define DWC3_RXINFOQ 4
201#define DWC3_PSTATQ 5
202#define DWC3_DESCFETCHQ 6
203#define DWC3_EVENTQ 7
204#define DWC3_AUXEVENTQ 8
205
206
207#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
208#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
209#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
210
211
212#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
213#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
214#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
215#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
216#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
217#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
218#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
219#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
220
221
222#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
223#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
224#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
225#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
226#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
227#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
228#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
229#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
230
231
232#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
233#define DWC3_GCTL_U2RSTECN BIT(16)
234#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
235#define DWC3_GCTL_CLK_BUS (0)
236#define DWC3_GCTL_CLK_PIPE (1)
237#define DWC3_GCTL_CLK_PIPEHALF (2)
238#define DWC3_GCTL_CLK_MASK (3)
239
240#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
241#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
242#define DWC3_GCTL_PRTCAP_HOST 1
243#define DWC3_GCTL_PRTCAP_DEVICE 2
244#define DWC3_GCTL_PRTCAP_OTG 3
245
246#define DWC3_GCTL_CORESOFTRESET BIT(11)
247#define DWC3_GCTL_SOFITPSYNC BIT(10)
248#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
249#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
250#define DWC3_GCTL_DISSCRAMBLE BIT(3)
251#define DWC3_GCTL_U2EXIT_LFPS BIT(2)
252#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
253#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
254
255
256#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
257
258
259#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
260#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
261#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
262#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
263
264
265#define DWC3_GSTS_OTG_IP BIT(10)
266#define DWC3_GSTS_BC_IP BIT(9)
267#define DWC3_GSTS_ADP_IP BIT(8)
268#define DWC3_GSTS_HOST_IP BIT(7)
269#define DWC3_GSTS_DEVICE_IP BIT(6)
270#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
271#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
272#define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
273#define DWC3_GSTS_CURMOD_DEVICE 0
274#define DWC3_GSTS_CURMOD_HOST 1
275
276
277#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
278#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
279#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
280#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
281#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
282#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
283#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
284#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
285#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
286#define USBTRDTIM_UTMI_8_BIT 9
287#define USBTRDTIM_UTMI_16_BIT 5
288#define UTMI_PHYIF_16_BIT 1
289#define UTMI_PHYIF_8_BIT 0
290
291
292#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
293#define DWC3_GUSB2PHYACC_DONE BIT(24)
294#define DWC3_GUSB2PHYACC_BUSY BIT(23)
295#define DWC3_GUSB2PHYACC_WRITE BIT(22)
296#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
297#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
298#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
299
300
301#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
302#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
303#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
304#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
305#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
306#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
307#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
308#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
309#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
310#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
311#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
312#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
313#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
314#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
315
316
317#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15)
318#define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff)
319#define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
320#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
321
322
323#define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff)
324#define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
325
326
327#define DWC3_GEVNTSIZ_INTMASK BIT(31)
328#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
329
330
331#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
332#define DWC3_GHWPARAMS0_MODE_GADGET 0
333#define DWC3_GHWPARAMS0_MODE_HOST 1
334#define DWC3_GHWPARAMS0_MODE_DRD 2
335#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
336#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
337#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
338#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
339#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
340
341
342#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
343#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
344#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
345#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
346#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
347#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
348#define DWC3_GHWPARAMS1_ENDBC BIT(31)
349
350
351#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
352#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
353#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
354#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2
355#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
356#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
357#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
358#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
359#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
360#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
361#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
362#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
363
364
365#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
366#define DWC3_MAX_HIBER_SCRATCHBUFS 15
367
368
369#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
370#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
371#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
372#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
373#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
374#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
375
376
377#define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
378
379
380#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
381#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
382
383
384#define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0)
385
386
387#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
388#define DWC3_GFLADJ_30MHZ_MASK 0x3f
389
390
391#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
392
393
394#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
395
396
397#define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30)
398
399#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
400#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
401
402#define DWC3_DCFG_SPEED_MASK (7 << 0)
403#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)
404#define DWC3_DCFG_SUPERSPEED (4 << 0)
405#define DWC3_DCFG_HIGHSPEED (0 << 0)
406#define DWC3_DCFG_FULLSPEED BIT(0)
407
408#define DWC3_DCFG_NUMP_SHIFT 17
409#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
410#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
411#define DWC3_DCFG_LPM_CAP BIT(22)
412#define DWC3_DCFG_IGNSTRMPP BIT(23)
413
414
415#define DWC3_DCTL_RUN_STOP BIT(31)
416#define DWC3_DCTL_CSFTRST BIT(30)
417#define DWC3_DCTL_LSFTRST BIT(29)
418
419#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
420#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
421
422#define DWC3_DCTL_APPL1RES BIT(23)
423
424
425#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
426#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
427#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
428#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
429#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
430#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
431#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
432
433
434#define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
435
436#define DWC3_DCTL_KEEP_CONNECT BIT(19)
437#define DWC3_DCTL_L1_HIBER_EN BIT(18)
438#define DWC3_DCTL_CRS BIT(17)
439#define DWC3_DCTL_CSS BIT(16)
440
441#define DWC3_DCTL_INITU2ENA BIT(12)
442#define DWC3_DCTL_ACCEPTU2ENA BIT(11)
443#define DWC3_DCTL_INITU1ENA BIT(10)
444#define DWC3_DCTL_ACCEPTU1ENA BIT(9)
445#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
446
447#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
448#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
449
450#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
451#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
452#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
453#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
454#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
455#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
456#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
457
458
459#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
460#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
461#define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
462#define DWC3_DEVTEN_ERRTICERREN BIT(9)
463#define DWC3_DEVTEN_SOFEN BIT(7)
464#define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6)
465#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
466#define DWC3_DEVTEN_WKUPEVTEN BIT(4)
467#define DWC3_DEVTEN_ULSTCNGEN BIT(3)
468#define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
469#define DWC3_DEVTEN_USBRSTEN BIT(1)
470#define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
471
472#define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3)
473
474
475#define DWC3_DSTS_DCNRD BIT(29)
476
477
478#define DWC3_DSTS_PWRUPREQ BIT(24)
479
480
481#define DWC3_DSTS_RSS BIT(25)
482#define DWC3_DSTS_SSS BIT(24)
483
484#define DWC3_DSTS_COREIDLE BIT(23)
485#define DWC3_DSTS_DEVCTRLHLT BIT(22)
486
487#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
488#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
489
490#define DWC3_DSTS_RXFIFOEMPTY BIT(17)
491
492#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
493#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
494
495#define DWC3_DSTS_CONNECTSPD (7 << 0)
496
497#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0)
498#define DWC3_DSTS_SUPERSPEED (4 << 0)
499#define DWC3_DSTS_HIGHSPEED (0 << 0)
500#define DWC3_DSTS_FULLSPEED BIT(0)
501
502
503#define DWC3_DGCMD_SET_LMP 0x01
504#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
505#define DWC3_DGCMD_XMIT_FUNCTION 0x03
506
507
508#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
509#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
510
511#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
512#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
513#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
514#define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
515#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
516
517#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
518#define DWC3_DGCMD_CMDACT BIT(10)
519#define DWC3_DGCMD_CMDIOC BIT(8)
520
521
522#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
523#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
524#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
525#define DWC3_DGCMDPAR_TX_FIFO BIT(5)
526#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
527#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
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529
530#define DWC3_DEPCMD_PARAM_SHIFT 16
531#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
532#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
533#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
534#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
535#define DWC3_DEPCMD_CLEARPENDIN BIT(11)
536#define DWC3_DEPCMD_CMDACT BIT(10)
537#define DWC3_DEPCMD_CMDIOC BIT(8)
538
539#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
540#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
541#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
542#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
543#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
544#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
545
546#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
547
548#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
549#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
550#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
551
552#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
553
554
555#define DWC3_DALEPENA_EP(n) BIT(n)
556
557#define DWC3_DEPCMD_TYPE_CONTROL 0
558#define DWC3_DEPCMD_TYPE_ISOC 1
559#define DWC3_DEPCMD_TYPE_BULK 2
560#define DWC3_DEPCMD_TYPE_INTR 3
561
562#define DWC3_DEV_IMOD_COUNT_SHIFT 16
563#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
564#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
565#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
566
567
568#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
569#define DWC3_OCFG_HIBDISMASK BIT(4)
570#define DWC3_OCFG_SFTRSTMASK BIT(3)
571#define DWC3_OCFG_OTGVERSION BIT(2)
572#define DWC3_OCFG_HNPCAP BIT(1)
573#define DWC3_OCFG_SRPCAP BIT(0)
574
575
576#define DWC3_OCTL_OTG3GOERR BIT(7)
577#define DWC3_OCTL_PERIMODE BIT(6)
578#define DWC3_OCTL_PRTPWRCTL BIT(5)
579#define DWC3_OCTL_HNPREQ BIT(4)
580#define DWC3_OCTL_SESREQ BIT(3)
581#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
582#define DWC3_OCTL_DEVSETHNPEN BIT(1)
583#define DWC3_OCTL_HSTSETHNPEN BIT(0)
584
585
586#define DWC3_OEVT_DEVICEMODE BIT(31)
587#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
588#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
589#define DWC3_OEVT_HIBENTRY BIT(25)
590#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
591#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
592#define DWC3_OEVT_HRRINITNOTIF BIT(22)
593#define DWC3_OEVT_ADEVIDLE BIT(21)
594#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
595#define DWC3_OEVT_ADEVHOST BIT(19)
596#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
597#define DWC3_OEVT_ADEVSRPDET BIT(17)
598#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
599#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
600#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
601#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
602#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
603#define DWC3_OEVT_BSESSVLD BIT(3)
604#define DWC3_OEVT_HSTNEGSTS BIT(2)
605#define DWC3_OEVT_SESREQSTS BIT(1)
606#define DWC3_OEVT_ERROR BIT(0)
607
608
609#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
610#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
611#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
612#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
613#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
614#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
615#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
616#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
617#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
618#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
619#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
620#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
621#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
622#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
623#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
624#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
625
626
627#define DWC3_OSTS_DEVRUNSTP BIT(13)
628#define DWC3_OSTS_XHCIRUNSTP BIT(12)
629#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
630#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
631#define DWC3_OSTS_BSESVLD BIT(2)
632#define DWC3_OSTS_VBUSVLD BIT(1)
633#define DWC3_OSTS_CONIDSTS BIT(0)
634
635
636
637struct dwc3_trb;
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650struct dwc3_event_buffer {
651 void *buf;
652 void *cache;
653 unsigned int length;
654 unsigned int lpos;
655 unsigned int count;
656 unsigned int flags;
657
658#define DWC3_EVENT_PENDING BIT(0)
659
660 dma_addr_t dma;
661
662 struct dwc3 *dwc;
663};
664
665#define DWC3_EP_FLAG_STALLED BIT(0)
666#define DWC3_EP_FLAG_WEDGED BIT(1)
667
668#define DWC3_EP_DIRECTION_TX true
669#define DWC3_EP_DIRECTION_RX false
670
671#define DWC3_TRB_NUM 256
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700struct dwc3_ep {
701 struct usb_ep endpoint;
702 struct list_head cancelled_list;
703 struct list_head pending_list;
704 struct list_head started_list;
705
706 void __iomem *regs;
707
708 struct dwc3_trb *trb_pool;
709 dma_addr_t trb_pool_dma;
710 struct dwc3 *dwc;
711
712 u32 saved_state;
713 unsigned int flags;
714#define DWC3_EP_ENABLED BIT(0)
715#define DWC3_EP_STALL BIT(1)
716#define DWC3_EP_WEDGE BIT(2)
717#define DWC3_EP_TRANSFER_STARTED BIT(3)
718#define DWC3_EP_END_TRANSFER_PENDING BIT(4)
719#define DWC3_EP_PENDING_REQUEST BIT(5)
720#define DWC3_EP_DELAY_START BIT(6)
721#define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
722#define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8)
723#define DWC3_EP_FORCE_RESTART_STREAM BIT(9)
724#define DWC3_EP_FIRST_STREAM_PRIMED BIT(10)
725#define DWC3_EP_PENDING_CLEAR_STALL BIT(11)
726
727
728#define DWC3_EP0_DIR_IN BIT(31)
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738
739 u8 trb_enqueue;
740 u8 trb_dequeue;
741
742 u8 number;
743 u8 type;
744 u8 resource_index;
745 u32 frame_number;
746 u32 interval;
747
748 char name[20];
749
750 unsigned direction:1;
751 unsigned stream_capable:1;
752
753
754 u8 combo_num;
755 int start_cmd_status;
756};
757
758enum dwc3_phy {
759 DWC3_PHY_UNKNOWN = 0,
760 DWC3_PHY_USB3,
761 DWC3_PHY_USB2,
762};
763
764enum dwc3_ep0_next {
765 DWC3_EP0_UNKNOWN = 0,
766 DWC3_EP0_COMPLETE,
767 DWC3_EP0_NRDY_DATA,
768 DWC3_EP0_NRDY_STATUS,
769};
770
771enum dwc3_ep0_state {
772 EP0_UNCONNECTED = 0,
773 EP0_SETUP_PHASE,
774 EP0_DATA_PHASE,
775 EP0_STATUS_PHASE,
776};
777
778enum dwc3_link_state {
779
780 DWC3_LINK_STATE_U0 = 0x00,
781 DWC3_LINK_STATE_U1 = 0x01,
782 DWC3_LINK_STATE_U2 = 0x02,
783 DWC3_LINK_STATE_U3 = 0x03,
784 DWC3_LINK_STATE_SS_DIS = 0x04,
785 DWC3_LINK_STATE_RX_DET = 0x05,
786 DWC3_LINK_STATE_SS_INACT = 0x06,
787 DWC3_LINK_STATE_POLL = 0x07,
788 DWC3_LINK_STATE_RECOV = 0x08,
789 DWC3_LINK_STATE_HRESET = 0x09,
790 DWC3_LINK_STATE_CMPLY = 0x0a,
791 DWC3_LINK_STATE_LPBK = 0x0b,
792 DWC3_LINK_STATE_RESET = 0x0e,
793 DWC3_LINK_STATE_RESUME = 0x0f,
794 DWC3_LINK_STATE_MASK = 0x0f,
795};
796
797
798#define DWC3_TRB_SIZE_MASK (0x00ffffff)
799#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
800#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
801#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
802
803#define DWC3_TRBSTS_OK 0
804#define DWC3_TRBSTS_MISSED_ISOC 1
805#define DWC3_TRBSTS_SETUP_PENDING 2
806#define DWC3_TRB_STS_XFER_IN_PROG 4
807
808
809#define DWC3_TRB_CTRL_HWO BIT(0)
810#define DWC3_TRB_CTRL_LST BIT(1)
811#define DWC3_TRB_CTRL_CHN BIT(2)
812#define DWC3_TRB_CTRL_CSP BIT(3)
813#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
814#define DWC3_TRB_CTRL_ISP_IMI BIT(10)
815#define DWC3_TRB_CTRL_IOC BIT(11)
816#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
817#define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
818
819#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
820#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
821#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
822#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
823#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
824#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
825#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
826#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
827#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
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836struct dwc3_trb {
837 u32 bpl;
838 u32 bph;
839 u32 size;
840 u32 ctrl;
841} __packed;
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856struct dwc3_hwparams {
857 u32 hwparams0;
858 u32 hwparams1;
859 u32 hwparams2;
860 u32 hwparams3;
861 u32 hwparams4;
862 u32 hwparams5;
863 u32 hwparams6;
864 u32 hwparams7;
865 u32 hwparams8;
866 u32 hwparams9;
867};
868
869
870#define DWC3_MODE(n) ((n) & 0x7)
871
872
873#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
874
875
876#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
877#define DWC3_NUM_EPS_MASK (0x3f << 12)
878#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
879 (DWC3_NUM_EPS_MASK)) >> 12)
880#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
881 (DWC3_NUM_IN_EPS_MASK)) >> 18)
882
883
884#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
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906struct dwc3_request {
907 struct usb_request request;
908 struct list_head list;
909 struct dwc3_ep *dep;
910 struct scatterlist *sg;
911 struct scatterlist *start_sg;
912
913 unsigned int num_pending_sgs;
914 unsigned int num_queued_sgs;
915 unsigned int remaining;
916
917 unsigned int status;
918#define DWC3_REQUEST_STATUS_QUEUED 0
919#define DWC3_REQUEST_STATUS_STARTED 1
920#define DWC3_REQUEST_STATUS_DISCONNECTED 2
921#define DWC3_REQUEST_STATUS_DEQUEUED 3
922#define DWC3_REQUEST_STATUS_STALLED 4
923#define DWC3_REQUEST_STATUS_COMPLETED 5
924#define DWC3_REQUEST_STATUS_UNKNOWN -1
925
926 u8 epnum;
927 struct dwc3_trb *trb;
928 dma_addr_t trb_dma;
929
930 unsigned int num_trbs;
931
932 unsigned int needs_extra_trb:1;
933 unsigned int direction:1;
934 unsigned int mapped:1;
935};
936
937
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939
940
941struct dwc3_scratchpad_array {
942 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
943};
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1091struct dwc3 {
1092 struct work_struct drd_work;
1093 struct dwc3_trb *ep0_trb;
1094 void *bounce;
1095 void *scratchbuf;
1096 u8 *setup_buf;
1097 dma_addr_t ep0_trb_addr;
1098 dma_addr_t bounce_addr;
1099 dma_addr_t scratch_addr;
1100 struct dwc3_request ep0_usb_req;
1101 struct completion ep0_in_setup;
1102
1103
1104 spinlock_t lock;
1105
1106
1107 struct mutex mutex;
1108
1109 struct device *dev;
1110 struct device *sysdev;
1111
1112 struct platform_device *xhci;
1113 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1114
1115 struct dwc3_event_buffer *ev_buf;
1116 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1117
1118 struct usb_gadget *gadget;
1119 struct usb_gadget_driver *gadget_driver;
1120
1121 struct clk_bulk_data *clks;
1122 int num_clks;
1123
1124 struct reset_control *reset;
1125
1126 struct usb_phy *usb2_phy;
1127 struct usb_phy *usb3_phy;
1128
1129 struct phy *usb2_generic_phy;
1130 struct phy *usb3_generic_phy;
1131
1132 bool phys_ready;
1133
1134 struct ulpi *ulpi;
1135 bool ulpi_ready;
1136
1137 void __iomem *regs;
1138 size_t regs_size;
1139
1140 enum usb_dr_mode dr_mode;
1141 u32 current_dr_role;
1142 u32 desired_dr_role;
1143 struct extcon_dev *edev;
1144 struct notifier_block edev_nb;
1145 enum usb_phy_interface hsphy_mode;
1146 struct usb_role_switch *role_sw;
1147 enum usb_dr_mode role_switch_default_mode;
1148
1149 struct power_supply *usb_psy;
1150
1151 u32 fladj;
1152 u32 irq_gadget;
1153 u32 otg_irq;
1154 u32 current_otg_role;
1155 u32 desired_otg_role;
1156 bool otg_restart_host;
1157 u32 nr_scratch;
1158 u32 u1u2;
1159 u32 maximum_speed;
1160 u32 gadget_max_speed;
1161 enum usb_ssp_rate max_ssp_rate;
1162 enum usb_ssp_rate gadget_ssp_rate;
1163
1164 u32 ip;
1165
1166#define DWC3_IP 0x5533
1167#define DWC31_IP 0x3331
1168#define DWC32_IP 0x3332
1169
1170 u32 revision;
1171
1172#define DWC3_REVISION_ANY 0x0
1173#define DWC3_REVISION_173A 0x5533173a
1174#define DWC3_REVISION_175A 0x5533175a
1175#define DWC3_REVISION_180A 0x5533180a
1176#define DWC3_REVISION_183A 0x5533183a
1177#define DWC3_REVISION_185A 0x5533185a
1178#define DWC3_REVISION_187A 0x5533187a
1179#define DWC3_REVISION_188A 0x5533188a
1180#define DWC3_REVISION_190A 0x5533190a
1181#define DWC3_REVISION_194A 0x5533194a
1182#define DWC3_REVISION_200A 0x5533200a
1183#define DWC3_REVISION_202A 0x5533202a
1184#define DWC3_REVISION_210A 0x5533210a
1185#define DWC3_REVISION_220A 0x5533220a
1186#define DWC3_REVISION_230A 0x5533230a
1187#define DWC3_REVISION_240A 0x5533240a
1188#define DWC3_REVISION_250A 0x5533250a
1189#define DWC3_REVISION_260A 0x5533260a
1190#define DWC3_REVISION_270A 0x5533270a
1191#define DWC3_REVISION_280A 0x5533280a
1192#define DWC3_REVISION_290A 0x5533290a
1193#define DWC3_REVISION_300A 0x5533300a
1194#define DWC3_REVISION_310A 0x5533310a
1195#define DWC3_REVISION_330A 0x5533330a
1196
1197#define DWC31_REVISION_ANY 0x0
1198#define DWC31_REVISION_110A 0x3131302a
1199#define DWC31_REVISION_120A 0x3132302a
1200#define DWC31_REVISION_160A 0x3136302a
1201#define DWC31_REVISION_170A 0x3137302a
1202#define DWC31_REVISION_180A 0x3138302a
1203#define DWC31_REVISION_190A 0x3139302a
1204
1205#define DWC32_REVISION_ANY 0x0
1206#define DWC32_REVISION_100A 0x3130302a
1207
1208 u32 version_type;
1209
1210#define DWC31_VERSIONTYPE_ANY 0x0
1211#define DWC31_VERSIONTYPE_EA01 0x65613031
1212#define DWC31_VERSIONTYPE_EA02 0x65613032
1213#define DWC31_VERSIONTYPE_EA03 0x65613033
1214#define DWC31_VERSIONTYPE_EA04 0x65613034
1215#define DWC31_VERSIONTYPE_EA05 0x65613035
1216#define DWC31_VERSIONTYPE_EA06 0x65613036
1217
1218 enum dwc3_ep0_next ep0_next_event;
1219 enum dwc3_ep0_state ep0state;
1220 enum dwc3_link_state link_state;
1221
1222 u16 u2sel;
1223 u16 u2pel;
1224 u8 u1sel;
1225 u8 u1pel;
1226
1227 u8 speed;
1228
1229 u8 num_eps;
1230
1231 struct dwc3_hwparams hwparams;
1232 struct debugfs_regset32 *regset;
1233
1234 u32 dbg_lsp_select;
1235
1236 u8 test_mode;
1237 u8 test_mode_nr;
1238 u8 lpm_nyet_threshold;
1239 u8 hird_threshold;
1240 u8 rx_thr_num_pkt_prd;
1241 u8 rx_max_burst_prd;
1242 u8 tx_thr_num_pkt_prd;
1243 u8 tx_max_burst_prd;
1244 u8 tx_fifo_resize_max_num;
1245
1246 const char *hsphy_interface;
1247
1248 unsigned connected:1;
1249 unsigned delayed_status:1;
1250 unsigned ep0_bounced:1;
1251 unsigned ep0_expect_in:1;
1252 unsigned has_hibernation:1;
1253 unsigned sysdev_is_parent:1;
1254 unsigned has_lpm_erratum:1;
1255 unsigned is_utmi_l1_suspend:1;
1256 unsigned is_fpga:1;
1257 unsigned pending_events:1;
1258 unsigned do_fifo_resize:1;
1259 unsigned pullups_connected:1;
1260 unsigned setup_packet_pending:1;
1261 unsigned three_stage_setup:1;
1262 unsigned dis_start_transfer_quirk:1;
1263 unsigned usb3_lpm_capable:1;
1264 unsigned usb2_lpm_disable:1;
1265 unsigned usb2_gadget_lpm_disable:1;
1266
1267 unsigned disable_scramble_quirk:1;
1268 unsigned u2exit_lfps_quirk:1;
1269 unsigned u2ss_inp3_quirk:1;
1270 unsigned req_p1p2p3_quirk:1;
1271 unsigned del_p1p2p3_quirk:1;
1272 unsigned del_phy_power_chg_quirk:1;
1273 unsigned lfps_filter_quirk:1;
1274 unsigned rx_detect_poll_quirk:1;
1275 unsigned dis_u3_susphy_quirk:1;
1276 unsigned dis_u2_susphy_quirk:1;
1277 unsigned dis_enblslpm_quirk:1;
1278 unsigned dis_u1_entry_quirk:1;
1279 unsigned dis_u2_entry_quirk:1;
1280 unsigned dis_rxdet_inp3_quirk:1;
1281 unsigned dis_u2_freeclk_exists_quirk:1;
1282 unsigned dis_del_phy_power_chg_quirk:1;
1283 unsigned dis_tx_ipgap_linecheck_quirk:1;
1284 unsigned parkmode_disable_ss_quirk:1;
1285
1286 unsigned tx_de_emphasis_quirk:1;
1287 unsigned tx_de_emphasis:2;
1288
1289 unsigned dis_metastability_quirk:1;
1290
1291 unsigned dis_split_quirk:1;
1292 unsigned async_callbacks:1;
1293
1294 u16 imod_interval;
1295
1296 int max_cfg_eps;
1297 int last_fifo_depth;
1298 int num_ep_resized;
1299};
1300
1301#define INCRX_BURST_MODE 0
1302#define INCRX_UNDEF_LENGTH_BURST_MODE 1
1303
1304#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1305
1306
1307
1308struct dwc3_event_type {
1309 u32 is_devspec:1;
1310 u32 type:7;
1311 u32 reserved8_31:24;
1312} __packed;
1313
1314#define DWC3_DEPEVT_XFERCOMPLETE 0x01
1315#define DWC3_DEPEVT_XFERINPROGRESS 0x02
1316#define DWC3_DEPEVT_XFERNOTREADY 0x03
1317#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1318#define DWC3_DEPEVT_STREAMEVT 0x06
1319#define DWC3_DEPEVT_EPCMDCMPLT 0x07
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340struct dwc3_event_depevt {
1341 u32 one_bit:1;
1342 u32 endpoint_number:5;
1343 u32 endpoint_event:4;
1344 u32 reserved11_10:2;
1345 u32 status:4;
1346
1347
1348#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1349
1350
1351#define DEPEVT_STATUS_BUSERR BIT(0)
1352#define DEPEVT_STATUS_SHORT BIT(1)
1353#define DEPEVT_STATUS_IOC BIT(2)
1354#define DEPEVT_STATUS_LST BIT(3)
1355#define DEPEVT_STATUS_MISSED_ISOC BIT(3)
1356
1357
1358#define DEPEVT_STREAMEVT_FOUND 1
1359#define DEPEVT_STREAMEVT_NOTFOUND 2
1360
1361
1362#define DEPEVT_STREAM_PRIME 0xfffe
1363#define DEPEVT_STREAM_NOSTREAM 0x0
1364
1365
1366#define DEPEVT_STATUS_CONTROL_DATA 1
1367#define DEPEVT_STATUS_CONTROL_STATUS 2
1368#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1369
1370
1371#define DEPEVT_TRANSFER_NO_RESOURCE 1
1372#define DEPEVT_TRANSFER_BUS_EXPIRY 2
1373
1374 u32 parameters:16;
1375
1376
1377#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1378} __packed;
1379
1380
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1399
1400
1401
1402struct dwc3_event_devt {
1403 u32 one_bit:1;
1404 u32 device_event:7;
1405 u32 type:4;
1406 u32 reserved15_12:4;
1407 u32 event_info:9;
1408 u32 reserved31_25:7;
1409} __packed;
1410
1411
1412
1413
1414
1415
1416
1417
1418struct dwc3_event_gevt {
1419 u32 one_bit:1;
1420 u32 device_event:7;
1421 u32 phy_port_number:4;
1422 u32 reserved31_12:20;
1423} __packed;
1424
1425
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1430
1431
1432
1433union dwc3_event {
1434 u32 raw;
1435 struct dwc3_event_type type;
1436 struct dwc3_event_depevt depevt;
1437 struct dwc3_event_devt devt;
1438 struct dwc3_event_gevt gevt;
1439};
1440
1441
1442
1443
1444
1445
1446
1447
1448struct dwc3_gadget_ep_cmd_params {
1449 u32 param2;
1450 u32 param1;
1451 u32 param0;
1452};
1453
1454
1455
1456
1457
1458#define DWC3_HAS_PERIPHERAL BIT(0)
1459#define DWC3_HAS_XHCI BIT(1)
1460#define DWC3_HAS_OTG BIT(3)
1461
1462
1463void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1464void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1465u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1466
1467#define DWC3_IP_IS(_ip) \
1468 (dwc->ip == _ip##_IP)
1469
1470#define DWC3_VER_IS(_ip, _ver) \
1471 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1472
1473#define DWC3_VER_IS_PRIOR(_ip, _ver) \
1474 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1475
1476#define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
1477 (DWC3_IP_IS(_ip) && \
1478 dwc->revision >= _ip##_REVISION_##_from && \
1479 (!(_ip##_REVISION_##_to) || \
1480 dwc->revision <= _ip##_REVISION_##_to))
1481
1482#define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
1483 (DWC3_VER_IS(_ip, _ver) && \
1484 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
1485 (!(_ip##_VERSIONTYPE_##_to) || \
1486 dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1487
1488
1489
1490
1491
1492
1493
1494static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
1495{
1496 u32 mdwidth;
1497
1498 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1499 if (DWC3_IP_IS(DWC32))
1500 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1501
1502 return mdwidth;
1503}
1504
1505bool dwc3_has_imod(struct dwc3 *dwc);
1506
1507int dwc3_event_buffers_setup(struct dwc3 *dwc);
1508void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1509
1510#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1511int dwc3_host_init(struct dwc3 *dwc);
1512void dwc3_host_exit(struct dwc3 *dwc);
1513#else
1514static inline int dwc3_host_init(struct dwc3 *dwc)
1515{ return 0; }
1516static inline void dwc3_host_exit(struct dwc3 *dwc)
1517{ }
1518#endif
1519
1520#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1521int dwc3_gadget_init(struct dwc3 *dwc);
1522void dwc3_gadget_exit(struct dwc3 *dwc);
1523int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1524int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1525int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1526int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1527 struct dwc3_gadget_ep_cmd_params *params);
1528int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1529 u32 param);
1530void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1531#else
1532static inline int dwc3_gadget_init(struct dwc3 *dwc)
1533{ return 0; }
1534static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1535{ }
1536static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1537{ return 0; }
1538static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1539{ return 0; }
1540static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1541 enum dwc3_link_state state)
1542{ return 0; }
1543
1544static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1545 struct dwc3_gadget_ep_cmd_params *params)
1546{ return 0; }
1547static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1548 int cmd, u32 param)
1549{ return 0; }
1550static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
1551{ }
1552#endif
1553
1554#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1555int dwc3_drd_init(struct dwc3 *dwc);
1556void dwc3_drd_exit(struct dwc3 *dwc);
1557void dwc3_otg_init(struct dwc3 *dwc);
1558void dwc3_otg_exit(struct dwc3 *dwc);
1559void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1560void dwc3_otg_host_init(struct dwc3 *dwc);
1561#else
1562static inline int dwc3_drd_init(struct dwc3 *dwc)
1563{ return 0; }
1564static inline void dwc3_drd_exit(struct dwc3 *dwc)
1565{ }
1566static inline void dwc3_otg_init(struct dwc3 *dwc)
1567{ }
1568static inline void dwc3_otg_exit(struct dwc3 *dwc)
1569{ }
1570static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1571{ }
1572static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1573{ }
1574#endif
1575
1576
1577#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1578int dwc3_gadget_suspend(struct dwc3 *dwc);
1579int dwc3_gadget_resume(struct dwc3 *dwc);
1580void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1581#else
1582static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1583{
1584 return 0;
1585}
1586
1587static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1588{
1589 return 0;
1590}
1591
1592static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1593{
1594}
1595#endif
1596
1597#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1598int dwc3_ulpi_init(struct dwc3 *dwc);
1599void dwc3_ulpi_exit(struct dwc3 *dwc);
1600#else
1601static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1602{ return 0; }
1603static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1604{ }
1605#endif
1606
1607#endif
1608