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18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/i2c.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/prefetch.h>
28#include <linux/proc_fs.h>
29#include <linux/slab.h>
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/isp1301.h>
33
34#ifdef CONFIG_USB_GADGET_DEBUG_FILES
35#include <linux/debugfs.h>
36#include <linux/seq_file.h>
37#endif
38
39
40
41
42typedef void (*usc_chg_event)(int);
43struct lpc32xx_usbd_cfg {
44 int vbus_drv_pol;
45 usc_chg_event conn_chgb;
46 usc_chg_event susp_chgb;
47 usc_chg_event rmwk_chgb;
48};
49
50
51
52
53
54
55#define NUM_ENDPOINTS 16
56
57
58
59
60#define IRQ_USB_LP 0
61#define IRQ_USB_HP 1
62#define IRQ_USB_DEVDMA 2
63#define IRQ_USB_ATX 3
64
65#define EP_OUT 0
66#define EP_IN 1
67
68
69#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
70
71#define EP_INT_TYPE 0
72#define EP_ISO_TYPE 1
73#define EP_BLK_TYPE 2
74#define EP_CTL_TYPE 3
75
76
77#define WAIT_FOR_SETUP 0
78#define DATA_IN 1
79#define DATA_OUT 2
80
81
82
83
84struct lpc32xx_usbd_dd_gad {
85 u32 dd_next_phy;
86 u32 dd_setup;
87 u32 dd_buffer_addr;
88 u32 dd_status;
89 u32 dd_iso_ps_mem_addr;
90 u32 this_dma;
91 u32 iso_status[6];
92 u32 dd_next_v;
93};
94
95
96
97
98struct lpc32xx_ep {
99 struct usb_ep ep;
100 struct list_head queue;
101 struct lpc32xx_udc *udc;
102
103 u32 hwep_num_base;
104 u32 hwep_num;
105 u32 maxpacket;
106 u32 lep;
107
108 bool is_in;
109 bool req_pending;
110 u32 eptype;
111
112 u32 totalints;
113
114 bool wedge;
115};
116
117enum atx_type {
118 ISP1301,
119 STOTG04,
120};
121
122
123
124
125struct lpc32xx_udc {
126 struct usb_gadget gadget;
127 struct usb_gadget_driver *driver;
128 struct platform_device *pdev;
129 struct device *dev;
130 spinlock_t lock;
131 struct i2c_client *isp1301_i2c_client;
132
133
134 struct lpc32xx_usbd_cfg *board;
135 void __iomem *udp_baseaddr;
136 int udp_irq[4];
137 struct clk *usb_slv_clk;
138
139
140 u32 *udca_v_base;
141 u32 udca_p_base;
142 struct dma_pool *dd_cache;
143
144
145 u32 enabled_devints;
146 u32 enabled_hwepints;
147 u32 dev_status;
148 u32 realized_eps;
149
150
151 u8 vbus;
152 u8 last_vbus;
153 int pullup;
154 int poweron;
155 enum atx_type atx;
156
157
158 struct work_struct pullup_job;
159 struct work_struct power_job;
160
161
162 struct lpc32xx_ep ep[NUM_ENDPOINTS];
163 bool enabled;
164 bool clocked;
165 bool suspended;
166 int ep0state;
167 atomic_t enabled_ep_cnt;
168 wait_queue_head_t ep_disable_wait_queue;
169};
170
171
172
173
174struct lpc32xx_request {
175 struct usb_request req;
176 struct list_head queue;
177 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
178 bool mapped;
179 bool send_zlp;
180};
181
182static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
183{
184 return container_of(g, struct lpc32xx_udc, gadget);
185}
186
187#define ep_dbg(epp, fmt, arg...) \
188 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
189#define ep_err(epp, fmt, arg...) \
190 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
191#define ep_info(epp, fmt, arg...) \
192 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
193#define ep_warn(epp, fmt, arg...) \
194 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
195
196#define UDCA_BUFF_SIZE (128)
197
198
199
200
201
202#define USBD_DEVINTST(x) ((x) + 0x200)
203#define USBD_DEVINTEN(x) ((x) + 0x204)
204#define USBD_DEVINTCLR(x) ((x) + 0x208)
205#define USBD_DEVINTSET(x) ((x) + 0x20C)
206#define USBD_CMDCODE(x) ((x) + 0x210)
207#define USBD_CMDDATA(x) ((x) + 0x214)
208#define USBD_RXDATA(x) ((x) + 0x218)
209#define USBD_TXDATA(x) ((x) + 0x21C)
210#define USBD_RXPLEN(x) ((x) + 0x220)
211#define USBD_TXPLEN(x) ((x) + 0x224)
212#define USBD_CTRL(x) ((x) + 0x228)
213#define USBD_DEVINTPRI(x) ((x) + 0x22C)
214#define USBD_EPINTST(x) ((x) + 0x230)
215#define USBD_EPINTEN(x) ((x) + 0x234)
216#define USBD_EPINTCLR(x) ((x) + 0x238)
217#define USBD_EPINTSET(x) ((x) + 0x23C)
218#define USBD_EPINTPRI(x) ((x) + 0x240)
219#define USBD_REEP(x) ((x) + 0x244)
220#define USBD_EPIND(x) ((x) + 0x248)
221#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
222
223
224
225#define USBD_DMARST(x) ((x) + 0x250)
226#define USBD_DMARCLR(x) ((x) + 0x254)
227#define USBD_DMARSET(x) ((x) + 0x258)
228
229#define USBD_UDCAH(x) ((x) + 0x280)
230
231
232#define USBD_EPDMAST(x) ((x) + 0x284)
233#define USBD_EPDMAEN(x) ((x) + 0x288)
234#define USBD_EPDMADIS(x) ((x) + 0x28C)
235
236#define USBD_DMAINTST(x) ((x) + 0x290)
237#define USBD_DMAINTEN(x) ((x) + 0x294)
238
239#define USBD_EOTINTST(x) ((x) + 0x2A0)
240#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
241#define USBD_EOTINTSET(x) ((x) + 0x2A8)
242
243#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
244#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
245#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
246
247#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
248#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
249#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
250
251
252
253
254
255#define USBD_ERR_INT (1 << 9)
256#define USBD_EP_RLZED (1 << 8)
257#define USBD_TXENDPKT (1 << 7)
258#define USBD_RXENDPKT (1 << 6)
259#define USBD_CDFULL (1 << 5)
260#define USBD_CCEMPTY (1 << 4)
261#define USBD_DEV_STAT (1 << 3)
262#define USBD_EP_SLOW (1 << 2)
263#define USBD_EP_FAST (1 << 1)
264#define USBD_FRAME (1 << 0)
265
266
267
268
269
270
271#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
272
273
274#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
275
276
277
278
279
280
281
282
283
284
285#define USBD_EP_SEL(e) (1 << (e))
286
287
288
289
290#define USBD_SYS_ERR_INT (1 << 2)
291#define USBD_NEW_DD_INT (1 << 1)
292#define USBD_EOT_INT (1 << 0)
293
294
295
296
297#define USBD_PKT_RDY (1 << 11)
298#define USBD_DV (1 << 10)
299#define USBD_PK_LEN_MASK 0x3FF
300
301
302
303
304#define USBD_LOG_ENDPOINT(e) ((e) << 2)
305#define USBD_WR_EN (1 << 1)
306#define USBD_RD_EN (1 << 0)
307
308
309
310
311#define USBD_CMD_CODE(c) ((c) << 16)
312#define USBD_CMD_PHASE(p) ((p) << 8)
313
314
315
316
317#define USBD_DMAEP(e) (1 << (e))
318
319
320struct lpc32xx_usbd_dd {
321 u32 *dd_next;
322 u32 dd_setup;
323 u32 dd_buffer_addr;
324 u32 dd_status;
325 u32 dd_iso_ps_mem_addr;
326};
327
328
329#define DD_SETUP_ATLE_DMA_MODE 0x01
330#define DD_SETUP_NEXT_DD_VALID 0x04
331#define DD_SETUP_ISO_EP 0x10
332#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
333#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
334
335
336#define DD_STATUS_DD_RETIRED 0x01
337#define DD_STATUS_STS_MASK 0x1E
338#define DD_STATUS_STS_NS 0x00
339#define DD_STATUS_STS_BS 0x02
340#define DD_STATUS_STS_NC 0x04
341#define DD_STATUS_STS_DUR 0x06
342#define DD_STATUS_STS_DOR 0x08
343#define DD_STATUS_STS_SE 0x12
344#define DD_STATUS_PKT_VAL 0x20
345#define DD_STATUS_LSB_EX 0x40
346#define DD_STATUS_MSB_EX 0x80
347#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
348#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
349
350
351
352
353
354
355
356#define FRAME_INT 0x00000001
357#define EP_FAST_INT 0x00000002
358#define EP_SLOW_INT 0x00000004
359#define DEV_STAT_INT 0x00000008
360#define CCEMTY_INT 0x00000010
361#define CDFULL_INT 0x00000020
362#define RxENDPKT_INT 0x00000040
363#define TxENDPKT_INT 0x00000080
364#define EP_RLZED_INT 0x00000100
365#define ERR_INT 0x00000200
366
367
368#define PKT_LNGTH_MASK 0x000003FF
369#define PKT_DV 0x00000400
370#define PKT_RDY 0x00000800
371
372
373#define CTRL_RD_EN 0x00000001
374#define CTRL_WR_EN 0x00000002
375
376
377#define CMD_SET_ADDR 0x00D00500
378#define CMD_CFG_DEV 0x00D80500
379#define CMD_SET_MODE 0x00F30500
380#define CMD_RD_FRAME 0x00F50500
381#define DAT_RD_FRAME 0x00F50200
382#define CMD_RD_TEST 0x00FD0500
383#define DAT_RD_TEST 0x00FD0200
384#define CMD_SET_DEV_STAT 0x00FE0500
385#define CMD_GET_DEV_STAT 0x00FE0500
386#define DAT_GET_DEV_STAT 0x00FE0200
387#define CMD_GET_ERR_CODE 0x00FF0500
388#define DAT_GET_ERR_CODE 0x00FF0200
389#define CMD_RD_ERR_STAT 0x00FB0500
390#define DAT_RD_ERR_STAT 0x00FB0200
391#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
392#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
393#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
394#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
395#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
396#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
397#define CMD_CLR_BUF 0x00F20500
398#define DAT_CLR_BUF 0x00F20200
399#define CMD_VALID_BUF 0x00FA0500
400
401
402#define DEV_ADDR_MASK 0x7F
403#define DEV_EN 0x80
404
405
406#define CONF_DVICE 0x01
407
408
409#define AP_CLK 0x01
410#define INAK_CI 0x02
411#define INAK_CO 0x04
412#define INAK_II 0x08
413#define INAK_IO 0x10
414#define INAK_BI 0x20
415#define INAK_BO 0x40
416
417
418#define DEV_CON 0x01
419#define DEV_CON_CH 0x02
420#define DEV_SUS 0x04
421#define DEV_SUS_CH 0x08
422#define DEV_RST 0x10
423
424
425#define ERR_EC_MASK 0x0F
426#define ERR_EA 0x10
427
428
429#define ERR_PID 0x01
430#define ERR_UEPKT 0x02
431#define ERR_DCRC 0x04
432#define ERR_TIMOUT 0x08
433#define ERR_EOP 0x10
434#define ERR_B_OVRN 0x20
435#define ERR_BTSTF 0x40
436#define ERR_TGL 0x80
437
438
439#define EP_SEL_F 0x01
440#define EP_SEL_ST 0x02
441#define EP_SEL_STP 0x04
442#define EP_SEL_PO 0x08
443#define EP_SEL_EPN 0x10
444#define EP_SEL_B_1_FULL 0x20
445#define EP_SEL_B_2_FULL 0x40
446
447
448#define EP_STAT_ST 0x01
449#define EP_STAT_DA 0x20
450#define EP_STAT_RF_MO 0x40
451#define EP_STAT_CND_ST 0x80
452
453
454#define CLR_BUF_PO 0x01
455
456
457#define EOT_INT 0x01
458#define NDD_REQ_INT 0x02
459#define SYS_ERR_INT 0x04
460
461#define DRIVER_VERSION "1.03"
462static const char driver_name[] = "lpc32xx_udc";
463
464
465
466
467
468
469#ifdef CONFIG_USB_GADGET_DEBUG_FILES
470static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
471static const char debug_filename[] = "driver/udc";
472
473static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
474{
475 struct lpc32xx_request *req;
476
477 seq_printf(s, "\n");
478 seq_printf(s, "%12s, maxpacket %4d %3s",
479 ep->ep.name, ep->ep.maxpacket,
480 ep->is_in ? "in" : "out");
481 seq_printf(s, " type %4s", epnames[ep->eptype]);
482 seq_printf(s, " ints: %12d", ep->totalints);
483
484 if (list_empty(&ep->queue))
485 seq_printf(s, "\t(queue empty)\n");
486 else {
487 list_for_each_entry(req, &ep->queue, queue) {
488 u32 length = req->req.actual;
489
490 seq_printf(s, "\treq %p len %d/%d buf %p\n",
491 &req->req, length,
492 req->req.length, req->req.buf);
493 }
494 }
495}
496
497static int udc_show(struct seq_file *s, void *unused)
498{
499 struct lpc32xx_udc *udc = s->private;
500 struct lpc32xx_ep *ep;
501 unsigned long flags;
502
503 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
504
505 spin_lock_irqsave(&udc->lock, flags);
506
507 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
508 udc->vbus ? "present" : "off",
509 udc->enabled ? (udc->vbus ? "active" : "enabled") :
510 "disabled",
511 udc->gadget.is_selfpowered ? "self" : "VBUS",
512 udc->suspended ? ", suspended" : "",
513 udc->driver ? udc->driver->driver.name : "(none)");
514
515 if (udc->enabled && udc->vbus) {
516 proc_ep_show(s, &udc->ep[0]);
517 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
518 proc_ep_show(s, ep);
519 }
520
521 spin_unlock_irqrestore(&udc->lock, flags);
522
523 return 0;
524}
525
526DEFINE_SHOW_ATTRIBUTE(udc);
527
528static void create_debug_file(struct lpc32xx_udc *udc)
529{
530 debugfs_create_file(debug_filename, 0, NULL, udc, &udc_fops);
531}
532
533static void remove_debug_file(struct lpc32xx_udc *udc)
534{
535 debugfs_remove(debugfs_lookup(debug_filename, NULL));
536}
537
538#else
539static inline void create_debug_file(struct lpc32xx_udc *udc) {}
540static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
541#endif
542
543
544static void isp1301_udc_configure(struct lpc32xx_udc *udc)
545{
546 u8 value;
547 s32 vendor, product;
548
549 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
550 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
551
552 if (vendor == 0x0483 && product == 0xa0c4)
553 udc->atx = STOTG04;
554
555
556
557
558
559 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
560 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
561 MC1_UART_EN);
562
563
564 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
565 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
566 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
567 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
568
569
570
571
572 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
573 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
574
575 value = MC2_BI_DI;
576 if (udc->atx != STOTG04)
577 value |= MC2_SPD_SUSP_CTRL;
578 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
579 ISP1301_I2C_MODE_CONTROL_2, value);
580
581
582 if (udc->board->vbus_drv_pol != 0)
583 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
584 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
585 else
586 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
587 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
588 OTG1_VBUS_DRV);
589
590
591
592
593 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
594 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
595 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
596 ISP1301_I2C_OTG_CONTROL_1,
597 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
598
599
600 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
601 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
602 msleep(1);
603 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
604 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
605 OTG1_VBUS_DISCHRG);
606
607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
608 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
609
610 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
611 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
612 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
613 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
614
615 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
616 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
617 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
618 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
619
620}
621
622
623static void isp1301_pullup_set(struct lpc32xx_udc *udc)
624{
625 if (udc->pullup)
626
627 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
628 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
629 else
630
631 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
632 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
633 OTG1_DP_PULLUP);
634}
635
636static void pullup_work(struct work_struct *work)
637{
638 struct lpc32xx_udc *udc =
639 container_of(work, struct lpc32xx_udc, pullup_job);
640
641 isp1301_pullup_set(udc);
642}
643
644static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
645 int block)
646{
647 if (en_pullup == udc->pullup)
648 return;
649
650 udc->pullup = en_pullup;
651 if (block)
652 isp1301_pullup_set(udc);
653 else
654
655 schedule_work(&udc->pullup_job);
656}
657
658#ifdef CONFIG_PM
659
660static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
661{
662
663 if (udc->atx == STOTG04)
664 return;
665
666 if (enable != 0)
667
668
669 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
670 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
671 MC2_GLOBAL_PWR_DN);
672 else
673
674 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
675 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
676}
677
678static void power_work(struct work_struct *work)
679{
680 struct lpc32xx_udc *udc =
681 container_of(work, struct lpc32xx_udc, power_job);
682
683 isp1301_set_powerstate(udc, udc->poweron);
684}
685#endif
686
687
688
689
690
691
692
693static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
694{
695 u32 pass = 0;
696 int to;
697
698
699 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
700 (void) tmp;
701
702 while (pass == 0) {
703 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
704
705
706 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
707 to = 10000;
708 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
709 USBD_CCEMPTY) == 0) && (to > 0)) {
710 to--;
711 }
712
713 if (to > 0)
714 pass = 1;
715
716 cpu_relax();
717 }
718}
719
720
721static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
722 u32 data)
723{
724 udc_protocol_cmd_w(udc, cmd);
725 udc_protocol_cmd_w(udc, data);
726}
727
728
729
730static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
731{
732 int to = 1000;
733
734
735 writel((USBD_CDFULL | USBD_CCEMPTY),
736 USBD_DEVINTCLR(udc->udp_baseaddr));
737
738
739 udc_protocol_cmd_w(udc, cmd);
740
741 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
742 && (to > 0))
743 to--;
744 if (!to)
745 dev_dbg(udc->dev,
746 "Protocol engine didn't receive response (CDFULL)\n");
747
748 return readl(USBD_CMDDATA(udc->udp_baseaddr));
749}
750
751
752
753
754
755
756
757static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
758{
759 udc->enabled_devints |= devmask;
760 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
761}
762
763
764static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
765{
766 udc->enabled_devints &= ~mask;
767 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
768}
769
770
771static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
772{
773 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
774}
775
776
777
778
779
780
781
782static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
783{
784 udc->enabled_hwepints |= (1 << hwep);
785 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
786}
787
788
789static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
790{
791 udc->enabled_hwepints &= ~(1 << hwep);
792 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
793}
794
795
796static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
797{
798 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
799}
800
801
802static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
803{
804 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
805}
806
807
808static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
809{
810 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
811}
812
813
814
815
816
817
818
819
820
821static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
822 u32 maxpacket)
823{
824 int to = 1000;
825
826 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
827 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
828 udc->realized_eps |= (1 << hwep);
829 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
830 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
831
832
833 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
834 USBD_EP_RLZED)) && (to > 0))
835 to--;
836 if (!to)
837 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
838
839 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
840}
841
842
843static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
844{
845 udc->realized_eps &= ~(1 << hwep);
846 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
847}
848
849
850
851
852
853
854
855static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
856{
857 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
858 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
859}
860
861
862static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
863{
864 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
865 DAT_WR_BYTE(EP_STAT_DA));
866}
867
868
869static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
870{
871 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
872 DAT_WR_BYTE(EP_STAT_ST));
873}
874
875
876static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
877{
878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
879 DAT_WR_BYTE(0));
880}
881
882
883static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
884{
885 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
886}
887
888
889
890
891
892
893
894static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
895{
896 udc_select_hwep(udc, hwep);
897 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
898}
899
900
901static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
902{
903 udc_select_hwep(udc, hwep);
904 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
905}
906
907static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
908{
909
910 uda_clear_hwepint(udc, hwep);
911 return udc_selep_clrint(udc, hwep);
912}
913
914
915
916
917
918
919
920static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
921{
922 dma_addr_t dma;
923 struct lpc32xx_usbd_dd_gad *dd;
924
925 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
926 if (dd)
927 dd->this_dma = dma;
928
929 return dd;
930}
931
932
933static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
934{
935 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
936}
937
938
939
940
941
942
943
944
945
946static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
947{
948 if (enable != 0) {
949 if (udc->clocked)
950 return;
951
952 udc->clocked = 1;
953 clk_prepare_enable(udc->usb_slv_clk);
954 } else {
955 if (!udc->clocked)
956 return;
957
958 udc->clocked = 0;
959 clk_disable_unprepare(udc->usb_slv_clk);
960 }
961}
962
963
964static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
965{
966
967
968 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
969 DAT_WR_BYTE(DEV_EN | addr));
970}
971
972
973
974
975static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
976{
977 struct lpc32xx_request *req;
978 u32 hwep = ep->hwep_num;
979
980 ep->req_pending = 1;
981
982
983 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
984
985
986 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
987
988
989 udc_ep_dma_enable(udc, hwep);
990
991
992 if (req->req.length % ep->ep.maxpacket)
993 req->send_zlp = 0;
994
995 return 0;
996}
997
998
999
1000
1001static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1002{
1003 struct lpc32xx_request *req;
1004 u32 hwep = ep->hwep_num;
1005
1006 ep->req_pending = 1;
1007
1008
1009 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1010
1011
1012 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1013
1014
1015 udc_ep_dma_enable(udc, hwep);
1016 return 0;
1017}
1018
1019static void udc_disable(struct lpc32xx_udc *udc)
1020{
1021 u32 i;
1022
1023
1024 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1025 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1026
1027
1028 uda_disable_devint(udc, 0x3FF);
1029
1030
1031 for (i = 0; i < 32; i++) {
1032 uda_disable_hwepint(udc, i);
1033 uda_clear_hwepint(udc, i);
1034 udc_disable_hwep(udc, i);
1035 udc_unrealize_hwep(udc, i);
1036 udc->udca_v_base[i] = 0;
1037
1038
1039 udc_ep_dma_disable(udc, i);
1040 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1041 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1042 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1043 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1044 }
1045
1046
1047 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1048
1049 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1050}
1051
1052static void udc_enable(struct lpc32xx_udc *udc)
1053{
1054 u32 i;
1055 struct lpc32xx_ep *ep = &udc->ep[0];
1056
1057
1058 udc_disable(udc);
1059
1060
1061 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1062
1063
1064 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1065 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1066
1067
1068 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1069
1070
1071 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1072
1073
1074 for (i = 0; i <= 1; i++) {
1075 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1076 uda_enable_hwepint(udc, i);
1077 udc_select_hwep(udc, i);
1078 udc_clrstall_hwep(udc, i);
1079 udc_clr_buffer_hwep(udc, i);
1080 }
1081
1082
1083 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1084 USBD_EP_FAST));
1085 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1086 USBD_EP_FAST));
1087
1088
1089
1090 udc_set_address(udc, 0);
1091 udc_set_address(udc, 0);
1092
1093
1094 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1095 USBD_DMAINTEN(udc->udp_baseaddr));
1096
1097 udc->dev_status = 0;
1098}
1099
1100
1101
1102
1103
1104
1105
1106static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1107{
1108
1109 if (udc->board->conn_chgb != NULL)
1110 udc->board->conn_chgb(conn);
1111}
1112
1113
1114static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1115{
1116
1117 if (udc->board->susp_chgb != NULL)
1118 udc->board->susp_chgb(conn);
1119
1120 if (conn)
1121 udc->suspended = 0;
1122 else
1123 udc->suspended = 1;
1124}
1125
1126
1127static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1128{
1129 if (udc->board->rmwk_chgb != NULL)
1130 udc->board->rmwk_chgb(udc->dev_status &
1131 (1 << USB_DEVICE_REMOTE_WAKEUP));
1132}
1133
1134
1135static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1136{
1137 int n, i, bl;
1138 u16 *p16;
1139 u32 *p32, tmp, cbytes;
1140
1141
1142 switch (((uintptr_t) data) & 0x3) {
1143 case 0:
1144 p32 = (u32 *) data;
1145 cbytes = (bytes & ~0x3);
1146
1147
1148 for (n = 0; n < cbytes; n += 4)
1149 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1150
1151
1152 bl = bytes - cbytes;
1153 if (bl) {
1154 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1155 for (n = 0; n < bl; n++)
1156 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1157
1158 }
1159 break;
1160
1161 case 1:
1162 case 3:
1163
1164 for (n = 0; n < bytes; n += 4) {
1165 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1166
1167 bl = bytes - n;
1168 if (bl > 4)
1169 bl = 4;
1170
1171 for (i = 0; i < bl; i++)
1172 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
1173 }
1174 break;
1175
1176 case 2:
1177 p16 = (u16 *) data;
1178 cbytes = (bytes & ~0x3);
1179
1180
1181 for (n = 0; n < cbytes; n += 4) {
1182 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1183 *p16++ = (u16)(tmp & 0xFFFF);
1184 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1185 }
1186
1187
1188 bl = bytes - cbytes;
1189 if (bl) {
1190 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1191 for (n = 0; n < bl; n++)
1192 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1193 }
1194 break;
1195 }
1196}
1197
1198
1199
1200
1201
1202static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1203 u32 bytes)
1204{
1205 u32 tmpv;
1206 int to = 1000;
1207 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1208
1209
1210 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1211
1212
1213 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1214 PKT_RDY) == 0) && (to > 0))
1215 to--;
1216 if (!to)
1217 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1218
1219
1220 tmp = tmpv & PKT_LNGTH_MASK;
1221 if (bytes < tmp)
1222 tmp = bytes;
1223
1224 if ((tmp > 0) && (data != NULL))
1225 udc_pop_fifo(udc, (u8 *) data, tmp);
1226
1227 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1228
1229
1230 udc_clr_buffer_hwep(udc, hwep);
1231
1232 return tmp;
1233}
1234
1235
1236static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1237{
1238 int n, i, bl;
1239 u16 *p16;
1240 u32 *p32, tmp, cbytes;
1241
1242
1243 switch (((uintptr_t) data) & 0x3) {
1244 case 0:
1245 p32 = (u32 *) data;
1246 cbytes = (bytes & ~0x3);
1247
1248
1249 for (n = 0; n < cbytes; n += 4)
1250 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1251
1252
1253 bl = bytes - cbytes;
1254 if (bl) {
1255 tmp = 0;
1256 for (n = 0; n < bl; n++)
1257 tmp |= data[cbytes + n] << (n * 8);
1258
1259 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1260 }
1261 break;
1262
1263 case 1:
1264 case 3:
1265
1266 for (n = 0; n < bytes; n += 4) {
1267 bl = bytes - n;
1268 if (bl > 4)
1269 bl = 4;
1270
1271 tmp = 0;
1272 for (i = 0; i < bl; i++)
1273 tmp |= data[n + i] << (i * 8);
1274
1275 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1276 }
1277 break;
1278
1279 case 2:
1280 p16 = (u16 *) data;
1281 cbytes = (bytes & ~0x3);
1282
1283
1284 for (n = 0; n < cbytes; n += 4) {
1285 tmp = *p16++ & 0xFFFF;
1286 tmp |= (*p16++ & 0xFFFF) << 16;
1287 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1288 }
1289
1290
1291 bl = bytes - cbytes;
1292 if (bl) {
1293 tmp = 0;
1294 for (n = 0; n < bl; n++)
1295 tmp |= data[cbytes + n] << (n * 8);
1296
1297 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1298 }
1299 break;
1300 }
1301}
1302
1303
1304
1305
1306static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1307 u32 bytes)
1308{
1309 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1310
1311 if ((bytes > 0) && (data == NULL))
1312 return;
1313
1314
1315 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1316
1317 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1318
1319
1320 if (bytes == 0)
1321 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1322 else
1323 udc_stuff_fifo(udc, (u8 *) data, bytes);
1324
1325 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1326
1327 udc_val_buffer_hwep(udc, hwep);
1328}
1329
1330
1331
1332static void uda_usb_reset(struct lpc32xx_udc *udc)
1333{
1334 u32 i = 0;
1335
1336 udc_enable(udc);
1337 udc->gadget.speed = USB_SPEED_FULL;
1338
1339 for (i = 1; i < NUM_ENDPOINTS; i++) {
1340 struct lpc32xx_ep *ep = &udc->ep[i];
1341 ep->req_pending = 0;
1342 }
1343}
1344
1345
1346static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1347{
1348 udc_write_hwep(udc, EP_IN, NULL, 0);
1349}
1350
1351
1352static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1353{
1354 u16 flo, fhi;
1355
1356 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1357 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1358 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1359
1360 return (fhi << 8) | flo;
1361}
1362
1363
1364static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1365{
1366 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1367}
1368
1369
1370static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1371{
1372 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1373}
1374
1375
1376static void udc_reinit(struct lpc32xx_udc *udc)
1377{
1378 u32 i;
1379
1380 INIT_LIST_HEAD(&udc->gadget.ep_list);
1381 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1382
1383 for (i = 0; i < NUM_ENDPOINTS; i++) {
1384 struct lpc32xx_ep *ep = &udc->ep[i];
1385
1386 if (i != 0)
1387 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1388 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
1389 INIT_LIST_HEAD(&ep->queue);
1390 ep->req_pending = 0;
1391 }
1392
1393 udc->ep0state = WAIT_FOR_SETUP;
1394}
1395
1396
1397static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1398{
1399 struct lpc32xx_udc *udc = ep->udc;
1400
1401 list_del_init(&req->queue);
1402 if (req->req.status == -EINPROGRESS)
1403 req->req.status = status;
1404 else
1405 status = req->req.status;
1406
1407 if (ep->lep) {
1408 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
1409
1410
1411 udc_dd_free(udc, req->dd_desc_ptr);
1412 }
1413
1414 if (status && status != -ESHUTDOWN)
1415 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1416
1417 ep->req_pending = 0;
1418 spin_unlock(&udc->lock);
1419 usb_gadget_giveback_request(&ep->ep, &req->req);
1420 spin_lock(&udc->lock);
1421}
1422
1423
1424static void nuke(struct lpc32xx_ep *ep, int status)
1425{
1426 struct lpc32xx_request *req;
1427
1428 while (!list_empty(&ep->queue)) {
1429 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1430 done(ep, req, status);
1431 }
1432
1433 if (status == -ESHUTDOWN) {
1434 uda_disable_hwepint(ep->udc, ep->hwep_num);
1435 udc_disable_hwep(ep->udc, ep->hwep_num);
1436 }
1437}
1438
1439
1440static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1441{
1442 struct lpc32xx_request *req;
1443 struct lpc32xx_ep *ep0 = &udc->ep[0];
1444 u32 tsend, ts = 0;
1445
1446 if (list_empty(&ep0->queue))
1447
1448 return 0;
1449 else
1450 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1451 queue);
1452
1453 tsend = ts = req->req.length - req->req.actual;
1454 if (ts == 0) {
1455
1456 udc_ep0_send_zlp(udc);
1457 done(ep0, req, 0);
1458 return 1;
1459 } else if (ts > ep0->ep.maxpacket)
1460 ts = ep0->ep.maxpacket;
1461
1462
1463 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1464
1465
1466 req->req.actual += ts;
1467
1468 if (tsend >= ep0->ep.maxpacket)
1469 return 0;
1470
1471
1472 udc->ep0state = WAIT_FOR_SETUP;
1473 done(ep0, req, 0);
1474 return 1;
1475}
1476
1477
1478static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1479{
1480 struct lpc32xx_request *req;
1481 struct lpc32xx_ep *ep0 = &udc->ep[0];
1482 u32 tr, bufferspace;
1483
1484 if (list_empty(&ep0->queue))
1485 return 0;
1486 else
1487 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1488 queue);
1489
1490 if (req) {
1491 if (req->req.length == 0) {
1492
1493 done(ep0, req, 0);
1494 udc->ep0state = WAIT_FOR_SETUP;
1495 return 1;
1496 }
1497
1498
1499 bufferspace = req->req.length - req->req.actual;
1500 if (bufferspace > ep0->ep.maxpacket)
1501 bufferspace = ep0->ep.maxpacket;
1502
1503
1504 prefetchw(req->req.buf + req->req.actual);
1505 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1506 bufferspace);
1507 req->req.actual += bufferspace;
1508
1509 if (tr < ep0->ep.maxpacket) {
1510
1511 done(ep0, req, 0);
1512 udc->ep0state = WAIT_FOR_SETUP;
1513 return 1;
1514 }
1515 }
1516
1517 return 0;
1518}
1519
1520
1521static void stop_activity(struct lpc32xx_udc *udc)
1522{
1523 struct usb_gadget_driver *driver = udc->driver;
1524 int i;
1525
1526 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1527 driver = NULL;
1528
1529 udc->gadget.speed = USB_SPEED_UNKNOWN;
1530 udc->suspended = 0;
1531
1532 for (i = 0; i < NUM_ENDPOINTS; i++) {
1533 struct lpc32xx_ep *ep = &udc->ep[i];
1534 nuke(ep, -ESHUTDOWN);
1535 }
1536 if (driver) {
1537 spin_unlock(&udc->lock);
1538 driver->disconnect(&udc->gadget);
1539 spin_lock(&udc->lock);
1540 }
1541
1542 isp1301_pullup_enable(udc, 0, 0);
1543 udc_disable(udc);
1544 udc_reinit(udc);
1545}
1546
1547
1548
1549
1550
1551static void pullup(struct lpc32xx_udc *udc, int is_on)
1552{
1553 if (!udc->clocked)
1554 return;
1555
1556 if (!udc->enabled || !udc->vbus)
1557 is_on = 0;
1558
1559 if (is_on != udc->pullup)
1560 isp1301_pullup_enable(udc, is_on, 0);
1561}
1562
1563
1564static int lpc32xx_ep_disable(struct usb_ep *_ep)
1565{
1566 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1567 struct lpc32xx_udc *udc = ep->udc;
1568 unsigned long flags;
1569
1570 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1571 return -EINVAL;
1572 spin_lock_irqsave(&udc->lock, flags);
1573
1574 nuke(ep, -ESHUTDOWN);
1575
1576
1577 udc_ep_dma_disable(udc, ep->hwep_num);
1578 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1579 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1580 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1581 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1582
1583
1584 udc->udca_v_base[ep->hwep_num] = 0;
1585
1586
1587 uda_clear_hwepint(udc, ep->hwep_num);
1588 udc_unrealize_hwep(udc, ep->hwep_num);
1589
1590 ep->hwep_num = 0;
1591
1592 spin_unlock_irqrestore(&udc->lock, flags);
1593
1594 atomic_dec(&udc->enabled_ep_cnt);
1595 wake_up(&udc->ep_disable_wait_queue);
1596
1597 return 0;
1598}
1599
1600
1601static int lpc32xx_ep_enable(struct usb_ep *_ep,
1602 const struct usb_endpoint_descriptor *desc)
1603{
1604 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1605 struct lpc32xx_udc *udc;
1606 u16 maxpacket;
1607 u32 tmp;
1608 unsigned long flags;
1609
1610
1611 if ((!_ep) || (!ep) || (!desc) ||
1612 (desc->bDescriptorType != USB_DT_ENDPOINT))
1613 return -EINVAL;
1614
1615 udc = ep->udc;
1616 maxpacket = usb_endpoint_maxp(desc);
1617 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1618 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1619 return -EINVAL;
1620 }
1621
1622
1623 if (ep->hwep_num_base == 0) {
1624 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1625 return -EINVAL;
1626 }
1627
1628
1629 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1630 dev_dbg(udc->dev, "bogus device state\n");
1631 return -ESHUTDOWN;
1632 }
1633
1634 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1635 switch (tmp) {
1636 case USB_ENDPOINT_XFER_CONTROL:
1637 return -EINVAL;
1638
1639 case USB_ENDPOINT_XFER_INT:
1640 if (maxpacket > ep->maxpacket) {
1641 dev_dbg(udc->dev,
1642 "Bad INT endpoint maxpacket %d\n", maxpacket);
1643 return -EINVAL;
1644 }
1645 break;
1646
1647 case USB_ENDPOINT_XFER_BULK:
1648 switch (maxpacket) {
1649 case 8:
1650 case 16:
1651 case 32:
1652 case 64:
1653 break;
1654
1655 default:
1656 dev_dbg(udc->dev,
1657 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1658 return -EINVAL;
1659 }
1660 break;
1661
1662 case USB_ENDPOINT_XFER_ISOC:
1663 break;
1664 }
1665 spin_lock_irqsave(&udc->lock, flags);
1666
1667
1668 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1669 ep->ep.maxpacket = maxpacket;
1670
1671
1672 if (ep->is_in)
1673
1674 ep->hwep_num = ep->hwep_num_base + EP_IN;
1675 else
1676 ep->hwep_num = ep->hwep_num_base;
1677
1678 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1679 ep->hwep_num, maxpacket, (ep->is_in == 1));
1680
1681
1682
1683 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1684 udc_clr_buffer_hwep(udc, ep->hwep_num);
1685 uda_disable_hwepint(udc, ep->hwep_num);
1686 udc_clrstall_hwep(udc, ep->hwep_num);
1687
1688
1689 udc_ep_dma_disable(udc, ep->hwep_num);
1690 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1691 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1692 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1693 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1694
1695 spin_unlock_irqrestore(&udc->lock, flags);
1696
1697 atomic_inc(&udc->enabled_ep_cnt);
1698 return 0;
1699}
1700
1701
1702
1703
1704
1705static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1706 gfp_t gfp_flags)
1707{
1708 struct lpc32xx_request *req;
1709
1710 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1711 if (!req)
1712 return NULL;
1713
1714 INIT_LIST_HEAD(&req->queue);
1715 return &req->req;
1716}
1717
1718
1719
1720
1721
1722static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1723 struct usb_request *_req)
1724{
1725 struct lpc32xx_request *req;
1726
1727 req = container_of(_req, struct lpc32xx_request, req);
1728 BUG_ON(!list_empty(&req->queue));
1729 kfree(req);
1730}
1731
1732
1733static int lpc32xx_ep_queue(struct usb_ep *_ep,
1734 struct usb_request *_req, gfp_t gfp_flags)
1735{
1736 struct lpc32xx_request *req;
1737 struct lpc32xx_ep *ep;
1738 struct lpc32xx_udc *udc;
1739 unsigned long flags;
1740 int status = 0;
1741
1742 req = container_of(_req, struct lpc32xx_request, req);
1743 ep = container_of(_ep, struct lpc32xx_ep, ep);
1744
1745 if (!_ep || !_req || !_req->complete || !_req->buf ||
1746 !list_empty(&req->queue))
1747 return -EINVAL;
1748
1749 udc = ep->udc;
1750
1751 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1752 return -EPIPE;
1753
1754 if (ep->lep) {
1755 struct lpc32xx_usbd_dd_gad *dd;
1756
1757 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1758 if (status)
1759 return status;
1760
1761
1762 dd = udc_dd_alloc(udc);
1763 if (!dd) {
1764
1765 return -ENOMEM;
1766 }
1767 req->dd_desc_ptr = dd;
1768
1769
1770 dd->dd_next_phy = dd->dd_next_v = 0;
1771 dd->dd_buffer_addr = req->req.dma;
1772 dd->dd_status = 0;
1773
1774
1775 if (ep->eptype == EP_ISO_TYPE) {
1776 dd->dd_setup = DD_SETUP_ISO_EP |
1777 DD_SETUP_PACKETLEN(0) |
1778 DD_SETUP_DMALENBYTES(1);
1779 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1780 if (ep->is_in)
1781 dd->iso_status[0] = req->req.length;
1782 else
1783 dd->iso_status[0] = 0;
1784 } else
1785 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1786 DD_SETUP_DMALENBYTES(req->req.length);
1787 }
1788
1789 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1790 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1791
1792 spin_lock_irqsave(&udc->lock, flags);
1793
1794 _req->status = -EINPROGRESS;
1795 _req->actual = 0;
1796 req->send_zlp = _req->zero;
1797
1798
1799 if (list_empty(&ep->queue)) {
1800 list_add_tail(&req->queue, &ep->queue);
1801
1802 if (ep->hwep_num_base == 0) {
1803
1804 if (ep->is_in) {
1805
1806 udc->ep0state = DATA_IN;
1807 status = udc_ep0_in_req(udc);
1808 } else {
1809
1810 udc->ep0state = DATA_OUT;
1811 status = udc_ep0_out_req(udc);
1812 }
1813 } else if (ep->is_in) {
1814
1815 if (!ep->req_pending)
1816 udc_ep_in_req_dma(udc, ep);
1817 } else
1818
1819 if (!ep->req_pending)
1820 udc_ep_out_req_dma(udc, ep);
1821 } else
1822 list_add_tail(&req->queue, &ep->queue);
1823
1824 spin_unlock_irqrestore(&udc->lock, flags);
1825
1826 return (status < 0) ? status : 0;
1827}
1828
1829
1830static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1831{
1832 struct lpc32xx_ep *ep;
1833 struct lpc32xx_request *req;
1834 unsigned long flags;
1835
1836 ep = container_of(_ep, struct lpc32xx_ep, ep);
1837 if (!_ep || ep->hwep_num_base == 0)
1838 return -EINVAL;
1839
1840 spin_lock_irqsave(&ep->udc->lock, flags);
1841
1842
1843 list_for_each_entry(req, &ep->queue, queue) {
1844 if (&req->req == _req)
1845 break;
1846 }
1847 if (&req->req != _req) {
1848 spin_unlock_irqrestore(&ep->udc->lock, flags);
1849 return -EINVAL;
1850 }
1851
1852 done(ep, req, -ECONNRESET);
1853
1854 spin_unlock_irqrestore(&ep->udc->lock, flags);
1855
1856 return 0;
1857}
1858
1859
1860static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1861{
1862 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1863 struct lpc32xx_udc *udc;
1864 unsigned long flags;
1865
1866 if ((!ep) || (ep->hwep_num <= 1))
1867 return -EINVAL;
1868
1869
1870 if (ep->is_in)
1871 return -EAGAIN;
1872
1873 udc = ep->udc;
1874 spin_lock_irqsave(&udc->lock, flags);
1875
1876 if (value == 1) {
1877
1878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1879 DAT_WR_BYTE(EP_STAT_ST));
1880 } else {
1881
1882 ep->wedge = 0;
1883 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1884 DAT_WR_BYTE(0));
1885 }
1886
1887 spin_unlock_irqrestore(&udc->lock, flags);
1888
1889 return 0;
1890}
1891
1892
1893static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1894{
1895 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1896
1897 if (!_ep || !ep->udc)
1898 return -EINVAL;
1899
1900 ep->wedge = 1;
1901
1902 return usb_ep_set_halt(_ep);
1903}
1904
1905static const struct usb_ep_ops lpc32xx_ep_ops = {
1906 .enable = lpc32xx_ep_enable,
1907 .disable = lpc32xx_ep_disable,
1908 .alloc_request = lpc32xx_ep_alloc_request,
1909 .free_request = lpc32xx_ep_free_request,
1910 .queue = lpc32xx_ep_queue,
1911 .dequeue = lpc32xx_ep_dequeue,
1912 .set_halt = lpc32xx_ep_set_halt,
1913 .set_wedge = lpc32xx_ep_set_wedge,
1914};
1915
1916
1917static void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1918{
1919
1920 udc_clearep_getsts(udc, ep->hwep_num);
1921
1922
1923 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1924}
1925
1926
1927
1928
1929
1930
1931static void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1932{
1933 u32 epstatus;
1934 struct lpc32xx_request *req;
1935
1936 if (ep->hwep_num <= 0)
1937 return;
1938
1939 uda_clear_hwepint(udc, ep->hwep_num);
1940
1941
1942 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1943 return;
1944
1945
1946 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1947
1948
1949
1950
1951
1952 if (epstatus & EP_SEL_F)
1953 return;
1954
1955 if (ep->is_in) {
1956 udc_send_in_zlp(udc, ep);
1957 uda_disable_hwepint(udc, ep->hwep_num);
1958 } else
1959 return;
1960
1961
1962 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1963 if (req) {
1964 done(ep, req, 0);
1965
1966
1967 if (!list_empty(&ep->queue)) {
1968 if (ep->is_in)
1969 udc_ep_in_req_dma(udc, ep);
1970 else
1971 udc_ep_out_req_dma(udc, ep);
1972 } else
1973 ep->req_pending = 0;
1974 }
1975}
1976
1977
1978
1979static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1980{
1981 u32 status;
1982 struct lpc32xx_request *req;
1983 struct lpc32xx_usbd_dd_gad *dd;
1984
1985#ifdef CONFIG_USB_GADGET_DEBUG_FILES
1986 ep->totalints++;
1987#endif
1988
1989 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1990 if (!req) {
1991 ep_err(ep, "DMA interrupt on no req!\n");
1992 return;
1993 }
1994 dd = req->dd_desc_ptr;
1995
1996
1997 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
1998 ep_warn(ep, "DMA descriptor did not retire\n");
1999
2000
2001 udc_ep_dma_disable(udc, ep->hwep_num);
2002 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2003 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2004
2005
2006 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2007 (1 << ep->hwep_num)) {
2008 writel((1 << ep->hwep_num),
2009 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2010 ep_err(ep, "AHB critical error!\n");
2011 ep->req_pending = 0;
2012
2013
2014
2015
2016 done(ep, req, -ECONNABORTED);
2017 return;
2018 }
2019
2020
2021 status = dd->dd_status;
2022 switch (status & DD_STATUS_STS_MASK) {
2023 case DD_STATUS_STS_NS:
2024
2025 ep->req_pending = 0;
2026 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2027 status);
2028
2029 done(ep, req, -ECONNABORTED);
2030 return;
2031
2032 case DD_STATUS_STS_BS:
2033
2034 ep->req_pending = 0;
2035 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2036 status);
2037 done(ep, req, -ECONNABORTED);
2038 return;
2039
2040 case DD_STATUS_STS_NC:
2041 case DD_STATUS_STS_DUR:
2042
2043
2044 break;
2045
2046 default:
2047
2048 ep->req_pending = 0;
2049 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2050 status);
2051 done(ep, req, -ECONNABORTED);
2052 return;
2053 }
2054
2055
2056 if (ep->eptype == EP_ISO_TYPE) {
2057 if (ep->is_in)
2058 req->req.actual = req->req.length;
2059 else
2060 req->req.actual = dd->iso_status[0] & 0xFFFF;
2061 } else
2062 req->req.actual += DD_STATUS_CURDMACNT(status);
2063
2064
2065
2066 if (req->send_zlp) {
2067
2068
2069
2070
2071
2072 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2073 udc_clearep_getsts(udc, ep->hwep_num);
2074 uda_enable_hwepint(udc, ep->hwep_num);
2075 udc_clearep_getsts(udc, ep->hwep_num);
2076
2077
2078 return;
2079 } else
2080 udc_send_in_zlp(udc, ep);
2081 }
2082
2083
2084 done(ep, req, 0);
2085
2086
2087 udc_clearep_getsts(udc, ep->hwep_num);
2088 if (!list_empty((&ep->queue))) {
2089 if (ep->is_in)
2090 udc_ep_in_req_dma(udc, ep);
2091 else
2092 udc_ep_out_req_dma(udc, ep);
2093 } else
2094 ep->req_pending = 0;
2095
2096}
2097
2098
2099
2100
2101
2102
2103static void udc_handle_dev(struct lpc32xx_udc *udc)
2104{
2105 u32 tmp;
2106
2107 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2108 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2109
2110 if (tmp & DEV_RST)
2111 uda_usb_reset(udc);
2112 else if (tmp & DEV_CON_CH)
2113 uda_power_event(udc, (tmp & DEV_CON));
2114 else if (tmp & DEV_SUS_CH) {
2115 if (tmp & DEV_SUS) {
2116 if (udc->vbus == 0)
2117 stop_activity(udc);
2118 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2119 udc->driver) {
2120
2121 udc->poweron = 0;
2122 schedule_work(&udc->pullup_job);
2123 uda_resm_susp_event(udc, 1);
2124 }
2125 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2126 udc->driver && udc->vbus) {
2127 uda_resm_susp_event(udc, 0);
2128
2129 udc->poweron = 1;
2130 schedule_work(&udc->pullup_job);
2131 }
2132 }
2133}
2134
2135static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2136{
2137 struct lpc32xx_ep *ep;
2138 u32 ep0buff = 0, tmp;
2139
2140 switch (reqtype & USB_RECIP_MASK) {
2141 case USB_RECIP_INTERFACE:
2142 break;
2143
2144 case USB_RECIP_DEVICE:
2145 ep0buff = udc->gadget.is_selfpowered;
2146 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2147 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2148 break;
2149
2150 case USB_RECIP_ENDPOINT:
2151 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2152 ep = &udc->ep[tmp];
2153 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2154 return -EOPNOTSUPP;
2155
2156 if (wIndex & USB_DIR_IN) {
2157 if (!ep->is_in)
2158 return -EOPNOTSUPP;
2159 } else if (ep->is_in)
2160 return -EOPNOTSUPP;
2161
2162
2163 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2164 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2165
2166 if (tmp & EP_SEL_ST)
2167 ep0buff = (1 << USB_ENDPOINT_HALT);
2168 else
2169 ep0buff = 0;
2170 break;
2171
2172 default:
2173 break;
2174 }
2175
2176
2177 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2178
2179 return 0;
2180}
2181
2182static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2183{
2184 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2185 struct usb_ctrlrequest ctrlpkt;
2186 int i, bytes;
2187 u16 wIndex, wValue, reqtype, req, tmp;
2188
2189
2190 nuke(ep0, -EPROTO);
2191
2192
2193 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2194 if (bytes != 8) {
2195 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2196 bytes);
2197 return;
2198 }
2199
2200
2201 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2202 wValue = le16_to_cpu(ctrlpkt.wValue);
2203 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2204
2205
2206 if (likely(reqtype & USB_DIR_IN))
2207 ep0->is_in = 1;
2208 else
2209 ep0->is_in = 0;
2210
2211
2212 req = le16_to_cpu(ctrlpkt.bRequest);
2213 switch (req) {
2214 case USB_REQ_CLEAR_FEATURE:
2215 case USB_REQ_SET_FEATURE:
2216 switch (reqtype) {
2217 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2218 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2219 goto stall;
2220
2221
2222 if (req == USB_REQ_CLEAR_FEATURE)
2223 udc->dev_status &=
2224 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2225 else
2226 udc->dev_status |=
2227 (1 << USB_DEVICE_REMOTE_WAKEUP);
2228 uda_remwkp_cgh(udc);
2229 goto zlp_send;
2230
2231 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2232 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2233 if ((wValue != USB_ENDPOINT_HALT) ||
2234 (tmp >= NUM_ENDPOINTS))
2235 break;
2236
2237
2238 ep = &udc->ep[tmp];
2239 tmp = ep->hwep_num;
2240 if (tmp == 0)
2241 break;
2242
2243 if (req == USB_REQ_SET_FEATURE)
2244 udc_stall_hwep(udc, tmp);
2245 else if (!ep->wedge)
2246 udc_clrstall_hwep(udc, tmp);
2247
2248 goto zlp_send;
2249
2250 default:
2251 break;
2252 }
2253 break;
2254
2255 case USB_REQ_SET_ADDRESS:
2256 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2257 udc_set_address(udc, wValue);
2258 goto zlp_send;
2259 }
2260 break;
2261
2262 case USB_REQ_GET_STATUS:
2263 udc_get_status(udc, reqtype, wIndex);
2264 return;
2265
2266 default:
2267 break;
2268 }
2269
2270 if (likely(udc->driver)) {
2271
2272
2273 spin_unlock(&udc->lock);
2274 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2275
2276 spin_lock(&udc->lock);
2277 if (req == USB_REQ_SET_CONFIGURATION) {
2278
2279 if (wValue) {
2280
2281 udc_set_device_configured(udc);
2282
2283 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2284 DAT_WR_BYTE(AP_CLK |
2285 INAK_BI | INAK_II));
2286 } else {
2287
2288 udc_set_device_unconfigured(udc);
2289
2290
2291 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2292 DAT_WR_BYTE(AP_CLK));
2293 }
2294 }
2295
2296 if (i < 0) {
2297
2298 dev_dbg(udc->dev,
2299 "req %02x.%02x protocol STALL; stat %d\n",
2300 reqtype, req, i);
2301 udc->ep0state = WAIT_FOR_SETUP;
2302 goto stall;
2303 }
2304 }
2305
2306 if (!ep0->is_in)
2307 udc_ep0_send_zlp(udc);
2308
2309 return;
2310
2311stall:
2312 udc_stall_hwep(udc, EP_IN);
2313 return;
2314
2315zlp_send:
2316 udc_ep0_send_zlp(udc);
2317 return;
2318}
2319
2320
2321static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2322{
2323 struct lpc32xx_ep *ep0 = &udc->ep[0];
2324 u32 epstatus;
2325
2326
2327 epstatus = udc_clearep_getsts(udc, EP_IN);
2328
2329#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2330 ep0->totalints++;
2331#endif
2332
2333
2334 if (epstatus & EP_SEL_ST) {
2335 udc_clrstall_hwep(udc, EP_IN);
2336 nuke(ep0, -ECONNABORTED);
2337 udc->ep0state = WAIT_FOR_SETUP;
2338 return;
2339 }
2340
2341
2342 if (!(epstatus & EP_SEL_F)) {
2343
2344 if (udc->ep0state == DATA_IN)
2345 udc_ep0_in_req(udc);
2346 else {
2347
2348 nuke(ep0, -ECONNABORTED);
2349 udc->ep0state = WAIT_FOR_SETUP;
2350 }
2351 }
2352}
2353
2354
2355static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2356{
2357 struct lpc32xx_ep *ep0 = &udc->ep[0];
2358 u32 epstatus;
2359
2360
2361 epstatus = udc_clearep_getsts(udc, EP_OUT);
2362
2363
2364#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2365 ep0->totalints++;
2366#endif
2367
2368
2369 if (epstatus & EP_SEL_ST) {
2370 udc_clrstall_hwep(udc, EP_OUT);
2371 nuke(ep0, -ECONNABORTED);
2372 udc->ep0state = WAIT_FOR_SETUP;
2373 return;
2374 }
2375
2376
2377 if (epstatus & EP_SEL_EPN)
2378 return;
2379
2380 if (epstatus & EP_SEL_STP) {
2381 nuke(ep0, 0);
2382 udc->ep0state = WAIT_FOR_SETUP;
2383 }
2384
2385
2386 if (epstatus & EP_SEL_F)
2387
2388 switch (udc->ep0state) {
2389 case WAIT_FOR_SETUP:
2390 udc_handle_ep0_setup(udc);
2391 break;
2392
2393 case DATA_OUT:
2394 udc_ep0_out_req(udc);
2395 break;
2396
2397 default:
2398
2399 nuke(ep0, -ECONNABORTED);
2400 udc->ep0state = WAIT_FOR_SETUP;
2401 }
2402}
2403
2404
2405static int lpc32xx_get_frame(struct usb_gadget *gadget)
2406{
2407 int frame;
2408 unsigned long flags;
2409 struct lpc32xx_udc *udc = to_udc(gadget);
2410
2411 if (!udc->clocked)
2412 return -EINVAL;
2413
2414 spin_lock_irqsave(&udc->lock, flags);
2415
2416 frame = (int) udc_get_current_frame(udc);
2417
2418 spin_unlock_irqrestore(&udc->lock, flags);
2419
2420 return frame;
2421}
2422
2423static int lpc32xx_wakeup(struct usb_gadget *gadget)
2424{
2425 return -ENOTSUPP;
2426}
2427
2428static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2429{
2430 gadget->is_selfpowered = (is_on != 0);
2431
2432 return 0;
2433}
2434
2435
2436
2437
2438
2439static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2440{
2441 unsigned long flags;
2442 struct lpc32xx_udc *udc = to_udc(gadget);
2443
2444 spin_lock_irqsave(&udc->lock, flags);
2445
2446
2447 if (udc->driver) {
2448 udc_clk_set(udc, 1);
2449 udc_enable(udc);
2450 pullup(udc, is_active);
2451 } else {
2452 stop_activity(udc);
2453 pullup(udc, 0);
2454
2455 spin_unlock_irqrestore(&udc->lock, flags);
2456
2457
2458
2459
2460
2461 if (atomic_read(&udc->enabled_ep_cnt))
2462 wait_event_interruptible(udc->ep_disable_wait_queue,
2463 (atomic_read(&udc->enabled_ep_cnt) == 0));
2464
2465 spin_lock_irqsave(&udc->lock, flags);
2466
2467 udc_clk_set(udc, 0);
2468 }
2469
2470 spin_unlock_irqrestore(&udc->lock, flags);
2471
2472 return 0;
2473}
2474
2475
2476static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2477{
2478 struct lpc32xx_udc *udc = to_udc(gadget);
2479
2480
2481 pullup(udc, is_on);
2482
2483 return 0;
2484}
2485
2486static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2487static int lpc32xx_stop(struct usb_gadget *);
2488
2489static const struct usb_gadget_ops lpc32xx_udc_ops = {
2490 .get_frame = lpc32xx_get_frame,
2491 .wakeup = lpc32xx_wakeup,
2492 .set_selfpowered = lpc32xx_set_selfpowered,
2493 .vbus_session = lpc32xx_vbus_session,
2494 .pullup = lpc32xx_pullup,
2495 .udc_start = lpc32xx_start,
2496 .udc_stop = lpc32xx_stop,
2497};
2498
2499static void nop_release(struct device *dev)
2500{
2501
2502}
2503
2504static const struct lpc32xx_udc controller_template = {
2505 .gadget = {
2506 .ops = &lpc32xx_udc_ops,
2507 .name = driver_name,
2508 .dev = {
2509 .init_name = "gadget",
2510 .release = nop_release,
2511 }
2512 },
2513 .ep[0] = {
2514 .ep = {
2515 .name = "ep0",
2516 .ops = &lpc32xx_ep_ops,
2517 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2518 USB_EP_CAPS_DIR_ALL),
2519 },
2520 .maxpacket = 64,
2521 .hwep_num_base = 0,
2522 .hwep_num = 0,
2523 .lep = 0,
2524 .eptype = EP_CTL_TYPE,
2525 },
2526 .ep[1] = {
2527 .ep = {
2528 .name = "ep1-int",
2529 .ops = &lpc32xx_ep_ops,
2530 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2531 USB_EP_CAPS_DIR_ALL),
2532 },
2533 .maxpacket = 64,
2534 .hwep_num_base = 2,
2535 .hwep_num = 0,
2536 .lep = 1,
2537 .eptype = EP_INT_TYPE,
2538 },
2539 .ep[2] = {
2540 .ep = {
2541 .name = "ep2-bulk",
2542 .ops = &lpc32xx_ep_ops,
2543 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2544 USB_EP_CAPS_DIR_ALL),
2545 },
2546 .maxpacket = 64,
2547 .hwep_num_base = 4,
2548 .hwep_num = 0,
2549 .lep = 2,
2550 .eptype = EP_BLK_TYPE,
2551 },
2552 .ep[3] = {
2553 .ep = {
2554 .name = "ep3-iso",
2555 .ops = &lpc32xx_ep_ops,
2556 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2557 USB_EP_CAPS_DIR_ALL),
2558 },
2559 .maxpacket = 1023,
2560 .hwep_num_base = 6,
2561 .hwep_num = 0,
2562 .lep = 3,
2563 .eptype = EP_ISO_TYPE,
2564 },
2565 .ep[4] = {
2566 .ep = {
2567 .name = "ep4-int",
2568 .ops = &lpc32xx_ep_ops,
2569 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2570 USB_EP_CAPS_DIR_ALL),
2571 },
2572 .maxpacket = 64,
2573 .hwep_num_base = 8,
2574 .hwep_num = 0,
2575 .lep = 4,
2576 .eptype = EP_INT_TYPE,
2577 },
2578 .ep[5] = {
2579 .ep = {
2580 .name = "ep5-bulk",
2581 .ops = &lpc32xx_ep_ops,
2582 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2583 USB_EP_CAPS_DIR_ALL),
2584 },
2585 .maxpacket = 64,
2586 .hwep_num_base = 10,
2587 .hwep_num = 0,
2588 .lep = 5,
2589 .eptype = EP_BLK_TYPE,
2590 },
2591 .ep[6] = {
2592 .ep = {
2593 .name = "ep6-iso",
2594 .ops = &lpc32xx_ep_ops,
2595 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2596 USB_EP_CAPS_DIR_ALL),
2597 },
2598 .maxpacket = 1023,
2599 .hwep_num_base = 12,
2600 .hwep_num = 0,
2601 .lep = 6,
2602 .eptype = EP_ISO_TYPE,
2603 },
2604 .ep[7] = {
2605 .ep = {
2606 .name = "ep7-int",
2607 .ops = &lpc32xx_ep_ops,
2608 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2609 USB_EP_CAPS_DIR_ALL),
2610 },
2611 .maxpacket = 64,
2612 .hwep_num_base = 14,
2613 .hwep_num = 0,
2614 .lep = 7,
2615 .eptype = EP_INT_TYPE,
2616 },
2617 .ep[8] = {
2618 .ep = {
2619 .name = "ep8-bulk",
2620 .ops = &lpc32xx_ep_ops,
2621 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2622 USB_EP_CAPS_DIR_ALL),
2623 },
2624 .maxpacket = 64,
2625 .hwep_num_base = 16,
2626 .hwep_num = 0,
2627 .lep = 8,
2628 .eptype = EP_BLK_TYPE,
2629 },
2630 .ep[9] = {
2631 .ep = {
2632 .name = "ep9-iso",
2633 .ops = &lpc32xx_ep_ops,
2634 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2635 USB_EP_CAPS_DIR_ALL),
2636 },
2637 .maxpacket = 1023,
2638 .hwep_num_base = 18,
2639 .hwep_num = 0,
2640 .lep = 9,
2641 .eptype = EP_ISO_TYPE,
2642 },
2643 .ep[10] = {
2644 .ep = {
2645 .name = "ep10-int",
2646 .ops = &lpc32xx_ep_ops,
2647 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2648 USB_EP_CAPS_DIR_ALL),
2649 },
2650 .maxpacket = 64,
2651 .hwep_num_base = 20,
2652 .hwep_num = 0,
2653 .lep = 10,
2654 .eptype = EP_INT_TYPE,
2655 },
2656 .ep[11] = {
2657 .ep = {
2658 .name = "ep11-bulk",
2659 .ops = &lpc32xx_ep_ops,
2660 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2661 USB_EP_CAPS_DIR_ALL),
2662 },
2663 .maxpacket = 64,
2664 .hwep_num_base = 22,
2665 .hwep_num = 0,
2666 .lep = 11,
2667 .eptype = EP_BLK_TYPE,
2668 },
2669 .ep[12] = {
2670 .ep = {
2671 .name = "ep12-iso",
2672 .ops = &lpc32xx_ep_ops,
2673 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2674 USB_EP_CAPS_DIR_ALL),
2675 },
2676 .maxpacket = 1023,
2677 .hwep_num_base = 24,
2678 .hwep_num = 0,
2679 .lep = 12,
2680 .eptype = EP_ISO_TYPE,
2681 },
2682 .ep[13] = {
2683 .ep = {
2684 .name = "ep13-int",
2685 .ops = &lpc32xx_ep_ops,
2686 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2687 USB_EP_CAPS_DIR_ALL),
2688 },
2689 .maxpacket = 64,
2690 .hwep_num_base = 26,
2691 .hwep_num = 0,
2692 .lep = 13,
2693 .eptype = EP_INT_TYPE,
2694 },
2695 .ep[14] = {
2696 .ep = {
2697 .name = "ep14-bulk",
2698 .ops = &lpc32xx_ep_ops,
2699 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2700 USB_EP_CAPS_DIR_ALL),
2701 },
2702 .maxpacket = 64,
2703 .hwep_num_base = 28,
2704 .hwep_num = 0,
2705 .lep = 14,
2706 .eptype = EP_BLK_TYPE,
2707 },
2708 .ep[15] = {
2709 .ep = {
2710 .name = "ep15-bulk",
2711 .ops = &lpc32xx_ep_ops,
2712 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2713 USB_EP_CAPS_DIR_ALL),
2714 },
2715 .maxpacket = 1023,
2716 .hwep_num_base = 30,
2717 .hwep_num = 0,
2718 .lep = 15,
2719 .eptype = EP_BLK_TYPE,
2720 },
2721};
2722
2723
2724static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2725{
2726 u32 tmp, devstat;
2727 struct lpc32xx_udc *udc = _udc;
2728
2729 spin_lock(&udc->lock);
2730
2731
2732 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2733
2734 devstat &= ~USBD_EP_FAST;
2735 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2736 devstat = devstat & udc->enabled_devints;
2737
2738
2739 if (devstat & USBD_DEV_STAT)
2740 udc_handle_dev(udc);
2741
2742
2743
2744
2745
2746
2747 if (devstat & ERR_INT) {
2748
2749
2750
2751
2752 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2753 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2754 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2755 }
2756
2757 spin_unlock(&udc->lock);
2758
2759 return IRQ_HANDLED;
2760}
2761
2762
2763static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2764{
2765 u32 tmp;
2766 struct lpc32xx_udc *udc = _udc;
2767
2768 spin_lock(&udc->lock);
2769
2770
2771 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2772
2773
2774 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2775
2776
2777 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2778
2779 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2780 udc_handle_ep0_in(udc);
2781
2782
2783 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2784 udc_handle_ep0_out(udc);
2785 }
2786
2787
2788 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2789 int i;
2790
2791
2792 for (i = 1; i < NUM_ENDPOINTS; i++) {
2793 if (tmp & (1 << udc->ep[i].hwep_num))
2794 udc_handle_eps(udc, &udc->ep[i]);
2795 }
2796 }
2797
2798 spin_unlock(&udc->lock);
2799
2800 return IRQ_HANDLED;
2801}
2802
2803static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2804{
2805 struct lpc32xx_udc *udc = _udc;
2806
2807 int i;
2808 u32 tmp;
2809
2810 spin_lock(&udc->lock);
2811
2812
2813 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2814 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2815 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2816 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2817 for (i = 1; i < NUM_ENDPOINTS; i++) {
2818 if (tmp & (1 << udc->ep[i].hwep_num))
2819 udc_handle_dma_ep(udc, &udc->ep[i]);
2820 }
2821
2822 spin_unlock(&udc->lock);
2823
2824 return IRQ_HANDLED;
2825}
2826
2827
2828
2829
2830
2831
2832static void vbus_work(struct lpc32xx_udc *udc)
2833{
2834 u8 value;
2835
2836 if (udc->enabled != 0) {
2837
2838 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2839 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2840
2841
2842 msleep(100);
2843
2844
2845 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2846 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2847 OTG1_VBUS_DISCHRG);
2848
2849
2850 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2851 ISP1301_I2C_INTERRUPT_LATCH |
2852 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2853
2854
2855 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2856 ISP1301_I2C_INTERRUPT_SOURCE);
2857
2858
2859 if (value & INT_SESS_VLD)
2860 udc->vbus = 1;
2861 else
2862 udc->vbus = 0;
2863
2864
2865 if (udc->last_vbus != udc->vbus) {
2866 udc->last_vbus = udc->vbus;
2867 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2868 }
2869 }
2870}
2871
2872static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2873{
2874 struct lpc32xx_udc *udc = _udc;
2875
2876 vbus_work(udc);
2877
2878 return IRQ_HANDLED;
2879}
2880
2881static int lpc32xx_start(struct usb_gadget *gadget,
2882 struct usb_gadget_driver *driver)
2883{
2884 struct lpc32xx_udc *udc = to_udc(gadget);
2885
2886 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2887 dev_err(udc->dev, "bad parameter.\n");
2888 return -EINVAL;
2889 }
2890
2891 if (udc->driver) {
2892 dev_err(udc->dev, "UDC already has a gadget driver\n");
2893 return -EBUSY;
2894 }
2895
2896 udc->driver = driver;
2897 udc->gadget.dev.of_node = udc->dev->of_node;
2898 udc->enabled = 1;
2899 udc->gadget.is_selfpowered = 1;
2900 udc->vbus = 0;
2901
2902
2903 udc->last_vbus = udc->vbus = 0;
2904 vbus_work(udc);
2905
2906
2907 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2908 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2909 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2910 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
2911
2912 return 0;
2913}
2914
2915static int lpc32xx_stop(struct usb_gadget *gadget)
2916{
2917 struct lpc32xx_udc *udc = to_udc(gadget);
2918
2919 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2920 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2921 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2922 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2923
2924 if (udc->clocked) {
2925 spin_lock(&udc->lock);
2926 stop_activity(udc);
2927 spin_unlock(&udc->lock);
2928
2929
2930
2931
2932
2933
2934 if (atomic_read(&udc->enabled_ep_cnt))
2935 wait_event_interruptible(udc->ep_disable_wait_queue,
2936 (atomic_read(&udc->enabled_ep_cnt) == 0));
2937
2938 spin_lock(&udc->lock);
2939 udc_clk_set(udc, 0);
2940 spin_unlock(&udc->lock);
2941 }
2942
2943 udc->enabled = 0;
2944 udc->driver = NULL;
2945
2946 return 0;
2947}
2948
2949static void lpc32xx_udc_shutdown(struct platform_device *dev)
2950{
2951
2952 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
2953
2954 pullup(udc, 0);
2955}
2956
2957
2958
2959
2960
2961static void lpc32xx_usbd_conn_chg(int conn)
2962{
2963
2964
2965}
2966
2967static void lpc32xx_usbd_susp_chg(int susp)
2968{
2969
2970}
2971
2972static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2973{
2974
2975}
2976
2977static struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2978 .vbus_drv_pol = 0,
2979 .conn_chgb = &lpc32xx_usbd_conn_chg,
2980 .susp_chgb = &lpc32xx_usbd_susp_chg,
2981 .rmwk_chgb = &lpc32xx_rmwkup_chg,
2982};
2983
2984
2985static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
2986
2987static int lpc32xx_udc_probe(struct platform_device *pdev)
2988{
2989 struct device *dev = &pdev->dev;
2990 struct lpc32xx_udc *udc;
2991 int retval, i;
2992 dma_addr_t dma_handle;
2993 struct device_node *isp1301_node;
2994
2995 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL);
2996 if (!udc)
2997 return -ENOMEM;
2998
2999 for (i = 0; i <= 15; i++)
3000 udc->ep[i].udc = udc;
3001 udc->gadget.ep0 = &udc->ep[0].ep;
3002
3003
3004 udc->gadget.dev.parent = dev;
3005 udc->pdev = pdev;
3006 udc->dev = &pdev->dev;
3007 udc->enabled = 0;
3008
3009 if (pdev->dev.of_node) {
3010 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3011 "transceiver", 0);
3012 } else {
3013 isp1301_node = NULL;
3014 }
3015
3016 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3017 if (!udc->isp1301_i2c_client) {
3018 return -EPROBE_DEFER;
3019 }
3020
3021 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3022 udc->isp1301_i2c_client->addr);
3023
3024 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3025 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3026 if (retval)
3027 return retval;
3028
3029 udc->board = &lpc32xx_usbddata;
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040 spin_lock_init(&udc->lock);
3041
3042
3043 for (i = 0; i < 4; i++) {
3044 udc->udp_irq[i] = platform_get_irq(pdev, i);
3045 if (udc->udp_irq[i] < 0)
3046 return udc->udp_irq[i];
3047 }
3048
3049 udc->udp_baseaddr = devm_platform_ioremap_resource(pdev, 0);
3050 if (IS_ERR(udc->udp_baseaddr)) {
3051 dev_err(udc->dev, "IO map failure\n");
3052 return PTR_ERR(udc->udp_baseaddr);
3053 }
3054
3055
3056 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL);
3057 if (IS_ERR(udc->usb_slv_clk)) {
3058 dev_err(udc->dev, "failed to acquire USB device clock\n");
3059 return PTR_ERR(udc->usb_slv_clk);
3060 }
3061
3062
3063 retval = clk_prepare_enable(udc->usb_slv_clk);
3064 if (retval < 0) {
3065 dev_err(udc->dev, "failed to start USB device clock\n");
3066 return retval;
3067 }
3068
3069
3070 udc->poweron = udc->pullup = 0;
3071 INIT_WORK(&udc->pullup_job, pullup_work);
3072#ifdef CONFIG_PM
3073 INIT_WORK(&udc->power_job, power_work);
3074#endif
3075
3076
3077 udc->clocked = 1;
3078
3079 isp1301_udc_configure(udc);
3080
3081 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3082 &dma_handle,
3083 (GFP_KERNEL | GFP_DMA));
3084 if (!udc->udca_v_base) {
3085 dev_err(udc->dev, "error getting UDCA region\n");
3086 retval = -ENOMEM;
3087 goto i2c_fail;
3088 }
3089 udc->udca_p_base = dma_handle;
3090 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3091 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3092
3093
3094 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3095 sizeof(struct lpc32xx_usbd_dd_gad),
3096 sizeof(u32), 0);
3097 if (!udc->dd_cache) {
3098 dev_err(udc->dev, "error getting DD DMA region\n");
3099 retval = -ENOMEM;
3100 goto dma_alloc_fail;
3101 }
3102
3103
3104 udc_disable(udc);
3105 udc_reinit(udc);
3106
3107
3108
3109 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP],
3110 lpc32xx_usb_lp_irq, 0, "udc_lp", udc);
3111 if (retval < 0) {
3112 dev_err(udc->dev, "LP request irq %d failed\n",
3113 udc->udp_irq[IRQ_USB_LP]);
3114 goto irq_req_fail;
3115 }
3116 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP],
3117 lpc32xx_usb_hp_irq, 0, "udc_hp", udc);
3118 if (retval < 0) {
3119 dev_err(udc->dev, "HP request irq %d failed\n",
3120 udc->udp_irq[IRQ_USB_HP]);
3121 goto irq_req_fail;
3122 }
3123
3124 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA],
3125 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3126 if (retval < 0) {
3127 dev_err(udc->dev, "DEV request irq %d failed\n",
3128 udc->udp_irq[IRQ_USB_DEVDMA]);
3129 goto irq_req_fail;
3130 }
3131
3132
3133
3134 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL,
3135 lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3136 "udc_otg", udc);
3137 if (retval < 0) {
3138 dev_err(udc->dev, "VBUS request irq %d failed\n",
3139 udc->udp_irq[IRQ_USB_ATX]);
3140 goto irq_req_fail;
3141 }
3142
3143
3144 init_waitqueue_head(&udc->ep_disable_wait_queue);
3145 atomic_set(&udc->enabled_ep_cnt, 0);
3146
3147 retval = usb_add_gadget_udc(dev, &udc->gadget);
3148 if (retval < 0)
3149 goto add_gadget_fail;
3150
3151 dev_set_drvdata(dev, udc);
3152 device_init_wakeup(dev, 1);
3153 create_debug_file(udc);
3154
3155
3156 udc_clk_set(udc, 0);
3157
3158 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3159 return 0;
3160
3161add_gadget_fail:
3162irq_req_fail:
3163 dma_pool_destroy(udc->dd_cache);
3164dma_alloc_fail:
3165 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3166 udc->udca_v_base, udc->udca_p_base);
3167i2c_fail:
3168 clk_disable_unprepare(udc->usb_slv_clk);
3169 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3170
3171 return retval;
3172}
3173
3174static int lpc32xx_udc_remove(struct platform_device *pdev)
3175{
3176 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3177
3178 usb_del_gadget_udc(&udc->gadget);
3179 if (udc->driver)
3180 return -EBUSY;
3181
3182 udc_clk_set(udc, 1);
3183 udc_disable(udc);
3184 pullup(udc, 0);
3185
3186 device_init_wakeup(&pdev->dev, 0);
3187 remove_debug_file(udc);
3188
3189 dma_pool_destroy(udc->dd_cache);
3190 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3191 udc->udca_v_base, udc->udca_p_base);
3192
3193 clk_disable_unprepare(udc->usb_slv_clk);
3194
3195 return 0;
3196}
3197
3198#ifdef CONFIG_PM
3199static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3200{
3201 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3202
3203 if (udc->clocked) {
3204
3205 udc->poweron = 0;
3206 isp1301_set_powerstate(udc, 0);
3207
3208
3209 udc_clk_set(udc, 0);
3210
3211
3212
3213 udc->clocked = 1;
3214
3215
3216 clk_disable_unprepare(udc->usb_slv_clk);
3217 }
3218
3219 return 0;
3220}
3221
3222static int lpc32xx_udc_resume(struct platform_device *pdev)
3223{
3224 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3225
3226 if (udc->clocked) {
3227
3228 clk_prepare_enable(udc->usb_slv_clk);
3229
3230
3231 udc_clk_set(udc, 1);
3232
3233
3234 udc->poweron = 1;
3235 isp1301_set_powerstate(udc, 1);
3236 }
3237
3238 return 0;
3239}
3240#else
3241#define lpc32xx_udc_suspend NULL
3242#define lpc32xx_udc_resume NULL
3243#endif
3244
3245#ifdef CONFIG_OF
3246static const struct of_device_id lpc32xx_udc_of_match[] = {
3247 { .compatible = "nxp,lpc3220-udc", },
3248 { },
3249};
3250MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3251#endif
3252
3253static struct platform_driver lpc32xx_udc_driver = {
3254 .remove = lpc32xx_udc_remove,
3255 .shutdown = lpc32xx_udc_shutdown,
3256 .suspend = lpc32xx_udc_suspend,
3257 .resume = lpc32xx_udc_resume,
3258 .driver = {
3259 .name = driver_name,
3260 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3261 },
3262};
3263
3264module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
3265
3266MODULE_DESCRIPTION("LPC32XX udc driver");
3267MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3268MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3269MODULE_LICENSE("GPL");
3270MODULE_ALIAS("platform:lpc32xx_udc");
3271