1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2011 Marvell International Ltd. All rights reserved. 4 */ 5 6#ifndef __MV_U3D_H 7#define __MV_U3D_H 8 9#define MV_U3D_EP_CONTEXT_ALIGNMENT 32 10#define MV_U3D_TRB_ALIGNMENT 16 11#define MV_U3D_DMA_BOUNDARY 4096 12#define MV_U3D_EP0_MAX_PKT_SIZE 512 13 14/* ep0 transfer state */ 15#define MV_U3D_WAIT_FOR_SETUP 0 16#define MV_U3D_DATA_STATE_XMIT 1 17#define MV_U3D_DATA_STATE_NEED_ZLP 2 18#define MV_U3D_WAIT_FOR_OUT_STATUS 3 19#define MV_U3D_DATA_STATE_RECV 4 20#define MV_U3D_STATUS_STAGE 5 21 22#define MV_U3D_EP_MAX_LENGTH_TRANSFER 0x10000 23 24/* USB3 Interrupt Status */ 25#define MV_U3D_USBINT_SETUP 0x00000001 26#define MV_U3D_USBINT_RX_COMPLETE 0x00000002 27#define MV_U3D_USBINT_TX_COMPLETE 0x00000004 28#define MV_U3D_USBINT_UNDER_RUN 0x00000008 29#define MV_U3D_USBINT_RXDESC_ERR 0x00000010 30#define MV_U3D_USBINT_TXDESC_ERR 0x00000020 31#define MV_U3D_USBINT_RX_TRB_COMPLETE 0x00000040 32#define MV_U3D_USBINT_TX_TRB_COMPLETE 0x00000080 33#define MV_U3D_USBINT_VBUS_VALID 0x00010000 34#define MV_U3D_USBINT_STORAGE_CMD_FULL 0x00020000 35#define MV_U3D_USBINT_LINK_CHG 0x01000000 36 37/* USB3 Interrupt Enable */ 38#define MV_U3D_INTR_ENABLE_SETUP 0x00000001 39#define MV_U3D_INTR_ENABLE_RX_COMPLETE 0x00000002 40#define MV_U3D_INTR_ENABLE_TX_COMPLETE 0x00000004 41#define MV_U3D_INTR_ENABLE_UNDER_RUN 0x00000008 42#define MV_U3D_INTR_ENABLE_RXDESC_ERR 0x00000010 43#define MV_U3D_INTR_ENABLE_TXDESC_ERR 0x00000020 44#define MV_U3D_INTR_ENABLE_RX_TRB_COMPLETE 0x00000040 45#define MV_U3D_INTR_ENABLE_TX_TRB_COMPLETE 0x00000080 46#define MV_U3D_INTR_ENABLE_RX_BUFFER_ERR 0x00000100 47#define MV_U3D_INTR_ENABLE_VBUS_VALID 0x00010000 48#define MV_U3D_INTR_ENABLE_STORAGE_CMD_FULL 0x00020000 49#define MV_U3D_INTR_ENABLE_LINK_CHG 0x01000000 50#define MV_U3D_INTR_ENABLE_PRIME_STATUS 0x02000000 51 52/* USB3 Link Change */ 53#define MV_U3D_LINK_CHANGE_LINK_UP 0x00000001 54#define MV_U3D_LINK_CHANGE_SUSPEND 0x00000002 55#define MV_U3D_LINK_CHANGE_RESUME 0x00000004 56#define MV_U3D_LINK_CHANGE_WRESET 0x00000008 57#define MV_U3D_LINK_CHANGE_HRESET 0x00000010 58#define MV_U3D_LINK_CHANGE_VBUS_INVALID 0x00000020 59#define MV_U3D_LINK_CHANGE_INACT 0x00000040 60#define MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0 0x00000080 61#define MV_U3D_LINK_CHANGE_U1 0x00000100 62#define MV_U3D_LINK_CHANGE_U2 0x00000200 63#define MV_U3D_LINK_CHANGE_U3 0x00000400 64 65/* bridge setting */ 66#define MV_U3D_BRIDGE_SETTING_VBUS_VALID (1 << 16) 67 68/* Command Register Bit Masks */ 69#define MV_U3D_CMD_RUN_STOP 0x00000001 70#define MV_U3D_CMD_CTRL_RESET 0x00000002 71 72/* ep control register */ 73#define MV_U3D_EPXCR_EP_TYPE_CONTROL 0 74#define MV_U3D_EPXCR_EP_TYPE_ISOC 1 75#define MV_U3D_EPXCR_EP_TYPE_BULK 2 76#define MV_U3D_EPXCR_EP_TYPE_INT 3 77#define MV_U3D_EPXCR_EP_ENABLE_SHIFT 4 78#define MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT 12 79#define MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT 16 80#define MV_U3D_USB_BULK_BURST_OUT 6 81#define MV_U3D_USB_BULK_BURST_IN 14 82 83#define MV_U3D_EPXCR_EP_FLUSH (1 << 7) 84#define MV_U3D_EPXCR_EP_HALT (1 << 1) 85#define MV_U3D_EPXCR_EP_INIT (1) 86 87/* TX/RX Status Register */ 88#define MV_U3D_XFERSTATUS_COMPLETE_SHIFT 24 89#define MV_U3D_COMPLETE_INVALID 0 90#define MV_U3D_COMPLETE_SUCCESS 1 91#define MV_U3D_COMPLETE_BUFF_ERR 2 92#define MV_U3D_COMPLETE_SHORT_PACKET 3 93#define MV_U3D_COMPLETE_TRB_ERR 5 94#define MV_U3D_XFERSTATUS_TRB_LENGTH_MASK (0xFFFFFF) 95 96#define MV_U3D_USB_LINK_BYPASS_VBUS 0x8 97 98#define MV_U3D_LTSSM_PHY_INIT_DONE 0x80000000 99#define MV_U3D_LTSSM_NEVER_GO_COMPLIANCE 0x40000000 100 101#define MV_U3D_USB3_OP_REGS_OFFSET 0x100 102#define MV_U3D_USB3_PHY_OFFSET 0xB800 103 104#define DCS_ENABLE 0x1 105 106/* timeout */ 107#define MV_U3D_RESET_TIMEOUT 10000 108#define MV_U3D_FLUSH_TIMEOUT 100000 109#define MV_U3D_OWN_TIMEOUT 10000 110#define LOOPS_USEC_SHIFT 4 111#define LOOPS_USEC (1 << LOOPS_USEC_SHIFT) 112#define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT) 113 114/* ep direction */ 115#define MV_U3D_EP_DIR_IN 1 116#define MV_U3D_EP_DIR_OUT 0 117#define mv_u3d_ep_dir(ep) (((ep)->ep_num == 0) ? \ 118 ((ep)->u3d->ep0_dir) : ((ep)->direction)) 119 120/* usb capability registers */ 121struct mv_u3d_cap_regs { 122 u32 rsvd[5]; 123 u32 dboff; /* doorbell register offset */ 124 u32 rtsoff; /* runtime register offset */ 125 u32 vuoff; /* vendor unique register offset */ 126}; 127 128/* operation registers */ 129struct mv_u3d_op_regs { 130 u32 usbcmd; /* Command register */ 131 u32 rsvd1[11]; 132 u32 dcbaapl; /* Device Context Base Address low register */ 133 u32 dcbaaph; /* Device Context Base Address high register */ 134 u32 rsvd2[243]; 135 u32 portsc; /* port status and control register*/ 136 u32 portlinkinfo; /* port link info register*/ 137 u32 rsvd3[9917]; 138 u32 doorbell; /* doorbell register */ 139}; 140 141/* control endpoint enable registers */ 142struct epxcr { 143 u32 epxoutcr0; /* ep out control 0 register */ 144 u32 epxoutcr1; /* ep out control 1 register */ 145 u32 epxincr0; /* ep in control 0 register */ 146 u32 epxincr1; /* ep in control 1 register */ 147}; 148 149/* transfer status registers */ 150struct xferstatus { 151 u32 curdeqlo; /* current TRB pointer low */ 152 u32 curdeqhi; /* current TRB pointer high */ 153 u32 statuslo; /* transfer status low */ 154 u32 statushi; /* transfer status high */ 155}; 156 157/* vendor unique control registers */ 158struct mv_u3d_vuc_regs { 159 u32 ctrlepenable; /* control endpoint enable register */ 160 u32 setuplock; /* setup lock register */ 161 u32 endcomplete; /* endpoint transfer complete register */ 162 u32 intrcause; /* interrupt cause register */ 163 u32 intrenable; /* interrupt enable register */ 164 u32 trbcomplete; /* TRB complete register */ 165 u32 linkchange; /* link change register */ 166 u32 rsvd1[5]; 167 u32 trbunderrun; /* TRB underrun register */ 168 u32 rsvd2[43]; 169 u32 bridgesetting; /* bridge setting register */ 170 u32 rsvd3[7]; 171 struct xferstatus txst[16]; /* TX status register */ 172 struct xferstatus rxst[16]; /* RX status register */ 173 u32 ltssm; /* LTSSM control register */ 174 u32 pipe; /* PIPE control register */ 175 u32 linkcr0; /* link control 0 register */ 176 u32 linkcr1; /* link control 1 register */ 177 u32 rsvd6[60]; 178 u32 mib0; /* MIB0 counter register */ 179 u32 usblink; /* usb link control register */ 180 u32 ltssmstate; /* LTSSM state register */ 181 u32 linkerrorcause; /* link error cause register */ 182 u32 rsvd7[60]; 183 u32 devaddrtiebrkr; /* device address and tie breaker */ 184 u32 itpinfo0; /* ITP info 0 register */ 185 u32 itpinfo1; /* ITP info 1 register */ 186 u32 rsvd8[61]; 187 struct epxcr epcr[16]; /* ep control register */ 188 u32 rsvd9[64]; 189 u32 phyaddr; /* PHY address register */ 190 u32 phydata; /* PHY data register */ 191}; 192 193/* Endpoint context structure */ 194struct mv_u3d_ep_context { 195 u32 rsvd0; 196 u32 rsvd1; 197 u32 trb_addr_lo; /* TRB address low 32 bit */ 198 u32 trb_addr_hi; /* TRB address high 32 bit */ 199 u32 rsvd2; 200 u32 rsvd3; 201 struct usb_ctrlrequest setup_buffer; /* setup data buffer */ 202}; 203 204/* TRB control data structure */ 205struct mv_u3d_trb_ctrl { 206 u32 own:1; /* owner of TRB */ 207 u32 rsvd1:3; 208 u32 chain:1; /* associate this TRB with the 209 next TRB on the Ring */ 210 u32 ioc:1; /* interrupt on complete */ 211 u32 rsvd2:4; 212 u32 type:6; /* TRB type */ 213#define TYPE_NORMAL 1 214#define TYPE_DATA 3 215#define TYPE_LINK 6 216 u32 dir:1; /* Working at data stage of control endpoint 217 operation. 0 is OUT and 1 is IN. */ 218 u32 rsvd3:15; 219}; 220 221/* TRB data structure 222 * For multiple TRB, all the TRBs' physical address should be continuous. 223 */ 224struct mv_u3d_trb_hw { 225 u32 buf_addr_lo; /* data buffer address low 32 bit */ 226 u32 buf_addr_hi; /* data buffer address high 32 bit */ 227 u32 trb_len; /* transfer length */ 228 struct mv_u3d_trb_ctrl ctrl; /* TRB control data */ 229}; 230 231/* TRB structure */ 232struct mv_u3d_trb { 233 struct mv_u3d_trb_hw *trb_hw; /* point to the trb_hw structure */ 234 dma_addr_t trb_dma; /* dma address for this trb_hw */ 235 struct list_head trb_list; /* trb list */ 236}; 237 238/* device data structure */ 239struct mv_u3d { 240 struct usb_gadget gadget; 241 struct usb_gadget_driver *driver; 242 spinlock_t lock; /* device lock */ 243 struct completion *done; 244 struct device *dev; 245 int irq; 246 247 /* usb controller registers */ 248 struct mv_u3d_cap_regs __iomem *cap_regs; 249 struct mv_u3d_op_regs __iomem *op_regs; 250 struct mv_u3d_vuc_regs __iomem *vuc_regs; 251 void __iomem *phy_regs; 252 253 unsigned int max_eps; 254 struct mv_u3d_ep_context *ep_context; 255 size_t ep_context_size; 256 dma_addr_t ep_context_dma; 257 258 struct dma_pool *trb_pool; /* for TRB data structure */ 259 struct mv_u3d_ep *eps; 260 261 struct mv_u3d_req *status_req; /* ep0 status request */ 262 struct usb_ctrlrequest local_setup_buff; /* store setup data*/ 263 264 unsigned int resume_state; /* USB state to resume */ 265 unsigned int usb_state; /* USB current state */ 266 unsigned int ep0_state; /* Endpoint zero state */ 267 unsigned int ep0_dir; 268 269 unsigned int dev_addr; /* device address */ 270 271 unsigned int errors; 272 273 unsigned softconnect:1; 274 unsigned vbus_active:1; /* vbus is active or not */ 275 unsigned remote_wakeup:1; /* support remote wakeup */ 276 unsigned clock_gating:1; /* clock gating or not */ 277 unsigned active:1; /* udc is active or not */ 278 unsigned vbus_valid_detect:1; /* udc vbus detection */ 279 280 struct mv_usb_addon_irq *vbus; 281 unsigned int power; 282 283 struct clk *clk; 284}; 285 286/* endpoint data structure */ 287struct mv_u3d_ep { 288 struct usb_ep ep; 289 struct mv_u3d *u3d; 290 struct list_head queue; /* ep request queued hardware */ 291 struct list_head req_list; /* list of ep request */ 292 struct mv_u3d_ep_context *ep_context; /* ep context */ 293 u32 direction; 294 char name[14]; 295 u32 processing; /* there is ep request 296 queued on haredware */ 297 spinlock_t req_lock; /* ep lock */ 298 unsigned wedge:1; 299 unsigned enabled:1; 300 unsigned ep_type:2; 301 unsigned ep_num:8; 302}; 303 304/* request data structure */ 305struct mv_u3d_req { 306 struct usb_request req; 307 struct mv_u3d_ep *ep; 308 struct list_head queue; /* ep requst queued on hardware */ 309 struct list_head list; /* ep request list */ 310 struct list_head trb_list; /* trb list of a request */ 311 312 struct mv_u3d_trb *trb_head; /* point to first trb of a request */ 313 unsigned trb_count; /* TRB number in the chain */ 314 unsigned chain; /* TRB chain or not */ 315}; 316 317#endif 318