1
2
3
4
5
6#ifndef __LINUX_EHCI_HCD_H
7#define __LINUX_EHCI_HCD_H
8
9
10
11
12
13
14
15
16
17
18
19#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
20typedef __u32 __bitwise __hc32;
21typedef __u16 __bitwise __hc16;
22#else
23#define __hc32 __le32
24#define __hc16 __le16
25#endif
26
27
28#ifdef CONFIG_DYNAMIC_DEBUG
29#define EHCI_STATS
30#endif
31
32struct ehci_stats {
33
34 unsigned long normal;
35 unsigned long error;
36 unsigned long iaa;
37 unsigned long lost_iaa;
38
39
40 unsigned long complete;
41 unsigned long unlink;
42};
43
44
45
46
47
48struct ehci_per_sched {
49 struct usb_device *udev;
50 struct usb_host_endpoint *ep;
51 struct list_head ps_list;
52 u16 tt_usecs;
53 u16 cs_mask;
54 u16 period;
55 u16 phase;
56 u8 bw_phase;
57
58 u8 phase_uf;
59 u8 usecs, c_usecs;
60 u8 bw_uperiod;
61
62 u8 bw_period;
63};
64#define NO_FRAME 29999
65
66
67
68
69
70
71
72
73
74
75
76#define EHCI_MAX_ROOT_PORTS 15
77
78
79
80
81
82enum ehci_rh_state {
83 EHCI_RH_HALTED,
84 EHCI_RH_SUSPENDED,
85 EHCI_RH_RUNNING,
86 EHCI_RH_STOPPING
87};
88
89
90
91
92
93
94enum ehci_hrtimer_event {
95 EHCI_HRTIMER_POLL_ASS,
96 EHCI_HRTIMER_POLL_PSS,
97 EHCI_HRTIMER_POLL_DEAD,
98 EHCI_HRTIMER_UNLINK_INTR,
99 EHCI_HRTIMER_FREE_ITDS,
100 EHCI_HRTIMER_ACTIVE_UNLINK,
101 EHCI_HRTIMER_START_UNLINK_INTR,
102 EHCI_HRTIMER_ASYNC_UNLINKS,
103 EHCI_HRTIMER_IAA_WATCHDOG,
104 EHCI_HRTIMER_DISABLE_PERIODIC,
105 EHCI_HRTIMER_DISABLE_ASYNC,
106 EHCI_HRTIMER_IO_WATCHDOG,
107 EHCI_HRTIMER_NUM_EVENTS
108};
109#define EHCI_HRTIMER_NO_EVENT 99
110
111struct ehci_hcd {
112
113 enum ehci_hrtimer_event next_hrtimer_event;
114 unsigned enabled_hrtimer_events;
115 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
116 struct hrtimer hrtimer;
117
118 int PSS_poll_count;
119 int ASS_poll_count;
120 int died_poll_count;
121
122
123 struct ehci_caps __iomem *caps;
124 struct ehci_regs __iomem *regs;
125 struct ehci_dbg_port __iomem *debug;
126
127 __u32 hcs_params;
128 spinlock_t lock;
129 enum ehci_rh_state rh_state;
130
131
132 bool scanning:1;
133 bool need_rescan:1;
134 bool intr_unlinking:1;
135 bool iaa_in_progress:1;
136 bool async_unlinking:1;
137 bool shutdown:1;
138 struct ehci_qh *qh_scan_next;
139
140
141 struct ehci_qh *async;
142 struct ehci_qh *dummy;
143 struct list_head async_unlink;
144 struct list_head async_idle;
145 unsigned async_unlink_cycle;
146 unsigned async_count;
147 __hc32 old_current;
148 __hc32 old_token;
149
150
151#define DEFAULT_I_TDPS 1024
152 unsigned periodic_size;
153 __hc32 *periodic;
154 dma_addr_t periodic_dma;
155 struct list_head intr_qh_list;
156 unsigned i_thresh;
157
158 union ehci_shadow *pshadow;
159 struct list_head intr_unlink_wait;
160 struct list_head intr_unlink;
161 unsigned intr_unlink_wait_cycle;
162 unsigned intr_unlink_cycle;
163 unsigned now_frame;
164 unsigned last_iso_frame;
165 unsigned intr_count;
166 unsigned isoc_count;
167 unsigned periodic_count;
168 unsigned uframe_periodic_max;
169
170
171
172 struct list_head cached_itd_list;
173 struct ehci_itd *last_itd_to_free;
174 struct list_head cached_sitd_list;
175 struct ehci_sitd *last_sitd_to_free;
176
177
178 unsigned long reset_done[EHCI_MAX_ROOT_PORTS];
179
180
181 unsigned long bus_suspended;
182
183 unsigned long companion_ports;
184
185 unsigned long owned_ports;
186
187 unsigned long port_c_suspend;
188
189 unsigned long suspended_ports;
190
191 unsigned long resuming_ports;
192
193
194
195 struct dma_pool *qh_pool;
196 struct dma_pool *qtd_pool;
197 struct dma_pool *itd_pool;
198 struct dma_pool *sitd_pool;
199
200 unsigned random_frame;
201 unsigned long next_statechange;
202 ktime_t last_periodic_enable;
203 u32 command;
204
205
206 unsigned no_selective_suspend:1;
207 unsigned has_fsl_port_bug:1;
208 unsigned has_fsl_hs_errata:1;
209 unsigned has_fsl_susp_errata:1;
210 unsigned big_endian_mmio:1;
211 unsigned big_endian_desc:1;
212 unsigned big_endian_capbase:1;
213 unsigned has_amcc_usb23:1;
214 unsigned need_io_watchdog:1;
215 unsigned amd_pll_fix:1;
216 unsigned use_dummy_qh:1;
217 unsigned has_synopsys_hc_bug:1;
218 unsigned frame_index_bug:1;
219 unsigned need_oc_pp_cycle:1;
220 unsigned imx28_write_fix:1;
221 unsigned spurious_oc:1;
222
223
224 #define OHCI_CTRL_HCFS (3 << 6)
225 #define OHCI_USB_OPER (2 << 6)
226 #define OHCI_USB_SUSPEND (3 << 6)
227
228 #define OHCI_HCCTRL_OFFSET 0x4
229 #define OHCI_HCCTRL_LEN 0x4
230 __hc32 *ohci_hcctrl_reg;
231 unsigned has_hostpc:1;
232 unsigned has_tdi_phy_lpm:1;
233 unsigned has_ppcd:1;
234 u8 sbrn;
235
236
237#ifdef EHCI_STATS
238 struct ehci_stats stats;
239# define INCR(x) ((x)++)
240#else
241# define INCR(x) do {} while (0)
242#endif
243
244
245#ifdef CONFIG_DYNAMIC_DEBUG
246 struct dentry *debug_dir;
247#endif
248
249
250#define EHCI_BANDWIDTH_SIZE 64
251#define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3)
252 u8 bandwidth[EHCI_BANDWIDTH_SIZE];
253
254 u8 tt_budget[EHCI_BANDWIDTH_SIZE];
255
256 struct list_head tt_list;
257
258
259 unsigned long priv[] __aligned(sizeof(s64));
260};
261
262
263static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd)
264{
265 return (struct ehci_hcd *) (hcd->hcd_priv);
266}
267static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)
268{
269 return container_of((void *) ehci, struct usb_hcd, hcd_priv);
270}
271
272
273
274#include <linux/usb/ehci_def.h>
275
276
277
278#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
279
280
281
282
283
284
285
286
287
288struct ehci_qtd {
289
290 __hc32 hw_next;
291 __hc32 hw_alt_next;
292 __hc32 hw_token;
293#define QTD_TOGGLE (1 << 31)
294#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
295#define QTD_IOC (1 << 15)
296#define QTD_CERR(tok) (((tok)>>10) & 0x3)
297#define QTD_PID(tok) (((tok)>>8) & 0x3)
298#define QTD_STS_ACTIVE (1 << 7)
299#define QTD_STS_HALT (1 << 6)
300#define QTD_STS_DBE (1 << 5)
301#define QTD_STS_BABBLE (1 << 4)
302#define QTD_STS_XACT (1 << 3)
303#define QTD_STS_MMF (1 << 2)
304#define QTD_STS_STS (1 << 1)
305#define QTD_STS_PING (1 << 0)
306
307#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
308#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
309#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
310
311 __hc32 hw_buf[5];
312 __hc32 hw_buf_hi[5];
313
314
315 dma_addr_t qtd_dma;
316 struct list_head qtd_list;
317 struct urb *urb;
318 size_t length;
319} __aligned(32);
320
321
322#define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f)
323
324#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
325
326
327
328
329#define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
330
331
332
333
334
335
336
337
338
339#define Q_TYPE_ITD (0 << 1)
340#define Q_TYPE_QH (1 << 1)
341#define Q_TYPE_SITD (2 << 1)
342#define Q_TYPE_FSTN (3 << 1)
343
344
345#define QH_NEXT(ehci, dma) \
346 (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
347
348
349#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1)
350
351
352
353
354
355
356
357
358
359union ehci_shadow {
360 struct ehci_qh *qh;
361 struct ehci_itd *itd;
362 struct ehci_sitd *sitd;
363 struct ehci_fstn *fstn;
364 __hc32 *hw_next;
365 void *ptr;
366};
367
368
369
370
371
372
373
374
375
376
377
378
379struct ehci_qh_hw {
380 __hc32 hw_next;
381 __hc32 hw_info1;
382#define QH_CONTROL_EP (1 << 27)
383#define QH_HEAD (1 << 15)
384#define QH_TOGGLE_CTL (1 << 14)
385#define QH_HIGH_SPEED (2 << 12)
386#define QH_LOW_SPEED (1 << 12)
387#define QH_FULL_SPEED (0 << 12)
388#define QH_INACTIVATE (1 << 7)
389 __hc32 hw_info2;
390#define QH_SMASK 0x000000ff
391#define QH_CMASK 0x0000ff00
392#define QH_HUBADDR 0x007f0000
393#define QH_HUBPORT 0x3f800000
394#define QH_MULT 0xc0000000
395 __hc32 hw_current;
396
397
398 __hc32 hw_qtd_next;
399 __hc32 hw_alt_next;
400 __hc32 hw_token;
401 __hc32 hw_buf[5];
402 __hc32 hw_buf_hi[5];
403} __aligned(32);
404
405struct ehci_qh {
406 struct ehci_qh_hw *hw;
407
408 dma_addr_t qh_dma;
409 union ehci_shadow qh_next;
410 struct list_head qtd_list;
411 struct list_head intr_node;
412 struct ehci_qtd *dummy;
413 struct list_head unlink_node;
414 struct ehci_per_sched ps;
415
416 unsigned unlink_cycle;
417
418 u8 qh_state;
419#define QH_STATE_LINKED 1
420#define QH_STATE_UNLINK 2
421#define QH_STATE_IDLE 3
422#define QH_STATE_UNLINK_WAIT 4
423#define QH_STATE_COMPLETING 5
424
425 u8 xacterrs;
426#define QH_XACTERR_MAX 32
427
428 u8 unlink_reason;
429#define QH_UNLINK_HALTED 0x01
430#define QH_UNLINK_SHORT_READ 0x02
431#define QH_UNLINK_DUMMY_OVERLAY 0x04
432#define QH_UNLINK_SHUTDOWN 0x08
433#define QH_UNLINK_QUEUE_EMPTY 0x10
434#define QH_UNLINK_REQUESTED 0x20
435
436 u8 gap_uf;
437
438 unsigned is_out:1;
439 unsigned clearing_tt:1;
440 unsigned dequeue_during_giveback:1;
441 unsigned should_be_inactive:1;
442};
443
444
445
446
447struct ehci_iso_packet {
448
449 u64 bufp;
450 __hc32 transaction;
451 u8 cross;
452
453 u32 buf1;
454};
455
456
457
458
459
460struct ehci_iso_sched {
461 struct list_head td_list;
462 unsigned span;
463 unsigned first_packet;
464 struct ehci_iso_packet packet[];
465};
466
467
468
469
470
471struct ehci_iso_stream {
472
473 struct ehci_qh_hw *hw;
474
475 u8 bEndpointAddress;
476 u8 highspeed;
477 struct list_head td_list;
478 struct list_head free_list;
479
480
481 struct ehci_per_sched ps;
482 unsigned next_uframe;
483 __hc32 splits;
484
485
486
487
488 u16 uperiod;
489 u16 maxp;
490 unsigned bandwidth;
491
492
493 __hc32 buf0;
494 __hc32 buf1;
495 __hc32 buf2;
496
497
498 __hc32 address;
499};
500
501
502
503
504
505
506
507
508
509struct ehci_itd {
510
511 __hc32 hw_next;
512 __hc32 hw_transaction[8];
513#define EHCI_ISOC_ACTIVE (1<<31)
514#define EHCI_ISOC_BUF_ERR (1<<30)
515#define EHCI_ISOC_BABBLE (1<<29)
516#define EHCI_ISOC_XACTERR (1<<28)
517#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
518#define EHCI_ITD_IOC (1 << 15)
519
520#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
521
522 __hc32 hw_bufp[7];
523 __hc32 hw_bufp_hi[7];
524
525
526 dma_addr_t itd_dma;
527 union ehci_shadow itd_next;
528
529 struct urb *urb;
530 struct ehci_iso_stream *stream;
531 struct list_head itd_list;
532
533
534 unsigned frame;
535 unsigned pg;
536 unsigned index[8];
537} __aligned(32);
538
539
540
541
542
543
544
545
546
547struct ehci_sitd {
548
549 __hc32 hw_next;
550
551 __hc32 hw_fullspeed_ep;
552 __hc32 hw_uframe;
553 __hc32 hw_results;
554#define SITD_IOC (1 << 31)
555#define SITD_PAGE (1 << 30)
556#define SITD_LENGTH(x) (((x) >> 16) & 0x3ff)
557#define SITD_STS_ACTIVE (1 << 7)
558#define SITD_STS_ERR (1 << 6)
559#define SITD_STS_DBE (1 << 5)
560#define SITD_STS_BABBLE (1 << 4)
561#define SITD_STS_XACT (1 << 3)
562#define SITD_STS_MMF (1 << 2)
563#define SITD_STS_STS (1 << 1)
564
565#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
566
567 __hc32 hw_buf[2];
568 __hc32 hw_backpointer;
569 __hc32 hw_buf_hi[2];
570
571
572 dma_addr_t sitd_dma;
573 union ehci_shadow sitd_next;
574
575 struct urb *urb;
576 struct ehci_iso_stream *stream;
577 struct list_head sitd_list;
578 unsigned frame;
579 unsigned index;
580} __aligned(32);
581
582
583
584
585
586
587
588
589
590
591
592
593struct ehci_fstn {
594 __hc32 hw_next;
595 __hc32 hw_prev;
596
597
598 dma_addr_t fstn_dma;
599 union ehci_shadow fstn_next;
600} __aligned(32);
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622struct ehci_tt {
623 u16 bandwidth[EHCI_BANDWIDTH_FRAMES];
624
625 struct list_head tt_list;
626 struct list_head ps_list;
627 struct usb_tt *usb_tt;
628 int tt_port;
629};
630
631
632
633
634
635#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
636 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
637
638#define ehci_prepare_ports_for_controller_resume(ehci) \
639 ehci_adjust_port_wakeup_flags(ehci, false, false)
640
641
642
643#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
644
645
646
647
648
649
650
651
652#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
653
654
655static inline unsigned int
656ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
657{
658 if (ehci_is_TDI(ehci)) {
659 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
660 case 0:
661 return 0;
662 case 1:
663 return USB_PORT_STAT_LOW_SPEED;
664 case 2:
665 default:
666 return USB_PORT_STAT_HIGH_SPEED;
667 }
668 }
669 return USB_PORT_STAT_HIGH_SPEED;
670}
671
672#else
673
674#define ehci_is_TDI(e) (0)
675
676#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
677#endif
678
679
680
681#ifdef CONFIG_PPC_83xx
682
683
684
685#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
686#else
687#define ehci_has_fsl_portno_bug(e) (0)
688#endif
689
690#define PORTSC_FSL_PFSC 24
691
692#if defined(CONFIG_PPC_85xx)
693
694
695
696#define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
697#else
698#define ehci_has_fsl_hs_errata(e) (0)
699#endif
700
701
702
703
704
705
706#define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
723#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
724#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
725#else
726#define ehci_big_endian_mmio(e) 0
727#define ehci_big_endian_capbase(e) 0
728#endif
729
730
731
732
733
734#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
735#define readl_be(addr) __raw_readl((__force unsigned *)addr)
736#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
737#endif
738
739static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
740 __u32 __iomem *regs)
741{
742#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
743 return ehci_big_endian_mmio(ehci) ?
744 readl_be(regs) :
745 readl(regs);
746#else
747 return readl(regs);
748#endif
749}
750
751#ifdef CONFIG_SOC_IMX28
752static inline void imx28_ehci_writel(const unsigned int val,
753 volatile __u32 __iomem *addr)
754{
755 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
756}
757#else
758static inline void imx28_ehci_writel(const unsigned int val,
759 volatile __u32 __iomem *addr)
760{
761}
762#endif
763static inline void ehci_writel(const struct ehci_hcd *ehci,
764 const unsigned int val, __u32 __iomem *regs)
765{
766#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
767 ehci_big_endian_mmio(ehci) ?
768 writel_be(val, regs) :
769 writel(val, regs);
770#else
771 if (ehci->imx28_write_fix)
772 imx28_ehci_writel(val, regs);
773 else
774 writel(val, regs);
775#endif
776}
777
778
779
780
781
782
783#ifdef CONFIG_44x
784static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
785{
786 u32 hc_control;
787
788 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
789 if (operational)
790 hc_control |= OHCI_USB_OPER;
791 else
792 hc_control |= OHCI_USB_SUSPEND;
793
794 writel_be(hc_control, ehci->ohci_hcctrl_reg);
795 (void) readl_be(ehci->ohci_hcctrl_reg);
796}
797#else
798static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
799{ }
800#endif
801
802
803
804
805
806
807
808
809
810
811#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
812#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
813
814
815static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
816{
817 return ehci_big_endian_desc(ehci)
818 ? (__force __hc32)cpu_to_be32(x)
819 : (__force __hc32)cpu_to_le32(x);
820}
821
822
823static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
824{
825 return ehci_big_endian_desc(ehci)
826 ? be32_to_cpu((__force __be32)x)
827 : le32_to_cpu((__force __le32)x);
828}
829
830static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
831{
832 return ehci_big_endian_desc(ehci)
833 ? be32_to_cpup((__force __be32 *)x)
834 : le32_to_cpup((__force __le32 *)x);
835}
836
837#else
838
839
840static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)
841{
842 return cpu_to_le32(x);
843}
844
845
846static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)
847{
848 return le32_to_cpu(x);
849}
850
851static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)
852{
853 return le32_to_cpup(x);
854}
855
856#endif
857
858
859
860#define ehci_dbg(ehci, fmt, args...) \
861 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
862#define ehci_err(ehci, fmt, args...) \
863 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
864#define ehci_info(ehci, fmt, args...) \
865 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
866#define ehci_warn(ehci, fmt, args...) \
867 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
868
869
870
871
872
873struct ehci_driver_overrides {
874 size_t extra_priv_size;
875 int (*reset)(struct usb_hcd *hcd);
876 int (*port_power)(struct usb_hcd *hcd,
877 int portnum, bool enable);
878};
879
880extern void ehci_init_driver(struct hc_driver *drv,
881 const struct ehci_driver_overrides *over);
882extern int ehci_setup(struct usb_hcd *hcd);
883extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
884 u32 mask, u32 done, int usec);
885extern int ehci_reset(struct ehci_hcd *ehci);
886
887extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
888extern int ehci_resume(struct usb_hcd *hcd, bool force_reset);
889extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
890 bool suspending, bool do_wakeup);
891
892extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
893 u16 wIndex, char *buf, u16 wLength);
894
895#endif
896