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12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25
26#define XHCI_MSG_MAX 500
27
28
29#define XHCI_SBRN_OFFSET (0x60)
30
31
32#define MAX_HC_SLOTS 256
33
34#define MAX_HC_PORTS 127
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52
53struct xhci_cap_regs {
54 __le32 hc_capbase;
55 __le32 hcs_params1;
56 __le32 hcs_params2;
57 __le32 hcs_params3;
58 __le32 hcc_params;
59 __le32 db_off;
60 __le32 run_regs_off;
61 __le32 hcc_params2;
62
63};
64
65
66
67#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
68
69#define HC_VERSION(p) (((p) >> 16) & 0xffff)
70
71
72
73#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
74#define HCS_SLOTS_MASK 0xff
75
76#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
77
78#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
79
80
81
82
83#define HCS_IST(p) (((p) >> 0) & 0xf)
84
85#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
86
87
88
89#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
90
91
92
93#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
94
95#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
96
97
98
99#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
100
101#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
102
103
104
105#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
106
107#define HCC_PPC(p) ((p) & (1 << 3))
108
109#define HCS_INDICATOR(p) ((p) & (1 << 4))
110
111#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
112
113#define HCC_LTC(p) ((p) & (1 << 6))
114
115#define HCC_NSS(p) ((p) & (1 << 7))
116
117#define HCC_SPC(p) ((p) & (1 << 9))
118
119#define HCC_CFC(p) ((p) & (1 << 11))
120
121#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122
123#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
126
127
128#define DBOFF_MASK (~0x3)
129
130
131#define RTSOFF_MASK (~0x1f)
132
133
134
135#define HCC2_U3C(p) ((p) & (1 << 0))
136
137#define HCC2_CMC(p) ((p) & (1 << 1))
138
139#define HCC2_FSC(p) ((p) & (1 << 2))
140
141#define HCC2_CTC(p) ((p) & (1 << 3))
142
143#define HCC2_LEC(p) ((p) & (1 << 4))
144
145#define HCC2_CIC(p) ((p) & (1 << 5))
146
147#define HCC2_ETC(p) ((p) & (1 << 6))
148
149
150#define NUM_PORT_REGS 4
151
152#define PORTSC 0
153#define PORTPMSC 1
154#define PORTLI 2
155#define PORTHLPMC 3
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179struct xhci_op_regs {
180 __le32 command;
181 __le32 status;
182 __le32 page_size;
183 __le32 reserved1;
184 __le32 reserved2;
185 __le32 dev_notification;
186 __le64 cmd_ring;
187
188 __le32 reserved3[4];
189 __le64 dcbaa_ptr;
190 __le32 config_reg;
191
192 __le32 reserved4[241];
193
194 __le32 port_status_base;
195 __le32 port_power_base;
196 __le32 port_link_base;
197 __le32 reserved5;
198
199 __le32 reserved6[NUM_PORT_REGS*254];
200};
201
202
203
204#define CMD_RUN XHCI_CMD_RUN
205
206
207
208
209#define CMD_RESET (1 << 1)
210
211#define CMD_EIE XHCI_CMD_EIE
212
213#define CMD_HSEIE XHCI_CMD_HSEIE
214
215
216#define CMD_LRESET (1 << 7)
217
218#define CMD_CSS (1 << 8)
219#define CMD_CRS (1 << 9)
220
221#define CMD_EWE XHCI_CMD_EWE
222
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226
227#define CMD_PM_INDEX (1 << 11)
228
229#define CMD_ETE (1 << 14)
230
231
232
233#define IMAN_IE (1 << 1)
234#define IMAN_IP (1 << 0)
235
236
237
238#define STS_HALT XHCI_STS_HALT
239
240#define STS_FATAL (1 << 2)
241
242#define STS_EINT (1 << 3)
243
244#define STS_PORT (1 << 4)
245
246
247#define STS_SAVE (1 << 8)
248
249#define STS_RESTORE (1 << 9)
250
251#define STS_SRE (1 << 10)
252
253#define STS_CNR XHCI_STS_CNR
254
255#define STS_HCE (1 << 12)
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262
263#define DEV_NOTE_MASK (0xffff)
264#define ENABLE_DEV_NOTE(x) (1 << (x))
265
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267
268#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
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272
273#define CMD_RING_PAUSE (1 << 1)
274
275#define CMD_RING_ABORT (1 << 2)
276
277#define CMD_RING_RUNNING (1 << 3)
278
279
280#define CMD_RING_RSVD_BITS (0x3f)
281
282
283
284#define MAX_DEVS(p) ((p) & 0xff)
285
286#define CONFIG_U3E (1 << 8)
287
288#define CONFIG_CIE (1 << 9)
289
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292
293#define PORT_CONNECT (1 << 0)
294
295#define PORT_PE (1 << 1)
296
297
298#define PORT_OC (1 << 3)
299
300#define PORT_RESET (1 << 4)
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304
305#define PORT_PLS_MASK (0xf << 5)
306#define XDEV_U0 (0x0 << 5)
307#define XDEV_U1 (0x1 << 5)
308#define XDEV_U2 (0x2 << 5)
309#define XDEV_U3 (0x3 << 5)
310#define XDEV_DISABLED (0x4 << 5)
311#define XDEV_RXDETECT (0x5 << 5)
312#define XDEV_INACTIVE (0x6 << 5)
313#define XDEV_POLLING (0x7 << 5)
314#define XDEV_RECOVERY (0x8 << 5)
315#define XDEV_HOT_RESET (0x9 << 5)
316#define XDEV_COMP_MODE (0xa << 5)
317#define XDEV_TEST_MODE (0xb << 5)
318#define XDEV_RESUME (0xf << 5)
319
320
321#define PORT_POWER (1 << 9)
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329
330#define DEV_SPEED_MASK (0xf << 10)
331#define XDEV_FS (0x1 << 10)
332#define XDEV_LS (0x2 << 10)
333#define XDEV_HS (0x3 << 10)
334#define XDEV_SS (0x4 << 10)
335#define XDEV_SSP (0x5 << 10)
336#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
337#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
338#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
339#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
340#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
341#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
342#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
343#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
344
345
346#define SLOT_SPEED_FS (XDEV_FS << 10)
347#define SLOT_SPEED_LS (XDEV_LS << 10)
348#define SLOT_SPEED_HS (XDEV_HS << 10)
349#define SLOT_SPEED_SS (XDEV_SS << 10)
350#define SLOT_SPEED_SSP (XDEV_SSP << 10)
351
352#define PORT_LED_OFF (0 << 14)
353#define PORT_LED_AMBER (1 << 14)
354#define PORT_LED_GREEN (2 << 14)
355#define PORT_LED_MASK (3 << 14)
356
357#define PORT_LINK_STROBE (1 << 16)
358
359#define PORT_CSC (1 << 17)
360
361#define PORT_PEC (1 << 18)
362
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367#define PORT_WRC (1 << 19)
368
369#define PORT_OCC (1 << 20)
370
371#define PORT_RC (1 << 21)
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385#define PORT_PLC (1 << 22)
386
387#define PORT_CEC (1 << 23)
388#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
389 PORT_RC | PORT_PLC | PORT_CEC)
390
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395
396#define PORT_CAS (1 << 24)
397
398#define PORT_WKCONN_E (1 << 25)
399
400#define PORT_WKDISC_E (1 << 26)
401
402#define PORT_WKOC_E (1 << 27)
403
404
405#define PORT_DEV_REMOVE (1 << 30)
406
407#define PORT_WR (1 << 31)
408
409
410#define DUPLICATE_ENTRY ((u8)(-1))
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415
416#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
417#define PORT_U1_TIMEOUT_MASK 0xff
418
419#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
420#define PORT_U2_TIMEOUT_MASK (0xff << 8)
421
422
423
424#define PORT_L1S_MASK 7
425#define PORT_L1S_SUCCESS 1
426#define PORT_RWE (1 << 3)
427#define PORT_HIRD(p) (((p) & 0xf) << 4)
428#define PORT_HIRD_MASK (0xf << 4)
429#define PORT_L1DS_MASK (0xff << 8)
430#define PORT_L1DS(p) (((p) & 0xff) << 8)
431#define PORT_HLE (1 << 16)
432#define PORT_TEST_MODE_SHIFT 28
433
434
435#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
436#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
437
438
439#define PORT_HIRDM(p)((p) & 3)
440#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
441#define PORT_BESLD(p)(((p) & 0xf) << 10)
442
443
444#define XHCI_L1_TIMEOUT 512
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455
456#define XHCI_DEFAULT_BESL 4
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464#define XHCI_PORT_POLLING_LFPS_TIME 36
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483struct xhci_intr_reg {
484 __le32 irq_pending;
485 __le32 irq_control;
486 __le32 erst_size;
487 __le32 rsvd;
488 __le64 erst_base;
489 __le64 erst_dequeue;
490};
491
492
493#define ER_IRQ_PENDING(p) ((p) & 0x1)
494
495
496#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
497#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
498#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
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505#define ER_IRQ_INTERVAL_MASK (0xffff)
506
507#define ER_IRQ_COUNTER_MASK (0xffff << 16)
508
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510
511#define ERST_SIZE_MASK (0xffff << 16)
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517#define ERST_DESI_MASK (0x7)
518
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521#define ERST_EHB (1 << 3)
522#define ERST_PTR_MASK (0xf)
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533struct xhci_run_regs {
534 __le32 microframe_index;
535 __le32 rsvd[7];
536 struct xhci_intr_reg ir_set[128];
537};
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548struct xhci_doorbell_array {
549 __le32 doorbell[256];
550};
551
552#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
553#define DB_VALUE_HOST 0x00000000
554
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562
563struct xhci_protocol_caps {
564 u32 revision;
565 u32 name_string;
566 u32 port_info;
567};
568
569#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
570#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
571#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
572#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
573#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
574
575#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
576#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
577#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
578#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
579#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
580#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
581
582#define PLT_MASK (0x03 << 6)
583#define PLT_SYM (0x00 << 6)
584#define PLT_ASYM_RX (0x02 << 6)
585#define PLT_ASYM_TX (0x03 << 6)
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597struct xhci_container_ctx {
598 unsigned type;
599#define XHCI_CTX_TYPE_DEVICE 0x1
600#define XHCI_CTX_TYPE_INPUT 0x2
601
602 int size;
603
604 u8 *bytes;
605 dma_addr_t dma;
606};
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619struct xhci_slot_ctx {
620 __le32 dev_info;
621 __le32 dev_info2;
622 __le32 tt_info;
623 __le32 dev_state;
624
625 __le32 reserved[4];
626};
627
628
629
630#define ROUTE_STRING_MASK (0xfffff)
631
632#define DEV_SPEED (0xf << 20)
633#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
634
635
636#define DEV_MTT (0x1 << 25)
637
638#define DEV_HUB (0x1 << 26)
639
640#define LAST_CTX_MASK (0x1f << 27)
641#define LAST_CTX(p) ((p) << 27)
642#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
643#define SLOT_FLAG (1 << 0)
644#define EP0_FLAG (1 << 1)
645
646
647
648#define MAX_EXIT (0xffff)
649
650#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
651#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
652
653#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
654#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
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661
662#define TT_SLOT (0xff)
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666
667#define TT_PORT (0xff << 8)
668#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
669#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
670
671
672
673#define DEV_ADDR_MASK (0xff)
674
675
676#define SLOT_STATE (0x1f << 27)
677#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
678
679#define SLOT_STATE_DISABLED 0
680#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
681#define SLOT_STATE_DEFAULT 1
682#define SLOT_STATE_ADDRESSED 2
683#define SLOT_STATE_CONFIGURED 3
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703struct xhci_ep_ctx {
704 __le32 ep_info;
705 __le32 ep_info2;
706 __le64 deq;
707 __le32 tx_info;
708
709 __le32 reserved[3];
710};
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721
722#define EP_STATE_MASK (0x7)
723#define EP_STATE_DISABLED 0
724#define EP_STATE_RUNNING 1
725#define EP_STATE_HALTED 2
726#define EP_STATE_STOPPED 3
727#define EP_STATE_ERROR 4
728#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
729
730
731#define EP_MULT(p) (((p) & 0x3) << 8)
732#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
733
734
735
736#define EP_INTERVAL(p) (((p) & 0xff) << 16)
737#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
738#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
739#define EP_MAXPSTREAMS_MASK (0x1f << 10)
740#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
741#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
742
743#define EP_HAS_LSA (1 << 15)
744
745#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
746
747
748
749
750
751
752#define FORCE_EVENT (0x1)
753#define ERROR_COUNT(p) (((p) & 0x3) << 1)
754#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
755#define EP_TYPE(p) ((p) << 3)
756#define ISOC_OUT_EP 1
757#define BULK_OUT_EP 2
758#define INT_OUT_EP 3
759#define CTRL_EP 4
760#define ISOC_IN_EP 5
761#define BULK_IN_EP 6
762#define INT_IN_EP 7
763
764
765#define MAX_BURST(p) (((p)&0xff) << 8)
766#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
767#define MAX_PACKET(p) (((p)&0xffff) << 16)
768#define MAX_PACKET_MASK (0xffff << 16)
769#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
770
771
772#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
773#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
774#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
775#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
776
777
778#define EP_CTX_CYCLE_MASK (1 << 0)
779#define SCTX_DEQ_MASK (~0xfL)
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787
788
789struct xhci_input_control_ctx {
790 __le32 drop_flags;
791 __le32 add_flags;
792 __le32 rsvd2[6];
793};
794
795#define EP_IS_ADDED(ctrl_ctx, i) \
796 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
797#define EP_IS_DROPPED(ctrl_ctx, i) \
798 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
799
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802
803
804struct xhci_command {
805
806 struct xhci_container_ctx *in_ctx;
807 u32 status;
808 int slot_id;
809
810
811
812 struct completion *completion;
813 union xhci_trb *command_trb;
814 struct list_head cmd_list;
815};
816
817
818#define DROP_EP(x) (0x1 << x)
819
820#define ADD_EP(x) (0x1 << x)
821
822struct xhci_stream_ctx {
823
824 __le64 stream_ring;
825
826 __le32 reserved[2];
827};
828
829
830#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
831
832#define SCT_SEC_TR 0
833
834#define SCT_PRI_TR 1
835
836#define SCT_SSA_8 2
837#define SCT_SSA_16 3
838#define SCT_SSA_32 4
839#define SCT_SSA_64 5
840#define SCT_SSA_128 6
841#define SCT_SSA_256 7
842
843
844struct xhci_stream_info {
845 struct xhci_ring **stream_rings;
846
847 unsigned int num_streams;
848
849
850
851 struct xhci_stream_ctx *stream_ctx_array;
852 unsigned int num_stream_ctxs;
853 dma_addr_t ctx_array_dma;
854
855 struct radix_tree_root trb_address_map;
856 struct xhci_command *free_streams_command;
857};
858
859#define SMALL_STREAM_ARRAY_SIZE 256
860#define MEDIUM_STREAM_ARRAY_SIZE 1024
861
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866
867
868struct xhci_bw_info {
869
870 unsigned int ep_interval;
871
872 unsigned int mult;
873 unsigned int num_packets;
874 unsigned int max_packet_size;
875 unsigned int max_esit_payload;
876 unsigned int type;
877};
878
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881
882
883
884#define FS_BLOCK 1
885#define HS_BLOCK 4
886#define SS_BLOCK 16
887#define DMI_BLOCK 32
888
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890
891
892
893
894#define DMI_OVERHEAD 8
895#define DMI_OVERHEAD_BURST 4
896#define SS_OVERHEAD 8
897#define SS_OVERHEAD_BURST 32
898#define HS_OVERHEAD 26
899#define FS_OVERHEAD 20
900#define LS_OVERHEAD 128
901
902
903
904
905
906#define TT_HS_OVERHEAD (31 + 94)
907#define TT_DMI_OVERHEAD (25 + 12)
908
909
910#define FS_BW_LIMIT 1285
911#define TT_BW_LIMIT 1320
912#define HS_BW_LIMIT 1607
913#define SS_BW_LIMIT_IN 3906
914#define DMI_BW_LIMIT_IN 3906
915#define SS_BW_LIMIT_OUT 3906
916#define DMI_BW_LIMIT_OUT 3906
917
918
919#define FS_BW_RESERVED 10
920#define HS_BW_RESERVED 20
921#define SS_BW_RESERVED 10
922
923struct xhci_virt_ep {
924 struct xhci_virt_device *vdev;
925 unsigned int ep_index;
926 struct xhci_ring *ring;
927
928 struct xhci_stream_info *stream_info;
929
930
931
932 struct xhci_ring *new_ring;
933 unsigned int ep_state;
934#define SET_DEQ_PENDING (1 << 0)
935#define EP_HALTED (1 << 1)
936#define EP_STOP_CMD_PENDING (1 << 2)
937
938#define EP_GETTING_STREAMS (1 << 3)
939#define EP_HAS_STREAMS (1 << 4)
940
941#define EP_GETTING_NO_STREAMS (1 << 5)
942#define EP_HARD_CLEAR_TOGGLE (1 << 6)
943#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
944
945#define EP_CLEARING_TT (1 << 8)
946
947 struct list_head cancelled_td_list;
948
949 struct timer_list stop_cmd_timer;
950 struct xhci_hcd *xhci;
951
952
953
954
955 struct xhci_segment *queued_deq_seg;
956 union xhci_trb *queued_deq_ptr;
957
958
959
960
961
962
963
964 bool skip;
965
966 struct xhci_bw_info bw_info;
967 struct list_head bw_endpoint_list;
968
969 int next_frame_id;
970
971 bool use_extended_tbc;
972};
973
974enum xhci_overhead_type {
975 LS_OVERHEAD_TYPE = 0,
976 FS_OVERHEAD_TYPE,
977 HS_OVERHEAD_TYPE,
978};
979
980struct xhci_interval_bw {
981 unsigned int num_packets;
982
983
984
985 struct list_head endpoints;
986
987 unsigned int overhead[3];
988};
989
990#define XHCI_MAX_INTERVAL 16
991
992struct xhci_interval_bw_table {
993 unsigned int interval0_esit_payload;
994 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
995
996 unsigned int bw_used;
997 unsigned int ss_bw_in;
998 unsigned int ss_bw_out;
999};
1000
1001#define EP_CTX_PER_DEV 31
1002
1003struct xhci_virt_device {
1004 int slot_id;
1005 struct usb_device *udev;
1006
1007
1008
1009
1010
1011
1012
1013
1014 struct xhci_container_ctx *out_ctx;
1015
1016 struct xhci_container_ctx *in_ctx;
1017 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1018 u8 fake_port;
1019 u8 real_port;
1020 struct xhci_interval_bw_table *bw_table;
1021 struct xhci_tt_bw_info *tt_info;
1022
1023
1024
1025
1026
1027
1028 unsigned long flags;
1029#define VDEV_PORT_ERROR BIT(0)
1030
1031
1032 u16 current_mel;
1033
1034 void *debugfs_private;
1035};
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045struct xhci_root_port_bw_info {
1046 struct list_head tts;
1047 unsigned int num_active_tts;
1048 struct xhci_interval_bw_table bw_table;
1049};
1050
1051struct xhci_tt_bw_info {
1052 struct list_head tt_list;
1053 int slot_id;
1054 int ttport;
1055 struct xhci_interval_bw_table bw_table;
1056 int active_eps;
1057};
1058
1059
1060
1061
1062
1063
1064struct xhci_device_context_array {
1065
1066 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1067
1068 dma_addr_t dma;
1069};
1070
1071
1072
1073
1074
1075
1076
1077struct xhci_transfer_event {
1078
1079 __le64 buffer;
1080 __le32 transfer_len;
1081
1082 __le32 flags;
1083};
1084
1085
1086
1087#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1088
1089
1090#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1091
1092
1093#define COMP_CODE_MASK (0xff << 24)
1094#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1095#define COMP_INVALID 0
1096#define COMP_SUCCESS 1
1097#define COMP_DATA_BUFFER_ERROR 2
1098#define COMP_BABBLE_DETECTED_ERROR 3
1099#define COMP_USB_TRANSACTION_ERROR 4
1100#define COMP_TRB_ERROR 5
1101#define COMP_STALL_ERROR 6
1102#define COMP_RESOURCE_ERROR 7
1103#define COMP_BANDWIDTH_ERROR 8
1104#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1105#define COMP_INVALID_STREAM_TYPE_ERROR 10
1106#define COMP_SLOT_NOT_ENABLED_ERROR 11
1107#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1108#define COMP_SHORT_PACKET 13
1109#define COMP_RING_UNDERRUN 14
1110#define COMP_RING_OVERRUN 15
1111#define COMP_VF_EVENT_RING_FULL_ERROR 16
1112#define COMP_PARAMETER_ERROR 17
1113#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1114#define COMP_CONTEXT_STATE_ERROR 19
1115#define COMP_NO_PING_RESPONSE_ERROR 20
1116#define COMP_EVENT_RING_FULL_ERROR 21
1117#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1118#define COMP_MISSED_SERVICE_ERROR 23
1119#define COMP_COMMAND_RING_STOPPED 24
1120#define COMP_COMMAND_ABORTED 25
1121#define COMP_STOPPED 26
1122#define COMP_STOPPED_LENGTH_INVALID 27
1123#define COMP_STOPPED_SHORT_PACKET 28
1124#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1125#define COMP_ISOCH_BUFFER_OVERRUN 31
1126#define COMP_EVENT_LOST_ERROR 32
1127#define COMP_UNDEFINED_ERROR 33
1128#define COMP_INVALID_STREAM_ID_ERROR 34
1129#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1130#define COMP_SPLIT_TRANSACTION_ERROR 36
1131
1132static inline const char *xhci_trb_comp_code_string(u8 status)
1133{
1134 switch (status) {
1135 case COMP_INVALID:
1136 return "Invalid";
1137 case COMP_SUCCESS:
1138 return "Success";
1139 case COMP_DATA_BUFFER_ERROR:
1140 return "Data Buffer Error";
1141 case COMP_BABBLE_DETECTED_ERROR:
1142 return "Babble Detected";
1143 case COMP_USB_TRANSACTION_ERROR:
1144 return "USB Transaction Error";
1145 case COMP_TRB_ERROR:
1146 return "TRB Error";
1147 case COMP_STALL_ERROR:
1148 return "Stall Error";
1149 case COMP_RESOURCE_ERROR:
1150 return "Resource Error";
1151 case COMP_BANDWIDTH_ERROR:
1152 return "Bandwidth Error";
1153 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1154 return "No Slots Available Error";
1155 case COMP_INVALID_STREAM_TYPE_ERROR:
1156 return "Invalid Stream Type Error";
1157 case COMP_SLOT_NOT_ENABLED_ERROR:
1158 return "Slot Not Enabled Error";
1159 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1160 return "Endpoint Not Enabled Error";
1161 case COMP_SHORT_PACKET:
1162 return "Short Packet";
1163 case COMP_RING_UNDERRUN:
1164 return "Ring Underrun";
1165 case COMP_RING_OVERRUN:
1166 return "Ring Overrun";
1167 case COMP_VF_EVENT_RING_FULL_ERROR:
1168 return "VF Event Ring Full Error";
1169 case COMP_PARAMETER_ERROR:
1170 return "Parameter Error";
1171 case COMP_BANDWIDTH_OVERRUN_ERROR:
1172 return "Bandwidth Overrun Error";
1173 case COMP_CONTEXT_STATE_ERROR:
1174 return "Context State Error";
1175 case COMP_NO_PING_RESPONSE_ERROR:
1176 return "No Ping Response Error";
1177 case COMP_EVENT_RING_FULL_ERROR:
1178 return "Event Ring Full Error";
1179 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1180 return "Incompatible Device Error";
1181 case COMP_MISSED_SERVICE_ERROR:
1182 return "Missed Service Error";
1183 case COMP_COMMAND_RING_STOPPED:
1184 return "Command Ring Stopped";
1185 case COMP_COMMAND_ABORTED:
1186 return "Command Aborted";
1187 case COMP_STOPPED:
1188 return "Stopped";
1189 case COMP_STOPPED_LENGTH_INVALID:
1190 return "Stopped - Length Invalid";
1191 case COMP_STOPPED_SHORT_PACKET:
1192 return "Stopped - Short Packet";
1193 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1194 return "Max Exit Latency Too Large Error";
1195 case COMP_ISOCH_BUFFER_OVERRUN:
1196 return "Isoch Buffer Overrun";
1197 case COMP_EVENT_LOST_ERROR:
1198 return "Event Lost Error";
1199 case COMP_UNDEFINED_ERROR:
1200 return "Undefined Error";
1201 case COMP_INVALID_STREAM_ID_ERROR:
1202 return "Invalid Stream ID Error";
1203 case COMP_SECONDARY_BANDWIDTH_ERROR:
1204 return "Secondary Bandwidth Error";
1205 case COMP_SPLIT_TRANSACTION_ERROR:
1206 return "Split Transaction Error";
1207 default:
1208 return "Unknown!!";
1209 }
1210}
1211
1212struct xhci_link_trb {
1213
1214 __le64 segment_ptr;
1215 __le32 intr_target;
1216 __le32 control;
1217};
1218
1219
1220#define LINK_TOGGLE (0x1<<1)
1221
1222
1223struct xhci_event_cmd {
1224
1225 __le64 cmd_trb;
1226 __le32 status;
1227 __le32 flags;
1228};
1229
1230
1231
1232
1233#define TRB_BSR (1<<9)
1234
1235
1236#define TRB_DC (1<<9)
1237
1238
1239#define TRB_TSP (1<<9)
1240
1241enum xhci_ep_reset_type {
1242 EP_HARD_RESET,
1243 EP_SOFT_RESET,
1244};
1245
1246
1247#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1248#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1249
1250
1251#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1252
1253
1254#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1255
1256
1257#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1258#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1259
1260enum xhci_setup_dev {
1261 SETUP_CONTEXT_ONLY,
1262 SETUP_CONTEXT_ADDRESS,
1263};
1264
1265
1266
1267#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1268#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1269
1270
1271#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1272#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1273
1274#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1275#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1276#define LAST_EP_INDEX 30
1277
1278
1279#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1280#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1281#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1282
1283
1284#define TRB_TC (1<<1)
1285
1286
1287
1288#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1289
1290#define EVENT_DATA (1 << 2)
1291
1292
1293
1294#define TRB_LEN(p) ((p) & 0x1ffff)
1295
1296#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1297#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1298
1299#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1300
1301#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1302#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1303
1304#define TRB_TBC(p) (((p) & 0x3) << 7)
1305#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1306
1307
1308#define TRB_CYCLE (1<<0)
1309
1310
1311
1312
1313#define TRB_ENT (1<<1)
1314
1315#define TRB_ISP (1<<2)
1316
1317#define TRB_NO_SNOOP (1<<3)
1318
1319#define TRB_CHAIN (1<<4)
1320
1321#define TRB_IOC (1<<5)
1322
1323#define TRB_IDT (1<<6)
1324
1325#define TRB_IDT_MAX_SIZE 8
1326
1327
1328#define TRB_BEI (1<<9)
1329
1330
1331#define TRB_DIR_IN (1<<16)
1332#define TRB_TX_TYPE(p) ((p) << 16)
1333#define TRB_DATA_OUT 2
1334#define TRB_DATA_IN 3
1335
1336
1337#define TRB_SIA (1<<31)
1338#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1339
1340
1341#define TRB_CACHE_SIZE_HS 8
1342#define TRB_CACHE_SIZE_SS 16
1343
1344struct xhci_generic_trb {
1345 __le32 field[4];
1346};
1347
1348union xhci_trb {
1349 struct xhci_link_trb link;
1350 struct xhci_transfer_event trans_event;
1351 struct xhci_event_cmd event_cmd;
1352 struct xhci_generic_trb generic;
1353};
1354
1355
1356#define TRB_TYPE_BITMASK (0xfc00)
1357#define TRB_TYPE(p) ((p) << 10)
1358#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1359
1360
1361#define TRB_NORMAL 1
1362
1363#define TRB_SETUP 2
1364
1365#define TRB_DATA 3
1366
1367#define TRB_STATUS 4
1368
1369#define TRB_ISOC 5
1370
1371#define TRB_LINK 6
1372#define TRB_EVENT_DATA 7
1373
1374#define TRB_TR_NOOP 8
1375
1376
1377#define TRB_ENABLE_SLOT 9
1378
1379#define TRB_DISABLE_SLOT 10
1380
1381#define TRB_ADDR_DEV 11
1382
1383#define TRB_CONFIG_EP 12
1384
1385#define TRB_EVAL_CONTEXT 13
1386
1387#define TRB_RESET_EP 14
1388
1389#define TRB_STOP_RING 15
1390
1391#define TRB_SET_DEQ 16
1392
1393#define TRB_RESET_DEV 17
1394
1395#define TRB_FORCE_EVENT 18
1396
1397#define TRB_NEG_BANDWIDTH 19
1398
1399#define TRB_SET_LT 20
1400
1401#define TRB_GET_BW 21
1402
1403#define TRB_FORCE_HEADER 22
1404
1405#define TRB_CMD_NOOP 23
1406
1407
1408
1409#define TRB_TRANSFER 32
1410
1411#define TRB_COMPLETION 33
1412
1413#define TRB_PORT_STATUS 34
1414
1415#define TRB_BANDWIDTH_EVENT 35
1416
1417#define TRB_DOORBELL 36
1418
1419#define TRB_HC_EVENT 37
1420
1421#define TRB_DEV_NOTE 38
1422
1423#define TRB_MFINDEX_WRAP 39
1424
1425#define TRB_VENDOR_DEFINED_LOW 48
1426
1427#define TRB_NEC_CMD_COMP 48
1428
1429#define TRB_NEC_GET_FW 49
1430
1431static inline const char *xhci_trb_type_string(u8 type)
1432{
1433 switch (type) {
1434 case TRB_NORMAL:
1435 return "Normal";
1436 case TRB_SETUP:
1437 return "Setup Stage";
1438 case TRB_DATA:
1439 return "Data Stage";
1440 case TRB_STATUS:
1441 return "Status Stage";
1442 case TRB_ISOC:
1443 return "Isoch";
1444 case TRB_LINK:
1445 return "Link";
1446 case TRB_EVENT_DATA:
1447 return "Event Data";
1448 case TRB_TR_NOOP:
1449 return "No-Op";
1450 case TRB_ENABLE_SLOT:
1451 return "Enable Slot Command";
1452 case TRB_DISABLE_SLOT:
1453 return "Disable Slot Command";
1454 case TRB_ADDR_DEV:
1455 return "Address Device Command";
1456 case TRB_CONFIG_EP:
1457 return "Configure Endpoint Command";
1458 case TRB_EVAL_CONTEXT:
1459 return "Evaluate Context Command";
1460 case TRB_RESET_EP:
1461 return "Reset Endpoint Command";
1462 case TRB_STOP_RING:
1463 return "Stop Ring Command";
1464 case TRB_SET_DEQ:
1465 return "Set TR Dequeue Pointer Command";
1466 case TRB_RESET_DEV:
1467 return "Reset Device Command";
1468 case TRB_FORCE_EVENT:
1469 return "Force Event Command";
1470 case TRB_NEG_BANDWIDTH:
1471 return "Negotiate Bandwidth Command";
1472 case TRB_SET_LT:
1473 return "Set Latency Tolerance Value Command";
1474 case TRB_GET_BW:
1475 return "Get Port Bandwidth Command";
1476 case TRB_FORCE_HEADER:
1477 return "Force Header Command";
1478 case TRB_CMD_NOOP:
1479 return "No-Op Command";
1480 case TRB_TRANSFER:
1481 return "Transfer Event";
1482 case TRB_COMPLETION:
1483 return "Command Completion Event";
1484 case TRB_PORT_STATUS:
1485 return "Port Status Change Event";
1486 case TRB_BANDWIDTH_EVENT:
1487 return "Bandwidth Request Event";
1488 case TRB_DOORBELL:
1489 return "Doorbell Event";
1490 case TRB_HC_EVENT:
1491 return "Host Controller Event";
1492 case TRB_DEV_NOTE:
1493 return "Device Notification Event";
1494 case TRB_MFINDEX_WRAP:
1495 return "MFINDEX Wrap Event";
1496 case TRB_NEC_CMD_COMP:
1497 return "NEC Command Completion Event";
1498 case TRB_NEC_GET_FW:
1499 return "NET Get Firmware Revision Command";
1500 default:
1501 return "UNKNOWN";
1502 }
1503}
1504
1505#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1506
1507#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1508 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1509#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1510 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1511
1512#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1513#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1514
1515
1516
1517
1518
1519
1520#define TRBS_PER_SEGMENT 256
1521
1522#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1523#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1524#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1525
1526#define TRB_MAX_BUFF_SHIFT 16
1527#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1528
1529#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1530 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1531#define MAX_SOFT_RETRY 3
1532
1533
1534
1535
1536#define AVOID_BEI_INTERVAL_MIN 8
1537#define AVOID_BEI_INTERVAL_MAX 32
1538
1539struct xhci_segment {
1540 union xhci_trb *trbs;
1541
1542 struct xhci_segment *next;
1543 dma_addr_t dma;
1544
1545 dma_addr_t bounce_dma;
1546 void *bounce_buf;
1547 unsigned int bounce_offs;
1548 unsigned int bounce_len;
1549};
1550
1551enum xhci_cancelled_td_status {
1552 TD_DIRTY = 0,
1553 TD_HALTED,
1554 TD_CLEARING_CACHE,
1555 TD_CLEARED,
1556};
1557
1558struct xhci_td {
1559 struct list_head td_list;
1560 struct list_head cancelled_td_list;
1561 int status;
1562 enum xhci_cancelled_td_status cancel_status;
1563 struct urb *urb;
1564 struct xhci_segment *start_seg;
1565 union xhci_trb *first_trb;
1566 union xhci_trb *last_trb;
1567 struct xhci_segment *last_trb_seg;
1568 struct xhci_segment *bounce_seg;
1569
1570 bool urb_length_set;
1571 unsigned int num_trbs;
1572};
1573
1574
1575#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1576
1577
1578struct xhci_cd {
1579 struct xhci_command *command;
1580 union xhci_trb *cmd_trb;
1581};
1582
1583enum xhci_ring_type {
1584 TYPE_CTRL = 0,
1585 TYPE_ISOC,
1586 TYPE_BULK,
1587 TYPE_INTR,
1588 TYPE_STREAM,
1589 TYPE_COMMAND,
1590 TYPE_EVENT,
1591};
1592
1593static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1594{
1595 switch (type) {
1596 case TYPE_CTRL:
1597 return "CTRL";
1598 case TYPE_ISOC:
1599 return "ISOC";
1600 case TYPE_BULK:
1601 return "BULK";
1602 case TYPE_INTR:
1603 return "INTR";
1604 case TYPE_STREAM:
1605 return "STREAM";
1606 case TYPE_COMMAND:
1607 return "CMD";
1608 case TYPE_EVENT:
1609 return "EVENT";
1610 }
1611
1612 return "UNKNOWN";
1613}
1614
1615struct xhci_ring {
1616 struct xhci_segment *first_seg;
1617 struct xhci_segment *last_seg;
1618 union xhci_trb *enqueue;
1619 struct xhci_segment *enq_seg;
1620 union xhci_trb *dequeue;
1621 struct xhci_segment *deq_seg;
1622 struct list_head td_list;
1623
1624
1625
1626
1627
1628 u32 cycle_state;
1629 unsigned int err_count;
1630 unsigned int stream_id;
1631 unsigned int num_segs;
1632 unsigned int num_trbs_free;
1633 unsigned int num_trbs_free_temp;
1634 unsigned int bounce_buf_len;
1635 enum xhci_ring_type type;
1636 bool last_td_was_short;
1637 struct radix_tree_root *trb_address_map;
1638};
1639
1640struct xhci_erst_entry {
1641
1642 __le64 seg_addr;
1643 __le32 seg_size;
1644
1645 __le32 rsvd;
1646};
1647
1648struct xhci_erst {
1649 struct xhci_erst_entry *entries;
1650 unsigned int num_entries;
1651
1652 dma_addr_t erst_dma_addr;
1653
1654 unsigned int erst_size;
1655};
1656
1657struct xhci_scratchpad {
1658 u64 *sp_array;
1659 dma_addr_t sp_dma;
1660 void **sp_buffers;
1661};
1662
1663struct urb_priv {
1664 int num_tds;
1665 int num_tds_done;
1666 struct xhci_td td[];
1667};
1668
1669
1670
1671
1672
1673
1674#define ERST_NUM_SEGS 1
1675
1676#define POLL_TIMEOUT 60
1677
1678#define XHCI_STOP_EP_CMD_TIMEOUT 5
1679
1680
1681struct s3_save {
1682 u32 command;
1683 u32 dev_nt;
1684 u64 dcbaa_ptr;
1685 u32 config_reg;
1686 u32 irq_pending;
1687 u32 irq_control;
1688 u32 erst_size;
1689 u64 erst_base;
1690 u64 erst_dequeue;
1691};
1692
1693
1694struct dev_info {
1695 u32 dev_id;
1696 struct list_head list;
1697};
1698
1699struct xhci_bus_state {
1700 unsigned long bus_suspended;
1701 unsigned long next_statechange;
1702
1703
1704
1705 u32 port_c_suspend;
1706 u32 suspended_ports;
1707 u32 port_remote_wakeup;
1708 unsigned long resume_done[USB_MAXCHILDREN];
1709
1710 unsigned long resuming_ports;
1711
1712 unsigned long rexit_ports;
1713 struct completion rexit_done[USB_MAXCHILDREN];
1714 struct completion u3exit_done[USB_MAXCHILDREN];
1715};
1716
1717
1718
1719
1720
1721
1722#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1723struct xhci_port_cap {
1724 u32 *psi;
1725 u8 psi_count;
1726 u8 psi_uid_count;
1727 u8 maj_rev;
1728 u8 min_rev;
1729};
1730
1731struct xhci_port {
1732 __le32 __iomem *addr;
1733 int hw_portnum;
1734 int hcd_portnum;
1735 struct xhci_hub *rhub;
1736 struct xhci_port_cap *port_cap;
1737};
1738
1739struct xhci_hub {
1740 struct xhci_port **ports;
1741 unsigned int num_ports;
1742 struct usb_hcd *hcd;
1743
1744 struct xhci_bus_state bus_state;
1745
1746 u8 maj_rev;
1747 u8 min_rev;
1748};
1749
1750
1751struct xhci_hcd {
1752 struct usb_hcd *main_hcd;
1753 struct usb_hcd *shared_hcd;
1754
1755 struct xhci_cap_regs __iomem *cap_regs;
1756 struct xhci_op_regs __iomem *op_regs;
1757 struct xhci_run_regs __iomem *run_regs;
1758 struct xhci_doorbell_array __iomem *dba;
1759
1760 struct xhci_intr_reg __iomem *ir_set;
1761
1762
1763 __u32 hcs_params1;
1764 __u32 hcs_params2;
1765 __u32 hcs_params3;
1766 __u32 hcc_params;
1767 __u32 hcc_params2;
1768
1769 spinlock_t lock;
1770
1771
1772 u8 sbrn;
1773 u16 hci_version;
1774 u8 max_slots;
1775 u8 max_interrupters;
1776 u8 max_ports;
1777 u8 isoc_threshold;
1778
1779 u32 imod_interval;
1780 u32 isoc_bei_interval;
1781 int event_ring_max;
1782
1783 int page_size;
1784
1785 int page_shift;
1786
1787 int msix_count;
1788
1789 struct clk *clk;
1790 struct clk *reg_clk;
1791
1792 struct reset_control *reset;
1793
1794 struct xhci_device_context_array *dcbaa;
1795 struct xhci_ring *cmd_ring;
1796 unsigned int cmd_ring_state;
1797#define CMD_RING_STATE_RUNNING (1 << 0)
1798#define CMD_RING_STATE_ABORTED (1 << 1)
1799#define CMD_RING_STATE_STOPPED (1 << 2)
1800 struct list_head cmd_list;
1801 unsigned int cmd_ring_reserved_trbs;
1802 struct delayed_work cmd_timer;
1803 struct completion cmd_ring_stop_completion;
1804 struct xhci_command *current_cmd;
1805 struct xhci_ring *event_ring;
1806 struct xhci_erst erst;
1807
1808 struct xhci_scratchpad *scratchpad;
1809
1810 struct list_head lpm_failed_devs;
1811
1812
1813
1814 struct mutex mutex;
1815
1816 struct xhci_command *lpm_command;
1817
1818 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1819
1820 struct xhci_root_port_bw_info *rh_bw;
1821
1822
1823 struct dma_pool *device_pool;
1824 struct dma_pool *segment_pool;
1825 struct dma_pool *small_streams_pool;
1826 struct dma_pool *medium_streams_pool;
1827
1828
1829 unsigned int xhc_state;
1830
1831 u32 command;
1832 struct s3_save s3;
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845#define XHCI_STATE_DYING (1 << 0)
1846#define XHCI_STATE_HALTED (1 << 1)
1847#define XHCI_STATE_REMOVING (1 << 2)
1848 unsigned long long quirks;
1849#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1850#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1851#define XHCI_NEC_HOST BIT_ULL(2)
1852#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1853#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1864#define XHCI_BROKEN_MSI BIT_ULL(6)
1865#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1866#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1867#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1868#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1869#define XHCI_LPM_SUPPORT BIT_ULL(11)
1870#define XHCI_INTEL_HOST BIT_ULL(12)
1871#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1872#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1873#define XHCI_AVOID_BEI BIT_ULL(15)
1874#define XHCI_PLAT BIT_ULL(16)
1875#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1876#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1877
1878#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1879#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1880#define XHCI_MTK_HOST BIT_ULL(21)
1881#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1882#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1883#define XHCI_MISSING_CAS BIT_ULL(24)
1884
1885#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1886#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1887#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1888#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1889#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1890#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1891#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1892#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1893#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1894#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1895#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1896#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1897#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1898#define XHCI_DISABLE_SPARSE BIT_ULL(38)
1899#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1900#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1901#define XHCI_BROKEN_D3COLD BIT_ULL(41)
1902#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1903
1904 unsigned int num_active_eps;
1905 unsigned int limit_active_eps;
1906 struct xhci_port *hw_ports;
1907 struct xhci_hub usb2_rhub;
1908 struct xhci_hub usb3_rhub;
1909
1910 unsigned hw_lpm_support:1;
1911
1912 unsigned broken_suspend:1;
1913
1914 u32 *ext_caps;
1915 unsigned int num_ext_caps;
1916
1917 struct xhci_port_cap *port_caps;
1918 unsigned int num_port_caps;
1919
1920 struct timer_list comp_mode_recovery_timer;
1921 u32 port_status_u0;
1922 u16 test_mode;
1923
1924#define COMP_MODE_RCVRY_MSECS 2000
1925
1926 struct dentry *debugfs_root;
1927 struct dentry *debugfs_slots;
1928 struct list_head regset_list;
1929
1930 void *dbc;
1931
1932 unsigned long priv[] __aligned(sizeof(s64));
1933};
1934
1935
1936struct xhci_driver_overrides {
1937 size_t extra_priv_size;
1938 int (*reset)(struct usb_hcd *hcd);
1939 int (*start)(struct usb_hcd *hcd);
1940 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1941 struct usb_host_endpoint *ep);
1942 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1943 struct usb_host_endpoint *ep);
1944 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1945 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1946};
1947
1948#define XHCI_CFC_DELAY 10
1949
1950
1951static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1952{
1953 struct usb_hcd *primary_hcd;
1954
1955 if (usb_hcd_is_primary_hcd(hcd))
1956 primary_hcd = hcd;
1957 else
1958 primary_hcd = hcd->primary_hcd;
1959
1960 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1961}
1962
1963static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1964{
1965 return xhci->main_hcd;
1966}
1967
1968#define xhci_dbg(xhci, fmt, args...) \
1969 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1970#define xhci_err(xhci, fmt, args...) \
1971 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1972#define xhci_warn(xhci, fmt, args...) \
1973 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1974#define xhci_warn_ratelimited(xhci, fmt, args...) \
1975 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1976#define xhci_info(xhci, fmt, args...) \
1977 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1989 __le64 __iomem *regs)
1990{
1991 return lo_hi_readq(regs);
1992}
1993static inline void xhci_write_64(struct xhci_hcd *xhci,
1994 const u64 val, __le64 __iomem *regs)
1995{
1996 lo_hi_writeq(val, regs);
1997}
1998
1999static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
2000{
2001 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
2002}
2003
2004
2005char *xhci_get_slot_state(struct xhci_hcd *xhci,
2006 struct xhci_container_ctx *ctx);
2007void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2008 const char *fmt, ...);
2009
2010
2011void xhci_mem_cleanup(struct xhci_hcd *xhci);
2012int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2013void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2014int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2015int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2016void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2017 struct usb_device *udev);
2018unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2019unsigned int xhci_get_endpoint_address(unsigned int ep_index);
2020unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2021void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2022void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2023 struct xhci_virt_device *virt_dev,
2024 int old_active_eps);
2025void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2026void xhci_update_bw_info(struct xhci_hcd *xhci,
2027 struct xhci_container_ctx *in_ctx,
2028 struct xhci_input_control_ctx *ctrl_ctx,
2029 struct xhci_virt_device *virt_dev);
2030void xhci_endpoint_copy(struct xhci_hcd *xhci,
2031 struct xhci_container_ctx *in_ctx,
2032 struct xhci_container_ctx *out_ctx,
2033 unsigned int ep_index);
2034void xhci_slot_copy(struct xhci_hcd *xhci,
2035 struct xhci_container_ctx *in_ctx,
2036 struct xhci_container_ctx *out_ctx);
2037int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2038 struct usb_device *udev, struct usb_host_endpoint *ep,
2039 gfp_t mem_flags);
2040struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2041 unsigned int num_segs, unsigned int cycle_state,
2042 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2043void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2044int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2045 unsigned int num_trbs, gfp_t flags);
2046int xhci_alloc_erst(struct xhci_hcd *xhci,
2047 struct xhci_ring *evt_ring,
2048 struct xhci_erst *erst,
2049 gfp_t flags);
2050void xhci_initialize_ring_info(struct xhci_ring *ring,
2051 unsigned int cycle_state);
2052void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2053void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2054 struct xhci_virt_device *virt_dev,
2055 unsigned int ep_index);
2056struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2057 unsigned int num_stream_ctxs,
2058 unsigned int num_streams,
2059 unsigned int max_packet, gfp_t flags);
2060void xhci_free_stream_info(struct xhci_hcd *xhci,
2061 struct xhci_stream_info *stream_info);
2062void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2063 struct xhci_ep_ctx *ep_ctx,
2064 struct xhci_stream_info *stream_info);
2065void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2066 struct xhci_virt_ep *ep);
2067void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2068 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2069struct xhci_ring *xhci_dma_to_transfer_ring(
2070 struct xhci_virt_ep *ep,
2071 u64 address);
2072struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2073 bool allocate_completion, gfp_t mem_flags);
2074struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2075 bool allocate_completion, gfp_t mem_flags);
2076void xhci_urb_free_priv(struct urb_priv *urb_priv);
2077void xhci_free_command(struct xhci_hcd *xhci,
2078 struct xhci_command *command);
2079struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2080 int type, gfp_t flags);
2081void xhci_free_container_ctx(struct xhci_hcd *xhci,
2082 struct xhci_container_ctx *ctx);
2083
2084
2085typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2086int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2087void xhci_quiesce(struct xhci_hcd *xhci);
2088int xhci_halt(struct xhci_hcd *xhci);
2089int xhci_start(struct xhci_hcd *xhci);
2090int xhci_reset(struct xhci_hcd *xhci);
2091int xhci_run(struct usb_hcd *hcd);
2092int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2093void xhci_shutdown(struct usb_hcd *hcd);
2094void xhci_init_driver(struct hc_driver *drv,
2095 const struct xhci_driver_overrides *over);
2096int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2097 struct usb_host_endpoint *ep);
2098int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2099 struct usb_host_endpoint *ep);
2100int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2101void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2102int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2103int xhci_ext_cap_init(struct xhci_hcd *xhci);
2104
2105int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2106int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2107
2108irqreturn_t xhci_irq(struct usb_hcd *hcd);
2109irqreturn_t xhci_msi_irq(int irq, void *hcd);
2110int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2111int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2112 struct xhci_virt_device *virt_dev,
2113 struct usb_device *hdev,
2114 struct usb_tt *tt, gfp_t mem_flags);
2115
2116
2117dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2118struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2119 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2120 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2121int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2122void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2123int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2124 u32 trb_type, u32 slot_id);
2125int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2126 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2127int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2128 u32 field1, u32 field2, u32 field3, u32 field4);
2129int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2130 int slot_id, unsigned int ep_index, int suspend);
2131int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2132 int slot_id, unsigned int ep_index);
2133int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2134 int slot_id, unsigned int ep_index);
2135int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2136 int slot_id, unsigned int ep_index);
2137int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2138 struct urb *urb, int slot_id, unsigned int ep_index);
2139int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2140 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2141 bool command_must_succeed);
2142int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2143 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2144int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2145 int slot_id, unsigned int ep_index,
2146 enum xhci_ep_reset_type reset_type);
2147int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2148 u32 slot_id);
2149void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2150 unsigned int ep_index, unsigned int stream_id,
2151 struct xhci_td *td);
2152void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2153void xhci_handle_command_timeout(struct work_struct *work);
2154
2155void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2156 unsigned int ep_index, unsigned int stream_id);
2157void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2158 unsigned int slot_id,
2159 unsigned int ep_index);
2160void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2161void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2162unsigned int count_trbs(u64 addr, u64 len);
2163
2164
2165void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2166 u32 link_state);
2167void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2168 u32 port_bit);
2169int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2170 char *buf, u16 wLength);
2171int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2172int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2173struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2174
2175void xhci_hc_died(struct xhci_hcd *xhci);
2176
2177#ifdef CONFIG_PM
2178int xhci_bus_suspend(struct usb_hcd *hcd);
2179int xhci_bus_resume(struct usb_hcd *hcd);
2180unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2181#else
2182#define xhci_bus_suspend NULL
2183#define xhci_bus_resume NULL
2184#define xhci_get_resuming_ports NULL
2185#endif
2186
2187u32 xhci_port_state_to_neutral(u32 state);
2188int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2189 u16 port);
2190void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2191
2192
2193struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2194struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2195struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2196
2197struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2198 unsigned int slot_id, unsigned int ep_index,
2199 unsigned int stream_id);
2200
2201static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2202 struct urb *urb)
2203{
2204 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2205 xhci_get_endpoint_index(&urb->ep->desc),
2206 urb->stream_id);
2207}
2208
2209
2210
2211
2212
2213
2214static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2215{
2216 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2217 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2218 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2219 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2220 !urb->num_sgs)
2221 return true;
2222
2223 return false;
2224}
2225
2226static inline char *xhci_slot_state_string(u32 state)
2227{
2228 switch (state) {
2229 case SLOT_STATE_ENABLED:
2230 return "enabled/disabled";
2231 case SLOT_STATE_DEFAULT:
2232 return "default";
2233 case SLOT_STATE_ADDRESSED:
2234 return "addressed";
2235 case SLOT_STATE_CONFIGURED:
2236 return "configured";
2237 default:
2238 return "reserved";
2239 }
2240}
2241
2242static inline const char *xhci_decode_trb(char *str, size_t size,
2243 u32 field0, u32 field1, u32 field2, u32 field3)
2244{
2245 int type = TRB_FIELD_TO_TYPE(field3);
2246
2247 switch (type) {
2248 case TRB_LINK:
2249 snprintf(str, size,
2250 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2251 field1, field0, GET_INTR_TARGET(field2),
2252 xhci_trb_type_string(type),
2253 field3 & TRB_IOC ? 'I' : 'i',
2254 field3 & TRB_CHAIN ? 'C' : 'c',
2255 field3 & TRB_TC ? 'T' : 't',
2256 field3 & TRB_CYCLE ? 'C' : 'c');
2257 break;
2258 case TRB_TRANSFER:
2259 case TRB_COMPLETION:
2260 case TRB_PORT_STATUS:
2261 case TRB_BANDWIDTH_EVENT:
2262 case TRB_DOORBELL:
2263 case TRB_HC_EVENT:
2264 case TRB_DEV_NOTE:
2265 case TRB_MFINDEX_WRAP:
2266 snprintf(str, size,
2267 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2268 field1, field0,
2269 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2270 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2271
2272 TRB_TO_EP_INDEX(field3) + 1,
2273 xhci_trb_type_string(type),
2274 field3 & EVENT_DATA ? 'E' : 'e',
2275 field3 & TRB_CYCLE ? 'C' : 'c');
2276
2277 break;
2278 case TRB_SETUP:
2279 snprintf(str, size,
2280 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2281 field0 & 0xff,
2282 (field0 & 0xff00) >> 8,
2283 (field0 & 0xff000000) >> 24,
2284 (field0 & 0xff0000) >> 16,
2285 (field1 & 0xff00) >> 8,
2286 field1 & 0xff,
2287 (field1 & 0xff000000) >> 16 |
2288 (field1 & 0xff0000) >> 16,
2289 TRB_LEN(field2), GET_TD_SIZE(field2),
2290 GET_INTR_TARGET(field2),
2291 xhci_trb_type_string(type),
2292 field3 & TRB_IDT ? 'I' : 'i',
2293 field3 & TRB_IOC ? 'I' : 'i',
2294 field3 & TRB_CYCLE ? 'C' : 'c');
2295 break;
2296 case TRB_DATA:
2297 snprintf(str, size,
2298 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2299 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2300 GET_INTR_TARGET(field2),
2301 xhci_trb_type_string(type),
2302 field3 & TRB_IDT ? 'I' : 'i',
2303 field3 & TRB_IOC ? 'I' : 'i',
2304 field3 & TRB_CHAIN ? 'C' : 'c',
2305 field3 & TRB_NO_SNOOP ? 'S' : 's',
2306 field3 & TRB_ISP ? 'I' : 'i',
2307 field3 & TRB_ENT ? 'E' : 'e',
2308 field3 & TRB_CYCLE ? 'C' : 'c');
2309 break;
2310 case TRB_STATUS:
2311 snprintf(str, size,
2312 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2313 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2314 GET_INTR_TARGET(field2),
2315 xhci_trb_type_string(type),
2316 field3 & TRB_IOC ? 'I' : 'i',
2317 field3 & TRB_CHAIN ? 'C' : 'c',
2318 field3 & TRB_ENT ? 'E' : 'e',
2319 field3 & TRB_CYCLE ? 'C' : 'c');
2320 break;
2321 case TRB_NORMAL:
2322 case TRB_ISOC:
2323 case TRB_EVENT_DATA:
2324 case TRB_TR_NOOP:
2325 snprintf(str, size,
2326 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2327 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2328 GET_INTR_TARGET(field2),
2329 xhci_trb_type_string(type),
2330 field3 & TRB_BEI ? 'B' : 'b',
2331 field3 & TRB_IDT ? 'I' : 'i',
2332 field3 & TRB_IOC ? 'I' : 'i',
2333 field3 & TRB_CHAIN ? 'C' : 'c',
2334 field3 & TRB_NO_SNOOP ? 'S' : 's',
2335 field3 & TRB_ISP ? 'I' : 'i',
2336 field3 & TRB_ENT ? 'E' : 'e',
2337 field3 & TRB_CYCLE ? 'C' : 'c');
2338 break;
2339
2340 case TRB_CMD_NOOP:
2341 case TRB_ENABLE_SLOT:
2342 snprintf(str, size,
2343 "%s: flags %c",
2344 xhci_trb_type_string(type),
2345 field3 & TRB_CYCLE ? 'C' : 'c');
2346 break;
2347 case TRB_DISABLE_SLOT:
2348 case TRB_NEG_BANDWIDTH:
2349 snprintf(str, size,
2350 "%s: slot %d flags %c",
2351 xhci_trb_type_string(type),
2352 TRB_TO_SLOT_ID(field3),
2353 field3 & TRB_CYCLE ? 'C' : 'c');
2354 break;
2355 case TRB_ADDR_DEV:
2356 snprintf(str, size,
2357 "%s: ctx %08x%08x slot %d flags %c:%c",
2358 xhci_trb_type_string(type),
2359 field1, field0,
2360 TRB_TO_SLOT_ID(field3),
2361 field3 & TRB_BSR ? 'B' : 'b',
2362 field3 & TRB_CYCLE ? 'C' : 'c');
2363 break;
2364 case TRB_CONFIG_EP:
2365 snprintf(str, size,
2366 "%s: ctx %08x%08x slot %d flags %c:%c",
2367 xhci_trb_type_string(type),
2368 field1, field0,
2369 TRB_TO_SLOT_ID(field3),
2370 field3 & TRB_DC ? 'D' : 'd',
2371 field3 & TRB_CYCLE ? 'C' : 'c');
2372 break;
2373 case TRB_EVAL_CONTEXT:
2374 snprintf(str, size,
2375 "%s: ctx %08x%08x slot %d flags %c",
2376 xhci_trb_type_string(type),
2377 field1, field0,
2378 TRB_TO_SLOT_ID(field3),
2379 field3 & TRB_CYCLE ? 'C' : 'c');
2380 break;
2381 case TRB_RESET_EP:
2382 snprintf(str, size,
2383 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2384 xhci_trb_type_string(type),
2385 field1, field0,
2386 TRB_TO_SLOT_ID(field3),
2387
2388 TRB_TO_EP_INDEX(field3) + 1,
2389 field3 & TRB_TSP ? 'T' : 't',
2390 field3 & TRB_CYCLE ? 'C' : 'c');
2391 break;
2392 case TRB_STOP_RING:
2393 sprintf(str,
2394 "%s: slot %d sp %d ep %d flags %c",
2395 xhci_trb_type_string(type),
2396 TRB_TO_SLOT_ID(field3),
2397 TRB_TO_SUSPEND_PORT(field3),
2398
2399 TRB_TO_EP_INDEX(field3) + 1,
2400 field3 & TRB_CYCLE ? 'C' : 'c');
2401 break;
2402 case TRB_SET_DEQ:
2403 snprintf(str, size,
2404 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2405 xhci_trb_type_string(type),
2406 field1, field0,
2407 TRB_TO_STREAM_ID(field2),
2408 TRB_TO_SLOT_ID(field3),
2409
2410 TRB_TO_EP_INDEX(field3) + 1,
2411 field3 & TRB_CYCLE ? 'C' : 'c');
2412 break;
2413 case TRB_RESET_DEV:
2414 snprintf(str, size,
2415 "%s: slot %d flags %c",
2416 xhci_trb_type_string(type),
2417 TRB_TO_SLOT_ID(field3),
2418 field3 & TRB_CYCLE ? 'C' : 'c');
2419 break;
2420 case TRB_FORCE_EVENT:
2421 snprintf(str, size,
2422 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2423 xhci_trb_type_string(type),
2424 field1, field0,
2425 TRB_TO_VF_INTR_TARGET(field2),
2426 TRB_TO_VF_ID(field3),
2427 field3 & TRB_CYCLE ? 'C' : 'c');
2428 break;
2429 case TRB_SET_LT:
2430 snprintf(str, size,
2431 "%s: belt %d flags %c",
2432 xhci_trb_type_string(type),
2433 TRB_TO_BELT(field3),
2434 field3 & TRB_CYCLE ? 'C' : 'c');
2435 break;
2436 case TRB_GET_BW:
2437 snprintf(str, size,
2438 "%s: ctx %08x%08x slot %d speed %d flags %c",
2439 xhci_trb_type_string(type),
2440 field1, field0,
2441 TRB_TO_SLOT_ID(field3),
2442 TRB_TO_DEV_SPEED(field3),
2443 field3 & TRB_CYCLE ? 'C' : 'c');
2444 break;
2445 case TRB_FORCE_HEADER:
2446 snprintf(str, size,
2447 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2448 xhci_trb_type_string(type),
2449 field2, field1, field0 & 0xffffffe0,
2450 TRB_TO_PACKET_TYPE(field0),
2451 TRB_TO_ROOTHUB_PORT(field3),
2452 field3 & TRB_CYCLE ? 'C' : 'c');
2453 break;
2454 default:
2455 snprintf(str, size,
2456 "type '%s' -> raw %08x %08x %08x %08x",
2457 xhci_trb_type_string(type),
2458 field0, field1, field2, field3);
2459 }
2460
2461 return str;
2462}
2463
2464static inline const char *xhci_decode_ctrl_ctx(char *str,
2465 unsigned long drop, unsigned long add)
2466{
2467 unsigned int bit;
2468 int ret = 0;
2469
2470 if (drop) {
2471 ret = sprintf(str, "Drop:");
2472 for_each_set_bit(bit, &drop, 32)
2473 ret += sprintf(str + ret, " %d%s",
2474 bit / 2,
2475 bit % 2 ? "in":"out");
2476 ret += sprintf(str + ret, ", ");
2477 }
2478
2479 if (add) {
2480 ret += sprintf(str + ret, "Add:%s%s",
2481 (add & SLOT_FLAG) ? " slot":"",
2482 (add & EP0_FLAG) ? " ep0":"");
2483 add &= ~(SLOT_FLAG | EP0_FLAG);
2484 for_each_set_bit(bit, &add, 32)
2485 ret += sprintf(str + ret, " %d%s",
2486 bit / 2,
2487 bit % 2 ? "in":"out");
2488 }
2489 return str;
2490}
2491
2492static inline const char *xhci_decode_slot_context(char *str,
2493 u32 info, u32 info2, u32 tt_info, u32 state)
2494{
2495 u32 speed;
2496 u32 hub;
2497 u32 mtt;
2498 int ret = 0;
2499
2500 speed = info & DEV_SPEED;
2501 hub = info & DEV_HUB;
2502 mtt = info & DEV_MTT;
2503
2504 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2505 info & ROUTE_STRING_MASK,
2506 ({ char *s;
2507 switch (speed) {
2508 case SLOT_SPEED_FS:
2509 s = "full-speed";
2510 break;
2511 case SLOT_SPEED_LS:
2512 s = "low-speed";
2513 break;
2514 case SLOT_SPEED_HS:
2515 s = "high-speed";
2516 break;
2517 case SLOT_SPEED_SS:
2518 s = "super-speed";
2519 break;
2520 case SLOT_SPEED_SSP:
2521 s = "super-speed plus";
2522 break;
2523 default:
2524 s = "UNKNOWN speed";
2525 } s; }),
2526 mtt ? " multi-TT" : "",
2527 hub ? " Hub" : "",
2528 (info & LAST_CTX_MASK) >> 27,
2529 info2 & MAX_EXIT,
2530 DEVINFO_TO_ROOT_HUB_PORT(info2),
2531 DEVINFO_TO_MAX_PORTS(info2));
2532
2533 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2534 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2535 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2536 state & DEV_ADDR_MASK,
2537 xhci_slot_state_string(GET_SLOT_STATE(state)));
2538
2539 return str;
2540}
2541
2542
2543static inline const char *xhci_portsc_link_state_string(u32 portsc)
2544{
2545 switch (portsc & PORT_PLS_MASK) {
2546 case XDEV_U0:
2547 return "U0";
2548 case XDEV_U1:
2549 return "U1";
2550 case XDEV_U2:
2551 return "U2";
2552 case XDEV_U3:
2553 return "U3";
2554 case XDEV_DISABLED:
2555 return "Disabled";
2556 case XDEV_RXDETECT:
2557 return "RxDetect";
2558 case XDEV_INACTIVE:
2559 return "Inactive";
2560 case XDEV_POLLING:
2561 return "Polling";
2562 case XDEV_RECOVERY:
2563 return "Recovery";
2564 case XDEV_HOT_RESET:
2565 return "Hot Reset";
2566 case XDEV_COMP_MODE:
2567 return "Compliance mode";
2568 case XDEV_TEST_MODE:
2569 return "Test mode";
2570 case XDEV_RESUME:
2571 return "Resume";
2572 default:
2573 break;
2574 }
2575 return "Unknown";
2576}
2577
2578static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2579{
2580 int ret;
2581
2582 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2583 portsc & PORT_POWER ? "Powered" : "Powered-off",
2584 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2585 portsc & PORT_PE ? "Enabled" : "Disabled",
2586 xhci_portsc_link_state_string(portsc),
2587 DEV_PORT_SPEED(portsc));
2588
2589 if (portsc & PORT_OC)
2590 ret += sprintf(str + ret, "OverCurrent ");
2591 if (portsc & PORT_RESET)
2592 ret += sprintf(str + ret, "In-Reset ");
2593
2594 ret += sprintf(str + ret, "Change: ");
2595 if (portsc & PORT_CSC)
2596 ret += sprintf(str + ret, "CSC ");
2597 if (portsc & PORT_PEC)
2598 ret += sprintf(str + ret, "PEC ");
2599 if (portsc & PORT_WRC)
2600 ret += sprintf(str + ret, "WRC ");
2601 if (portsc & PORT_OCC)
2602 ret += sprintf(str + ret, "OCC ");
2603 if (portsc & PORT_RC)
2604 ret += sprintf(str + ret, "PRC ");
2605 if (portsc & PORT_PLC)
2606 ret += sprintf(str + ret, "PLC ");
2607 if (portsc & PORT_CEC)
2608 ret += sprintf(str + ret, "CEC ");
2609 if (portsc & PORT_CAS)
2610 ret += sprintf(str + ret, "CAS ");
2611
2612 ret += sprintf(str + ret, "Wake: ");
2613 if (portsc & PORT_WKCONN_E)
2614 ret += sprintf(str + ret, "WCE ");
2615 if (portsc & PORT_WKDISC_E)
2616 ret += sprintf(str + ret, "WDE ");
2617 if (portsc & PORT_WKOC_E)
2618 ret += sprintf(str + ret, "WOE ");
2619
2620 return str;
2621}
2622
2623static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2624{
2625 int ret = 0;
2626
2627 if (usbsts == ~(u32)0)
2628 return " 0xffffffff";
2629 if (usbsts & STS_HALT)
2630 ret += sprintf(str + ret, " HCHalted");
2631 if (usbsts & STS_FATAL)
2632 ret += sprintf(str + ret, " HSE");
2633 if (usbsts & STS_EINT)
2634 ret += sprintf(str + ret, " EINT");
2635 if (usbsts & STS_PORT)
2636 ret += sprintf(str + ret, " PCD");
2637 if (usbsts & STS_SAVE)
2638 ret += sprintf(str + ret, " SSS");
2639 if (usbsts & STS_RESTORE)
2640 ret += sprintf(str + ret, " RSS");
2641 if (usbsts & STS_SRE)
2642 ret += sprintf(str + ret, " SRE");
2643 if (usbsts & STS_CNR)
2644 ret += sprintf(str + ret, " CNR");
2645 if (usbsts & STS_HCE)
2646 ret += sprintf(str + ret, " HCE");
2647
2648 return str;
2649}
2650
2651static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2652{
2653 u8 ep;
2654 u16 stream;
2655 int ret;
2656
2657 ep = (doorbell & 0xff);
2658 stream = doorbell >> 16;
2659
2660 if (slot == 0) {
2661 sprintf(str, "Command Ring %d", doorbell);
2662 return str;
2663 }
2664 ret = sprintf(str, "Slot %d ", slot);
2665 if (ep > 0 && ep < 32)
2666 ret = sprintf(str + ret, "ep%d%s",
2667 ep / 2,
2668 ep % 2 ? "in" : "out");
2669 else if (ep == 0 || ep < 248)
2670 ret = sprintf(str + ret, "Reserved %d", ep);
2671 else
2672 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2673 if (stream)
2674 ret = sprintf(str + ret, " Stream %d", stream);
2675
2676 return str;
2677}
2678
2679static inline const char *xhci_ep_state_string(u8 state)
2680{
2681 switch (state) {
2682 case EP_STATE_DISABLED:
2683 return "disabled";
2684 case EP_STATE_RUNNING:
2685 return "running";
2686 case EP_STATE_HALTED:
2687 return "halted";
2688 case EP_STATE_STOPPED:
2689 return "stopped";
2690 case EP_STATE_ERROR:
2691 return "error";
2692 default:
2693 return "INVALID";
2694 }
2695}
2696
2697static inline const char *xhci_ep_type_string(u8 type)
2698{
2699 switch (type) {
2700 case ISOC_OUT_EP:
2701 return "Isoc OUT";
2702 case BULK_OUT_EP:
2703 return "Bulk OUT";
2704 case INT_OUT_EP:
2705 return "Int OUT";
2706 case CTRL_EP:
2707 return "Ctrl";
2708 case ISOC_IN_EP:
2709 return "Isoc IN";
2710 case BULK_IN_EP:
2711 return "Bulk IN";
2712 case INT_IN_EP:
2713 return "Int IN";
2714 default:
2715 return "INVALID";
2716 }
2717}
2718
2719static inline const char *xhci_decode_ep_context(char *str, u32 info,
2720 u32 info2, u64 deq, u32 tx_info)
2721{
2722 int ret;
2723
2724 u32 esit;
2725 u16 maxp;
2726 u16 avg;
2727
2728 u8 max_pstr;
2729 u8 ep_state;
2730 u8 interval;
2731 u8 ep_type;
2732 u8 burst;
2733 u8 cerr;
2734 u8 mult;
2735
2736 bool lsa;
2737 bool hid;
2738
2739 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2740 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2741
2742 ep_state = info & EP_STATE_MASK;
2743 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2744 interval = CTX_TO_EP_INTERVAL(info);
2745 mult = CTX_TO_EP_MULT(info) + 1;
2746 lsa = !!(info & EP_HAS_LSA);
2747
2748 cerr = (info2 & (3 << 1)) >> 1;
2749 ep_type = CTX_TO_EP_TYPE(info2);
2750 hid = !!(info2 & (1 << 7));
2751 burst = CTX_TO_MAX_BURST(info2);
2752 maxp = MAX_PACKET_DECODED(info2);
2753
2754 avg = EP_AVG_TRB_LENGTH(tx_info);
2755
2756 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2757 xhci_ep_state_string(ep_state), mult,
2758 max_pstr, lsa ? "LSA " : "");
2759
2760 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2761 (1 << interval) * 125, esit, cerr);
2762
2763 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2764 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2765 burst, maxp, deq);
2766
2767 ret += sprintf(str + ret, "avg trb len %d", avg);
2768
2769 return str;
2770}
2771
2772#endif
2773