1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright (C) 2005-2006 by Texas Instruments */ 3 4#ifndef _CPPI_DMA_H_ 5#define _CPPI_DMA_H_ 6 7#include <linux/slab.h> 8#include <linux/list.h> 9#include <linux/errno.h> 10#include <linux/dmapool.h> 11#include <linux/dmaengine.h> 12 13#include "musb_core.h" 14#include "musb_dma.h" 15 16/* CPPI RX/TX state RAM */ 17 18struct cppi_tx_stateram { 19 u32 tx_head; /* "DMA packet" head descriptor */ 20 u32 tx_buf; 21 u32 tx_current; /* current descriptor */ 22 u32 tx_buf_current; 23 u32 tx_info; /* flags, remaining buflen */ 24 u32 tx_rem_len; 25 u32 tx_dummy; /* unused */ 26 u32 tx_complete; 27}; 28 29struct cppi_rx_stateram { 30 u32 rx_skipbytes; 31 u32 rx_head; 32 u32 rx_sop; /* "DMA packet" head descriptor */ 33 u32 rx_current; /* current descriptor */ 34 u32 rx_buf_current; 35 u32 rx_len_len; 36 u32 rx_cnt_cnt; 37 u32 rx_complete; 38}; 39 40/* hw_options bits in CPPI buffer descriptors */ 41#define CPPI_SOP_SET ((u32)(1 << 31)) 42#define CPPI_EOP_SET ((u32)(1 << 30)) 43#define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */ 44#define CPPI_EOQ_MASK ((u32)(1 << 28)) 45#define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */ 46#define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */ 47 48#define CPPI_RECV_PKTLEN_MASK 0xFFFF 49#define CPPI_BUFFER_LEN_MASK 0xFFFF 50 51#define CPPI_TEAR_READY ((u32)(1 << 31)) 52 53/* CPPI data structure definitions */ 54 55#define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */ 56 57struct cppi_descriptor { 58 /* hardware overlay */ 59 u32 hw_next; /* next buffer descriptor Pointer */ 60 u32 hw_bufp; /* i/o buffer pointer */ 61 u32 hw_off_len; /* buffer_offset16, buffer_length16 */ 62 u32 hw_options; /* flags: SOP, EOP etc*/ 63 64 struct cppi_descriptor *next; 65 dma_addr_t dma; /* address of this descriptor */ 66 u32 buflen; /* for RX: original buffer length */ 67} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN))); 68 69 70struct cppi; 71 72/* CPPI Channel Control structure */ 73struct cppi_channel { 74 struct dma_channel channel; 75 76 /* back pointer to the DMA controller structure */ 77 struct cppi *controller; 78 79 /* which direction of which endpoint? */ 80 struct musb_hw_ep *hw_ep; 81 bool transmit; 82 u8 index; 83 84 /* DMA modes: RNDIS or "transparent" */ 85 u8 is_rndis; 86 87 /* book keeping for current transfer request */ 88 dma_addr_t buf_dma; 89 u32 buf_len; 90 u32 maxpacket; 91 u32 offset; /* dma requested */ 92 93 void __iomem *state_ram; /* CPPI state */ 94 95 struct cppi_descriptor *freelist; 96 97 /* BD management fields */ 98 struct cppi_descriptor *head; 99 struct cppi_descriptor *tail; 100 struct cppi_descriptor *last_processed; 101 102 /* use tx_complete in host role to track endpoints waiting for 103 * FIFONOTEMPTY to clear. 104 */ 105 struct list_head tx_complete; 106}; 107 108/* CPPI DMA controller object */ 109struct cppi { 110 struct dma_controller controller; 111 void __iomem *mregs; /* Mentor regs */ 112 void __iomem *tibase; /* TI/CPPI regs */ 113 114 int irq; 115 116 struct cppi_channel tx[4]; 117 struct cppi_channel rx[4]; 118 119 struct dma_pool *pool; 120 121 struct list_head tx_complete; 122}; 123 124/* CPPI IRQ handler */ 125extern irqreturn_t cppi_interrupt(int, void *); 126 127struct cppi41_dma_channel { 128 struct dma_channel channel; 129 struct cppi41_dma_controller *controller; 130 struct musb_hw_ep *hw_ep; 131 struct dma_chan *dc; 132 dma_cookie_t cookie; 133 u8 port_num; 134 u8 is_tx; 135 u8 is_allocated; 136 u8 usb_toggle; 137 138 dma_addr_t buf_addr; 139 u32 total_len; 140 u32 prog_len; 141 u32 transferred; 142 u32 packet_sz; 143 struct list_head tx_check; 144 int tx_zlp; 145}; 146 147#endif /* end of ifndef _CPPI_DMA_H_ */ 148