LXR linux/drivers/usb/renesas

   1/* SPDX-License-Identifier: GPL-1.0+ */
   2/*
   3 * Renesas USB driver
   4 *
   5 * Copyright (C) 2011 Renesas Solutions Corp.
   6 * Copyright (C) 2019 Renesas Electronics Corporation
   7 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   8 */
   9#ifndef RENESAS_USB_DRIVER_H
  10#define RENESAS_USB_DRIVER_H
  11
  12#include <linux/clk.h>
  13#include <linux/extcon.h>
  14#include <linux/platform_device.h>
  15#include <linux/reset.h>
  16#include <linux/usb/renesas_usbhs.h>
  17
  18struct usbhs_priv;
  19
  20#include "mod.h"
  21#include "pipe.h"
  22
  23/*
  24 *
  25 *              register define
  26 *
  27 */
  28#define SYSCFG          0x0000
  29#define BUSWAIT         0x0002
  30#define DVSTCTR         0x0008
  31#define TESTMODE        0x000C
  32#define CFIFO           0x0014
  33#define CFIFOSEL        0x0020
  34#define CFIFOCTR        0x0022
  35#define D0FIFO          0x0100
  36#define D0FIFOSEL       0x0028
  37#define D0FIFOCTR       0x002A
  38#define D1FIFO          0x0120
  39#define D1FIFOSEL       0x002C
  40#define D1FIFOCTR       0x002E
  41#define INTENB0         0x0030
  42#define INTENB1         0x0032
  43#define BRDYENB         0x0036
  44#define NRDYENB         0x0038
  45#define BEMPENB         0x003A
  46#define INTSTS0         0x0040
  47#define INTSTS1         0x0042
  48#define BRDYSTS         0x0046
  49#define NRDYSTS         0x0048
  50#define BEMPSTS         0x004A
  51#define FRMNUM          0x004C
  52#define USBREQ          0x0054  /* USB request type register */
  53#define USBVAL          0x0056  /* USB request value register */
  54#define USBINDX         0x0058  /* USB request index register */
  55#define USBLENG         0x005A  /* USB request length register */
  56#define DCPCFG          0x005C
  57#define DCPMAXP         0x005E
  58#define DCPCTR          0x0060
  59#define PIPESEL         0x0064
  60#define PIPECFG         0x0068
  61#define PIPEBUF         0x006A
  62#define PIPEMAXP        0x006C
  63#define PIPEPERI        0x006E
  64#define PIPEnCTR        0x0070
  65#define PIPE1TRE        0x0090
  66#define PIPE1TRN        0x0092
  67#define PIPE2TRE        0x0094
  68#define PIPE2TRN        0x0096
  69#define PIPE3TRE        0x0098
  70#define PIPE3TRN        0x009A
  71#define PIPE4TRE        0x009C
  72#define PIPE4TRN        0x009E
  73#define PIPE5TRE        0x00A0
  74#define PIPE5TRN        0x00A2
  75#define PIPEBTRE        0x00A4
  76#define PIPEBTRN        0x00A6
  77#define PIPECTRE        0x00A8
  78#define PIPECTRN        0x00AA
  79#define PIPEDTRE        0x00AC
  80#define PIPEDTRN        0x00AE
  81#define PIPEETRE        0x00B0
  82#define PIPEETRN        0x00B2
  83#define PIPEFTRE        0x00B4
  84#define PIPEFTRN        0x00B6
  85#define PIPE9TRE        0x00B8
  86#define PIPE9TRN        0x00BA
  87#define PIPEATRE        0x00BC
  88#define PIPEATRN        0x00BE
  89#define DEVADD0         0x00D0 /* Device address n configuration */
  90#define DEVADD1         0x00D2
  91#define DEVADD2         0x00D4
  92#define DEVADD3         0x00D6
  93#define DEVADD4         0x00D8
  94#define DEVADD5         0x00DA
  95#define DEVADD6         0x00DC
  96#define DEVADD7         0x00DE
  97#define DEVADD8         0x00E0
  98#define DEVADD9         0x00E2
  99#define DEVADDA         0x00E4
 100#define D2FIFOSEL       0x00F0  /* for R-Car Gen2 */
 101#define D2FIFOCTR       0x00F2  /* for R-Car Gen2 */
 102#define D3FIFOSEL       0x00F4  /* for R-Car Gen2 */
 103#define D3FIFOCTR       0x00F6  /* for R-Car Gen2 */
 104#define SUSPMODE        0x0102  /* for RZ/A */
 105
 106/* SYSCFG */
 107#define SCKE    (1 << 10)       /* USB Module Clock Enable */
 108#define CNEN    (1 << 8)        /* Single-ended receiver operation Enable */
 109#define HSE     (1 << 7)        /* High-Speed Operation Enable */
 110#define DCFM    (1 << 6)        /* Controller Function Select */
 111#define DRPD    (1 << 5)        /* D+ Line/D- Line Resistance Control */
 112#define DPRPU   (1 << 4)        /* D+ Line Resistance Control */
 113#define USBE    (1 << 0)        /* USB Module Operation Enable */
 114#define UCKSEL  (1 << 2)        /* Clock Select for RZ/A1 */
 115#define UPLLE   (1 << 1)        /* USB PLL Enable for RZ/A1 */
 116
 117/* DVSTCTR */
 118#define EXTLP   (1 << 10)       /* Controls the EXTLP pin output state */
 119#define PWEN    (1 << 9)        /* Controls the PWEN pin output state */
 120#define USBRST  (1 << 6)        /* Bus Reset Output */
 121#define UACT    (1 << 4)        /* USB Bus Enable */
 122#define RHST    (0x7)           /* Reset Handshake */
 123#define  RHST_LOW_SPEED  1      /* Low-speed connection */
 124#define  RHST_FULL_SPEED 2      /* Full-speed connection */
 125#define  RHST_HIGH_SPEED 3      /* High-speed connection */
 126
 127/* CFIFOSEL */
 128#define DREQE   (1 << 12)       /* DMA Transfer Request Enable */
 129#define MBW_32  (0x2 << 10)     /* CFIFO Port Access Bit Width */
 130
 131/* CFIFOCTR */
 132#define BVAL    (1 << 15)       /* Buffer Memory Enable Flag */
 133#define BCLR    (1 << 14)       /* CPU buffer clear */
 134#define FRDY    (1 << 13)       /* FIFO Port Ready */
 135#define DTLN_MASK (0x0FFF)      /* Receive Data Length */
 136
 137/* INTENB0 */
 138#define VBSE    (1 << 15)       /* Enable IRQ VBUS_0 and VBUSIN_0 */
 139#define RSME    (1 << 14)       /* Enable IRQ Resume */
 140#define SOFE    (1 << 13)       /* Enable IRQ Frame Number Update */
 141#define DVSE    (1 << 12)       /* Enable IRQ Device State Transition */
 142#define CTRE    (1 << 11)       /* Enable IRQ Control Stage Transition */
 143#define BEMPE   (1 << 10)       /* Enable IRQ Buffer Empty */
 144#define NRDYE   (1 << 9)        /* Enable IRQ Buffer Not Ready Response */
 145#define BRDYE   (1 << 8)        /* Enable IRQ Buffer Ready */
 146
 147/* INTENB1 */
 148#define BCHGE   (1 << 14)       /* USB Bus Change Interrupt Enable */
 149#define DTCHE   (1 << 12)       /* Disconnection Detect Interrupt Enable */
 150#define ATTCHE  (1 << 11)       /* Connection Detect Interrupt Enable */
 151#define EOFERRE (1 << 6)        /* EOF Error Detect Interrupt Enable */
 152#define SIGNE   (1 << 5)        /* Setup Transaction Error Interrupt Enable */
 153#define SACKE   (1 << 4)        /* Setup Transaction ACK Interrupt Enable */
 154
 155/* INTSTS0 */
 156#define VBINT   (1 << 15)       /* VBUS0_0 and VBUS1_0 Interrupt Status */
 157#define DVST    (1 << 12)       /* Device State Transition Interrupt Status */
 158#define CTRT    (1 << 11)       /* Control Stage Interrupt Status */
 159#define BEMP    (1 << 10)       /* Buffer Empty Interrupt Status */
 160#define BRDY    (1 << 8)        /* Buffer Ready Interrupt Status */
 161#define VBSTS   (1 << 7)        /* VBUS_0 and VBUSIN_0 Input Status */
 162#define VALID   (1 << 3)        /* USB Request Receive */
 163
 164#define DVSQ_MASK               (0x7 << 4)      /* Device State */
 165#define  POWER_STATE            (0 << 4)
 166#define  DEFAULT_STATE          (1 << 4)
 167#define  ADDRESS_STATE          (2 << 4)
 168#define  CONFIGURATION_STATE    (3 << 4)
 169#define  SUSPENDED_STATE        (4 << 4)
 170
 171#define CTSQ_MASK               (0x7)   /* Control Transfer Stage */
 172#define  IDLE_SETUP_STAGE       0       /* Idle stage or setup stage */
 173#define  READ_DATA_STAGE        1       /* Control read data stage */
 174#define  READ_STATUS_STAGE      2       /* Control read status stage */
 175#define  WRITE_DATA_STAGE       3       /* Control write data stage */
 176#define  WRITE_STATUS_STAGE     4       /* Control write status stage */
 177#define  NODATA_STATUS_STAGE    5       /* Control write NoData status stage */
 178#define  SEQUENCE_ERROR         6       /* Control transfer sequence error */
 179
 180/* INTSTS1 */
 181#define OVRCR   (1 << 15) /* OVRCR Interrupt Status */
 182#define BCHG    (1 << 14) /* USB Bus Change Interrupt Status */
 183#define DTCH    (1 << 12) /* USB Disconnection Detect Interrupt Status */
 184#define ATTCH   (1 << 11) /* ATTCH Interrupt Status */
 185#define EOFERR  (1 << 6)  /* EOF Error Detect Interrupt Status */
 186#define SIGN    (1 << 5)  /* Setup Transaction Error Interrupt Status */
 187#define SACK    (1 << 4)  /* Setup Transaction ACK Response Interrupt Status */
 188
 189/* PIPECFG */
 190/* DCPCFG */
 191#define TYPE_NONE       (0 << 14)       /* Transfer Type */
 192#define TYPE_BULK       (1 << 14)
 193#define TYPE_INT        (2 << 14)
 194#define TYPE_ISO        (3 << 14)
 195#define BFRE            (1 << 10)       /* BRDY Interrupt Operation Spec. */
 196#define DBLB            (1 << 9)        /* Double Buffer Mode */
 197#define SHTNAK          (1 << 7)        /* Pipe Disable in Transfer End */
 198#define DIR_OUT         (1 << 4)        /* Transfer Direction */
 199
 200/* PIPEMAXP */
 201/* DCPMAXP */
 202#define DEVSEL_MASK     (0xF << 12)     /* Device Select */
 203#define DCP_MAXP_MASK   (0x7F)
 204#define PIPE_MAXP_MASK  (0x7FF)
 205
 206/* PIPEBUF */
 207#define BUFSIZE_SHIFT   10
 208#define BUFSIZE_MASK    (0x1F << BUFSIZE_SHIFT)
 209#define BUFNMB_MASK     (0xFF)
 210
 211/* PIPEnCTR */
 212/* DCPCTR */
 213#define BSTS            (1 << 15)       /* Buffer Status */
 214#define SUREQ           (1 << 14)       /* Sending SETUP Token */
 215#define INBUFM          (1 << 14)       /* (PIPEnCTR) Transfer Buffer Monitor */
 216#define CSSTS           (1 << 12)       /* CSSTS Status */
 217#define ACLRM           (1 << 9)        /* Buffer Auto-Clear Mode */
 218#define SQCLR           (1 << 8)        /* Toggle Bit Clear */
 219#define SQSET           (1 << 7)        /* Toggle Bit Set */
 220#define SQMON           (1 << 6)        /* Toggle Bit Check */
 221#define PBUSY           (1 << 5)        /* Pipe Busy */
 222#define PID_MASK        (0x3)           /* Response PID */
 223#define  PID_NAK        0
 224#define  PID_BUF        1
 225#define  PID_STALL10    2
 226#define  PID_STALL11    3
 227
 228#define CCPL            (1 << 2)        /* Control Transfer End Enable */
 229
 230/* PIPEnTRE */
 231#define TRENB           (1 << 9)        /* Transaction Counter Enable */
 232#define TRCLR           (1 << 8)        /* Transaction Counter Clear */
 233
 234/* FRMNUM */
 235#define FRNM_MASK       (0x7FF)
 236
 237/* DEVADDn */
 238#define UPPHUB(x)       (((x) & 0xF) << 11)     /* HUB Register */
 239#define HUBPORT(x)      (((x) & 0x7) << 8)      /* HUB Port for Target Device */
 240#define USBSPD(x)       (((x) & 0x3) << 6)      /* Device Transfer Rate */
 241#define USBSPD_SPEED_LOW        0x1
 242#define USBSPD_SPEED_FULL       0x2
 243#define USBSPD_SPEED_HIGH       0x3
 244
 245/* SUSPMODE */
 246#define SUSPM           (1 << 14)       /* SuspendM Control */
 247
 248/*
 249 *              struct
 250 */
 251struct usbhs_priv {
 252
 253        void __iomem *base;
 254        unsigned int irq;
 255        unsigned long irqflags;
 256
 257        const struct renesas_usbhs_platform_callback *pfunc;
 258        struct renesas_usbhs_driver_param       dparam;
 259
 260        struct delayed_work notify_hotplug_work;
 261        struct platform_device *pdev;
 262
 263        struct extcon_dev *edev;
 264
 265        spinlock_t              lock;
 266
 267        /*
 268         * module control
 269         */
 270        struct usbhs_mod_info mod_info;
 271
 272        /*
 273         * pipe control
 274         */
 275        struct usbhs_pipe_info pipe_info;
 276
 277        /*
 278         * fifo control
 279         */
 280        struct usbhs_fifo_info fifo_info;
 281
 282        struct phy *phy;
 283        struct reset_control *rsts;
 284        struct clk *clks[2];
 285};
 286
 287/*
 288 * common
 289 */
 290u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
 291void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
 292void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
 293
 294#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
 295#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
 296
 297int usbhs_get_id_as_gadget(struct platform_device *pdev);
 298
 299/*
 300 * sysconfig
 301 */
 302void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
 303void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
 304void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
 305void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);
 306
 307/*
 308 * usb request
 309 */
 310void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
 311void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
 312
 313/*
 314 * bus
 315 */
 316void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
 317void usbhs_bus_send_reset(struct usbhs_priv *priv);
 318int usbhs_bus_get_speed(struct usbhs_priv *priv);
 319int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
 320int usbhsc_schedule_notify_hotplug(struct platform_device *pdev);
 321
 322/*
 323 * frame
 324 */
 325int usbhs_frame_get_num(struct usbhs_priv *priv);
 326
 327/*
 328 * device config
 329 */
 330int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
 331                           u16 hubport, u16 speed);
 332
 333/*
 334 * interrupt functions
 335 */
 336void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit);
 337
 338/*
 339 * data
 340 */
 341struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
 342#define usbhs_get_dparam(priv, param)   (priv->dparam.param)
 343#define usbhs_priv_to_pdev(priv)        (priv->pdev)
 344#define usbhs_priv_to_dev(priv)         (&priv->pdev->dev)
 345#define usbhs_priv_to_lock(priv)        (&priv->lock)
 346
 347#endif /* RENESAS_USB_DRIVER_H */
 348