linux/drivers/video/fbdev/aty/aty128fb.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
   3 *  linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
   4 *
   5 *  Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
   6 *  Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
   7 *
   8 *                Ani Joshi / Jeff Garzik
   9 *                      - Code cleanup
  10 *
  11 *                Michel Danzer <michdaen@iiic.ethz.ch>
  12 *                      - 15/16 bit cleanup
  13 *                      - fix panning
  14 *
  15 *                Benjamin Herrenschmidt
  16 *                      - pmac-specific PM stuff
  17 *                      - various fixes & cleanups
  18 *
  19 *                Andreas Hundt <andi@convergence.de>
  20 *                      - FB_ACTIVATE fixes
  21 *
  22 *                Paul Mackerras <paulus@samba.org>
  23 *                      - Convert to new framebuffer API,
  24 *                        fix colormap setting at 16 bits/pixel (565)
  25 *
  26 *                Paul Mundt 
  27 *                      - PCI hotplug
  28 *
  29 *                Jon Smirl <jonsmirl@yahoo.com>
  30 *                      - PCI ID update
  31 *                      - replace ROM BIOS search
  32 *
  33 *  Based off of Geert's atyfb.c and vfb.c.
  34 *
  35 *  TODO:
  36 *              - monitor sensing (DDC)
  37 *              - virtual display
  38 *              - other platform support (only ppc/x86 supported)
  39 *              - hardware cursor support
  40 *
  41 *    Please cc: your patches to brad@neruo.com.
  42 */
  43
  44/*
  45 * A special note of gratitude to ATI's devrel for providing documentation,
  46 * example code and hardware. Thanks Nitya.     -atong and brad
  47 */
  48
  49
  50#include <linux/module.h>
  51#include <linux/moduleparam.h>
  52#include <linux/kernel.h>
  53#include <linux/errno.h>
  54#include <linux/string.h>
  55#include <linux/mm.h>
  56#include <linux/vmalloc.h>
  57#include <linux/delay.h>
  58#include <linux/interrupt.h>
  59#include <linux/uaccess.h>
  60#include <linux/fb.h>
  61#include <linux/init.h>
  62#include <linux/pci.h>
  63#include <linux/ioport.h>
  64#include <linux/console.h>
  65#include <linux/backlight.h>
  66#include <asm/io.h>
  67
  68#ifdef CONFIG_PPC_PMAC
  69#include <asm/machdep.h>
  70#include <asm/pmac_feature.h>
  71#include <asm/prom.h>
  72#include "../macmodes.h"
  73#endif
  74
  75#ifdef CONFIG_PMAC_BACKLIGHT
  76#include <asm/backlight.h>
  77#endif
  78
  79#ifdef CONFIG_BOOTX_TEXT
  80#include <asm/btext.h>
  81#endif /* CONFIG_BOOTX_TEXT */
  82
  83#include <video/aty128.h>
  84
  85/* Debug flag */
  86#undef DEBUG
  87
  88#ifdef DEBUG
  89#define DBG(fmt, args...) \
  90        printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
  91#else
  92#define DBG(fmt, args...)
  93#endif
  94
  95#ifndef CONFIG_PPC_PMAC
  96/* default mode */
  97static const struct fb_var_screeninfo default_var = {
  98        /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
  99        640, 480, 640, 480, 0, 0, 8, 0,
 100        {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 101        0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 102        0, FB_VMODE_NONINTERLACED
 103};
 104
 105#else /* CONFIG_PPC_PMAC */
 106/* default to 1024x768 at 75Hz on PPC - this will work
 107 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
 108static const struct fb_var_screeninfo default_var = {
 109        /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
 110        1024, 768, 1024, 768, 0, 0, 8, 0,
 111        {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 112        0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
 113        FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 114        FB_VMODE_NONINTERLACED
 115};
 116#endif /* CONFIG_PPC_PMAC */
 117
 118/* default modedb mode */
 119/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
 120static const struct fb_videomode defaultmode = {
 121        .refresh =      60,
 122        .xres =         640,
 123        .yres =         480,
 124        .pixclock =     39722,
 125        .left_margin =  48,
 126        .right_margin = 16,
 127        .upper_margin = 33,
 128        .lower_margin = 10,
 129        .hsync_len =    96,
 130        .vsync_len =    2,
 131        .sync =         0,
 132        .vmode =        FB_VMODE_NONINTERLACED
 133};
 134
 135/* Chip generations */
 136enum {
 137        rage_128,
 138        rage_128_pci,
 139        rage_128_pro,
 140        rage_128_pro_pci,
 141        rage_M3,
 142        rage_M3_pci,
 143        rage_M4,
 144        rage_128_ultra,
 145};
 146
 147/* Must match above enum */
 148static char * const r128_family[] = {
 149        "AGP",
 150        "PCI",
 151        "PRO AGP",
 152        "PRO PCI",
 153        "M3 AGP",
 154        "M3 PCI",
 155        "M4 AGP",
 156        "Ultra AGP",
 157};
 158
 159/*
 160 * PCI driver prototypes
 161 */
 162static int aty128_probe(struct pci_dev *pdev,
 163                               const struct pci_device_id *ent);
 164static void aty128_remove(struct pci_dev *pdev);
 165static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
 166static int aty128_pci_resume(struct pci_dev *pdev);
 167static int aty128_do_resume(struct pci_dev *pdev);
 168
 169/* supported Rage128 chipsets */
 170static const struct pci_device_id aty128_pci_tbl[] = {
 171        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
 172          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
 173        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
 174          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
 175        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
 176          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
 177        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
 178          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
 179        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
 180          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 181        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
 182          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 183        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
 184          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 185        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
 186          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 187        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
 188          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 189        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
 190          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 191        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
 192          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 193        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
 194          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 195        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
 196          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 197        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
 198          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 199        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
 200          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 201        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
 202          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 203        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
 204          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 205        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
 206          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 207        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
 208          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 209        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
 210          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 211        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
 212          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 213        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
 214          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
 215        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
 216          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 217        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
 218          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 219        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
 220          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 221        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
 222          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 223        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
 224          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 225        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
 226          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
 227        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
 228          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 229        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
 230          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 231        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
 232          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 233        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
 234          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 235        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
 236          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 237        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
 238          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 239        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
 240          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
 241        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
 242          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 243        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
 244          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 245        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
 246          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 247        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
 248          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 249        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
 250          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 251        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
 252          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
 253        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
 254          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 255        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
 256          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 257        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
 258          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 259        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
 260          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 261        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
 262          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 263        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
 264          PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
 265        { 0, }
 266};
 267
 268MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
 269
 270static struct pci_driver aty128fb_driver = {
 271        .name           = "aty128fb",
 272        .id_table       = aty128_pci_tbl,
 273        .probe          = aty128_probe,
 274        .remove         = aty128_remove,
 275        .suspend        = aty128_pci_suspend,
 276        .resume         = aty128_pci_resume,
 277};
 278
 279/* packed BIOS settings */
 280#ifndef CONFIG_PPC
 281typedef struct {
 282        u8 clock_chip_type;
 283        u8 struct_size;
 284        u8 accelerator_entry;
 285        u8 VGA_entry;
 286        u16 VGA_table_offset;
 287        u16 POST_table_offset;
 288        u16 XCLK;
 289        u16 MCLK;
 290        u8 num_PLL_blocks;
 291        u8 size_PLL_blocks;
 292        u16 PCLK_ref_freq;
 293        u16 PCLK_ref_divider;
 294        u32 PCLK_min_freq;
 295        u32 PCLK_max_freq;
 296        u16 MCLK_ref_freq;
 297        u16 MCLK_ref_divider;
 298        u32 MCLK_min_freq;
 299        u32 MCLK_max_freq;
 300        u16 XCLK_ref_freq;
 301        u16 XCLK_ref_divider;
 302        u32 XCLK_min_freq;
 303        u32 XCLK_max_freq;
 304} __attribute__ ((packed)) PLL_BLOCK;
 305#endif /* !CONFIG_PPC */
 306
 307/* onboard memory information */
 308struct aty128_meminfo {
 309        u8 ML;
 310        u8 MB;
 311        u8 Trcd;
 312        u8 Trp;
 313        u8 Twr;
 314        u8 CL;
 315        u8 Tr2w;
 316        u8 LoopLatency;
 317        u8 DspOn;
 318        u8 Rloop;
 319        const char *name;
 320};
 321
 322/* various memory configurations */
 323static const struct aty128_meminfo sdr_128 = {
 324        .ML = 4,
 325        .MB = 4,
 326        .Trcd = 3,
 327        .Trp = 3,
 328        .Twr = 1,
 329        .CL = 3,
 330        .Tr2w = 1,
 331        .LoopLatency = 16,
 332        .DspOn = 30,
 333        .Rloop = 16,
 334        .name = "128-bit SDR SGRAM (1:1)",
 335};
 336
 337static const struct aty128_meminfo sdr_64 = {
 338        .ML = 4,
 339        .MB = 8,
 340        .Trcd = 3,
 341        .Trp = 3,
 342        .Twr = 1,
 343        .CL = 3,
 344        .Tr2w = 1,
 345        .LoopLatency = 17,
 346        .DspOn = 46,
 347        .Rloop = 17,
 348        .name = "64-bit SDR SGRAM (1:1)",
 349};
 350
 351static const struct aty128_meminfo sdr_sgram = {
 352        .ML = 4,
 353        .MB = 4,
 354        .Trcd = 1,
 355        .Trp = 2,
 356        .Twr = 1,
 357        .CL = 2,
 358        .Tr2w = 1,
 359        .LoopLatency = 16,
 360        .DspOn = 24,
 361        .Rloop = 16,
 362        .name = "64-bit SDR SGRAM (2:1)",
 363};
 364
 365static const struct aty128_meminfo ddr_sgram = {
 366        .ML = 4,
 367        .MB = 4,
 368        .Trcd = 3,
 369        .Trp = 3,
 370        .Twr = 2,
 371        .CL = 3,
 372        .Tr2w = 1,
 373        .LoopLatency = 16,
 374        .DspOn = 31,
 375        .Rloop = 16,
 376        .name = "64-bit DDR SGRAM",
 377};
 378
 379static const struct fb_fix_screeninfo aty128fb_fix = {
 380        .id             = "ATY Rage128",
 381        .type           = FB_TYPE_PACKED_PIXELS,
 382        .visual         = FB_VISUAL_PSEUDOCOLOR,
 383        .xpanstep       = 8,
 384        .ypanstep       = 1,
 385        .mmio_len       = 0x2000,
 386        .accel          = FB_ACCEL_ATI_RAGE128,
 387};
 388
 389static char *mode_option = NULL;
 390
 391#ifdef CONFIG_PPC_PMAC
 392static int default_vmode = VMODE_1024_768_60;
 393static int default_cmode = CMODE_8;
 394#endif
 395
 396static int default_crt_on = 0;
 397static int default_lcd_on = 1;
 398static bool mtrr = true;
 399
 400#ifdef CONFIG_FB_ATY128_BACKLIGHT
 401#ifdef CONFIG_PMAC_BACKLIGHT
 402static int backlight = 1;
 403#else
 404static int backlight = 0;
 405#endif
 406#endif
 407
 408/* PLL constants */
 409struct aty128_constants {
 410        u32 ref_clk;
 411        u32 ppll_min;
 412        u32 ppll_max;
 413        u32 ref_divider;
 414        u32 xclk;
 415        u32 fifo_width;
 416        u32 fifo_depth;
 417};
 418
 419struct aty128_crtc {
 420        u32 gen_cntl;
 421        u32 h_total, h_sync_strt_wid;
 422        u32 v_total, v_sync_strt_wid;
 423        u32 pitch;
 424        u32 offset, offset_cntl;
 425        u32 xoffset, yoffset;
 426        u32 vxres, vyres;
 427        u32 depth, bpp;
 428};
 429
 430struct aty128_pll {
 431        u32 post_divider;
 432        u32 feedback_divider;
 433        u32 vclk;
 434};
 435
 436struct aty128_ddafifo {
 437        u32 dda_config;
 438        u32 dda_on_off;
 439};
 440
 441/* register values for a specific mode */
 442struct aty128fb_par {
 443        struct aty128_crtc crtc;
 444        struct aty128_pll pll;
 445        struct aty128_ddafifo fifo_reg;
 446        u32 accel_flags;
 447        struct aty128_constants constants;  /* PLL and others      */
 448        void __iomem *regbase;              /* remapped mmio       */
 449        u32 vram_size;                      /* onboard video ram   */
 450        int chip_gen;
 451        const struct aty128_meminfo *mem;   /* onboard mem info    */
 452        int wc_cookie;
 453        int blitter_may_be_busy;
 454        int fifo_slots;                 /* free slots in FIFO (64 max) */
 455
 456        int crt_on, lcd_on;
 457        struct pci_dev *pdev;
 458        struct fb_info *next;
 459        int     asleep;
 460        int     lock_blank;
 461
 462        u8      red[32];                /* see aty128fb_setcolreg */
 463        u8      green[64];
 464        u8      blue[32];
 465        u32     pseudo_palette[16];     /* used for TRUECOLOR */
 466};
 467
 468
 469#define round_div(n, d) ((n+(d/2))/d)
 470
 471static int aty128fb_check_var(struct fb_var_screeninfo *var,
 472                              struct fb_info *info);
 473static int aty128fb_set_par(struct fb_info *info);
 474static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 475                              u_int transp, struct fb_info *info);
 476static int aty128fb_pan_display(struct fb_var_screeninfo *var,
 477                           struct fb_info *fb);
 478static int aty128fb_blank(int blank, struct fb_info *fb);
 479static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
 480static int aty128fb_sync(struct fb_info *info);
 481
 482    /*
 483     *  Internal routines
 484     */
 485
 486static int aty128_encode_var(struct fb_var_screeninfo *var,
 487                             const struct aty128fb_par *par);
 488static int aty128_decode_var(struct fb_var_screeninfo *var,
 489                             struct aty128fb_par *par);
 490static void aty128_timings(struct aty128fb_par *par);
 491static void aty128_init_engine(struct aty128fb_par *par);
 492static void aty128_reset_engine(const struct aty128fb_par *par);
 493static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
 494static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
 495static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
 496static void wait_for_idle(struct aty128fb_par *par);
 497static u32 depth_to_dst(u32 depth);
 498
 499#ifdef CONFIG_FB_ATY128_BACKLIGHT
 500static void aty128_bl_set_power(struct fb_info *info, int power);
 501#endif
 502
 503#define BIOS_IN8(v)     (readb(bios + (v)))
 504#define BIOS_IN16(v)    (readb(bios + (v)) | \
 505                          (readb(bios + (v) + 1) << 8))
 506#define BIOS_IN32(v)    (readb(bios + (v)) | \
 507                          (readb(bios + (v) + 1) << 8) | \
 508                          (readb(bios + (v) + 2) << 16) | \
 509                          (readb(bios + (v) + 3) << 24))
 510
 511
 512static struct fb_ops aty128fb_ops = {
 513        .owner          = THIS_MODULE,
 514        .fb_check_var   = aty128fb_check_var,
 515        .fb_set_par     = aty128fb_set_par,
 516        .fb_setcolreg   = aty128fb_setcolreg,
 517        .fb_pan_display = aty128fb_pan_display,
 518        .fb_blank       = aty128fb_blank,
 519        .fb_ioctl       = aty128fb_ioctl,
 520        .fb_sync        = aty128fb_sync,
 521        .fb_fillrect    = cfb_fillrect,
 522        .fb_copyarea    = cfb_copyarea,
 523        .fb_imageblit   = cfb_imageblit,
 524};
 525
 526    /*
 527     * Functions to read from/write to the mmio registers
 528     *  - endian conversions may possibly be avoided by
 529     *    using the other register aperture. TODO.
 530     */
 531static inline u32 _aty_ld_le32(volatile unsigned int regindex, 
 532                               const struct aty128fb_par *par)
 533{
 534        return readl (par->regbase + regindex);
 535}
 536
 537static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 
 538                                const struct aty128fb_par *par)
 539{
 540        writel (val, par->regbase + regindex);
 541}
 542
 543static inline u8 _aty_ld_8(unsigned int regindex,
 544                           const struct aty128fb_par *par)
 545{
 546        return readb (par->regbase + regindex);
 547}
 548
 549static inline void _aty_st_8(unsigned int regindex, u8 val,
 550                             const struct aty128fb_par *par)
 551{
 552        writeb (val, par->regbase + regindex);
 553}
 554
 555#define aty_ld_le32(regindex)           _aty_ld_le32(regindex, par)
 556#define aty_st_le32(regindex, val)      _aty_st_le32(regindex, val, par)
 557#define aty_ld_8(regindex)              _aty_ld_8(regindex, par)
 558#define aty_st_8(regindex, val)         _aty_st_8(regindex, val, par)
 559
 560    /*
 561     * Functions to read from/write to the pll registers
 562     */
 563
 564#define aty_ld_pll(pll_index)           _aty_ld_pll(pll_index, par)
 565#define aty_st_pll(pll_index, val)      _aty_st_pll(pll_index, val, par)
 566
 567
 568static u32 _aty_ld_pll(unsigned int pll_index,
 569                       const struct aty128fb_par *par)
 570{       
 571        aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
 572        return aty_ld_le32(CLOCK_CNTL_DATA);
 573}
 574
 575    
 576static void _aty_st_pll(unsigned int pll_index, u32 val,
 577                        const struct aty128fb_par *par)
 578{
 579        aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
 580        aty_st_le32(CLOCK_CNTL_DATA, val);
 581}
 582
 583
 584/* return true when the PLL has completed an atomic update */
 585static int aty_pll_readupdate(const struct aty128fb_par *par)
 586{
 587        return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
 588}
 589
 590
 591static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
 592{
 593        unsigned long timeout = jiffies + HZ/100; // should be more than enough
 594        int reset = 1;
 595
 596        while (time_before(jiffies, timeout))
 597                if (aty_pll_readupdate(par)) {
 598                        reset = 0;
 599                        break;
 600                }
 601
 602        if (reset)      /* reset engine?? */
 603                printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
 604}
 605
 606
 607/* tell PLL to update */
 608static void aty_pll_writeupdate(const struct aty128fb_par *par)
 609{
 610        aty_pll_wait_readupdate(par);
 611
 612        aty_st_pll(PPLL_REF_DIV,
 613                   aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
 614}
 615
 616
 617/* write to the scratch register to test r/w functionality */
 618static int register_test(const struct aty128fb_par *par)
 619{
 620        u32 val;
 621        int flag = 0;
 622
 623        val = aty_ld_le32(BIOS_0_SCRATCH);
 624
 625        aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
 626        if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
 627                aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
 628
 629                if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
 630                        flag = 1; 
 631        }
 632
 633        aty_st_le32(BIOS_0_SCRATCH, val);       // restore value
 634        return flag;
 635}
 636
 637
 638/*
 639 * Accelerator engine functions
 640 */
 641static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
 642{
 643        int i;
 644
 645        for (;;) {
 646                for (i = 0; i < 2000000; i++) {
 647                        par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
 648                        if (par->fifo_slots >= entries)
 649                                return;
 650                }
 651                aty128_reset_engine(par);
 652        }
 653}
 654
 655
 656static void wait_for_idle(struct aty128fb_par *par)
 657{
 658        int i;
 659
 660        do_wait_for_fifo(64, par);
 661
 662        for (;;) {
 663                for (i = 0; i < 2000000; i++) {
 664                        if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
 665                                aty128_flush_pixel_cache(par);
 666                                par->blitter_may_be_busy = 0;
 667                                return;
 668                        }
 669                }
 670                aty128_reset_engine(par);
 671        }
 672}
 673
 674
 675static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
 676{
 677        if (par->fifo_slots < entries)
 678                do_wait_for_fifo(64, par);
 679        par->fifo_slots -= entries;
 680}
 681
 682
 683static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
 684{
 685        int i;
 686        u32 tmp;
 687
 688        tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
 689        tmp &= ~(0x00ff);
 690        tmp |= 0x00ff;
 691        aty_st_le32(PC_NGUI_CTLSTAT, tmp);
 692
 693        for (i = 0; i < 2000000; i++)
 694                if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
 695                        break;
 696}
 697
 698
 699static void aty128_reset_engine(const struct aty128fb_par *par)
 700{
 701        u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
 702
 703        aty128_flush_pixel_cache(par);
 704
 705        clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
 706        mclk_cntl = aty_ld_pll(MCLK_CNTL);
 707
 708        aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
 709
 710        gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
 711        aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
 712        aty_ld_le32(GEN_RESET_CNTL);
 713        aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
 714        aty_ld_le32(GEN_RESET_CNTL);
 715
 716        aty_st_pll(MCLK_CNTL, mclk_cntl);
 717        aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
 718        aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
 719
 720        /* use old pio mode */
 721        aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
 722
 723        DBG("engine reset");
 724}
 725
 726
 727static void aty128_init_engine(struct aty128fb_par *par)
 728{
 729        u32 pitch_value;
 730
 731        wait_for_idle(par);
 732
 733        /* 3D scaler not spoken here */
 734        wait_for_fifo(1, par);
 735        aty_st_le32(SCALE_3D_CNTL, 0x00000000);
 736
 737        aty128_reset_engine(par);
 738
 739        pitch_value = par->crtc.pitch;
 740        if (par->crtc.bpp == 24) {
 741                pitch_value = pitch_value * 3;
 742        }
 743
 744        wait_for_fifo(4, par);
 745        /* setup engine offset registers */
 746        aty_st_le32(DEFAULT_OFFSET, 0x00000000);
 747
 748        /* setup engine pitch registers */
 749        aty_st_le32(DEFAULT_PITCH, pitch_value);
 750
 751        /* set the default scissor register to max dimensions */
 752        aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
 753
 754        /* set the drawing controls registers */
 755        aty_st_le32(DP_GUI_MASTER_CNTL,
 756                    GMC_SRC_PITCH_OFFSET_DEFAULT                |
 757                    GMC_DST_PITCH_OFFSET_DEFAULT                |
 758                    GMC_SRC_CLIP_DEFAULT                        |
 759                    GMC_DST_CLIP_DEFAULT                        |
 760                    GMC_BRUSH_SOLIDCOLOR                        |
 761                    (depth_to_dst(par->crtc.depth) << 8)        |
 762                    GMC_SRC_DSTCOLOR                    |
 763                    GMC_BYTE_ORDER_MSB_TO_LSB           |
 764                    GMC_DP_CONVERSION_TEMP_6500         |
 765                    ROP3_PATCOPY                                |
 766                    GMC_DP_SRC_RECT                             |
 767                    GMC_3D_FCN_EN_CLR                   |
 768                    GMC_DST_CLR_CMP_FCN_CLEAR           |
 769                    GMC_AUX_CLIP_CLEAR                  |
 770                    GMC_WRITE_MASK_SET);
 771
 772        wait_for_fifo(8, par);
 773        /* clear the line drawing registers */
 774        aty_st_le32(DST_BRES_ERR, 0);
 775        aty_st_le32(DST_BRES_INC, 0);
 776        aty_st_le32(DST_BRES_DEC, 0);
 777
 778        /* set brush color registers */
 779        aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
 780        aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
 781
 782        /* set source color registers */
 783        aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF);   /* white */
 784        aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000);   /* black */
 785
 786        /* default write mask */
 787        aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
 788
 789        /* Wait for all the writes to be completed before returning */
 790        wait_for_idle(par);
 791}
 792
 793
 794/* convert depth values to their register representation */
 795static u32 depth_to_dst(u32 depth)
 796{
 797        if (depth <= 8)
 798                return DST_8BPP;
 799        else if (depth <= 15)
 800                return DST_15BPP;
 801        else if (depth == 16)
 802                return DST_16BPP;
 803        else if (depth <= 24)
 804                return DST_24BPP;
 805        else if (depth <= 32)
 806                return DST_32BPP;
 807
 808        return -EINVAL;
 809}
 810
 811/*
 812 * PLL informations retreival
 813 */
 814
 815
 816#ifndef __sparc__
 817static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
 818                                    struct pci_dev *dev)
 819{
 820        u16 dptr;
 821        u8 rom_type;
 822        void __iomem *bios;
 823        size_t rom_size;
 824
 825        /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
 826        unsigned int temp;
 827        temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
 828        temp &= 0x00ffffffu;
 829        temp |= 0x04 << 24;
 830        aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
 831        temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
 832
 833        bios = pci_map_rom(dev, &rom_size);
 834
 835        if (!bios) {
 836                printk(KERN_ERR "aty128fb: ROM failed to map\n");
 837                return NULL;
 838        }
 839
 840        /* Very simple test to make sure it appeared */
 841        if (BIOS_IN16(0) != 0xaa55) {
 842                printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
 843                        " be 0xaa55\n", BIOS_IN16(0));
 844                goto failed;
 845        }
 846
 847        /* Look for the PCI data to check the ROM type */
 848        dptr = BIOS_IN16(0x18);
 849
 850        /* Check the PCI data signature. If it's wrong, we still assume a normal
 851         * x86 ROM for now, until I've verified this works everywhere.
 852         * The goal here is more to phase out Open Firmware images.
 853         *
 854         * Currently, we only look at the first PCI data, we could iteratre and
 855         * deal with them all, and we should use fb_bios_start relative to start
 856         * of image and not relative start of ROM, but so far, I never found a
 857         * dual-image ATI card.
 858         *
 859         * typedef struct {
 860         *      u32     signature;      + 0x00
 861         *      u16     vendor;         + 0x04
 862         *      u16     device;         + 0x06
 863         *      u16     reserved_1;     + 0x08
 864         *      u16     dlen;           + 0x0a
 865         *      u8      drevision;      + 0x0c
 866         *      u8      class_hi;       + 0x0d
 867         *      u16     class_lo;       + 0x0e
 868         *      u16     ilen;           + 0x10
 869         *      u16     irevision;      + 0x12
 870         *      u8      type;           + 0x14
 871         *      u8      indicator;      + 0x15
 872         *      u16     reserved_2;     + 0x16
 873         * } pci_data_t;
 874         */
 875        if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
 876                printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
 877                       BIOS_IN32(dptr));
 878                goto anyway;
 879        }
 880        rom_type = BIOS_IN8(dptr + 0x14);
 881        switch(rom_type) {
 882        case 0:
 883                printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
 884                break;
 885        case 1:
 886                printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
 887                goto failed;
 888        case 2:
 889                printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
 890                goto failed;
 891        default:
 892                printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
 893                       rom_type);
 894                goto failed;
 895        }
 896 anyway:
 897        return bios;
 898
 899 failed:
 900        pci_unmap_rom(dev, bios);
 901        return NULL;
 902}
 903
 904static void aty128_get_pllinfo(struct aty128fb_par *par,
 905                               unsigned char __iomem *bios)
 906{
 907        unsigned int bios_hdr;
 908        unsigned int bios_pll;
 909
 910        bios_hdr = BIOS_IN16(0x48);
 911        bios_pll = BIOS_IN16(bios_hdr + 0x30);
 912        
 913        par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
 914        par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
 915        par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
 916        par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
 917        par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
 918
 919        DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
 920                        par->constants.ppll_max, par->constants.ppll_min,
 921                        par->constants.xclk, par->constants.ref_divider,
 922                        par->constants.ref_clk);
 923
 924}           
 925
 926#ifdef CONFIG_X86
 927static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
 928{
 929        /* I simplified this code as we used to miss the signatures in
 930         * a lot of case. It's now closer to XFree, we just don't check
 931         * for signatures at all... Something better will have to be done
 932         * if we end up having conflicts
 933         */
 934        u32  segstart;
 935        unsigned char __iomem *rom_base = NULL;
 936                                                
 937        for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
 938                rom_base = ioremap(segstart, 0x10000);
 939                if (rom_base == NULL)
 940                        return NULL;
 941                if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
 942                        break;
 943                iounmap(rom_base);
 944                rom_base = NULL;
 945        }
 946        return rom_base;
 947}
 948#endif
 949#endif /* ndef(__sparc__) */
 950
 951/* fill in known card constants if pll_block is not available */
 952static void aty128_timings(struct aty128fb_par *par)
 953{
 954#ifdef CONFIG_PPC
 955        /* instead of a table lookup, assume OF has properly
 956         * setup the PLL registers and use their values
 957         * to set the XCLK values and reference divider values */
 958
 959        u32 x_mpll_ref_fb_div;
 960        u32 xclk_cntl;
 961        u32 Nx, M;
 962        unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
 963#endif
 964
 965        if (!par->constants.ref_clk)
 966                par->constants.ref_clk = 2950;
 967
 968#ifdef CONFIG_PPC
 969        x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
 970        xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
 971        Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
 972        M  = x_mpll_ref_fb_div & 0x0000ff;
 973
 974        par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
 975                                        (M * PostDivSet[xclk_cntl]));
 976
 977        par->constants.ref_divider =
 978                aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
 979#endif
 980
 981        if (!par->constants.ref_divider) {
 982                par->constants.ref_divider = 0x3b;
 983
 984                aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
 985                aty_pll_writeupdate(par);
 986        }
 987        aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
 988        aty_pll_writeupdate(par);
 989
 990        /* from documentation */
 991        if (!par->constants.ppll_min)
 992                par->constants.ppll_min = 12500;
 993        if (!par->constants.ppll_max)
 994                par->constants.ppll_max = 25000;    /* 23000 on some cards? */
 995        if (!par->constants.xclk)
 996                par->constants.xclk = 0x1d4d;        /* same as mclk */
 997
 998        par->constants.fifo_width = 128;
 999        par->constants.fifo_depth = 32;
1000
1001        switch (aty_ld_le32(MEM_CNTL) & 0x3) {
1002        case 0:
1003                par->mem = &sdr_128;
1004                break;
1005        case 1:
1006                par->mem = &sdr_sgram;
1007                break;
1008        case 2:
1009                par->mem = &ddr_sgram;
1010                break;
1011        default:
1012                par->mem = &sdr_sgram;
1013        }
1014}
1015
1016
1017
1018/*
1019 * CRTC programming
1020 */
1021
1022/* Program the CRTC registers */
1023static void aty128_set_crtc(const struct aty128_crtc *crtc,
1024                            const struct aty128fb_par *par)
1025{
1026        aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
1027        aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
1028        aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
1029        aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
1030        aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
1031        aty_st_le32(CRTC_PITCH, crtc->pitch);
1032        aty_st_le32(CRTC_OFFSET, crtc->offset);
1033        aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1034        /* Disable ATOMIC updating.  Is this the right place? */
1035        aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1036}
1037
1038
1039static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1040                              struct aty128_crtc *crtc,
1041                              const struct aty128fb_par *par)
1042{
1043        u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1044        u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1045        u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1046        u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1047        u32 depth, bytpp;
1048        u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1049
1050        /* input */
1051        xres = var->xres;
1052        yres = var->yres;
1053        vxres   = var->xres_virtual;
1054        vyres   = var->yres_virtual;
1055        xoffset = var->xoffset;
1056        yoffset = var->yoffset;
1057        bpp   = var->bits_per_pixel;
1058        left  = var->left_margin;
1059        right = var->right_margin;
1060        upper = var->upper_margin;
1061        lower = var->lower_margin;
1062        hslen = var->hsync_len;
1063        vslen = var->vsync_len;
1064        sync  = var->sync;
1065        vmode = var->vmode;
1066
1067        if (bpp != 16)
1068                depth = bpp;
1069        else
1070                depth = (var->green.length == 6) ? 16 : 15;
1071
1072        /* check for mode eligibility
1073         * accept only non interlaced modes */
1074        if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1075                return -EINVAL;
1076
1077        /* convert (and round up) and validate */
1078        xres = (xres + 7) & ~7;
1079        xoffset = (xoffset + 7) & ~7;
1080
1081        if (vxres < xres + xoffset)
1082                vxres = xres + xoffset;
1083
1084        if (vyres < yres + yoffset)
1085                vyres = yres + yoffset;
1086
1087        /* convert depth into ATI register depth */
1088        dst = depth_to_dst(depth);
1089
1090        if (dst == -EINVAL) {
1091                printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1092                return -EINVAL;
1093        }
1094
1095        /* convert register depth to bytes per pixel */
1096        bytpp = mode_bytpp[dst];
1097
1098        /* make sure there is enough video ram for the mode */
1099        if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1100                printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1101                return -EINVAL;
1102        }
1103
1104        h_disp = (xres >> 3) - 1;
1105        h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1106
1107        v_disp = yres - 1;
1108        v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1109
1110        /* check to make sure h_total and v_total are in range */
1111        if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1112                printk(KERN_ERR "aty128fb: invalid width ranges\n");
1113                return -EINVAL;
1114        }
1115
1116        h_sync_wid = (hslen + 7) >> 3;
1117        if (h_sync_wid == 0)
1118                h_sync_wid = 1;
1119        else if (h_sync_wid > 0x3f)        /* 0x3f = max hwidth */
1120                h_sync_wid = 0x3f;
1121
1122        h_sync_strt = (h_disp << 3) + right;
1123
1124        v_sync_wid = vslen;
1125        if (v_sync_wid == 0)
1126                v_sync_wid = 1;
1127        else if (v_sync_wid > 0x1f)        /* 0x1f = max vwidth */
1128                v_sync_wid = 0x1f;
1129    
1130        v_sync_strt = v_disp + lower;
1131
1132        h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1133        v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1134    
1135        c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1136
1137        crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1138
1139        crtc->h_total = h_total | (h_disp << 16);
1140        crtc->v_total = v_total | (v_disp << 16);
1141
1142        crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1143                (h_sync_pol << 23);
1144        crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1145                (v_sync_pol << 23);
1146
1147        crtc->pitch = vxres >> 3;
1148
1149        crtc->offset = 0;
1150
1151        if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1152                crtc->offset_cntl = 0x00010000;
1153        else
1154                crtc->offset_cntl = 0;
1155
1156        crtc->vxres = vxres;
1157        crtc->vyres = vyres;
1158        crtc->xoffset = xoffset;
1159        crtc->yoffset = yoffset;
1160        crtc->depth = depth;
1161        crtc->bpp = bpp;
1162
1163        return 0;
1164}
1165
1166
1167static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1168{
1169
1170        /* fill in pixel info */
1171        var->red.msb_right = 0;
1172        var->green.msb_right = 0;
1173        var->blue.offset = 0;
1174        var->blue.msb_right = 0;
1175        var->transp.offset = 0;
1176        var->transp.length = 0;
1177        var->transp.msb_right = 0;
1178        switch (pix_width) {
1179        case CRTC_PIX_WIDTH_8BPP:
1180                var->bits_per_pixel = 8;
1181                var->red.offset = 0;
1182                var->red.length = 8;
1183                var->green.offset = 0;
1184                var->green.length = 8;
1185                var->blue.length = 8;
1186                break;
1187        case CRTC_PIX_WIDTH_15BPP:
1188                var->bits_per_pixel = 16;
1189                var->red.offset = 10;
1190                var->red.length = 5;
1191                var->green.offset = 5;
1192                var->green.length = 5;
1193                var->blue.length = 5;
1194                break;
1195        case CRTC_PIX_WIDTH_16BPP:
1196                var->bits_per_pixel = 16;
1197                var->red.offset = 11;
1198                var->red.length = 5;
1199                var->green.offset = 5;
1200                var->green.length = 6;
1201                var->blue.length = 5;
1202                break;
1203        case CRTC_PIX_WIDTH_24BPP:
1204                var->bits_per_pixel = 24;
1205                var->red.offset = 16;
1206                var->red.length = 8;
1207                var->green.offset = 8;
1208                var->green.length = 8;
1209                var->blue.length = 8;
1210                break;
1211        case CRTC_PIX_WIDTH_32BPP:
1212                var->bits_per_pixel = 32;
1213                var->red.offset = 16;
1214                var->red.length = 8;
1215                var->green.offset = 8;
1216                var->green.length = 8;
1217                var->blue.length = 8;
1218                var->transp.offset = 24;
1219                var->transp.length = 8;
1220                break;
1221        default:
1222                printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1223                return -EINVAL;
1224        }
1225
1226        return 0;
1227}
1228
1229
1230static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1231                              struct fb_var_screeninfo *var)
1232{
1233        u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1234        u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1235        u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1236        u32 pix_width;
1237
1238        /* fun with masking */
1239        h_total     = crtc->h_total & 0x1ff;
1240        h_disp      = (crtc->h_total >> 16) & 0xff;
1241        h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1242        h_sync_dly  = crtc->h_sync_strt_wid & 0x7;
1243        h_sync_wid  = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1244        h_sync_pol  = (crtc->h_sync_strt_wid >> 23) & 0x1;
1245        v_total     = crtc->v_total & 0x7ff;
1246        v_disp      = (crtc->v_total >> 16) & 0x7ff;
1247        v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1248        v_sync_wid  = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1249        v_sync_pol  = (crtc->v_sync_strt_wid >> 23) & 0x1;
1250        c_sync      = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1251        pix_width   = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1252
1253        /* do conversions */
1254        xres  = (h_disp + 1) << 3;
1255        yres  = v_disp + 1;
1256        left  = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1257        right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1258        hslen = h_sync_wid << 3;
1259        upper = v_total - v_sync_strt - v_sync_wid;
1260        lower = v_sync_strt - v_disp;
1261        vslen = v_sync_wid;
1262        sync  = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1263                (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1264                (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1265
1266        aty128_pix_width_to_var(pix_width, var);
1267
1268        var->xres = xres;
1269        var->yres = yres;
1270        var->xres_virtual = crtc->vxres;
1271        var->yres_virtual = crtc->vyres;
1272        var->xoffset = crtc->xoffset;
1273        var->yoffset = crtc->yoffset;
1274        var->left_margin  = left;
1275        var->right_margin = right;
1276        var->upper_margin = upper;
1277        var->lower_margin = lower;
1278        var->hsync_len = hslen;
1279        var->vsync_len = vslen;
1280        var->sync  = sync;
1281        var->vmode = FB_VMODE_NONINTERLACED;
1282
1283        return 0;
1284}
1285
1286static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1287{
1288        if (on) {
1289                aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1290                            CRT_CRTC_ON);
1291                aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1292                            DAC_PALETTE2_SNOOP_EN));
1293        } else
1294                aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1295                            ~CRT_CRTC_ON);
1296}
1297
1298static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1299{
1300        u32 reg;
1301#ifdef CONFIG_FB_ATY128_BACKLIGHT
1302        struct fb_info *info = pci_get_drvdata(par->pdev);
1303#endif
1304
1305        if (on) {
1306                reg = aty_ld_le32(LVDS_GEN_CNTL);
1307                reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1308                reg &= ~LVDS_DISPLAY_DIS;
1309                aty_st_le32(LVDS_GEN_CNTL, reg);
1310#ifdef CONFIG_FB_ATY128_BACKLIGHT
1311                aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1312#endif  
1313        } else {
1314#ifdef CONFIG_FB_ATY128_BACKLIGHT
1315                aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1316#endif  
1317                reg = aty_ld_le32(LVDS_GEN_CNTL);
1318                reg |= LVDS_DISPLAY_DIS;
1319                aty_st_le32(LVDS_GEN_CNTL, reg);
1320                mdelay(100);
1321                reg &= ~(LVDS_ON /*| LVDS_EN*/);
1322                aty_st_le32(LVDS_GEN_CNTL, reg);
1323        }
1324}
1325
1326static void aty128_set_pll(struct aty128_pll *pll,
1327                           const struct aty128fb_par *par)
1328{
1329        u32 div3;
1330
1331        unsigned char post_conv[] =     /* register values for post dividers */
1332        { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1333
1334        /* select PPLL_DIV_3 */
1335        aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1336
1337        /* reset PLL */
1338        aty_st_pll(PPLL_CNTL,
1339                   aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1340
1341        /* write the reference divider */
1342        aty_pll_wait_readupdate(par);
1343        aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1344        aty_pll_writeupdate(par);
1345
1346        div3 = aty_ld_pll(PPLL_DIV_3);
1347        div3 &= ~PPLL_FB3_DIV_MASK;
1348        div3 |= pll->feedback_divider;
1349        div3 &= ~PPLL_POST3_DIV_MASK;
1350        div3 |= post_conv[pll->post_divider] << 16;
1351
1352        /* write feedback and post dividers */
1353        aty_pll_wait_readupdate(par);
1354        aty_st_pll(PPLL_DIV_3, div3);
1355        aty_pll_writeupdate(par);
1356
1357        aty_pll_wait_readupdate(par);
1358        aty_st_pll(HTOTAL_CNTL, 0);     /* no horiz crtc adjustment */
1359        aty_pll_writeupdate(par);
1360
1361        /* clear the reset, just in case */
1362        aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1363}
1364
1365
1366static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1367                             const struct aty128fb_par *par)
1368{
1369        const struct aty128_constants c = par->constants;
1370        unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1371        u32 output_freq;
1372        u32 vclk;        /* in .01 MHz */
1373        int i = 0;
1374        u32 n, d;
1375
1376        vclk = 100000000 / period_in_ps;        /* convert units to 10 kHz */
1377
1378        /* adjust pixel clock if necessary */
1379        if (vclk > c.ppll_max)
1380                vclk = c.ppll_max;
1381        if (vclk * 12 < c.ppll_min)
1382                vclk = c.ppll_min/12;
1383
1384        /* now, find an acceptable divider */
1385        for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1386                output_freq = post_dividers[i] * vclk;
1387                if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1388                        pll->post_divider = post_dividers[i];
1389                        break;
1390                }
1391        }
1392
1393        if (i == ARRAY_SIZE(post_dividers))
1394                return -EINVAL;
1395
1396        /* calculate feedback divider */
1397        n = c.ref_divider * output_freq;
1398        d = c.ref_clk;
1399
1400        pll->feedback_divider = round_div(n, d);
1401        pll->vclk = vclk;
1402
1403        DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1404            "vclk_per: %d\n", pll->post_divider,
1405            pll->feedback_divider, vclk, output_freq,
1406            c.ref_divider, period_in_ps);
1407
1408        return 0;
1409}
1410
1411
1412static int aty128_pll_to_var(const struct aty128_pll *pll,
1413                             struct fb_var_screeninfo *var)
1414{
1415        var->pixclock = 100000000 / pll->vclk;
1416
1417        return 0;
1418}
1419
1420
1421static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1422                            const struct aty128fb_par *par)
1423{
1424        aty_st_le32(DDA_CONFIG, dsp->dda_config);
1425        aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1426}
1427
1428
1429static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1430                          const struct aty128_pll *pll,
1431                          u32 depth,
1432                          const struct aty128fb_par *par)
1433{
1434        const struct aty128_meminfo *m = par->mem;
1435        u32 xclk = par->constants.xclk;
1436        u32 fifo_width = par->constants.fifo_width;
1437        u32 fifo_depth = par->constants.fifo_depth;
1438        s32 x, b, p, ron, roff;
1439        u32 n, d, bpp;
1440
1441        /* round up to multiple of 8 */
1442        bpp = (depth+7) & ~7;
1443
1444        n = xclk * fifo_width;
1445        d = pll->vclk * bpp;
1446        x = round_div(n, d);
1447
1448        ron = 4 * m->MB +
1449                3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1450                2 * m->Trp +
1451                m->Twr +
1452                m->CL +
1453                m->Tr2w +
1454                x;
1455
1456        DBG("x %x\n", x);
1457
1458        b = 0;
1459        while (x) {
1460                x >>= 1;
1461                b++;
1462        }
1463        p = b + 1;
1464
1465        ron <<= (11 - p);
1466
1467        n <<= (11 - p);
1468        x = round_div(n, d);
1469        roff = x * (fifo_depth - 4);
1470
1471        if ((ron + m->Rloop) >= roff) {
1472                printk(KERN_ERR "aty128fb: Mode out of range!\n");
1473                return -EINVAL;
1474        }
1475
1476        DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1477            p, m->Rloop, x, ron, roff);
1478
1479        dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1480        dsp->dda_on_off = ron << 16 | roff;
1481
1482        return 0;
1483}
1484
1485
1486/*
1487 * This actually sets the video mode.
1488 */
1489static int aty128fb_set_par(struct fb_info *info)
1490{ 
1491        struct aty128fb_par *par = info->par;
1492        u32 config;
1493        int err;
1494
1495        if ((err = aty128_decode_var(&info->var, par)) != 0)
1496                return err;
1497
1498        if (par->blitter_may_be_busy)
1499                wait_for_idle(par);
1500
1501        /* clear all registers that may interfere with mode setting */
1502        aty_st_le32(OVR_CLR, 0);
1503        aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1504        aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1505        aty_st_le32(OV0_SCALE_CNTL, 0);
1506        aty_st_le32(MPP_TB_CONFIG, 0);
1507        aty_st_le32(MPP_GP_CONFIG, 0);
1508        aty_st_le32(SUBPIC_CNTL, 0);
1509        aty_st_le32(VIPH_CONTROL, 0);
1510        aty_st_le32(I2C_CNTL_1, 0);         /* turn off i2c */
1511        aty_st_le32(GEN_INT_CNTL, 0);   /* turn off interrupts */
1512        aty_st_le32(CAP0_TRIG_CNTL, 0);
1513        aty_st_le32(CAP1_TRIG_CNTL, 0);
1514
1515        aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1516
1517        aty128_set_crtc(&par->crtc, par);
1518        aty128_set_pll(&par->pll, par);
1519        aty128_set_fifo(&par->fifo_reg, par);
1520
1521        config = aty_ld_le32(CNFG_CNTL) & ~3;
1522
1523#if defined(__BIG_ENDIAN)
1524        if (par->crtc.bpp == 32)
1525                config |= 2;    /* make aperture do 32 bit swapping */
1526        else if (par->crtc.bpp == 16)
1527                config |= 1;    /* make aperture do 16 bit swapping */
1528#endif
1529
1530        aty_st_le32(CNFG_CNTL, config);
1531        aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1532
1533        info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1534        info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1535                : FB_VISUAL_DIRECTCOLOR;
1536
1537        if (par->chip_gen == rage_M3) {
1538                aty128_set_crt_enable(par, par->crt_on);
1539                aty128_set_lcd_enable(par, par->lcd_on);
1540        }
1541        if (par->accel_flags & FB_ACCELF_TEXT)
1542                aty128_init_engine(par);
1543
1544#ifdef CONFIG_BOOTX_TEXT
1545        btext_update_display(info->fix.smem_start,
1546                             (((par->crtc.h_total>>16) & 0xff)+1)*8,
1547                             ((par->crtc.v_total>>16) & 0x7ff)+1,
1548                             par->crtc.bpp,
1549                             par->crtc.vxres*par->crtc.bpp/8);
1550#endif /* CONFIG_BOOTX_TEXT */
1551
1552        return 0;
1553}
1554
1555/*
1556 *  encode/decode the User Defined Part of the Display
1557 */
1558
1559static int aty128_decode_var(struct fb_var_screeninfo *var,
1560                             struct aty128fb_par *par)
1561{
1562        int err;
1563        struct aty128_crtc crtc;
1564        struct aty128_pll pll;
1565        struct aty128_ddafifo fifo_reg;
1566
1567        if ((err = aty128_var_to_crtc(var, &crtc, par)))
1568                return err;
1569
1570        if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1571                return err;
1572
1573        if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1574                return err;
1575
1576        par->crtc = crtc;
1577        par->pll = pll;
1578        par->fifo_reg = fifo_reg;
1579        par->accel_flags = var->accel_flags;
1580
1581        return 0;
1582}
1583
1584
1585static int aty128_encode_var(struct fb_var_screeninfo *var,
1586                             const struct aty128fb_par *par)
1587{
1588        int err;
1589
1590        if ((err = aty128_crtc_to_var(&par->crtc, var)))
1591                return err;
1592
1593        if ((err = aty128_pll_to_var(&par->pll, var)))
1594                return err;
1595
1596        var->nonstd = 0;
1597        var->activate = 0;
1598
1599        var->height = -1;
1600        var->width = -1;
1601        var->accel_flags = par->accel_flags;
1602
1603        return 0;
1604}           
1605
1606
1607static int aty128fb_check_var(struct fb_var_screeninfo *var,
1608                              struct fb_info *info)
1609{
1610        struct aty128fb_par par;
1611        int err;
1612
1613        par = *(struct aty128fb_par *)info->par;
1614        if ((err = aty128_decode_var(var, &par)) != 0)
1615                return err;
1616        aty128_encode_var(var, &par);
1617        return 0;
1618}
1619
1620
1621/*
1622 *  Pan or Wrap the Display
1623 */
1624static int aty128fb_pan_display(struct fb_var_screeninfo *var,
1625                                struct fb_info *fb)
1626{
1627        struct aty128fb_par *par = fb->par;
1628        u32 xoffset, yoffset;
1629        u32 offset;
1630        u32 xres, yres;
1631
1632        xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1633        yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1634
1635        xoffset = (var->xoffset +7) & ~7;
1636        yoffset = var->yoffset;
1637
1638        if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1639                return -EINVAL;
1640
1641        par->crtc.xoffset = xoffset;
1642        par->crtc.yoffset = yoffset;
1643
1644        offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1645                                                                          & ~7;
1646
1647        if (par->crtc.bpp == 24)
1648                offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1649
1650        aty_st_le32(CRTC_OFFSET, offset);
1651
1652        return 0;
1653}
1654
1655
1656/*
1657 *  Helper function to store a single palette register
1658 */
1659static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1660                          struct aty128fb_par *par)
1661{
1662        if (par->chip_gen == rage_M3) {
1663                aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1664                            ~DAC_PALETTE_ACCESS_CNTL);
1665        }
1666
1667        aty_st_8(PALETTE_INDEX, regno);
1668        aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1669}
1670
1671static int aty128fb_sync(struct fb_info *info)
1672{
1673        struct aty128fb_par *par = info->par;
1674
1675        if (par->blitter_may_be_busy)
1676                wait_for_idle(par);
1677        return 0;
1678}
1679
1680#ifndef MODULE
1681static int aty128fb_setup(char *options)
1682{
1683        char *this_opt;
1684
1685        if (!options || !*options)
1686                return 0;
1687
1688        while ((this_opt = strsep(&options, ",")) != NULL) {
1689                if (!strncmp(this_opt, "lcd:", 4)) {
1690                        default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1691                        continue;
1692                } else if (!strncmp(this_opt, "crt:", 4)) {
1693                        default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1694                        continue;
1695                } else if (!strncmp(this_opt, "backlight:", 10)) {
1696#ifdef CONFIG_FB_ATY128_BACKLIGHT
1697                        backlight = simple_strtoul(this_opt+10, NULL, 0);
1698#endif
1699                        continue;
1700                }
1701                if(!strncmp(this_opt, "nomtrr", 6)) {
1702                        mtrr = false;
1703                        continue;
1704                }
1705#ifdef CONFIG_PPC_PMAC
1706                /* vmode and cmode deprecated */
1707                if (!strncmp(this_opt, "vmode:", 6)) {
1708                        unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1709                        if (vmode > 0 && vmode <= VMODE_MAX)
1710                                default_vmode = vmode;
1711                        continue;
1712                } else if (!strncmp(this_opt, "cmode:", 6)) {
1713                        unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1714                        switch (cmode) {
1715                        case 0:
1716                        case 8:
1717                                default_cmode = CMODE_8;
1718                                break;
1719                        case 15:
1720                        case 16:
1721                                default_cmode = CMODE_16;
1722                                break;
1723                        case 24:
1724                        case 32:
1725                                default_cmode = CMODE_32;
1726                                break;
1727                        }
1728                        continue;
1729                }
1730#endif /* CONFIG_PPC_PMAC */
1731                mode_option = this_opt;
1732        }
1733        return 0;
1734}
1735#endif  /*  MODULE  */
1736
1737/* Backlight */
1738#ifdef CONFIG_FB_ATY128_BACKLIGHT
1739#define MAX_LEVEL 0xFF
1740
1741static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1742                int level)
1743{
1744        struct fb_info *info = pci_get_drvdata(par->pdev);
1745        int atylevel;
1746
1747        /* Get and convert the value */
1748        /* No locking of bl_curve since we read a single value */
1749        atylevel = MAX_LEVEL -
1750                (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1751
1752        if (atylevel < 0)
1753                atylevel = 0;
1754        else if (atylevel > MAX_LEVEL)
1755                atylevel = MAX_LEVEL;
1756
1757        return atylevel;
1758}
1759
1760/* We turn off the LCD completely instead of just dimming the backlight.
1761 * This provides greater power saving and the display is useless without
1762 * backlight anyway
1763 */
1764#define BACKLIGHT_LVDS_OFF
1765/* That one prevents proper CRT output with LCD off */
1766#undef BACKLIGHT_DAC_OFF
1767
1768static int aty128_bl_update_status(struct backlight_device *bd)
1769{
1770        struct aty128fb_par *par = bl_get_data(bd);
1771        unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1772        int level;
1773
1774        if (bd->props.power != FB_BLANK_UNBLANK ||
1775            bd->props.fb_blank != FB_BLANK_UNBLANK ||
1776            !par->lcd_on)
1777                level = 0;
1778        else
1779                level = bd->props.brightness;
1780
1781        reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1782        if (level > 0) {
1783                reg |= LVDS_DIGION;
1784                if (!(reg & LVDS_ON)) {
1785                        reg &= ~LVDS_BLON;
1786                        aty_st_le32(LVDS_GEN_CNTL, reg);
1787                        aty_ld_le32(LVDS_GEN_CNTL);
1788                        mdelay(10);
1789                        reg |= LVDS_BLON;
1790                        aty_st_le32(LVDS_GEN_CNTL, reg);
1791                }
1792                reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1793                reg |= (aty128_bl_get_level_brightness(par, level) <<
1794                        LVDS_BL_MOD_LEVEL_SHIFT);
1795#ifdef BACKLIGHT_LVDS_OFF
1796                reg |= LVDS_ON | LVDS_EN;
1797                reg &= ~LVDS_DISPLAY_DIS;
1798#endif
1799                aty_st_le32(LVDS_GEN_CNTL, reg);
1800#ifdef BACKLIGHT_DAC_OFF
1801                aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1802#endif
1803        } else {
1804                reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1805                reg |= (aty128_bl_get_level_brightness(par, 0) <<
1806                        LVDS_BL_MOD_LEVEL_SHIFT);
1807#ifdef BACKLIGHT_LVDS_OFF
1808                reg |= LVDS_DISPLAY_DIS;
1809                aty_st_le32(LVDS_GEN_CNTL, reg);
1810                aty_ld_le32(LVDS_GEN_CNTL);
1811                udelay(10);
1812                reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1813#endif
1814                aty_st_le32(LVDS_GEN_CNTL, reg);
1815#ifdef BACKLIGHT_DAC_OFF
1816                aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1817#endif
1818        }
1819
1820        return 0;
1821}
1822
1823static const struct backlight_ops aty128_bl_data = {
1824        .update_status  = aty128_bl_update_status,
1825};
1826
1827static void aty128_bl_set_power(struct fb_info *info, int power)
1828{
1829        if (info->bl_dev) {
1830                info->bl_dev->props.power = power;
1831                backlight_update_status(info->bl_dev);
1832        }
1833}
1834
1835static void aty128_bl_init(struct aty128fb_par *par)
1836{
1837        struct backlight_properties props;
1838        struct fb_info *info = pci_get_drvdata(par->pdev);
1839        struct backlight_device *bd;
1840        char name[12];
1841
1842        /* Could be extended to Rage128Pro LVDS output too */
1843        if (par->chip_gen != rage_M3)
1844                return;
1845
1846#ifdef CONFIG_PMAC_BACKLIGHT
1847        if (!pmac_has_backlight_type("ati"))
1848                return;
1849#endif
1850
1851        snprintf(name, sizeof(name), "aty128bl%d", info->node);
1852
1853        memset(&props, 0, sizeof(struct backlight_properties));
1854        props.type = BACKLIGHT_RAW;
1855        props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1856        bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1857                                       &props);
1858        if (IS_ERR(bd)) {
1859                info->bl_dev = NULL;
1860                printk(KERN_WARNING "aty128: Backlight registration failed\n");
1861                goto error;
1862        }
1863
1864        info->bl_dev = bd;
1865        fb_bl_default_curve(info, 0,
1866                 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1867                219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1868
1869        bd->props.brightness = bd->props.max_brightness;
1870        bd->props.power = FB_BLANK_UNBLANK;
1871        backlight_update_status(bd);
1872
1873        printk("aty128: Backlight initialized (%s)\n", name);
1874
1875        return;
1876
1877error:
1878        return;
1879}
1880
1881static void aty128_bl_exit(struct backlight_device *bd)
1882{
1883        backlight_device_unregister(bd);
1884        printk("aty128: Backlight unloaded\n");
1885}
1886#endif /* CONFIG_FB_ATY128_BACKLIGHT */
1887
1888/*
1889 *  Initialisation
1890 */
1891
1892#ifdef CONFIG_PPC_PMAC__disabled
1893static void aty128_early_resume(void *data)
1894{
1895        struct aty128fb_par *par = data;
1896
1897        if (!console_trylock())
1898                return;
1899        pci_restore_state(par->pdev);
1900        aty128_do_resume(par->pdev);
1901        console_unlock();
1902}
1903#endif /* CONFIG_PPC_PMAC */
1904
1905static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1906{
1907        struct fb_info *info = pci_get_drvdata(pdev);
1908        struct aty128fb_par *par = info->par;
1909        struct fb_var_screeninfo var;
1910        char video_card[50];
1911        u8 chip_rev;
1912        u32 dac;
1913
1914        /* Get the chip revision */
1915        chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1916
1917        strcpy(video_card, "Rage128 XX ");
1918        video_card[8] = ent->device >> 8;
1919        video_card[9] = ent->device & 0xFF;
1920
1921        /* range check to make sure */
1922        if (ent->driver_data < ARRAY_SIZE(r128_family))
1923                strlcat(video_card, r128_family[ent->driver_data],
1924                        sizeof(video_card));
1925
1926        printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1927
1928        if (par->vram_size % (1024 * 1024) == 0)
1929                printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1930        else
1931                printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1932
1933        par->chip_gen = ent->driver_data;
1934
1935        /* fill in info */
1936        info->fbops = &aty128fb_ops;
1937        info->flags = FBINFO_FLAG_DEFAULT;
1938
1939        par->lcd_on = default_lcd_on;
1940        par->crt_on = default_crt_on;
1941
1942        var = default_var;
1943#ifdef CONFIG_PPC_PMAC
1944        if (machine_is(powermac)) {
1945                /* Indicate sleep capability */
1946                if (par->chip_gen == rage_M3) {
1947                        pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1948#if 0 /* Disable the early video resume hack for now as it's causing problems,
1949       * among others we now rely on the PCI core restoring the config space
1950       * for us, which isn't the case with that hack, and that code path causes
1951       * various things to be called with interrupts off while they shouldn't.
1952       * I'm leaving the code in as it can be useful for debugging purposes
1953       */
1954                        pmac_set_early_video_resume(aty128_early_resume, par);
1955#endif
1956                }
1957
1958                /* Find default mode */
1959                if (mode_option) {
1960                        if (!mac_find_mode(&var, info, mode_option, 8))
1961                                var = default_var;
1962                } else {
1963                        if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1964                                default_vmode = VMODE_1024_768_60;
1965
1966                        /* iMacs need that resolution
1967                         * PowerMac2,1 first r128 iMacs
1968                         * PowerMac2,2 summer 2000 iMacs
1969                         * PowerMac4,1 january 2001 iMacs "flower power"
1970                         */
1971                        if (of_machine_is_compatible("PowerMac2,1") ||
1972                            of_machine_is_compatible("PowerMac2,2") ||
1973                            of_machine_is_compatible("PowerMac4,1"))
1974                                default_vmode = VMODE_1024_768_75;
1975
1976                        /* iBook SE */
1977                        if (of_machine_is_compatible("PowerBook2,2"))
1978                                default_vmode = VMODE_800_600_60;
1979
1980                        /* PowerBook Firewire (Pismo), iBook Dual USB */
1981                        if (of_machine_is_compatible("PowerBook3,1") ||
1982                            of_machine_is_compatible("PowerBook4,1"))
1983                                default_vmode = VMODE_1024_768_60;
1984
1985                        /* PowerBook Titanium */
1986                        if (of_machine_is_compatible("PowerBook3,2"))
1987                                default_vmode = VMODE_1152_768_60;
1988        
1989                        if (default_cmode > 16) 
1990                                default_cmode = CMODE_32;
1991                        else if (default_cmode > 8) 
1992                                default_cmode = CMODE_16;
1993                        else 
1994                                default_cmode = CMODE_8;
1995
1996                        if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1997                                var = default_var;
1998                }
1999        } else
2000#endif /* CONFIG_PPC_PMAC */
2001        {
2002                if (mode_option)
2003                        if (fb_find_mode(&var, info, mode_option, NULL, 
2004                                         0, &defaultmode, 8) == 0)
2005                                var = default_var;
2006        }
2007
2008        var.accel_flags &= ~FB_ACCELF_TEXT;
2009//      var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
2010
2011        if (aty128fb_check_var(&var, info)) {
2012                printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
2013                return 0;
2014        }
2015
2016        /* setup the DAC the way we like it */
2017        dac = aty_ld_le32(DAC_CNTL);
2018        dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2019        dac |= DAC_MASK;
2020        if (par->chip_gen == rage_M3)
2021                dac |= DAC_PALETTE2_SNOOP_EN;
2022        aty_st_le32(DAC_CNTL, dac);
2023
2024        /* turn off bus mastering, just in case */
2025        aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2026
2027        info->var = var;
2028        fb_alloc_cmap(&info->cmap, 256, 0);
2029
2030        var.activate = FB_ACTIVATE_NOW;
2031
2032        aty128_init_engine(par);
2033
2034        par->pdev = pdev;
2035        par->asleep = 0;
2036        par->lock_blank = 0;
2037
2038#ifdef CONFIG_FB_ATY128_BACKLIGHT
2039        if (backlight)
2040                aty128_bl_init(par);
2041#endif
2042
2043        if (register_framebuffer(info) < 0)
2044                return 0;
2045
2046        fb_info(info, "%s frame buffer device on %s\n",
2047                info->fix.id, video_card);
2048
2049        return 1;       /* success! */
2050}
2051
2052#ifdef CONFIG_PCI
2053/* register a card    ++ajoshi */
2054static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2055{
2056        unsigned long fb_addr, reg_addr;
2057        struct aty128fb_par *par;
2058        struct fb_info *info;
2059        int err;
2060#ifndef __sparc__
2061        void __iomem *bios = NULL;
2062#endif
2063
2064        /* Enable device in PCI config */
2065        if ((err = pci_enable_device(pdev))) {
2066                printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2067                                err);
2068                return -ENODEV;
2069        }
2070
2071        fb_addr = pci_resource_start(pdev, 0);
2072        if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2073                                "aty128fb FB")) {
2074                printk(KERN_ERR "aty128fb: cannot reserve frame "
2075                                "buffer memory\n");
2076                return -ENODEV;
2077        }
2078
2079        reg_addr = pci_resource_start(pdev, 2);
2080        if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2081                                "aty128fb MMIO")) {
2082                printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2083                goto err_free_fb;
2084        }
2085
2086        /* We have the resources. Now virtualize them */
2087        info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2088        if (!info)
2089                goto err_free_mmio;
2090
2091        par = info->par;
2092
2093        info->pseudo_palette = par->pseudo_palette;
2094
2095        /* Virtualize mmio region */
2096        info->fix.mmio_start = reg_addr;
2097        par->regbase = pci_ioremap_bar(pdev, 2);
2098        if (!par->regbase)
2099                goto err_free_info;
2100
2101        /* Grab memory size from the card */
2102        // How does this relate to the resource length from the PCI hardware?
2103        par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2104
2105        /* Virtualize the framebuffer */
2106        info->screen_base = ioremap_wc(fb_addr, par->vram_size);
2107        if (!info->screen_base)
2108                goto err_unmap_out;
2109
2110        /* Set up info->fix */
2111        info->fix = aty128fb_fix;
2112        info->fix.smem_start = fb_addr;
2113        info->fix.smem_len = par->vram_size;
2114        info->fix.mmio_start = reg_addr;
2115
2116        /* If we can't test scratch registers, something is seriously wrong */
2117        if (!register_test(par)) {
2118                printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2119                goto err_out;
2120        }
2121
2122#ifndef __sparc__
2123        bios = aty128_map_ROM(par, pdev);
2124#ifdef CONFIG_X86
2125        if (bios == NULL)
2126                bios = aty128_find_mem_vbios(par);
2127#endif
2128        if (bios == NULL)
2129                printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2130        else {
2131                printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2132                aty128_get_pllinfo(par, bios);
2133                pci_unmap_rom(pdev, bios);
2134        }
2135#endif /* __sparc__ */
2136
2137        aty128_timings(par);
2138        pci_set_drvdata(pdev, info);
2139
2140        if (!aty128_init(pdev, ent))
2141                goto err_out;
2142
2143        if (mtrr)
2144                par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
2145                                                  par->vram_size);
2146        return 0;
2147
2148err_out:
2149        iounmap(info->screen_base);
2150err_unmap_out:
2151        iounmap(par->regbase);
2152err_free_info:
2153        framebuffer_release(info);
2154err_free_mmio:
2155        release_mem_region(pci_resource_start(pdev, 2),
2156                        pci_resource_len(pdev, 2));
2157err_free_fb:
2158        release_mem_region(pci_resource_start(pdev, 0),
2159                        pci_resource_len(pdev, 0));
2160        return -ENODEV;
2161}
2162
2163static void aty128_remove(struct pci_dev *pdev)
2164{
2165        struct fb_info *info = pci_get_drvdata(pdev);
2166        struct aty128fb_par *par;
2167
2168        if (!info)
2169                return;
2170
2171        par = info->par;
2172
2173        unregister_framebuffer(info);
2174
2175#ifdef CONFIG_FB_ATY128_BACKLIGHT
2176        aty128_bl_exit(info->bl_dev);
2177#endif
2178
2179        arch_phys_wc_del(par->wc_cookie);
2180        iounmap(par->regbase);
2181        iounmap(info->screen_base);
2182
2183        release_mem_region(pci_resource_start(pdev, 0),
2184                           pci_resource_len(pdev, 0));
2185        release_mem_region(pci_resource_start(pdev, 2),
2186                           pci_resource_len(pdev, 2));
2187        framebuffer_release(info);
2188}
2189#endif /* CONFIG_PCI */
2190
2191
2192
2193    /*
2194     *  Blank the display.
2195     */
2196static int aty128fb_blank(int blank, struct fb_info *fb)
2197{
2198        struct aty128fb_par *par = fb->par;
2199        u8 state;
2200
2201        if (par->lock_blank || par->asleep)
2202                return 0;
2203
2204        switch (blank) {
2205        case FB_BLANK_NORMAL:
2206                state = 4;
2207                break;
2208        case FB_BLANK_VSYNC_SUSPEND:
2209                state = 6;
2210                break;
2211        case FB_BLANK_HSYNC_SUSPEND:
2212                state = 5;
2213                break;
2214        case FB_BLANK_POWERDOWN:
2215                state = 7;
2216                break;
2217        case FB_BLANK_UNBLANK:
2218        default:
2219                state = 0;
2220                break;
2221        }
2222        aty_st_8(CRTC_EXT_CNTL+1, state);
2223
2224        if (par->chip_gen == rage_M3) {
2225                aty128_set_crt_enable(par, par->crt_on && !blank);
2226                aty128_set_lcd_enable(par, par->lcd_on && !blank);
2227        }
2228
2229        return 0;
2230}
2231
2232/*
2233 *  Set a single color register. The values supplied are already
2234 *  rounded down to the hardware's capabilities (according to the
2235 *  entries in the var structure). Return != 0 for invalid regno.
2236 */
2237static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2238                              u_int transp, struct fb_info *info)
2239{
2240        struct aty128fb_par *par = info->par;
2241
2242        if (regno > 255
2243            || (par->crtc.depth == 16 && regno > 63)
2244            || (par->crtc.depth == 15 && regno > 31))
2245                return 1;
2246
2247        red >>= 8;
2248        green >>= 8;
2249        blue >>= 8;
2250
2251        if (regno < 16) {
2252                int i;
2253                u32 *pal = info->pseudo_palette;
2254
2255                switch (par->crtc.depth) {
2256                case 15:
2257                        pal[regno] = (regno << 10) | (regno << 5) | regno;
2258                        break;
2259                case 16:
2260                        pal[regno] = (regno << 11) | (regno << 6) | regno;
2261                        break;
2262                case 24:
2263                        pal[regno] = (regno << 16) | (regno << 8) | regno;
2264                        break;
2265                case 32:
2266                        i = (regno << 8) | regno;
2267                        pal[regno] = (i << 16) | i;
2268                        break;
2269                }
2270        }
2271
2272        if (par->crtc.depth == 16 && regno > 0) {
2273                /*
2274                 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2275                 * have 32 slots for R and B values but 64 slots for G values.
2276                 * Thus the R and B values go in one slot but the G value
2277                 * goes in a different slot, and we have to avoid disturbing
2278                 * the other fields in the slots we touch.
2279                 */
2280                par->green[regno] = green;
2281                if (regno < 32) {
2282                        par->red[regno] = red;
2283                        par->blue[regno] = blue;
2284                        aty128_st_pal(regno * 8, red, par->green[regno*2],
2285                                      blue, par);
2286                }
2287                red = par->red[regno/2];
2288                blue = par->blue[regno/2];
2289                regno <<= 2;
2290        } else if (par->crtc.bpp == 16)
2291                regno <<= 3;
2292        aty128_st_pal(regno, red, green, blue, par);
2293
2294        return 0;
2295}
2296
2297#define ATY_MIRROR_LCD_ON       0x00000001
2298#define ATY_MIRROR_CRT_ON       0x00000002
2299
2300/* out param: u32*      backlight value: 0 to 15 */
2301#define FBIO_ATY128_GET_MIRROR  _IOR('@', 1, __u32)
2302/* in param: u32*       backlight value: 0 to 15 */
2303#define FBIO_ATY128_SET_MIRROR  _IOW('@', 2, __u32)
2304
2305static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2306{
2307        struct aty128fb_par *par = info->par;
2308        u32 value;
2309        int rc;
2310    
2311        switch (cmd) {
2312        case FBIO_ATY128_SET_MIRROR:
2313                if (par->chip_gen != rage_M3)
2314                        return -EINVAL;
2315                rc = get_user(value, (__u32 __user *)arg);
2316                if (rc)
2317                        return rc;
2318                par->lcd_on = (value & 0x01) != 0;
2319                par->crt_on = (value & 0x02) != 0;
2320                if (!par->crt_on && !par->lcd_on)
2321                        par->lcd_on = 1;
2322                aty128_set_crt_enable(par, par->crt_on);        
2323                aty128_set_lcd_enable(par, par->lcd_on);        
2324                return 0;
2325        case FBIO_ATY128_GET_MIRROR:
2326                if (par->chip_gen != rage_M3)
2327                        return -EINVAL;
2328                value = (par->crt_on << 1) | par->lcd_on;
2329                return put_user(value, (__u32 __user *)arg);
2330        }
2331        return -EINVAL;
2332}
2333
2334static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2335{
2336        u32     pmgt;
2337        struct pci_dev *pdev = par->pdev;
2338
2339        if (!par->pdev->pm_cap)
2340                return;
2341                
2342        /* Set the chip into the appropriate suspend mode (we use D2,
2343         * D3 would require a complete re-initialisation of the chip,
2344         * including PCI config registers, clocks, AGP configuration, ...)
2345         *
2346         * For resume, the core will have already brought us back to D0
2347         */
2348        if (suspend) {
2349                /* Make sure CRTC2 is reset. Remove that the day we decide to
2350                 * actually use CRTC2 and replace it with real code for disabling
2351                 * the CRTC2 output during sleep
2352                 */
2353                aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2354                        ~(CRTC2_EN));
2355
2356                /* Set the power management mode to be PCI based */
2357                /* Use this magic value for now */
2358                pmgt = 0x0c005407;
2359                aty_st_pll(POWER_MANAGEMENT, pmgt);
2360                (void)aty_ld_pll(POWER_MANAGEMENT);
2361                aty_st_le32(BUS_CNTL1, 0x00000010);
2362                aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2363                msleep(100);
2364
2365                /* Switch PCI power management to D2 */
2366                pci_set_power_state(pdev, PCI_D2);
2367        }
2368}
2369
2370static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2371{
2372        struct fb_info *info = pci_get_drvdata(pdev);
2373        struct aty128fb_par *par = info->par;
2374
2375        /* Because we may change PCI D state ourselves, we need to
2376         * first save the config space content so the core can
2377         * restore it properly on resume.
2378         */
2379        pci_save_state(pdev);
2380
2381        /* We don't do anything but D2, for now we return 0, but
2382         * we may want to change that. How do we know if the BIOS
2383         * can properly take care of D3 ? Also, with swsusp, we
2384         * know we'll be rebooted, ...
2385         */
2386#ifndef CONFIG_PPC_PMAC
2387        /* HACK ALERT ! Once I find a proper way to say to each driver
2388         * individually what will happen with it's PCI slot, I'll change
2389         * that. On laptops, the AGP slot is just unclocked, so D2 is
2390         * expected, while on desktops, the card is powered off
2391         */
2392        return 0;
2393#endif /* CONFIG_PPC_PMAC */
2394         
2395        if (state.event == pdev->dev.power.power_state.event)
2396                return 0;
2397
2398        printk(KERN_DEBUG "aty128fb: suspending...\n");
2399        
2400        console_lock();
2401
2402        fb_set_suspend(info, 1);
2403
2404        /* Make sure engine is reset */
2405        wait_for_idle(par);
2406        aty128_reset_engine(par);
2407        wait_for_idle(par);
2408
2409        /* Blank display and LCD */
2410        aty128fb_blank(FB_BLANK_POWERDOWN, info);
2411
2412        /* Sleep */
2413        par->asleep = 1;
2414        par->lock_blank = 1;
2415
2416#ifdef CONFIG_PPC_PMAC
2417        /* On powermac, we have hooks to properly suspend/resume AGP now,
2418         * use them here. We'll ultimately need some generic support here,
2419         * but the generic code isn't quite ready for that yet
2420         */
2421        pmac_suspend_agp_for_card(pdev);
2422#endif /* CONFIG_PPC_PMAC */
2423
2424        /* We need a way to make sure the fbdev layer will _not_ touch the
2425         * framebuffer before we put the chip to suspend state. On 2.4, I
2426         * used dummy fb ops, 2.5 need proper support for this at the
2427         * fbdev level
2428         */
2429        if (state.event != PM_EVENT_ON)
2430                aty128_set_suspend(par, 1);
2431
2432        console_unlock();
2433
2434        pdev->dev.power.power_state = state;
2435
2436        return 0;
2437}
2438
2439static int aty128_do_resume(struct pci_dev *pdev)
2440{
2441        struct fb_info *info = pci_get_drvdata(pdev);
2442        struct aty128fb_par *par = info->par;
2443
2444        if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2445                return 0;
2446
2447        /* PCI state will have been restored by the core, so
2448         * we should be in D0 now with our config space fully
2449         * restored
2450         */
2451
2452        /* Wakeup chip */
2453        aty128_set_suspend(par, 0);
2454        par->asleep = 0;
2455
2456        /* Restore display & engine */
2457        aty128_reset_engine(par);
2458        wait_for_idle(par);
2459        aty128fb_set_par(info);
2460        fb_pan_display(info, &info->var);
2461        fb_set_cmap(&info->cmap, info);
2462
2463        /* Refresh */
2464        fb_set_suspend(info, 0);
2465
2466        /* Unblank */
2467        par->lock_blank = 0;
2468        aty128fb_blank(0, info);
2469
2470#ifdef CONFIG_PPC_PMAC
2471        /* On powermac, we have hooks to properly suspend/resume AGP now,
2472         * use them here. We'll ultimately need some generic support here,
2473         * but the generic code isn't quite ready for that yet
2474         */
2475        pmac_resume_agp_for_card(pdev);
2476#endif /* CONFIG_PPC_PMAC */
2477
2478        pdev->dev.power.power_state = PMSG_ON;
2479
2480        printk(KERN_DEBUG "aty128fb: resumed !\n");
2481
2482        return 0;
2483}
2484
2485static int aty128_pci_resume(struct pci_dev *pdev)
2486{
2487        int rc;
2488
2489        console_lock();
2490        rc = aty128_do_resume(pdev);
2491        console_unlock();
2492
2493        return rc;
2494}
2495
2496
2497static int aty128fb_init(void)
2498{
2499#ifndef MODULE
2500        char *option = NULL;
2501
2502        if (fb_get_options("aty128fb", &option))
2503                return -ENODEV;
2504        aty128fb_setup(option);
2505#endif
2506
2507        return pci_register_driver(&aty128fb_driver);
2508}
2509
2510static void __exit aty128fb_exit(void)
2511{
2512        pci_unregister_driver(&aty128fb_driver);
2513}
2514
2515module_init(aty128fb_init);
2516
2517module_exit(aty128fb_exit);
2518
2519MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2520MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2521MODULE_LICENSE("GPL");
2522module_param(mode_option, charp, 0);
2523MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2524module_param_named(nomtrr, mtrr, invbool, 0);
2525MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2526