1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46#undef DEBUG
47
48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/errno.h>
51#include <linux/string.h>
52#include <linux/mm.h>
53#include <linux/slab.h>
54#include <linux/delay.h>
55#include <linux/interrupt.h>
56#include <linux/fb.h>
57#include <linux/init.h>
58#include <linux/pci.h>
59
60#ifdef CONFIG_SH_DREAMCAST
61#include <asm/machvec.h>
62#include <mach-dreamcast/mach/sysasic.h>
63#endif
64
65#ifdef CONFIG_PVR2_DMA
66#include <linux/pagemap.h>
67#include <mach/dma.h>
68#include <asm/dma.h>
69#endif
70
71#ifdef CONFIG_SH_STORE_QUEUES
72#include <linux/uaccess.h>
73#include <cpu/sq.h>
74#endif
75
76#ifndef PCI_DEVICE_ID_NEC_NEON250
77# define PCI_DEVICE_ID_NEC_NEON250 0x0067
78#endif
79
80
81#define DISP_BASE par->mmio_base
82#define DISP_BRDRCOLR (DISP_BASE + 0x40)
83#define DISP_DIWMODE (DISP_BASE + 0x44)
84#define DISP_DIWADDRL (DISP_BASE + 0x50)
85#define DISP_DIWADDRS (DISP_BASE + 0x54)
86#define DISP_DIWSIZE (DISP_BASE + 0x5c)
87#define DISP_SYNCCONF (DISP_BASE + 0xd0)
88#define DISP_BRDRHORZ (DISP_BASE + 0xd4)
89#define DISP_SYNCSIZE (DISP_BASE + 0xd8)
90#define DISP_BRDRVERT (DISP_BASE + 0xdc)
91#define DISP_DIWCONF (DISP_BASE + 0xe8)
92#define DISP_DIWHSTRT (DISP_BASE + 0xec)
93#define DISP_DIWVSTRT (DISP_BASE + 0xf0)
94#define DISP_PIXDEPTH (DISP_BASE + 0x108)
95
96
97#define TV_CLK 74239
98#define VGA_CLK 37119
99
100
101#define PAL_HTOTAL 863
102#define PAL_VTOTAL 312
103#define NTSC_HTOTAL 857
104#define NTSC_VTOTAL 262
105
106
107enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
108
109
110enum { VO_PAL, VO_NTSC, VO_VGA };
111
112
113enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
114
115struct pvr2_params { unsigned int val; char *name; };
116static struct pvr2_params cables[] = {
117 { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
118};
119
120static struct pvr2_params outputs[] = {
121 { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
122};
123
124
125
126
127
128static struct pvr2fb_par {
129 unsigned int hsync_total;
130 unsigned int vsync_total;
131 unsigned int borderstart_h;
132 unsigned int borderstop_h;
133 unsigned int borderstart_v;
134 unsigned int borderstop_v;
135 unsigned int diwstart_h;
136 unsigned int diwstart_v;
137
138 unsigned long disp_start;
139 unsigned char is_interlaced;
140 unsigned char is_doublescan;
141 unsigned char is_lowres;
142
143 void __iomem *mmio_base;
144 u32 palette[16];
145} *currentpar;
146
147static struct fb_info *fb_info;
148
149static struct fb_fix_screeninfo pvr2_fix = {
150 .id = "NEC PowerVR2",
151 .type = FB_TYPE_PACKED_PIXELS,
152 .visual = FB_VISUAL_TRUECOLOR,
153 .ypanstep = 1,
154 .ywrapstep = 1,
155 .accel = FB_ACCEL_NONE,
156};
157
158static const struct fb_var_screeninfo pvr2_var = {
159 .xres = 640,
160 .yres = 480,
161 .xres_virtual = 640,
162 .yres_virtual = 480,
163 .bits_per_pixel =16,
164 .red = { 11, 5, 0 },
165 .green = { 5, 6, 0 },
166 .blue = { 0, 5, 0 },
167 .activate = FB_ACTIVATE_NOW,
168 .height = -1,
169 .width = -1,
170 .vmode = FB_VMODE_NONINTERLACED,
171};
172
173static int cable_type = CT_VGA;
174static int video_output = VO_VGA;
175
176static int nopan = 0;
177static int nowrap = 1;
178
179
180
181
182static unsigned int do_vmode_full = 0;
183static unsigned int do_vmode_pan = 0;
184static short do_blank = 0;
185
186static unsigned int is_blanked = 0;
187
188#ifdef CONFIG_SH_STORE_QUEUES
189static unsigned long pvr2fb_map;
190#endif
191
192#ifdef CONFIG_PVR2_DMA
193static unsigned int shdma = PVR2_CASCADE_CHAN;
194static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
195#endif
196
197static struct fb_videomode pvr2_modedb[] = {
198
199
200
201
202
203
204 {
205
206 "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
207 FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
208 }, {
209
210
211 "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
212 FB_SYNC_BROADCAST, FB_VMODE_YWRAP
213 }, {
214
215 "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
216 0, FB_VMODE_YWRAP
217 },
218};
219
220#define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
221
222#define DEFMODE_NTSC 0
223#define DEFMODE_PAL 0
224#define DEFMODE_VGA 2
225
226static int defmode = DEFMODE_NTSC;
227static char *mode_option = NULL;
228
229static inline void pvr2fb_set_pal_type(unsigned int type)
230{
231 struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
232
233 fb_writel(type, par->mmio_base + 0x108);
234}
235
236static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
237 unsigned int regno,
238 unsigned int val)
239{
240 fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
241}
242
243static int pvr2fb_blank(int blank, struct fb_info *info)
244{
245 do_blank = blank ? blank : -1;
246 return 0;
247}
248
249static inline unsigned long get_line_length(int xres_virtual, int bpp)
250{
251 return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
252}
253
254static void set_color_bitfields(struct fb_var_screeninfo *var)
255{
256 switch (var->bits_per_pixel) {
257 case 16:
258 pvr2fb_set_pal_type(PAL_RGB565);
259 var->red.offset = 11; var->red.length = 5;
260 var->green.offset = 5; var->green.length = 6;
261 var->blue.offset = 0; var->blue.length = 5;
262 var->transp.offset = 0; var->transp.length = 0;
263 break;
264 case 24:
265 var->red.offset = 16; var->red.length = 8;
266 var->green.offset = 8; var->green.length = 8;
267 var->blue.offset = 0; var->blue.length = 8;
268 var->transp.offset = 0; var->transp.length = 0;
269 break;
270 case 32:
271 pvr2fb_set_pal_type(PAL_ARGB8888);
272 var->red.offset = 16; var->red.length = 8;
273 var->green.offset = 8; var->green.length = 8;
274 var->blue.offset = 0; var->blue.length = 8;
275 var->transp.offset = 24; var->transp.length = 8;
276 break;
277 }
278}
279
280static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
281 unsigned int green, unsigned int blue,
282 unsigned int transp, struct fb_info *info)
283{
284 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
285 unsigned int tmp;
286
287 if (regno > info->cmap.len)
288 return 1;
289
290
291
292
293
294
295 switch (info->var.bits_per_pixel) {
296 case 16:
297 tmp = (red & 0xf800) |
298 ((green & 0xfc00) >> 5) |
299 ((blue & 0xf800) >> 11);
300
301 pvr2fb_set_pal_entry(par, regno, tmp);
302 break;
303 case 24:
304 red >>= 8; green >>= 8; blue >>= 8;
305 tmp = (red << 16) | (green << 8) | blue;
306 break;
307 case 32:
308 red >>= 8; green >>= 8; blue >>= 8;
309 tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
310
311 pvr2fb_set_pal_entry(par, regno, tmp);
312 break;
313 default:
314 pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
315 return 1;
316 }
317
318 if (regno < 16)
319 ((u32*)(info->pseudo_palette))[regno] = tmp;
320
321 return 0;
322}
323
324
325
326
327
328
329#define PCTRA ((void __iomem *)0xff80002c)
330#define PDTRA ((void __iomem *)0xff800030)
331#define VOUTC ((void __iomem *)0xa0702c00)
332
333static int pvr2_init_cable(void)
334{
335 if (cable_type < 0) {
336 fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
337 PCTRA);
338 cable_type = (fb_readw(PDTRA) >> 8) & 3;
339 }
340
341
342
343
344 if (cable_type == CT_COMPOSITE)
345 fb_writel(3 << 8, VOUTC);
346 else if (cable_type == CT_RGB)
347 fb_writel(1 << 9, VOUTC);
348 else
349 fb_writel(0, VOUTC);
350
351 return cable_type;
352}
353
354static int pvr2fb_set_par(struct fb_info *info)
355{
356 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
357 struct fb_var_screeninfo *var = &info->var;
358 unsigned long line_length;
359 unsigned int vtotal;
360
361
362
363
364
365
366
367
368 cable_type = pvr2_init_cable();
369 if (cable_type == CT_VGA && video_output != VO_VGA)
370 video_output = VO_VGA;
371
372 var->vmode &= FB_VMODE_MASK;
373 if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
374 par->is_interlaced = 1;
375
376
377
378
379 if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
380 par->is_doublescan = 1;
381
382 par->hsync_total = var->left_margin + var->xres + var->right_margin +
383 var->hsync_len;
384 par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
385 var->vsync_len;
386
387 if (var->sync & FB_SYNC_BROADCAST) {
388 vtotal = par->vsync_total;
389 if (par->is_interlaced)
390 vtotal /= 2;
391 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
392
393
394 par->borderstart_h = 116;
395 par->borderstart_v = 44;
396 } else {
397
398 par->borderstart_h = 126;
399 par->borderstart_v = 18;
400 }
401 } else {
402
403
404
405
406
407
408 par->borderstart_h = 126;
409 par->borderstart_v = 40;
410 }
411
412
413 par->diwstart_h = par->borderstart_h + var->left_margin;
414 par->diwstart_v = par->borderstart_v + var->upper_margin;
415 par->borderstop_h = par->diwstart_h + var->xres +
416 var->right_margin;
417 par->borderstop_v = par->diwstart_v + var->yres +
418 var->lower_margin;
419
420 if (!par->is_interlaced)
421 par->borderstop_v /= 2;
422 if (info->var.xres < 640)
423 par->is_lowres = 1;
424
425 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
426 par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
427 info->fix.line_length = line_length;
428 return 0;
429}
430
431static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
432{
433 struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
434 unsigned int vtotal, hsync_total;
435 unsigned long line_length;
436
437 if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
438 pr_debug("Invalid pixclock value %d\n", var->pixclock);
439 return -EINVAL;
440 }
441
442 if (var->xres < 320)
443 var->xres = 320;
444 if (var->yres < 240)
445 var->yres = 240;
446 if (var->xres_virtual < var->xres)
447 var->xres_virtual = var->xres;
448 if (var->yres_virtual < var->yres)
449 var->yres_virtual = var->yres;
450
451 if (var->bits_per_pixel <= 16)
452 var->bits_per_pixel = 16;
453 else if (var->bits_per_pixel <= 24)
454 var->bits_per_pixel = 24;
455 else if (var->bits_per_pixel <= 32)
456 var->bits_per_pixel = 32;
457
458 set_color_bitfields(var);
459
460 if (var->vmode & FB_VMODE_YWRAP) {
461 if (var->xoffset || var->yoffset >= var->yres_virtual) {
462 var->xoffset = var->yoffset = 0;
463 } else {
464 if (var->xoffset > var->xres_virtual - var->xres ||
465 var->yoffset > var->yres_virtual - var->yres)
466 var->xoffset = var->yoffset = 0;
467 }
468 } else {
469 var->xoffset = var->yoffset = 0;
470 }
471
472
473
474
475
476 if (var->yres < 480 && video_output == VO_VGA)
477 var->vmode |= FB_VMODE_DOUBLE;
478
479 if (video_output != VO_VGA) {
480 var->sync |= FB_SYNC_BROADCAST;
481 var->vmode |= FB_VMODE_INTERLACED;
482 } else {
483 var->sync &= ~FB_SYNC_BROADCAST;
484 var->vmode &= ~FB_VMODE_INTERLACED;
485 var->vmode |= FB_VMODE_NONINTERLACED;
486 }
487
488 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
489 var->right_margin = par->borderstop_h -
490 (par->diwstart_h + var->xres);
491 var->left_margin = par->diwstart_h - par->borderstart_h;
492 var->hsync_len = par->borderstart_h +
493 (par->hsync_total - par->borderstop_h);
494
495 var->upper_margin = par->diwstart_v - par->borderstart_v;
496 var->lower_margin = par->borderstop_v -
497 (par->diwstart_v + var->yres);
498 var->vsync_len = par->borderstop_v +
499 (par->vsync_total - par->borderstop_v);
500 }
501
502 hsync_total = var->left_margin + var->xres + var->right_margin +
503 var->hsync_len;
504 vtotal = var->upper_margin + var->yres + var->lower_margin +
505 var->vsync_len;
506
507 if (var->sync & FB_SYNC_BROADCAST) {
508 if (var->vmode & FB_VMODE_INTERLACED)
509 vtotal /= 2;
510 if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
511
512
513 if (hsync_total != PAL_HTOTAL) {
514 pr_debug("invalid hsync total for PAL\n");
515 return -EINVAL;
516 }
517 } else {
518
519 if (hsync_total != NTSC_HTOTAL) {
520 pr_debug("invalid hsync total for NTSC\n");
521 return -EINVAL;
522 }
523 }
524 }
525
526
527 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
528 if (line_length * var->yres_virtual > info->fix.smem_len)
529 return -ENOMEM;
530
531 return 0;
532}
533
534static void pvr2_update_display(struct fb_info *info)
535{
536 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
537 struct fb_var_screeninfo *var = &info->var;
538
539
540 fb_writel(par->disp_start, DISP_DIWADDRL);
541 fb_writel(par->disp_start +
542 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
543 DISP_DIWADDRS);
544}
545
546
547
548
549
550
551
552static void pvr2_init_display(struct fb_info *info)
553{
554 struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
555 struct fb_var_screeninfo *var = &info->var;
556 unsigned int diw_height, diw_width, diw_modulo = 1;
557 unsigned int bytesperpixel = var->bits_per_pixel >> 3;
558
559
560 fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
561
562
563
564
565 if (video_output != VO_VGA && par->is_interlaced)
566 diw_modulo += info->fix.line_length / 4;
567 diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
568 diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
569 fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
570 DISP_DIWSIZE);
571
572
573 fb_writel(par->disp_start, DISP_DIWADDRL);
574 fb_writel(par->disp_start +
575 get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
576 DISP_DIWADDRS);
577
578
579 fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
580 fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
581 fb_writel(0, DISP_BRDRCOLR);
582
583
584 fb_writel(par->diwstart_h, DISP_DIWHSTRT);
585 fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
586
587
588 fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
589
590
591 fb_writel(((video_output == VO_VGA) << 23) |
592 (par->is_doublescan << 1) | 1, DISP_DIWMODE);
593
594
595 fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
596 fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);
597
598
599
600 fb_writel(0x100 | ((par->is_interlaced ) << 4), DISP_SYNCCONF);
601}
602
603
604
605#define BLANK_BIT (1<<3)
606
607static void pvr2_do_blank(void)
608{
609 struct pvr2fb_par *par = currentpar;
610 unsigned long diwconf;
611
612 diwconf = fb_readl(DISP_DIWCONF);
613 if (do_blank > 0)
614 fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
615 else
616 fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
617
618 is_blanked = do_blank > 0 ? do_blank : 0;
619}
620
621static irqreturn_t __maybe_unused pvr2fb_interrupt(int irq, void *dev_id)
622{
623 struct fb_info *info = dev_id;
624
625 if (do_vmode_pan || do_vmode_full)
626 pvr2_update_display(info);
627 if (do_vmode_full)
628 pvr2_init_display(info);
629 if (do_vmode_pan)
630 do_vmode_pan = 0;
631 if (do_vmode_full)
632 do_vmode_full = 0;
633 if (do_blank) {
634 pvr2_do_blank();
635 do_blank = 0;
636 }
637 return IRQ_HANDLED;
638}
639
640#ifdef CONFIG_PVR2_DMA
641static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
642 size_t count, loff_t *ppos)
643{
644 unsigned long dst, start, end, len;
645 unsigned int nr_pages;
646 struct page **pages;
647 int ret, i;
648
649 nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
650
651 pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
652 if (!pages)
653 return -ENOMEM;
654
655 ret = pin_user_pages_fast((unsigned long)buf, nr_pages, FOLL_WRITE, pages);
656 if (ret < nr_pages) {
657 if (ret < 0) {
658
659
660
661
662
663 nr_pages = 0;
664 } else {
665 nr_pages = ret;
666
667
668
669
670
671 ret = -EINVAL;
672 }
673 goto out_unmap;
674 }
675
676 dma_configure_channel(shdma, 0x12c1);
677
678 dst = (unsigned long)fb_info->screen_base + *ppos;
679 start = (unsigned long)page_address(pages[0]);
680 end = (unsigned long)page_address(pages[nr_pages]);
681 len = nr_pages << PAGE_SHIFT;
682
683
684 if (start + len == end) {
685
686 if ((*ppos + len) > fb_info->fix.smem_len) {
687 ret = -ENOSPC;
688 goto out_unmap;
689 }
690
691 dma_write(shdma, start, 0, len);
692 dma_write(pvr2dma, 0, dst, len);
693 dma_wait_for_completion(pvr2dma);
694
695 goto out;
696 }
697
698
699 for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
700 if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
701 ret = -ENOSPC;
702 goto out_unmap;
703 }
704
705 dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
706 dma_write_page(pvr2dma, 0, dst);
707 dma_wait_for_completion(pvr2dma);
708 }
709
710out:
711 *ppos += count;
712 ret = count;
713
714out_unmap:
715 unpin_user_pages(pages, nr_pages);
716 kfree(pages);
717
718 return ret;
719}
720#endif
721
722static const struct fb_ops pvr2fb_ops = {
723 .owner = THIS_MODULE,
724 .fb_setcolreg = pvr2fb_setcolreg,
725 .fb_blank = pvr2fb_blank,
726 .fb_check_var = pvr2fb_check_var,
727 .fb_set_par = pvr2fb_set_par,
728#ifdef CONFIG_PVR2_DMA
729 .fb_write = pvr2fb_write,
730#endif
731 .fb_fillrect = cfb_fillrect,
732 .fb_copyarea = cfb_copyarea,
733 .fb_imageblit = cfb_imageblit,
734};
735
736#ifndef MODULE
737static int pvr2_get_param_val(const struct pvr2_params *p, const char *s,
738 int size)
739{
740 int i;
741
742 for (i = 0; i < size; i++) {
743 if (!strncasecmp(p[i].name, s, strlen(s)))
744 return p[i].val;
745 }
746 return -1;
747}
748#endif
749
750static char *pvr2_get_param_name(const struct pvr2_params *p, int val,
751 int size)
752{
753 int i;
754
755 for (i = 0; i < size; i++) {
756 if (p[i].val == val)
757 return p[i].name;
758 }
759 return NULL;
760}
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780static int __maybe_unused pvr2fb_common_init(void)
781{
782 struct pvr2fb_par *par = currentpar;
783 unsigned long modememused, rev;
784
785 fb_info->screen_base = ioremap(pvr2_fix.smem_start,
786 pvr2_fix.smem_len);
787
788 if (!fb_info->screen_base) {
789 printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
790 goto out_err;
791 }
792
793 par->mmio_base = ioremap(pvr2_fix.mmio_start,
794 pvr2_fix.mmio_len);
795 if (!par->mmio_base) {
796 printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
797 goto out_err;
798 }
799
800 fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
801
802 pvr2_fix.ypanstep = nopan ? 0 : 1;
803 pvr2_fix.ywrapstep = nowrap ? 0 : 1;
804
805 fb_info->fbops = &pvr2fb_ops;
806 fb_info->fix = pvr2_fix;
807 fb_info->par = currentpar;
808 fb_info->pseudo_palette = currentpar->palette;
809 fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
810
811 if (video_output == VO_VGA)
812 defmode = DEFMODE_VGA;
813
814 if (!mode_option)
815 mode_option = "640x480@60";
816
817 if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
818 NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
819 fb_info->var = pvr2_var;
820
821 fb_alloc_cmap(&fb_info->cmap, 256, 0);
822
823 if (register_framebuffer(fb_info) < 0)
824 goto out_err;
825
826 pvr2_init_display(fb_info);
827
828 modememused = get_line_length(fb_info->var.xres_virtual,
829 fb_info->var.bits_per_pixel);
830 modememused *= fb_info->var.yres_virtual;
831
832 rev = fb_readl(par->mmio_base + 0x04);
833
834 fb_info(fb_info, "%s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
835 fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
836 modememused >> 10,
837 (unsigned long)(fb_info->fix.smem_len >> 10));
838 fb_info(fb_info, "Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
839 fb_info->var.xres, fb_info->var.yres,
840 fb_info->var.bits_per_pixel,
841 get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
842 pvr2_get_param_name(cables, cable_type, 3),
843 pvr2_get_param_name(outputs, video_output, 3));
844
845#ifdef CONFIG_SH_STORE_QUEUES
846 fb_notice(fb_info, "registering with SQ API\n");
847
848 pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
849 fb_info->fix.id, PAGE_SHARED);
850
851 fb_notice(fb_info, "Mapped video memory to SQ addr 0x%lx\n",
852 pvr2fb_map);
853#endif
854
855 return 0;
856
857out_err:
858 if (fb_info->screen_base)
859 iounmap(fb_info->screen_base);
860 if (par->mmio_base)
861 iounmap(par->mmio_base);
862
863 return -ENXIO;
864}
865
866#ifdef CONFIG_SH_DREAMCAST
867static int __init pvr2fb_dc_init(void)
868{
869 if (!mach_is_dreamcast())
870 return -ENXIO;
871
872
873 if (pvr2_init_cable() == CT_VGA) {
874 fb_info->monspecs.hfmin = 30000;
875 fb_info->monspecs.hfmax = 70000;
876 fb_info->monspecs.vfmin = 60;
877 fb_info->monspecs.vfmax = 60;
878 } else {
879
880 fb_info->monspecs.hfmin = 15469;
881 fb_info->monspecs.hfmax = 15781;
882 fb_info->monspecs.vfmin = 49;
883 fb_info->monspecs.vfmax = 51;
884 }
885
886
887
888
889 if (video_output < 0) {
890 if (cable_type == CT_VGA) {
891 video_output = VO_VGA;
892 } else {
893 video_output = VO_NTSC;
894 }
895 }
896
897
898
899
900 pvr2_fix.smem_start = 0xa5000000;
901 pvr2_fix.smem_len = 8 << 20;
902
903 pvr2_fix.mmio_start = 0xa05f8000;
904 pvr2_fix.mmio_len = 0x2000;
905
906 if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, IRQF_SHARED,
907 "pvr2 VBL handler", fb_info)) {
908 return -EBUSY;
909 }
910
911#ifdef CONFIG_PVR2_DMA
912 if (request_dma(pvr2dma, "pvr2") != 0) {
913 free_irq(HW_EVENT_VSYNC, fb_info);
914 return -EBUSY;
915 }
916#endif
917
918 return pvr2fb_common_init();
919}
920
921static void pvr2fb_dc_exit(void)
922{
923 if (fb_info->screen_base) {
924 iounmap(fb_info->screen_base);
925 fb_info->screen_base = NULL;
926 }
927 if (currentpar->mmio_base) {
928 iounmap(currentpar->mmio_base);
929 currentpar->mmio_base = NULL;
930 }
931
932 free_irq(HW_EVENT_VSYNC, fb_info);
933#ifdef CONFIG_PVR2_DMA
934 free_dma(pvr2dma);
935#endif
936}
937#endif
938
939#ifdef CONFIG_PCI
940static int pvr2fb_pci_probe(struct pci_dev *pdev,
941 const struct pci_device_id *ent)
942{
943 int ret;
944
945 ret = pci_enable_device(pdev);
946 if (ret) {
947 printk(KERN_ERR "pvr2fb: PCI enable failed\n");
948 return ret;
949 }
950
951 ret = pci_request_regions(pdev, "pvr2fb");
952 if (ret) {
953 printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
954 return ret;
955 }
956
957
958
959
960 pvr2_fix.smem_start = pci_resource_start(pdev, 0);
961 pvr2_fix.smem_len = pci_resource_len(pdev, 0);
962
963 pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
964 pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
965
966 fb_info->device = &pdev->dev;
967
968 return pvr2fb_common_init();
969}
970
971static void pvr2fb_pci_remove(struct pci_dev *pdev)
972{
973 if (fb_info->screen_base) {
974 iounmap(fb_info->screen_base);
975 fb_info->screen_base = NULL;
976 }
977 if (currentpar->mmio_base) {
978 iounmap(currentpar->mmio_base);
979 currentpar->mmio_base = NULL;
980 }
981
982 pci_release_regions(pdev);
983}
984
985static const struct pci_device_id pvr2fb_pci_tbl[] = {
986 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
987 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
988 { 0, },
989};
990
991MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
992
993static struct pci_driver pvr2fb_pci_driver = {
994 .name = "pvr2fb",
995 .id_table = pvr2fb_pci_tbl,
996 .probe = pvr2fb_pci_probe,
997 .remove = pvr2fb_pci_remove,
998};
999
1000static int __init pvr2fb_pci_init(void)
1001{
1002 return pci_register_driver(&pvr2fb_pci_driver);
1003}
1004
1005static void pvr2fb_pci_exit(void)
1006{
1007 pci_unregister_driver(&pvr2fb_pci_driver);
1008}
1009#endif
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021#ifndef MODULE
1022static int __init pvr2fb_setup(char *options)
1023{
1024 char *this_opt;
1025 char cable_arg[80];
1026 char output_arg[80];
1027
1028 if (!options || !*options)
1029 return 0;
1030
1031 cable_arg[0] = output_arg[0] = 0;
1032
1033 while ((this_opt = strsep(&options, ","))) {
1034 if (!*this_opt)
1035 continue;
1036 if (!strcmp(this_opt, "inverse")) {
1037 fb_invert_cmaps();
1038 } else if (!strncmp(this_opt, "cable:", 6)) {
1039 strcpy(cable_arg, this_opt + 6);
1040 } else if (!strncmp(this_opt, "output:", 7)) {
1041 strcpy(output_arg, this_opt + 7);
1042 } else if (!strncmp(this_opt, "nopan", 5)) {
1043 nopan = 1;
1044 } else if (!strncmp(this_opt, "nowrap", 6)) {
1045 nowrap = 1;
1046 } else {
1047 mode_option = this_opt;
1048 }
1049 }
1050
1051 if (*cable_arg)
1052 cable_type = pvr2_get_param_val(cables, cable_arg, 3);
1053 if (*output_arg)
1054 video_output = pvr2_get_param_val(outputs, output_arg, 3);
1055
1056 return 0;
1057}
1058#endif
1059
1060static struct pvr2_board {
1061 int (*init)(void);
1062 void (*exit)(void);
1063 char name[16];
1064} board_driver[] __refdata = {
1065#ifdef CONFIG_SH_DREAMCAST
1066 { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
1067#endif
1068#ifdef CONFIG_PCI
1069 { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
1070#endif
1071 { 0, },
1072};
1073
1074static int __init pvr2fb_init(void)
1075{
1076 int i, ret = -ENODEV;
1077
1078#ifndef MODULE
1079 char *option = NULL;
1080
1081 if (fb_get_options("pvr2fb", &option))
1082 return -ENODEV;
1083 pvr2fb_setup(option);
1084#endif
1085
1086 fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
1087 if (!fb_info)
1088 return -ENOMEM;
1089
1090 currentpar = fb_info->par;
1091
1092 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1093 struct pvr2_board *pvr_board = board_driver + i;
1094
1095 if (!pvr_board->init)
1096 continue;
1097
1098 ret = pvr_board->init();
1099
1100 if (ret != 0) {
1101 printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
1102 pvr_board->name);
1103 framebuffer_release(fb_info);
1104 break;
1105 }
1106 }
1107
1108 return ret;
1109}
1110
1111static void __exit pvr2fb_exit(void)
1112{
1113 int i;
1114
1115 for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
1116 struct pvr2_board *pvr_board = board_driver + i;
1117
1118 if (pvr_board->exit)
1119 pvr_board->exit();
1120 }
1121
1122#ifdef CONFIG_SH_STORE_QUEUES
1123 sq_unmap(pvr2fb_map);
1124#endif
1125
1126 unregister_framebuffer(fb_info);
1127 framebuffer_release(fb_info);
1128}
1129
1130module_init(pvr2fb_init);
1131module_exit(pvr2fb_exit);
1132
1133MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
1134MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
1135MODULE_LICENSE("GPL");
1136