linux/drivers/video/fbdev/pxafb.c
<<
>>
Prefs
   1/*
   2 *  linux/drivers/video/pxafb.c
   3 *
   4 *  Copyright (C) 1999 Eric A. Thomas.
   5 *  Copyright (C) 2004 Jean-Frederic Clere.
   6 *  Copyright (C) 2004 Ian Campbell.
   7 *  Copyright (C) 2004 Jeff Lackey.
   8 *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
   9 *  which in turn is
  10 *   Based on acornfb.c Copyright (C) Russell King.
  11 *
  12 * This file is subject to the terms and conditions of the GNU General Public
  13 * License.  See the file COPYING in the main directory of this archive for
  14 * more details.
  15 *
  16 *              Intel PXA250/210 LCD Controller Frame Buffer Driver
  17 *
  18 * Please direct your questions and comments on this driver to the following
  19 * email address:
  20 *
  21 *      linux-arm-kernel@lists.arm.linux.org.uk
  22 *
  23 * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
  24 *
  25 *   Copyright (C) 2004, Intel Corporation
  26 *
  27 *     2003/08/27: <yu.tang@intel.com>
  28 *     2004/03/10: <stanley.cai@intel.com>
  29 *     2004/10/28: <yan.yin@intel.com>
  30 *
  31 *   Copyright (C) 2006-2008 Marvell International Ltd.
  32 *   All Rights Reserved
  33 */
  34
  35#include <linux/module.h>
  36#include <linux/moduleparam.h>
  37#include <linux/kernel.h>
  38#include <linux/sched.h>
  39#include <linux/errno.h>
  40#include <linux/string.h>
  41#include <linux/interrupt.h>
  42#include <linux/slab.h>
  43#include <linux/mm.h>
  44#include <linux/fb.h>
  45#include <linux/delay.h>
  46#include <linux/init.h>
  47#include <linux/ioport.h>
  48#include <linux/cpufreq.h>
  49#include <linux/platform_device.h>
  50#include <linux/dma-mapping.h>
  51#include <linux/clk.h>
  52#include <linux/err.h>
  53#include <linux/completion.h>
  54#include <linux/mutex.h>
  55#include <linux/kthread.h>
  56#include <linux/freezer.h>
  57#include <linux/console.h>
  58#include <linux/of_graph.h>
  59#include <linux/regulator/consumer.h>
  60#include <video/of_display_timing.h>
  61#include <video/videomode.h>
  62
  63#include <mach/hardware.h>
  64#include <asm/io.h>
  65#include <asm/irq.h>
  66#include <asm/div64.h>
  67#include <mach/bitfield.h>
  68#include <linux/platform_data/video-pxafb.h>
  69
  70/*
  71 * Complain if VAR is out of range.
  72 */
  73#define DEBUG_VAR 1
  74
  75#include "pxafb.h"
  76
  77/* Bits which should not be set in machine configuration structures */
  78#define LCCR0_INVALID_CONFIG_MASK       (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
  79                                         LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
  80                                         LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
  81
  82#define LCCR3_INVALID_CONFIG_MASK       (LCCR3_HSP | LCCR3_VSP |\
  83                                         LCCR3_PCD | LCCR3_BPP(0xf))
  84
  85static int pxafb_activate_var(struct fb_var_screeninfo *var,
  86                                struct pxafb_info *);
  87static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  88static void setup_base_frame(struct pxafb_info *fbi,
  89                             struct fb_var_screeninfo *var, int branch);
  90static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
  91                           unsigned long offset, size_t size);
  92
  93static unsigned long video_mem_size = 0;
  94
  95static inline unsigned long
  96lcd_readl(struct pxafb_info *fbi, unsigned int off)
  97{
  98        return __raw_readl(fbi->mmio_base + off);
  99}
 100
 101static inline void
 102lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
 103{
 104        __raw_writel(val, fbi->mmio_base + off);
 105}
 106
 107static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
 108{
 109        unsigned long flags;
 110
 111        local_irq_save(flags);
 112        /*
 113         * We need to handle two requests being made at the same time.
 114         * There are two important cases:
 115         *  1. When we are changing VT (C_REENABLE) while unblanking
 116         *     (C_ENABLE) We must perform the unblanking, which will
 117         *     do our REENABLE for us.
 118         *  2. When we are blanking, but immediately unblank before
 119         *     we have blanked.  We do the "REENABLE" thing here as
 120         *     well, just to be sure.
 121         */
 122        if (fbi->task_state == C_ENABLE && state == C_REENABLE)
 123                state = (u_int) -1;
 124        if (fbi->task_state == C_DISABLE && state == C_ENABLE)
 125                state = C_REENABLE;
 126
 127        if (state != (u_int)-1) {
 128                fbi->task_state = state;
 129                schedule_work(&fbi->task);
 130        }
 131        local_irq_restore(flags);
 132}
 133
 134static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
 135{
 136        chan &= 0xffff;
 137        chan >>= 16 - bf->length;
 138        return chan << bf->offset;
 139}
 140
 141static int
 142pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
 143                       u_int trans, struct fb_info *info)
 144{
 145        struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 146        u_int val;
 147
 148        if (regno >= fbi->palette_size)
 149                return 1;
 150
 151        if (fbi->fb.var.grayscale) {
 152                fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
 153                return 0;
 154        }
 155
 156        switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
 157        case LCCR4_PAL_FOR_0:
 158                val  = ((red   >>  0) & 0xf800);
 159                val |= ((green >>  5) & 0x07e0);
 160                val |= ((blue  >> 11) & 0x001f);
 161                fbi->palette_cpu[regno] = val;
 162                break;
 163        case LCCR4_PAL_FOR_1:
 164                val  = ((red   << 8) & 0x00f80000);
 165                val |= ((green >> 0) & 0x0000fc00);
 166                val |= ((blue  >> 8) & 0x000000f8);
 167                ((u32 *)(fbi->palette_cpu))[regno] = val;
 168                break;
 169        case LCCR4_PAL_FOR_2:
 170                val  = ((red   << 8) & 0x00fc0000);
 171                val |= ((green >> 0) & 0x0000fc00);
 172                val |= ((blue  >> 8) & 0x000000fc);
 173                ((u32 *)(fbi->palette_cpu))[regno] = val;
 174                break;
 175        case LCCR4_PAL_FOR_3:
 176                val  = ((red   << 8) & 0x00ff0000);
 177                val |= ((green >> 0) & 0x0000ff00);
 178                val |= ((blue  >> 8) & 0x000000ff);
 179                ((u32 *)(fbi->palette_cpu))[regno] = val;
 180                break;
 181        }
 182
 183        return 0;
 184}
 185
 186static int
 187pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 188                   u_int trans, struct fb_info *info)
 189{
 190        struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 191        unsigned int val;
 192        int ret = 1;
 193
 194        /*
 195         * If inverse mode was selected, invert all the colours
 196         * rather than the register number.  The register number
 197         * is what you poke into the framebuffer to produce the
 198         * colour you requested.
 199         */
 200        if (fbi->cmap_inverse) {
 201                red   = 0xffff - red;
 202                green = 0xffff - green;
 203                blue  = 0xffff - blue;
 204        }
 205
 206        /*
 207         * If greyscale is true, then we convert the RGB value
 208         * to greyscale no matter what visual we are using.
 209         */
 210        if (fbi->fb.var.grayscale)
 211                red = green = blue = (19595 * red + 38470 * green +
 212                                        7471 * blue) >> 16;
 213
 214        switch (fbi->fb.fix.visual) {
 215        case FB_VISUAL_TRUECOLOR:
 216                /*
 217                 * 16-bit True Colour.  We encode the RGB value
 218                 * according to the RGB bitfield information.
 219                 */
 220                if (regno < 16) {
 221                        u32 *pal = fbi->fb.pseudo_palette;
 222
 223                        val  = chan_to_field(red, &fbi->fb.var.red);
 224                        val |= chan_to_field(green, &fbi->fb.var.green);
 225                        val |= chan_to_field(blue, &fbi->fb.var.blue);
 226
 227                        pal[regno] = val;
 228                        ret = 0;
 229                }
 230                break;
 231
 232        case FB_VISUAL_STATIC_PSEUDOCOLOR:
 233        case FB_VISUAL_PSEUDOCOLOR:
 234                ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
 235                break;
 236        }
 237
 238        return ret;
 239}
 240
 241/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
 242static inline int var_to_depth(struct fb_var_screeninfo *var)
 243{
 244        return var->red.length + var->green.length +
 245                var->blue.length + var->transp.length;
 246}
 247
 248/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
 249static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
 250{
 251        int bpp = -EINVAL;
 252
 253        switch (var->bits_per_pixel) {
 254        case 1:  bpp = 0; break;
 255        case 2:  bpp = 1; break;
 256        case 4:  bpp = 2; break;
 257        case 8:  bpp = 3; break;
 258        case 16: bpp = 4; break;
 259        case 24:
 260                switch (var_to_depth(var)) {
 261                case 18: bpp = 6; break; /* 18-bits/pixel packed */
 262                case 19: bpp = 8; break; /* 19-bits/pixel packed */
 263                case 24: bpp = 9; break;
 264                }
 265                break;
 266        case 32:
 267                switch (var_to_depth(var)) {
 268                case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
 269                case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
 270                case 25: bpp = 10; break;
 271                }
 272                break;
 273        }
 274        return bpp;
 275}
 276
 277/*
 278 *  pxafb_var_to_lccr3():
 279 *    Convert a bits per pixel value to the correct bit pattern for LCCR3
 280 *
 281 *  NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
 282 *  implication of the acutal use of transparency bit,  which we handle it
 283 *  here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
 284 *  Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
 285 *
 286 *  Transparency for palette pixel formats is not supported at the moment.
 287 */
 288static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
 289{
 290        int bpp = pxafb_var_to_bpp(var);
 291        uint32_t lccr3;
 292
 293        if (bpp < 0)
 294                return 0;
 295
 296        lccr3 = LCCR3_BPP(bpp);
 297
 298        switch (var_to_depth(var)) {
 299        case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
 300        case 18: lccr3 |= LCCR3_PDFOR_3; break;
 301        case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
 302                 break;
 303        case 19:
 304        case 25: lccr3 |= LCCR3_PDFOR_0; break;
 305        }
 306        return lccr3;
 307}
 308
 309#define SET_PIXFMT(v, r, g, b, t)                               \
 310({                                                              \
 311        (v)->transp.offset = (t) ? (r) + (g) + (b) : 0;         \
 312        (v)->transp.length = (t) ? (t) : 0;                     \
 313        (v)->blue.length   = (b); (v)->blue.offset = 0;         \
 314        (v)->green.length  = (g); (v)->green.offset = (b);      \
 315        (v)->red.length    = (r); (v)->red.offset = (b) + (g);  \
 316})
 317
 318/* set the RGBT bitfields of fb_var_screeninf according to
 319 * var->bits_per_pixel and given depth
 320 */
 321static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
 322{
 323        if (depth == 0)
 324                depth = var->bits_per_pixel;
 325
 326        if (var->bits_per_pixel < 16) {
 327                /* indexed pixel formats */
 328                var->red.offset    = 0; var->red.length    = 8;
 329                var->green.offset  = 0; var->green.length  = 8;
 330                var->blue.offset   = 0; var->blue.length   = 8;
 331                var->transp.offset = 0; var->transp.length = 8;
 332        }
 333
 334        switch (depth) {
 335        case 16: var->transp.length ?
 336                 SET_PIXFMT(var, 5, 5, 5, 1) :          /* RGBT555 */
 337                 SET_PIXFMT(var, 5, 6, 5, 0); break;    /* RGB565 */
 338        case 18: SET_PIXFMT(var, 6, 6, 6, 0); break;    /* RGB666 */
 339        case 19: SET_PIXFMT(var, 6, 6, 6, 1); break;    /* RGBT666 */
 340        case 24: var->transp.length ?
 341                 SET_PIXFMT(var, 8, 8, 7, 1) :          /* RGBT887 */
 342                 SET_PIXFMT(var, 8, 8, 8, 0); break;    /* RGB888 */
 343        case 25: SET_PIXFMT(var, 8, 8, 8, 1); break;    /* RGBT888 */
 344        }
 345}
 346
 347#ifdef CONFIG_CPU_FREQ
 348/*
 349 *  pxafb_display_dma_period()
 350 *    Calculate the minimum period (in picoseconds) between two DMA
 351 *    requests for the LCD controller.  If we hit this, it means we're
 352 *    doing nothing but LCD DMA.
 353 */
 354static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
 355{
 356        /*
 357         * Period = pixclock * bits_per_byte * bytes_per_transfer
 358         *              / memory_bits_per_pixel;
 359         */
 360        return var->pixclock * 8 * 16 / var->bits_per_pixel;
 361}
 362#endif
 363
 364/*
 365 * Select the smallest mode that allows the desired resolution to be
 366 * displayed. If desired parameters can be rounded up.
 367 */
 368static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
 369                                             struct fb_var_screeninfo *var)
 370{
 371        struct pxafb_mode_info *mode = NULL;
 372        struct pxafb_mode_info *modelist = mach->modes;
 373        unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
 374        unsigned int i;
 375
 376        for (i = 0; i < mach->num_modes; i++) {
 377                if (modelist[i].xres >= var->xres &&
 378                    modelist[i].yres >= var->yres &&
 379                    modelist[i].xres < best_x &&
 380                    modelist[i].yres < best_y &&
 381                    modelist[i].bpp >= var->bits_per_pixel) {
 382                        best_x = modelist[i].xres;
 383                        best_y = modelist[i].yres;
 384                        mode = &modelist[i];
 385                }
 386        }
 387
 388        return mode;
 389}
 390
 391static void pxafb_setmode(struct fb_var_screeninfo *var,
 392                          struct pxafb_mode_info *mode)
 393{
 394        var->xres               = mode->xres;
 395        var->yres               = mode->yres;
 396        var->bits_per_pixel     = mode->bpp;
 397        var->pixclock           = mode->pixclock;
 398        var->hsync_len          = mode->hsync_len;
 399        var->left_margin        = mode->left_margin;
 400        var->right_margin       = mode->right_margin;
 401        var->vsync_len          = mode->vsync_len;
 402        var->upper_margin       = mode->upper_margin;
 403        var->lower_margin       = mode->lower_margin;
 404        var->sync               = mode->sync;
 405        var->grayscale          = mode->cmap_greyscale;
 406        var->transp.length      = mode->transparency;
 407
 408        /* set the initial RGBA bitfields */
 409        pxafb_set_pixfmt(var, mode->depth);
 410}
 411
 412static int pxafb_adjust_timing(struct pxafb_info *fbi,
 413                               struct fb_var_screeninfo *var)
 414{
 415        int line_length;
 416
 417        var->xres = max_t(int, var->xres, MIN_XRES);
 418        var->yres = max_t(int, var->yres, MIN_YRES);
 419
 420        if (!(fbi->lccr0 & LCCR0_LCDT)) {
 421                clamp_val(var->hsync_len, 1, 64);
 422                clamp_val(var->vsync_len, 1, 64);
 423                clamp_val(var->left_margin,  1, 255);
 424                clamp_val(var->right_margin, 1, 255);
 425                clamp_val(var->upper_margin, 1, 255);
 426                clamp_val(var->lower_margin, 1, 255);
 427        }
 428
 429        /* make sure each line is aligned on word boundary */
 430        line_length = var->xres * var->bits_per_pixel / 8;
 431        line_length = ALIGN(line_length, 4);
 432        var->xres = line_length * 8 / var->bits_per_pixel;
 433
 434        /* we don't support xpan, force xres_virtual to be equal to xres */
 435        var->xres_virtual = var->xres;
 436
 437        if (var->accel_flags & FB_ACCELF_TEXT)
 438                var->yres_virtual = fbi->fb.fix.smem_len / line_length;
 439        else
 440                var->yres_virtual = max(var->yres_virtual, var->yres);
 441
 442        /* check for limits */
 443        if (var->xres > MAX_XRES || var->yres > MAX_YRES)
 444                return -EINVAL;
 445
 446        if (var->yres > var->yres_virtual)
 447                return -EINVAL;
 448
 449        return 0;
 450}
 451
 452/*
 453 *  pxafb_check_var():
 454 *    Get the video params out of 'var'. If a value doesn't fit, round it up,
 455 *    if it's too big, return -EINVAL.
 456 *
 457 *    Round up in the following order: bits_per_pixel, xres,
 458 *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
 459 *    bitfields, horizontal timing, vertical timing.
 460 */
 461static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 462{
 463        struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 464        struct pxafb_mach_info *inf = fbi->inf;
 465        int err;
 466
 467        if (inf->fixed_modes) {
 468                struct pxafb_mode_info *mode;
 469
 470                mode = pxafb_getmode(inf, var);
 471                if (!mode)
 472                        return -EINVAL;
 473                pxafb_setmode(var, mode);
 474        }
 475
 476        /* do a test conversion to BPP fields to check the color formats */
 477        err = pxafb_var_to_bpp(var);
 478        if (err < 0)
 479                return err;
 480
 481        pxafb_set_pixfmt(var, var_to_depth(var));
 482
 483        err = pxafb_adjust_timing(fbi, var);
 484        if (err)
 485                return err;
 486
 487#ifdef CONFIG_CPU_FREQ
 488        pr_debug("pxafb: dma period = %d ps\n",
 489                 pxafb_display_dma_period(var));
 490#endif
 491
 492        return 0;
 493}
 494
 495/*
 496 * pxafb_set_par():
 497 *      Set the user defined part of the display for the specified console
 498 */
 499static int pxafb_set_par(struct fb_info *info)
 500{
 501        struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 502        struct fb_var_screeninfo *var = &info->var;
 503
 504        if (var->bits_per_pixel >= 16)
 505                fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 506        else if (!fbi->cmap_static)
 507                fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 508        else {
 509                /*
 510                 * Some people have weird ideas about wanting static
 511                 * pseudocolor maps.  I suspect their user space
 512                 * applications are broken.
 513                 */
 514                fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
 515        }
 516
 517        fbi->fb.fix.line_length = var->xres_virtual *
 518                                  var->bits_per_pixel / 8;
 519        if (var->bits_per_pixel >= 16)
 520                fbi->palette_size = 0;
 521        else
 522                fbi->palette_size = var->bits_per_pixel == 1 ?
 523                                        4 : 1 << var->bits_per_pixel;
 524
 525        fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
 526
 527        if (fbi->fb.var.bits_per_pixel >= 16)
 528                fb_dealloc_cmap(&fbi->fb.cmap);
 529        else
 530                fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
 531
 532        pxafb_activate_var(var, fbi);
 533
 534        return 0;
 535}
 536
 537static int pxafb_pan_display(struct fb_var_screeninfo *var,
 538                             struct fb_info *info)
 539{
 540        struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 541        struct fb_var_screeninfo newvar;
 542        int dma = DMA_MAX + DMA_BASE;
 543
 544        if (fbi->state != C_ENABLE)
 545                return 0;
 546
 547        /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
 548         * was passed in and copy the rest from the old screeninfo.
 549         */
 550        memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
 551        newvar.xoffset = var->xoffset;
 552        newvar.yoffset = var->yoffset;
 553        newvar.vmode &= ~FB_VMODE_YWRAP;
 554        newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
 555
 556        setup_base_frame(fbi, &newvar, 1);
 557
 558        if (fbi->lccr0 & LCCR0_SDS)
 559                lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
 560
 561        lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
 562        return 0;
 563}
 564
 565/*
 566 * pxafb_blank():
 567 *      Blank the display by setting all palette values to zero.  Note, the
 568 *      16 bpp mode does not really use the palette, so this will not
 569 *      blank the display in all modes.
 570 */
 571static int pxafb_blank(int blank, struct fb_info *info)
 572{
 573        struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 574        int i;
 575
 576        switch (blank) {
 577        case FB_BLANK_POWERDOWN:
 578        case FB_BLANK_VSYNC_SUSPEND:
 579        case FB_BLANK_HSYNC_SUSPEND:
 580        case FB_BLANK_NORMAL:
 581                if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 582                    fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 583                        for (i = 0; i < fbi->palette_size; i++)
 584                                pxafb_setpalettereg(i, 0, 0, 0, 0, info);
 585
 586                pxafb_schedule_work(fbi, C_DISABLE);
 587                /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
 588                break;
 589
 590        case FB_BLANK_UNBLANK:
 591                /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
 592                if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 593                    fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 594                        fb_set_cmap(&fbi->fb.cmap, info);
 595                pxafb_schedule_work(fbi, C_ENABLE);
 596        }
 597        return 0;
 598}
 599
 600static struct fb_ops pxafb_ops = {
 601        .owner          = THIS_MODULE,
 602        .fb_check_var   = pxafb_check_var,
 603        .fb_set_par     = pxafb_set_par,
 604        .fb_pan_display = pxafb_pan_display,
 605        .fb_setcolreg   = pxafb_setcolreg,
 606        .fb_fillrect    = cfb_fillrect,
 607        .fb_copyarea    = cfb_copyarea,
 608        .fb_imageblit   = cfb_imageblit,
 609        .fb_blank       = pxafb_blank,
 610};
 611
 612#ifdef CONFIG_FB_PXA_OVERLAY
 613static void overlay1fb_setup(struct pxafb_layer *ofb)
 614{
 615        int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
 616        unsigned long start = ofb->video_mem_phys;
 617        setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
 618}
 619
 620/* Depending on the enable status of overlay1/2, the DMA should be
 621 * updated from FDADRx (when disabled) or FBRx (when enabled).
 622 */
 623static void overlay1fb_enable(struct pxafb_layer *ofb)
 624{
 625        int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
 626        uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
 627
 628        lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
 629        lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
 630        lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
 631}
 632
 633static void overlay1fb_disable(struct pxafb_layer *ofb)
 634{
 635        uint32_t lccr5;
 636
 637        if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN))
 638                return;
 639
 640        lccr5 = lcd_readl(ofb->fbi, LCCR5);
 641
 642        lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
 643
 644        lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
 645        lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
 646        lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
 647
 648        if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
 649                pr_warn("%s: timeout disabling overlay1\n", __func__);
 650
 651        lcd_writel(ofb->fbi, LCCR5, lccr5);
 652}
 653
 654static void overlay2fb_setup(struct pxafb_layer *ofb)
 655{
 656        int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
 657        unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
 658
 659        if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
 660                size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
 661                setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
 662        } else {
 663                size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
 664                switch (pfor) {
 665                case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
 666                case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
 667                case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
 668                }
 669                start[1] = start[0] + size;
 670                start[2] = start[1] + size / div;
 671                setup_frame_dma(ofb->fbi, DMA_OV2_Y,  -1, start[0], size);
 672                setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
 673                setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
 674        }
 675}
 676
 677static void overlay2fb_enable(struct pxafb_layer *ofb)
 678{
 679        int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
 680        int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
 681        uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y]  | (enabled ? 0x1 : 0);
 682        uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
 683        uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
 684
 685        if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
 686                lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
 687        else {
 688                lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
 689                lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
 690                lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
 691        }
 692        lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
 693        lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
 694}
 695
 696static void overlay2fb_disable(struct pxafb_layer *ofb)
 697{
 698        uint32_t lccr5;
 699
 700        if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN))
 701                return;
 702
 703        lccr5 = lcd_readl(ofb->fbi, LCCR5);
 704
 705        lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
 706
 707        lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
 708        lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
 709        lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y]  | 0x3);
 710        lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
 711        lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
 712
 713        if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
 714                pr_warn("%s: timeout disabling overlay2\n", __func__);
 715}
 716
 717static struct pxafb_layer_ops ofb_ops[] = {
 718        [0] = {
 719                .enable         = overlay1fb_enable,
 720                .disable        = overlay1fb_disable,
 721                .setup          = overlay1fb_setup,
 722        },
 723        [1] = {
 724                .enable         = overlay2fb_enable,
 725                .disable        = overlay2fb_disable,
 726                .setup          = overlay2fb_setup,
 727        },
 728};
 729
 730static int overlayfb_open(struct fb_info *info, int user)
 731{
 732        struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
 733
 734        /* no support for framebuffer console on overlay */
 735        if (user == 0)
 736                return -ENODEV;
 737
 738        if (ofb->usage++ == 0) {
 739                /* unblank the base framebuffer */
 740                console_lock();
 741                fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
 742                console_unlock();
 743        }
 744
 745        return 0;
 746}
 747
 748static int overlayfb_release(struct fb_info *info, int user)
 749{
 750        struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
 751
 752        if (ofb->usage == 1) {
 753                ofb->ops->disable(ofb);
 754                ofb->fb.var.height      = -1;
 755                ofb->fb.var.width       = -1;
 756                ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0;
 757                ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0;
 758
 759                ofb->usage--;
 760        }
 761        return 0;
 762}
 763
 764static int overlayfb_check_var(struct fb_var_screeninfo *var,
 765                               struct fb_info *info)
 766{
 767        struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
 768        struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
 769        int xpos, ypos, pfor, bpp;
 770
 771        xpos = NONSTD_TO_XPOS(var->nonstd);
 772        ypos = NONSTD_TO_YPOS(var->nonstd);
 773        pfor = NONSTD_TO_PFOR(var->nonstd);
 774
 775        bpp = pxafb_var_to_bpp(var);
 776        if (bpp < 0)
 777                return -EINVAL;
 778
 779        /* no support for YUV format on overlay1 */
 780        if (ofb->id == OVERLAY1 && pfor != 0)
 781                return -EINVAL;
 782
 783        /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
 784        switch (pfor) {
 785        case OVERLAY_FORMAT_RGB:
 786                bpp = pxafb_var_to_bpp(var);
 787                if (bpp < 0)
 788                        return -EINVAL;
 789
 790                pxafb_set_pixfmt(var, var_to_depth(var));
 791                break;
 792        case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
 793        case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
 794        case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
 795        case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
 796        default:
 797                return -EINVAL;
 798        }
 799
 800        /* each line must start at a 32-bit word boundary */
 801        if ((xpos * bpp) % 32)
 802                return -EINVAL;
 803
 804        /* xres must align on 32-bit word boundary */
 805        var->xres = roundup(var->xres * bpp, 32) / bpp;
 806
 807        if ((xpos + var->xres > base_var->xres) ||
 808            (ypos + var->yres > base_var->yres))
 809                return -EINVAL;
 810
 811        var->xres_virtual = var->xres;
 812        var->yres_virtual = max(var->yres, var->yres_virtual);
 813        return 0;
 814}
 815
 816static int overlayfb_check_video_memory(struct pxafb_layer *ofb)
 817{
 818        struct fb_var_screeninfo *var = &ofb->fb.var;
 819        int pfor = NONSTD_TO_PFOR(var->nonstd);
 820        int size, bpp = 0;
 821
 822        switch (pfor) {
 823        case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
 824        case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
 825        case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
 826        case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
 827        case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
 828        }
 829
 830        ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
 831
 832        size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
 833
 834        if (ofb->video_mem) {
 835                if (ofb->video_mem_size >= size)
 836                        return 0;
 837        }
 838        return -EINVAL;
 839}
 840
 841static int overlayfb_set_par(struct fb_info *info)
 842{
 843        struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
 844        struct fb_var_screeninfo *var = &info->var;
 845        int xpos, ypos, pfor, bpp, ret;
 846
 847        ret = overlayfb_check_video_memory(ofb);
 848        if (ret)
 849                return ret;
 850
 851        bpp  = pxafb_var_to_bpp(var);
 852        xpos = NONSTD_TO_XPOS(var->nonstd);
 853        ypos = NONSTD_TO_YPOS(var->nonstd);
 854        pfor = NONSTD_TO_PFOR(var->nonstd);
 855
 856        ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
 857                          OVLxC1_BPP(bpp);
 858        ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
 859
 860        if (ofb->id == OVERLAY2)
 861                ofb->control[1] |= OVL2C2_PFOR(pfor);
 862
 863        ofb->ops->setup(ofb);
 864        ofb->ops->enable(ofb);
 865        return 0;
 866}
 867
 868static struct fb_ops overlay_fb_ops = {
 869        .owner                  = THIS_MODULE,
 870        .fb_open                = overlayfb_open,
 871        .fb_release             = overlayfb_release,
 872        .fb_check_var           = overlayfb_check_var,
 873        .fb_set_par             = overlayfb_set_par,
 874};
 875
 876static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb,
 877                               int id)
 878{
 879        sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
 880
 881        ofb->fb.fix.type                = FB_TYPE_PACKED_PIXELS;
 882        ofb->fb.fix.xpanstep            = 0;
 883        ofb->fb.fix.ypanstep            = 1;
 884
 885        ofb->fb.var.activate            = FB_ACTIVATE_NOW;
 886        ofb->fb.var.height              = -1;
 887        ofb->fb.var.width               = -1;
 888        ofb->fb.var.vmode               = FB_VMODE_NONINTERLACED;
 889
 890        ofb->fb.fbops                   = &overlay_fb_ops;
 891        ofb->fb.flags                   = FBINFO_FLAG_DEFAULT;
 892        ofb->fb.node                    = -1;
 893        ofb->fb.pseudo_palette          = NULL;
 894
 895        ofb->id = id;
 896        ofb->ops = &ofb_ops[id];
 897        ofb->usage = 0;
 898        ofb->fbi = fbi;
 899        init_completion(&ofb->branch_done);
 900}
 901
 902static inline int pxafb_overlay_supported(void)
 903{
 904        if (cpu_is_pxa27x() || cpu_is_pxa3xx())
 905                return 1;
 906
 907        return 0;
 908}
 909
 910static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb,
 911                                          struct pxafb_layer *ofb)
 912{
 913        /* We assume that user will use at most video_mem_size for overlay fb,
 914         * anyway, it's useless to use 16bpp main plane and 24bpp overlay
 915         */
 916        ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size),
 917                GFP_KERNEL | __GFP_ZERO);
 918        if (ofb->video_mem == NULL)
 919                return -ENOMEM;
 920
 921        ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
 922        ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size);
 923
 924        mutex_lock(&ofb->fb.mm_lock);
 925        ofb->fb.fix.smem_start  = ofb->video_mem_phys;
 926        ofb->fb.fix.smem_len    = pxafb->video_mem_size;
 927        mutex_unlock(&ofb->fb.mm_lock);
 928
 929        ofb->fb.screen_base     = ofb->video_mem;
 930
 931        return 0;
 932}
 933
 934static void pxafb_overlay_init(struct pxafb_info *fbi)
 935{
 936        int i, ret;
 937
 938        if (!pxafb_overlay_supported())
 939                return;
 940
 941        for (i = 0; i < 2; i++) {
 942                struct pxafb_layer *ofb = &fbi->overlay[i];
 943                init_pxafb_overlay(fbi, ofb, i);
 944                ret = register_framebuffer(&ofb->fb);
 945                if (ret) {
 946                        dev_err(fbi->dev, "failed to register overlay %d\n", i);
 947                        continue;
 948                }
 949                ret = pxafb_overlay_map_video_memory(fbi, ofb);
 950                if (ret) {
 951                        dev_err(fbi->dev,
 952                                "failed to map video memory for overlay %d\n",
 953                                i);
 954                        unregister_framebuffer(&ofb->fb);
 955                        continue;
 956                }
 957                ofb->registered = 1;
 958        }
 959
 960        /* mask all IU/BS/EOF/SOF interrupts */
 961        lcd_writel(fbi, LCCR5, ~0);
 962
 963        pr_info("PXA Overlay driver loaded successfully!\n");
 964}
 965
 966static void pxafb_overlay_exit(struct pxafb_info *fbi)
 967{
 968        int i;
 969
 970        if (!pxafb_overlay_supported())
 971                return;
 972
 973        for (i = 0; i < 2; i++) {
 974                struct pxafb_layer *ofb = &fbi->overlay[i];
 975                if (ofb->registered) {
 976                        if (ofb->video_mem)
 977                                free_pages_exact(ofb->video_mem,
 978                                        ofb->video_mem_size);
 979                        unregister_framebuffer(&ofb->fb);
 980                }
 981        }
 982}
 983#else
 984static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
 985static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
 986#endif /* CONFIG_FB_PXA_OVERLAY */
 987
 988/*
 989 * Calculate the PCD value from the clock rate (in picoseconds).
 990 * We take account of the PPCR clock setting.
 991 * From PXA Developer's Manual:
 992 *
 993 *   PixelClock =      LCLK
 994 *                -------------
 995 *                2 ( PCD + 1 )
 996 *
 997 *   PCD =      LCLK
 998 *         ------------- - 1
 999 *         2(PixelClock)
1000 *
1001 * Where:
1002 *   LCLK = LCD/Memory Clock
1003 *   PCD = LCCR3[7:0]
1004 *
1005 * PixelClock here is in Hz while the pixclock argument given is the
1006 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
1007 *
1008 * The function get_lclk_frequency_10khz returns LCLK in units of
1009 * 10khz. Calling the result of this function lclk gives us the
1010 * following
1011 *
1012 *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
1013 *          -------------------------------------- - 1
1014 *                          2
1015 *
1016 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
1017 */
1018static inline unsigned int get_pcd(struct pxafb_info *fbi,
1019                                   unsigned int pixclock)
1020{
1021        unsigned long long pcd;
1022
1023        /* FIXME: Need to take into account Double Pixel Clock mode
1024         * (DPC) bit? or perhaps set it based on the various clock
1025         * speeds */
1026        pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
1027        pcd *= pixclock;
1028        do_div(pcd, 100000000 * 2);
1029        /* no need for this, since we should subtract 1 anyway. they cancel */
1030        /* pcd += 1; */ /* make up for integer math truncations */
1031        return (unsigned int)pcd;
1032}
1033
1034/*
1035 * Some touchscreens need hsync information from the video driver to
1036 * function correctly. We export it here.  Note that 'hsync_time' and
1037 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
1038 * of the hsync period in seconds.
1039 */
1040static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1041{
1042        unsigned long htime;
1043
1044        if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
1045                fbi->hsync_time = 0;
1046                return;
1047        }
1048
1049        htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1050
1051        fbi->hsync_time = htime;
1052}
1053
1054unsigned long pxafb_get_hsync_time(struct device *dev)
1055{
1056        struct pxafb_info *fbi = dev_get_drvdata(dev);
1057
1058        /* If display is blanked/suspended, hsync isn't active */
1059        if (!fbi || (fbi->state != C_ENABLE))
1060                return 0;
1061
1062        return fbi->hsync_time;
1063}
1064EXPORT_SYMBOL(pxafb_get_hsync_time);
1065
1066static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1067                           unsigned long start, size_t size)
1068{
1069        struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1070        unsigned int dma_desc_off, pal_desc_off;
1071
1072        if (dma < 0 || dma >= DMA_MAX * 2)
1073                return -EINVAL;
1074
1075        dma_desc = &fbi->dma_buff->dma_desc[dma];
1076        dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1077
1078        dma_desc->fsadr = start;
1079        dma_desc->fidr  = 0;
1080        dma_desc->ldcmd = size;
1081
1082        if (pal < 0 || pal >= PAL_MAX * 2) {
1083                dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1084                fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1085        } else {
1086                pal_desc = &fbi->dma_buff->pal_desc[pal];
1087                pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1088
1089                pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1090                pal_desc->fidr  = 0;
1091
1092                if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1093                        pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1094                else
1095                        pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1096
1097                pal_desc->ldcmd |= LDCMD_PAL;
1098
1099                /* flip back and forth between palette and frame buffer */
1100                pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1101                dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1102                fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1103        }
1104
1105        return 0;
1106}
1107
1108static void setup_base_frame(struct pxafb_info *fbi,
1109                             struct fb_var_screeninfo *var,
1110                             int branch)
1111{
1112        struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1113        int nbytes, dma, pal, bpp = var->bits_per_pixel;
1114        unsigned long offset;
1115
1116        dma = DMA_BASE + (branch ? DMA_MAX : 0);
1117        pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1118
1119        nbytes = fix->line_length * var->yres;
1120        offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1121
1122        if (fbi->lccr0 & LCCR0_SDS) {
1123                nbytes = nbytes / 2;
1124                setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1125        }
1126
1127        setup_frame_dma(fbi, dma, pal, offset, nbytes);
1128}
1129
1130#ifdef CONFIG_FB_PXA_SMARTPANEL
1131static int setup_smart_dma(struct pxafb_info *fbi)
1132{
1133        struct pxafb_dma_descriptor *dma_desc;
1134        unsigned long dma_desc_off, cmd_buff_off;
1135
1136        dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1137        dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1138        cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1139
1140        dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1141        dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1142        dma_desc->fidr  = 0;
1143        dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1144
1145        fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1146        return 0;
1147}
1148
1149int pxafb_smart_flush(struct fb_info *info)
1150{
1151        struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1152        uint32_t prsr;
1153        int ret = 0;
1154
1155        /* disable controller until all registers are set up */
1156        lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1157
1158        /* 1. make it an even number of commands to align on 32-bit boundary
1159         * 2. add the interrupt command to the end of the chain so we can
1160         *    keep track of the end of the transfer
1161         */
1162
1163        while (fbi->n_smart_cmds & 1)
1164                fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1165
1166        fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1167        fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1168        setup_smart_dma(fbi);
1169
1170        /* continue to execute next command */
1171        prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1172        lcd_writel(fbi, PRSR, prsr);
1173
1174        /* stop the processor in case it executed "wait for sync" cmd */
1175        lcd_writel(fbi, CMDCR, 0x0001);
1176
1177        /* don't send interrupts for fifo underruns on channel 6 */
1178        lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1179
1180        lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1181        lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1182        lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1183        lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1184        lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1185        lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1186
1187        /* begin sending */
1188        lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1189
1190        if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1191                pr_warn("%s: timeout waiting for command done\n", __func__);
1192                ret = -ETIMEDOUT;
1193        }
1194
1195        /* quick disable */
1196        prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1197        lcd_writel(fbi, PRSR, prsr);
1198        lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1199        lcd_writel(fbi, FDADR6, 0);
1200        fbi->n_smart_cmds = 0;
1201        return ret;
1202}
1203
1204int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1205{
1206        int i;
1207        struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1208
1209        for (i = 0; i < n_cmds; i++, cmds++) {
1210                /* if it is a software delay, flush and delay */
1211                if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1212                        pxafb_smart_flush(info);
1213                        mdelay(*cmds & 0xff);
1214                        continue;
1215                }
1216
1217                /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1218                if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1219                        pxafb_smart_flush(info);
1220
1221                fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1222        }
1223
1224        return 0;
1225}
1226
1227static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1228{
1229        unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1230        return (t == 0) ? 1 : t;
1231}
1232
1233static void setup_smart_timing(struct pxafb_info *fbi,
1234                                struct fb_var_screeninfo *var)
1235{
1236        struct pxafb_mach_info *inf = fbi->inf;
1237        struct pxafb_mode_info *mode = &inf->modes[0];
1238        unsigned long lclk = clk_get_rate(fbi->clk);
1239        unsigned t1, t2, t3, t4;
1240
1241        t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1242        t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1243        t3 = mode->op_hold_time;
1244        t4 = mode->cmd_inh_time;
1245
1246        fbi->reg_lccr1 =
1247                LCCR1_DisWdth(var->xres) |
1248                LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1249                LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1250                LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1251
1252        fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1253        fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1254        fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1255        fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1256
1257        /* FIXME: make this configurable */
1258        fbi->reg_cmdcr = 1;
1259}
1260
1261static int pxafb_smart_thread(void *arg)
1262{
1263        struct pxafb_info *fbi = arg;
1264        struct pxafb_mach_info *inf = fbi->inf;
1265
1266        if (!inf->smart_update) {
1267                pr_err("%s: not properly initialized, thread terminated\n",
1268                                __func__);
1269                return -EINVAL;
1270        }
1271
1272        pr_debug("%s(): task starting\n", __func__);
1273
1274        set_freezable();
1275        while (!kthread_should_stop()) {
1276
1277                if (try_to_freeze())
1278                        continue;
1279
1280                mutex_lock(&fbi->ctrlr_lock);
1281
1282                if (fbi->state == C_ENABLE) {
1283                        inf->smart_update(&fbi->fb);
1284                        complete(&fbi->refresh_done);
1285                }
1286
1287                mutex_unlock(&fbi->ctrlr_lock);
1288
1289                set_current_state(TASK_INTERRUPTIBLE);
1290                schedule_timeout(msecs_to_jiffies(30));
1291        }
1292
1293        pr_debug("%s(): task ending\n", __func__);
1294        return 0;
1295}
1296
1297static int pxafb_smart_init(struct pxafb_info *fbi)
1298{
1299        if (!(fbi->lccr0 & LCCR0_LCDT))
1300                return 0;
1301
1302        fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1303        fbi->n_smart_cmds = 0;
1304
1305        init_completion(&fbi->command_done);
1306        init_completion(&fbi->refresh_done);
1307
1308        fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1309                                        "lcd_refresh");
1310        if (IS_ERR(fbi->smart_thread)) {
1311                pr_err("%s: unable to create kernel thread\n", __func__);
1312                return PTR_ERR(fbi->smart_thread);
1313        }
1314
1315        return 0;
1316}
1317#else
1318static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1319#endif /* CONFIG_FB_PXA_SMARTPANEL */
1320
1321static void setup_parallel_timing(struct pxafb_info *fbi,
1322                                  struct fb_var_screeninfo *var)
1323{
1324        unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1325
1326        fbi->reg_lccr1 =
1327                LCCR1_DisWdth(var->xres) +
1328                LCCR1_HorSnchWdth(var->hsync_len) +
1329                LCCR1_BegLnDel(var->left_margin) +
1330                LCCR1_EndLnDel(var->right_margin);
1331
1332        /*
1333         * If we have a dual scan LCD, we need to halve
1334         * the YRES parameter.
1335         */
1336        lines_per_panel = var->yres;
1337        if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1338                lines_per_panel /= 2;
1339
1340        fbi->reg_lccr2 =
1341                LCCR2_DisHght(lines_per_panel) +
1342                LCCR2_VrtSnchWdth(var->vsync_len) +
1343                LCCR2_BegFrmDel(var->upper_margin) +
1344                LCCR2_EndFrmDel(var->lower_margin);
1345
1346        fbi->reg_lccr3 = fbi->lccr3 |
1347                (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1348                 LCCR3_HorSnchH : LCCR3_HorSnchL) |
1349                (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1350                 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1351
1352        if (pcd) {
1353                fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1354                set_hsync_time(fbi, pcd);
1355        }
1356}
1357
1358/*
1359 * pxafb_activate_var():
1360 *      Configures LCD Controller based on entries in var parameter.
1361 *      Settings are only written to the controller if changes were made.
1362 */
1363static int pxafb_activate_var(struct fb_var_screeninfo *var,
1364                              struct pxafb_info *fbi)
1365{
1366        u_long flags;
1367
1368        /* Update shadow copy atomically */
1369        local_irq_save(flags);
1370
1371#ifdef CONFIG_FB_PXA_SMARTPANEL
1372        if (fbi->lccr0 & LCCR0_LCDT)
1373                setup_smart_timing(fbi, var);
1374        else
1375#endif
1376                setup_parallel_timing(fbi, var);
1377
1378        setup_base_frame(fbi, var, 0);
1379
1380        fbi->reg_lccr0 = fbi->lccr0 |
1381                (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1382                 LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
1383
1384        fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1385
1386        fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1387        fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1388        local_irq_restore(flags);
1389
1390        /*
1391         * Only update the registers if the controller is enabled
1392         * and something has changed.
1393         */
1394        if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1395            (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1396            (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1397            (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1398            (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1399            (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1400            ((fbi->lccr0 & LCCR0_SDS) &&
1401            (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])))
1402                pxafb_schedule_work(fbi, C_REENABLE);
1403
1404        return 0;
1405}
1406
1407/*
1408 * NOTE!  The following functions are purely helpers for set_ctrlr_state.
1409 * Do not call them directly; set_ctrlr_state does the correct serialisation
1410 * to ensure that things happen in the right way 100% of time time.
1411 *      -- rmk
1412 */
1413static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1414{
1415        pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1416
1417        if (fbi->backlight_power)
1418                fbi->backlight_power(on);
1419}
1420
1421static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1422{
1423        pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1424
1425        if (fbi->lcd_power)
1426                fbi->lcd_power(on, &fbi->fb.var);
1427
1428        if (fbi->lcd_supply && fbi->lcd_supply_enabled != on) {
1429                int ret;
1430
1431                if (on)
1432                        ret = regulator_enable(fbi->lcd_supply);
1433                else
1434                        ret = regulator_disable(fbi->lcd_supply);
1435
1436                if (ret < 0)
1437                        pr_warn("Unable to %s LCD supply regulator: %d\n",
1438                                on ? "enable" : "disable", ret);
1439                else
1440                        fbi->lcd_supply_enabled = on;
1441        }
1442}
1443
1444static void pxafb_enable_controller(struct pxafb_info *fbi)
1445{
1446        pr_debug("pxafb: Enabling LCD controller\n");
1447        pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1448        pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1449        pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1450        pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1451        pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1452        pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1453
1454        /* enable LCD controller clock */
1455        if (clk_prepare_enable(fbi->clk)) {
1456                pr_err("%s: Failed to prepare clock\n", __func__);
1457                return;
1458        }
1459
1460        if (fbi->lccr0 & LCCR0_LCDT)
1461                return;
1462
1463        /* Sequence from 11.7.10 */
1464        lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1465        lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1466        lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1467        lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1468        lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1469
1470        lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1471        if (fbi->lccr0 & LCCR0_SDS)
1472                lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1473        lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1474}
1475
1476static void pxafb_disable_controller(struct pxafb_info *fbi)
1477{
1478        uint32_t lccr0;
1479
1480#ifdef CONFIG_FB_PXA_SMARTPANEL
1481        if (fbi->lccr0 & LCCR0_LCDT) {
1482                wait_for_completion_timeout(&fbi->refresh_done,
1483                                msecs_to_jiffies(200));
1484                return;
1485        }
1486#endif
1487
1488        /* Clear LCD Status Register */
1489        lcd_writel(fbi, LCSR, 0xffffffff);
1490
1491        lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1492        lcd_writel(fbi, LCCR0, lccr0);
1493        lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1494
1495        wait_for_completion_timeout(&fbi->disable_done, msecs_to_jiffies(200));
1496
1497        /* disable LCD controller clock */
1498        clk_disable_unprepare(fbi->clk);
1499}
1500
1501/*
1502 *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1503 */
1504static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1505{
1506        struct pxafb_info *fbi = dev_id;
1507        unsigned int lccr0, lcsr;
1508
1509        lcsr = lcd_readl(fbi, LCSR);
1510        if (lcsr & LCSR_LDD) {
1511                lccr0 = lcd_readl(fbi, LCCR0);
1512                lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1513                complete(&fbi->disable_done);
1514        }
1515
1516#ifdef CONFIG_FB_PXA_SMARTPANEL
1517        if (lcsr & LCSR_CMD_INT)
1518                complete(&fbi->command_done);
1519#endif
1520        lcd_writel(fbi, LCSR, lcsr);
1521
1522#ifdef CONFIG_FB_PXA_OVERLAY
1523        {
1524                unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1525                if (lcsr1 & LCSR1_BS(1))
1526                        complete(&fbi->overlay[0].branch_done);
1527
1528                if (lcsr1 & LCSR1_BS(2))
1529                        complete(&fbi->overlay[1].branch_done);
1530
1531                lcd_writel(fbi, LCSR1, lcsr1);
1532        }
1533#endif
1534        return IRQ_HANDLED;
1535}
1536
1537/*
1538 * This function must be called from task context only, since it will
1539 * sleep when disabling the LCD controller, or if we get two contending
1540 * processes trying to alter state.
1541 */
1542static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1543{
1544        u_int old_state;
1545
1546        mutex_lock(&fbi->ctrlr_lock);
1547
1548        old_state = fbi->state;
1549
1550        /*
1551         * Hack around fbcon initialisation.
1552         */
1553        if (old_state == C_STARTUP && state == C_REENABLE)
1554                state = C_ENABLE;
1555
1556        switch (state) {
1557        case C_DISABLE_CLKCHANGE:
1558                /*
1559                 * Disable controller for clock change.  If the
1560                 * controller is already disabled, then do nothing.
1561                 */
1562                if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1563                        fbi->state = state;
1564                        /* TODO __pxafb_lcd_power(fbi, 0); */
1565                        pxafb_disable_controller(fbi);
1566                }
1567                break;
1568
1569        case C_DISABLE_PM:
1570        case C_DISABLE:
1571                /*
1572                 * Disable controller
1573                 */
1574                if (old_state != C_DISABLE) {
1575                        fbi->state = state;
1576                        __pxafb_backlight_power(fbi, 0);
1577                        __pxafb_lcd_power(fbi, 0);
1578                        if (old_state != C_DISABLE_CLKCHANGE)
1579                                pxafb_disable_controller(fbi);
1580                }
1581                break;
1582
1583        case C_ENABLE_CLKCHANGE:
1584                /*
1585                 * Enable the controller after clock change.  Only
1586                 * do this if we were disabled for the clock change.
1587                 */
1588                if (old_state == C_DISABLE_CLKCHANGE) {
1589                        fbi->state = C_ENABLE;
1590                        pxafb_enable_controller(fbi);
1591                        /* TODO __pxafb_lcd_power(fbi, 1); */
1592                }
1593                break;
1594
1595        case C_REENABLE:
1596                /*
1597                 * Re-enable the controller only if it was already
1598                 * enabled.  This is so we reprogram the control
1599                 * registers.
1600                 */
1601                if (old_state == C_ENABLE) {
1602                        __pxafb_lcd_power(fbi, 0);
1603                        pxafb_disable_controller(fbi);
1604                        pxafb_enable_controller(fbi);
1605                        __pxafb_lcd_power(fbi, 1);
1606                }
1607                break;
1608
1609        case C_ENABLE_PM:
1610                /*
1611                 * Re-enable the controller after PM.  This is not
1612                 * perfect - think about the case where we were doing
1613                 * a clock change, and we suspended half-way through.
1614                 */
1615                if (old_state != C_DISABLE_PM)
1616                        break;
1617                /* fall through */
1618
1619        case C_ENABLE:
1620                /*
1621                 * Power up the LCD screen, enable controller, and
1622                 * turn on the backlight.
1623                 */
1624                if (old_state != C_ENABLE) {
1625                        fbi->state = C_ENABLE;
1626                        pxafb_enable_controller(fbi);
1627                        __pxafb_lcd_power(fbi, 1);
1628                        __pxafb_backlight_power(fbi, 1);
1629                }
1630                break;
1631        }
1632        mutex_unlock(&fbi->ctrlr_lock);
1633}
1634
1635/*
1636 * Our LCD controller task (which is called when we blank or unblank)
1637 * via keventd.
1638 */
1639static void pxafb_task(struct work_struct *work)
1640{
1641        struct pxafb_info *fbi =
1642                container_of(work, struct pxafb_info, task);
1643        u_int state = xchg(&fbi->task_state, -1);
1644
1645        set_ctrlr_state(fbi, state);
1646}
1647
1648#ifdef CONFIG_CPU_FREQ
1649/*
1650 * CPU clock speed change handler.  We need to adjust the LCD timing
1651 * parameters when the CPU clock is adjusted by the power management
1652 * subsystem.
1653 *
1654 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1655 */
1656static int
1657pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1658{
1659        struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1660        /* TODO struct cpufreq_freqs *f = data; */
1661        u_int pcd;
1662
1663        switch (val) {
1664        case CPUFREQ_PRECHANGE:
1665#ifdef CONFIG_FB_PXA_OVERLAY
1666                if (!(fbi->overlay[0].usage || fbi->overlay[1].usage))
1667#endif
1668                        set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1669                break;
1670
1671        case CPUFREQ_POSTCHANGE:
1672                pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1673                set_hsync_time(fbi, pcd);
1674                fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1675                                  LCCR3_PixClkDiv(pcd);
1676                set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1677                break;
1678        }
1679        return 0;
1680}
1681#endif
1682
1683#ifdef CONFIG_PM
1684/*
1685 * Power management hooks.  Note that we won't be called from IRQ context,
1686 * unlike the blank functions above, so we may sleep.
1687 */
1688static int pxafb_suspend(struct device *dev)
1689{
1690        struct pxafb_info *fbi = dev_get_drvdata(dev);
1691
1692        set_ctrlr_state(fbi, C_DISABLE_PM);
1693        return 0;
1694}
1695
1696static int pxafb_resume(struct device *dev)
1697{
1698        struct pxafb_info *fbi = dev_get_drvdata(dev);
1699
1700        set_ctrlr_state(fbi, C_ENABLE_PM);
1701        return 0;
1702}
1703
1704static const struct dev_pm_ops pxafb_pm_ops = {
1705        .suspend        = pxafb_suspend,
1706        .resume         = pxafb_resume,
1707};
1708#endif
1709
1710static int pxafb_init_video_memory(struct pxafb_info *fbi)
1711{
1712        int size = PAGE_ALIGN(fbi->video_mem_size);
1713
1714        fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1715        if (fbi->video_mem == NULL)
1716                return -ENOMEM;
1717
1718        fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1719        fbi->video_mem_size = size;
1720
1721        fbi->fb.fix.smem_start  = fbi->video_mem_phys;
1722        fbi->fb.fix.smem_len    = fbi->video_mem_size;
1723        fbi->fb.screen_base     = fbi->video_mem;
1724
1725        return fbi->video_mem ? 0 : -ENOMEM;
1726}
1727
1728static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1729                                   struct pxafb_mach_info *inf)
1730{
1731        unsigned int lcd_conn = inf->lcd_conn;
1732        struct pxafb_mode_info *m;
1733        int i;
1734
1735        fbi->cmap_inverse       = inf->cmap_inverse;
1736        fbi->cmap_static        = inf->cmap_static;
1737        fbi->lccr4              = inf->lccr4;
1738
1739        switch (lcd_conn & LCD_TYPE_MASK) {
1740        case LCD_TYPE_MONO_STN:
1741                fbi->lccr0 = LCCR0_CMS;
1742                break;
1743        case LCD_TYPE_MONO_DSTN:
1744                fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1745                break;
1746        case LCD_TYPE_COLOR_STN:
1747                fbi->lccr0 = 0;
1748                break;
1749        case LCD_TYPE_COLOR_DSTN:
1750                fbi->lccr0 = LCCR0_SDS;
1751                break;
1752        case LCD_TYPE_COLOR_TFT:
1753                fbi->lccr0 = LCCR0_PAS;
1754                break;
1755        case LCD_TYPE_SMART_PANEL:
1756                fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1757                break;
1758        default:
1759                /* fall back to backward compatibility way */
1760                fbi->lccr0 = inf->lccr0;
1761                fbi->lccr3 = inf->lccr3;
1762                goto decode_mode;
1763        }
1764
1765        if (lcd_conn == LCD_MONO_STN_8BPP)
1766                fbi->lccr0 |= LCCR0_DPD;
1767
1768        fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1769
1770        fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1771        fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1772        fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
1773
1774decode_mode:
1775        pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1776
1777        /* decide video memory size as follows:
1778         * 1. default to mode of maximum resolution
1779         * 2. allow platform to override
1780         * 3. allow module parameter to override
1781         */
1782        for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1783                fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1784                                m->xres * m->yres * m->bpp / 8);
1785
1786        if (inf->video_mem_size > fbi->video_mem_size)
1787                fbi->video_mem_size = inf->video_mem_size;
1788
1789        if (video_mem_size > fbi->video_mem_size)
1790                fbi->video_mem_size = video_mem_size;
1791}
1792
1793static struct pxafb_info *pxafb_init_fbinfo(struct device *dev,
1794                                            struct pxafb_mach_info *inf)
1795{
1796        struct pxafb_info *fbi;
1797        void *addr;
1798
1799        /* Alloc the pxafb_info and pseudo_palette in one step */
1800        fbi = devm_kzalloc(dev, sizeof(struct pxafb_info) + sizeof(u32) * 16,
1801                           GFP_KERNEL);
1802        if (!fbi)
1803                return ERR_PTR(-ENOMEM);
1804
1805        fbi->dev = dev;
1806        fbi->inf = inf;
1807
1808        fbi->clk = devm_clk_get(dev, NULL);
1809        if (IS_ERR(fbi->clk))
1810                return ERR_CAST(fbi->clk);
1811
1812        strcpy(fbi->fb.fix.id, PXA_NAME);
1813
1814        fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1815        fbi->fb.fix.type_aux    = 0;
1816        fbi->fb.fix.xpanstep    = 0;
1817        fbi->fb.fix.ypanstep    = 1;
1818        fbi->fb.fix.ywrapstep   = 0;
1819        fbi->fb.fix.accel       = FB_ACCEL_NONE;
1820
1821        fbi->fb.var.nonstd      = 0;
1822        fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1823        fbi->fb.var.height      = -1;
1824        fbi->fb.var.width       = -1;
1825        fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1826        fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1827
1828        fbi->fb.fbops           = &pxafb_ops;
1829        fbi->fb.flags           = FBINFO_DEFAULT;
1830        fbi->fb.node            = -1;
1831
1832        addr = fbi;
1833        addr = addr + sizeof(struct pxafb_info);
1834        fbi->fb.pseudo_palette  = addr;
1835
1836        fbi->state              = C_STARTUP;
1837        fbi->task_state         = (u_char)-1;
1838
1839        pxafb_decode_mach_info(fbi, inf);
1840
1841#ifdef CONFIG_FB_PXA_OVERLAY
1842        /* place overlay(s) on top of base */
1843        if (pxafb_overlay_supported())
1844                fbi->lccr0 |= LCCR0_OUC;
1845#endif
1846
1847        init_waitqueue_head(&fbi->ctrlr_wait);
1848        INIT_WORK(&fbi->task, pxafb_task);
1849        mutex_init(&fbi->ctrlr_lock);
1850        init_completion(&fbi->disable_done);
1851
1852        return fbi;
1853}
1854
1855#ifdef CONFIG_FB_PXA_PARAMETERS
1856static int parse_opt_mode(struct device *dev, const char *this_opt,
1857                          struct pxafb_mach_info *inf)
1858{
1859        const char *name = this_opt+5;
1860        unsigned int namelen = strlen(name);
1861        int res_specified = 0, bpp_specified = 0;
1862        unsigned int xres = 0, yres = 0, bpp = 0;
1863        int yres_specified = 0;
1864        int i;
1865        for (i = namelen-1; i >= 0; i--) {
1866                switch (name[i]) {
1867                case '-':
1868                        namelen = i;
1869                        if (!bpp_specified && !yres_specified) {
1870                                bpp = simple_strtoul(&name[i+1], NULL, 0);
1871                                bpp_specified = 1;
1872                        } else
1873                                goto done;
1874                        break;
1875                case 'x':
1876                        if (!yres_specified) {
1877                                yres = simple_strtoul(&name[i+1], NULL, 0);
1878                                yres_specified = 1;
1879                        } else
1880                                goto done;
1881                        break;
1882                case '0' ... '9':
1883                        break;
1884                default:
1885                        goto done;
1886                }
1887        }
1888        if (i < 0 && yres_specified) {
1889                xres = simple_strtoul(name, NULL, 0);
1890                res_specified = 1;
1891        }
1892done:
1893        if (res_specified) {
1894                dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1895                inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1896        }
1897        if (bpp_specified)
1898                switch (bpp) {
1899                case 1:
1900                case 2:
1901                case 4:
1902                case 8:
1903                case 16:
1904                        inf->modes[0].bpp = bpp;
1905                        dev_info(dev, "overriding bit depth: %d\n", bpp);
1906                        break;
1907                default:
1908                        dev_err(dev, "Depth %d is not valid\n", bpp);
1909                        return -EINVAL;
1910                }
1911        return 0;
1912}
1913
1914static int parse_opt(struct device *dev, char *this_opt,
1915                     struct pxafb_mach_info *inf)
1916{
1917        struct pxafb_mode_info *mode = &inf->modes[0];
1918        char s[64];
1919
1920        s[0] = '\0';
1921
1922        if (!strncmp(this_opt, "vmem:", 5)) {
1923                video_mem_size = memparse(this_opt + 5, NULL);
1924        } else if (!strncmp(this_opt, "mode:", 5)) {
1925                return parse_opt_mode(dev, this_opt, inf);
1926        } else if (!strncmp(this_opt, "pixclock:", 9)) {
1927                mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1928                sprintf(s, "pixclock: %ld\n", mode->pixclock);
1929        } else if (!strncmp(this_opt, "left:", 5)) {
1930                mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1931                sprintf(s, "left: %u\n", mode->left_margin);
1932        } else if (!strncmp(this_opt, "right:", 6)) {
1933                mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1934                sprintf(s, "right: %u\n", mode->right_margin);
1935        } else if (!strncmp(this_opt, "upper:", 6)) {
1936                mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1937                sprintf(s, "upper: %u\n", mode->upper_margin);
1938        } else if (!strncmp(this_opt, "lower:", 6)) {
1939                mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1940                sprintf(s, "lower: %u\n", mode->lower_margin);
1941        } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1942                mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1943                sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1944        } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1945                mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1946                sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1947        } else if (!strncmp(this_opt, "hsync:", 6)) {
1948                if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1949                        sprintf(s, "hsync: Active Low\n");
1950                        mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1951                } else {
1952                        sprintf(s, "hsync: Active High\n");
1953                        mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1954                }
1955        } else if (!strncmp(this_opt, "vsync:", 6)) {
1956                if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1957                        sprintf(s, "vsync: Active Low\n");
1958                        mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1959                } else {
1960                        sprintf(s, "vsync: Active High\n");
1961                        mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1962                }
1963        } else if (!strncmp(this_opt, "dpc:", 4)) {
1964                if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1965                        sprintf(s, "double pixel clock: false\n");
1966                        inf->lccr3 &= ~LCCR3_DPC;
1967                } else {
1968                        sprintf(s, "double pixel clock: true\n");
1969                        inf->lccr3 |= LCCR3_DPC;
1970                }
1971        } else if (!strncmp(this_opt, "outputen:", 9)) {
1972                if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1973                        sprintf(s, "output enable: active low\n");
1974                        inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1975                } else {
1976                        sprintf(s, "output enable: active high\n");
1977                        inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1978                }
1979        } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1980                if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1981                        sprintf(s, "pixel clock polarity: falling edge\n");
1982                        inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1983                } else {
1984                        sprintf(s, "pixel clock polarity: rising edge\n");
1985                        inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1986                }
1987        } else if (!strncmp(this_opt, "color", 5)) {
1988                inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1989        } else if (!strncmp(this_opt, "mono", 4)) {
1990                inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1991        } else if (!strncmp(this_opt, "active", 6)) {
1992                inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1993        } else if (!strncmp(this_opt, "passive", 7)) {
1994                inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1995        } else if (!strncmp(this_opt, "single", 6)) {
1996                inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1997        } else if (!strncmp(this_opt, "dual", 4)) {
1998                inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1999        } else if (!strncmp(this_opt, "4pix", 4)) {
2000                inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
2001        } else if (!strncmp(this_opt, "8pix", 4)) {
2002                inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
2003        } else {
2004                dev_err(dev, "unknown option: %s\n", this_opt);
2005                return -EINVAL;
2006        }
2007
2008        if (s[0] != '\0')
2009                dev_info(dev, "override %s", s);
2010
2011        return 0;
2012}
2013
2014static int pxafb_parse_options(struct device *dev, char *options,
2015                               struct pxafb_mach_info *inf)
2016{
2017        char *this_opt;
2018        int ret;
2019
2020        if (!options || !*options)
2021                return 0;
2022
2023        dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
2024
2025        /* could be made table driven or similar?... */
2026        while ((this_opt = strsep(&options, ",")) != NULL) {
2027                ret = parse_opt(dev, this_opt, inf);
2028                if (ret)
2029                        return ret;
2030        }
2031        return 0;
2032}
2033
2034static char g_options[256] = "";
2035
2036#ifndef MODULE
2037static int __init pxafb_setup_options(void)
2038{
2039        char *options = NULL;
2040
2041        if (fb_get_options("pxafb", &options))
2042                return -ENODEV;
2043
2044        if (options)
2045                strlcpy(g_options, options, sizeof(g_options));
2046
2047        return 0;
2048}
2049#else
2050#define pxafb_setup_options()           (0)
2051
2052module_param_string(options, g_options, sizeof(g_options), 0);
2053MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.rst)");
2054#endif
2055
2056#else
2057#define pxafb_parse_options(...)        (0)
2058#define pxafb_setup_options()           (0)
2059#endif
2060
2061#ifdef DEBUG_VAR
2062/* Check for various illegal bit-combinations. Currently only
2063 * a warning is given. */
2064static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf)
2065{
2066        if (inf->lcd_conn)
2067                return;
2068
2069        if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2070                dev_warn(dev, "machine LCCR0 setting contains "
2071                                "illegal bits: %08x\n",
2072                        inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2073        if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2074                dev_warn(dev, "machine LCCR3 setting contains "
2075                                "illegal bits: %08x\n",
2076                        inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2077        if (inf->lccr0 & LCCR0_DPD &&
2078            ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2079             (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2080             (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2081                dev_warn(dev, "Double Pixel Data (DPD) mode is "
2082                                "only valid in passive mono"
2083                                " single panel mode\n");
2084        if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2085            (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2086                dev_warn(dev, "Dual panel only valid in passive mode\n");
2087        if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2088             (inf->modes->upper_margin || inf->modes->lower_margin))
2089                dev_warn(dev, "Upper and lower margins must be 0 in "
2090                                "passive mode\n");
2091}
2092#else
2093#define pxafb_check_options(...)        do {} while (0)
2094#endif
2095
2096#if defined(CONFIG_OF)
2097static const char * const lcd_types[] = {
2098        "unknown", "mono-stn", "mono-dstn", "color-stn", "color-dstn",
2099        "color-tft", "smart-panel", NULL
2100};
2101
2102static int of_get_pxafb_display(struct device *dev, struct device_node *disp,
2103                                struct pxafb_mach_info *info, u32 bus_width)
2104{
2105        struct display_timings *timings;
2106        struct videomode vm;
2107        int i, ret = -EINVAL;
2108        const char *s;
2109
2110        ret = of_property_read_string(disp, "lcd-type", &s);
2111        if (ret)
2112                s = "color-tft";
2113
2114        i = match_string(lcd_types, -1, s);
2115        if (i < 0) {
2116                dev_err(dev, "lcd-type %s is unknown\n", s);
2117                return i;
2118        }
2119        info->lcd_conn |= LCD_CONN_TYPE(i);
2120        info->lcd_conn |= LCD_CONN_WIDTH(bus_width);
2121
2122        timings = of_get_display_timings(disp);
2123        if (!timings)
2124                return -EINVAL;
2125
2126        ret = -ENOMEM;
2127        info->modes = devm_kcalloc(dev, timings->num_timings,
2128                                   sizeof(info->modes[0]),
2129                                   GFP_KERNEL);
2130        if (!info->modes)
2131                goto out;
2132        info->num_modes = timings->num_timings;
2133
2134        for (i = 0; i < timings->num_timings; i++) {
2135                ret = videomode_from_timings(timings, &vm, i);
2136                if (ret) {
2137                        dev_err(dev, "videomode_from_timings %d failed: %d\n",
2138                                i, ret);
2139                        goto out;
2140                }
2141                if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
2142                        info->lcd_conn |= LCD_PCLK_EDGE_RISE;
2143                if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
2144                        info->lcd_conn |= LCD_PCLK_EDGE_FALL;
2145                if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
2146                        info->lcd_conn |= LCD_BIAS_ACTIVE_HIGH;
2147                if (vm.flags & DISPLAY_FLAGS_DE_LOW)
2148                        info->lcd_conn |= LCD_BIAS_ACTIVE_LOW;
2149                if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
2150                        info->modes[i].sync |= FB_SYNC_HOR_HIGH_ACT;
2151                if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
2152                        info->modes[i].sync |= FB_SYNC_VERT_HIGH_ACT;
2153
2154                info->modes[i].pixclock = 1000000000UL / (vm.pixelclock / 1000);
2155                info->modes[i].xres = vm.hactive;
2156                info->modes[i].yres = vm.vactive;
2157                info->modes[i].hsync_len = vm.hsync_len;
2158                info->modes[i].left_margin = vm.hback_porch;
2159                info->modes[i].right_margin = vm.hfront_porch;
2160                info->modes[i].vsync_len = vm.vsync_len;
2161                info->modes[i].upper_margin = vm.vback_porch;
2162                info->modes[i].lower_margin = vm.vfront_porch;
2163        }
2164        ret = 0;
2165
2166out:
2167        display_timings_release(timings);
2168        return ret;
2169}
2170
2171static int of_get_pxafb_mode_info(struct device *dev,
2172                                  struct pxafb_mach_info *info)
2173{
2174        struct device_node *display, *np;
2175        u32 bus_width;
2176        int ret, i;
2177
2178        np = of_graph_get_next_endpoint(dev->of_node, NULL);
2179        if (!np) {
2180                dev_err(dev, "could not find endpoint\n");
2181                return -EINVAL;
2182        }
2183        ret = of_property_read_u32(np, "bus-width", &bus_width);
2184        if (ret) {
2185                dev_err(dev, "no bus-width specified: %d\n", ret);
2186                of_node_put(np);
2187                return ret;
2188        }
2189
2190        display = of_graph_get_remote_port_parent(np);
2191        of_node_put(np);
2192        if (!display) {
2193                dev_err(dev, "no display defined\n");
2194                return -EINVAL;
2195        }
2196
2197        ret = of_get_pxafb_display(dev, display, info, bus_width);
2198        of_node_put(display);
2199        if (ret)
2200                return ret;
2201
2202        for (i = 0; i < info->num_modes; i++)
2203                info->modes[i].bpp = bus_width;
2204
2205        return 0;
2206}
2207
2208static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2209{
2210        int ret;
2211        struct pxafb_mach_info *info;
2212
2213        if (!dev->of_node)
2214                return NULL;
2215        info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2216        if (!info)
2217                return ERR_PTR(-ENOMEM);
2218        ret = of_get_pxafb_mode_info(dev, info);
2219        if (ret)
2220                return ERR_PTR(ret);
2221
2222        /*
2223         * On purpose, neither lccrX registers nor video memory size can be
2224         * specified through device-tree, they are considered more a debug hack
2225         * available through command line.
2226         */
2227        return info;
2228}
2229#else
2230static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2231{
2232        return NULL;
2233}
2234#endif
2235
2236static int pxafb_probe(struct platform_device *dev)
2237{
2238        struct pxafb_info *fbi;
2239        struct pxafb_mach_info *inf, *pdata;
2240        struct resource *r;
2241        int i, irq, ret;
2242
2243        dev_dbg(&dev->dev, "pxafb_probe\n");
2244
2245        ret = -ENOMEM;
2246        pdata = dev_get_platdata(&dev->dev);
2247        inf = devm_kmalloc(&dev->dev, sizeof(*inf), GFP_KERNEL);
2248        if (!inf)
2249                goto failed;
2250
2251        if (pdata) {
2252                *inf = *pdata;
2253                inf->modes =
2254                        devm_kmalloc_array(&dev->dev, pdata->num_modes,
2255                                           sizeof(inf->modes[0]), GFP_KERNEL);
2256                if (!inf->modes)
2257                        goto failed;
2258                for (i = 0; i < inf->num_modes; i++)
2259                        inf->modes[i] = pdata->modes[i];
2260        }
2261
2262        if (!pdata)
2263                inf = of_pxafb_of_mach_info(&dev->dev);
2264        if (IS_ERR_OR_NULL(inf))
2265                goto failed;
2266
2267        ret = pxafb_parse_options(&dev->dev, g_options, inf);
2268        if (ret < 0)
2269                goto failed;
2270
2271        pxafb_check_options(&dev->dev, inf);
2272
2273        dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2274                        inf->modes->xres,
2275                        inf->modes->yres,
2276                        inf->modes->bpp);
2277        if (inf->modes->xres == 0 ||
2278            inf->modes->yres == 0 ||
2279            inf->modes->bpp == 0) {
2280                dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2281                ret = -EINVAL;
2282                goto failed;
2283        }
2284
2285        fbi = pxafb_init_fbinfo(&dev->dev, inf);
2286        if (IS_ERR(fbi)) {
2287                dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2288                ret = PTR_ERR(fbi);
2289                goto failed;
2290        }
2291
2292        if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2293                fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2294
2295        fbi->backlight_power = inf->pxafb_backlight_power;
2296        fbi->lcd_power = inf->pxafb_lcd_power;
2297
2298        fbi->lcd_supply = devm_regulator_get_optional(&dev->dev, "lcd");
2299        if (IS_ERR(fbi->lcd_supply)) {
2300                if (PTR_ERR(fbi->lcd_supply) == -EPROBE_DEFER)
2301                        return -EPROBE_DEFER;
2302
2303                fbi->lcd_supply = NULL;
2304        }
2305
2306        r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2307        if (r == NULL) {
2308                dev_err(&dev->dev, "no I/O memory resource defined\n");
2309                ret = -ENODEV;
2310                goto failed;
2311        }
2312
2313        fbi->mmio_base = devm_ioremap_resource(&dev->dev, r);
2314        if (IS_ERR(fbi->mmio_base)) {
2315                dev_err(&dev->dev, "failed to get I/O memory\n");
2316                ret = -EBUSY;
2317                goto failed;
2318        }
2319
2320        fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2321        fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2322                                &fbi->dma_buff_phys, GFP_KERNEL);
2323        if (fbi->dma_buff == NULL) {
2324                dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2325                ret = -ENOMEM;
2326                goto failed;
2327        }
2328
2329        ret = pxafb_init_video_memory(fbi);
2330        if (ret) {
2331                dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2332                ret = -ENOMEM;
2333                goto failed_free_dma;
2334        }
2335
2336        irq = platform_get_irq(dev, 0);
2337        if (irq < 0) {
2338                dev_err(&dev->dev, "no IRQ defined\n");
2339                ret = -ENODEV;
2340                goto failed_free_mem;
2341        }
2342
2343        ret = devm_request_irq(&dev->dev, irq, pxafb_handle_irq, 0, "LCD", fbi);
2344        if (ret) {
2345                dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2346                ret = -EBUSY;
2347                goto failed_free_mem;
2348        }
2349
2350        ret = pxafb_smart_init(fbi);
2351        if (ret) {
2352                dev_err(&dev->dev, "failed to initialize smartpanel\n");
2353                goto failed_free_mem;
2354        }
2355
2356        /*
2357         * This makes sure that our colour bitfield
2358         * descriptors are correctly initialised.
2359         */
2360        ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2361        if (ret) {
2362                dev_err(&dev->dev, "failed to get suitable mode\n");
2363                goto failed_free_mem;
2364        }
2365
2366        ret = pxafb_set_par(&fbi->fb);
2367        if (ret) {
2368                dev_err(&dev->dev, "Failed to set parameters\n");
2369                goto failed_free_mem;
2370        }
2371
2372        platform_set_drvdata(dev, fbi);
2373
2374        ret = register_framebuffer(&fbi->fb);
2375        if (ret < 0) {
2376                dev_err(&dev->dev,
2377                        "Failed to register framebuffer device: %d\n", ret);
2378                goto failed_free_cmap;
2379        }
2380
2381        pxafb_overlay_init(fbi);
2382
2383#ifdef CONFIG_CPU_FREQ
2384        fbi->freq_transition.notifier_call = pxafb_freq_transition;
2385        cpufreq_register_notifier(&fbi->freq_transition,
2386                                CPUFREQ_TRANSITION_NOTIFIER);
2387#endif
2388
2389        /*
2390         * Ok, now enable the LCD controller
2391         */
2392        set_ctrlr_state(fbi, C_ENABLE);
2393
2394        return 0;
2395
2396failed_free_cmap:
2397        if (fbi->fb.cmap.len)
2398                fb_dealloc_cmap(&fbi->fb.cmap);
2399failed_free_mem:
2400        free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2401failed_free_dma:
2402        dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2403                        fbi->dma_buff, fbi->dma_buff_phys);
2404failed:
2405        return ret;
2406}
2407
2408static int pxafb_remove(struct platform_device *dev)
2409{
2410        struct pxafb_info *fbi = platform_get_drvdata(dev);
2411        struct fb_info *info;
2412
2413        if (!fbi)
2414                return 0;
2415
2416        info = &fbi->fb;
2417
2418        pxafb_overlay_exit(fbi);
2419        unregister_framebuffer(info);
2420
2421        pxafb_disable_controller(fbi);
2422
2423        if (fbi->fb.cmap.len)
2424                fb_dealloc_cmap(&fbi->fb.cmap);
2425
2426        free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2427
2428        dma_free_wc(&dev->dev, fbi->dma_buff_size, fbi->dma_buff,
2429                    fbi->dma_buff_phys);
2430
2431        return 0;
2432}
2433
2434static const struct of_device_id pxafb_of_dev_id[] = {
2435        { .compatible = "marvell,pxa270-lcdc", },
2436        { .compatible = "marvell,pxa300-lcdc", },
2437        { .compatible = "marvell,pxa2xx-lcdc", },
2438        { /* sentinel */ }
2439};
2440MODULE_DEVICE_TABLE(of, pxafb_of_dev_id);
2441
2442static struct platform_driver pxafb_driver = {
2443        .probe          = pxafb_probe,
2444        .remove         = pxafb_remove,
2445        .driver         = {
2446                .name   = "pxa2xx-fb",
2447                .of_match_table = pxafb_of_dev_id,
2448#ifdef CONFIG_PM
2449                .pm     = &pxafb_pm_ops,
2450#endif
2451        },
2452};
2453
2454static int __init pxafb_init(void)
2455{
2456        if (pxafb_setup_options())
2457                return -EINVAL;
2458
2459        return platform_driver_register(&pxafb_driver);
2460}
2461
2462static void __exit pxafb_exit(void)
2463{
2464        platform_driver_unregister(&pxafb_driver);
2465}
2466
2467module_init(pxafb_init);
2468module_exit(pxafb_exit);
2469
2470MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2471MODULE_LICENSE("GPL");
2472