1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __RIVAFB_H 3#define __RIVAFB_H 4 5#include <linux/fb.h> 6#include <video/vga.h> 7#include <linux/i2c.h> 8#include <linux/i2c-algo-bit.h> 9 10#include "riva_hw.h" 11 12/* GGI compatibility macros */ 13#define NUM_SEQ_REGS 0x05 14#define NUM_CRT_REGS 0x41 15#define NUM_GRC_REGS 0x09 16#define NUM_ATC_REGS 0x15 17 18/* I2C */ 19#define DDC_SCL_READ_MASK (1 << 2) 20#define DDC_SCL_WRITE_MASK (1 << 5) 21#define DDC_SDA_READ_MASK (1 << 3) 22#define DDC_SDA_WRITE_MASK (1 << 4) 23 24/* holds the state of the VGA core and extended Riva hw state from riva_hw.c. 25 * From KGI originally. */ 26struct riva_regs { 27 u8 attr[NUM_ATC_REGS]; 28 u8 crtc[NUM_CRT_REGS]; 29 u8 gra[NUM_GRC_REGS]; 30 u8 seq[NUM_SEQ_REGS]; 31 u8 misc_output; 32 RIVA_HW_STATE ext; 33}; 34 35struct riva_par; 36 37struct riva_i2c_chan { 38 struct riva_par *par; 39 unsigned long ddc_base; 40 struct i2c_adapter adapter; 41 struct i2c_algo_bit_data algo; 42}; 43 44struct riva_par { 45 RIVA_HW_INST riva; /* interface to riva_hw.c */ 46 u32 pseudo_palette[16]; /* default palette */ 47 u32 palette[16]; /* for Riva128 */ 48 u8 __iomem *ctrl_base; /* virtual control register base addr */ 49 unsigned dclk_max; /* max DCLK */ 50 51 struct riva_regs initial_state; /* initial startup video mode */ 52 struct riva_regs current_state; 53#ifdef CONFIG_X86 54 struct vgastate state; 55#endif 56 struct mutex open_lock; 57 unsigned int ref_count; 58 unsigned char *EDID; 59 unsigned int Chipset; 60 int forceCRTC; 61 Bool SecondCRTC; 62 int FlatPanel; 63 struct pci_dev *pdev; 64 int cursor_reset; 65 int wc_cookie; 66 struct riva_i2c_chan chan[3]; 67}; 68 69void riva_common_setup(struct riva_par *); 70unsigned long riva_get_memlen(struct riva_par *); 71unsigned long riva_get_maxdclk(struct riva_par *); 72void riva_delete_i2c_busses(struct riva_par *par); 73void riva_create_i2c_busses(struct riva_par *par); 74int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid); 75 76#endif /* __RIVAFB_H */ 77