1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) Intel Corp. 2007. 4 * All Rights Reserved. 5 * 6 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 7 * develop this driver. 8 * 9 * This file is part of the Vermilion Range fb driver. 10 * 11 * Authors: 12 * Thomas Hellström <thomas-at-tungstengraphics-dot-com> 13 */ 14 15#ifndef _VERMILION_H_ 16#define _VERMILION_H_ 17 18#include <linux/kernel.h> 19#include <linux/pci.h> 20#include <linux/atomic.h> 21#include <linux/mutex.h> 22 23#define VML_DEVICE_GPU 0x5002 24#define VML_DEVICE_VDC 0x5009 25 26#define VML_VRAM_AREAS 3 27#define VML_MAX_XRES 1024 28#define VML_MAX_YRES 768 29#define VML_MAX_XRES_VIRTUAL 1040 30 31/* 32 * Display controller registers: 33 */ 34 35/* Display controller 10-bit color representation */ 36 37#define VML_R_MASK 0x3FF00000 38#define VML_R_SHIFT 20 39#define VML_G_MASK 0x000FFC00 40#define VML_G_SHIFT 10 41#define VML_B_MASK 0x000003FF 42#define VML_B_SHIFT 0 43 44/* Graphics plane control */ 45#define VML_DSPCCNTR 0x00072180 46#define VML_GFX_ENABLE 0x80000000 47#define VML_GFX_GAMMABYPASS 0x40000000 48#define VML_GFX_ARGB1555 0x0C000000 49#define VML_GFX_RGB0888 0x18000000 50#define VML_GFX_ARGB8888 0x1C000000 51#define VML_GFX_ALPHACONST 0x02000000 52#define VML_GFX_ALPHAMULT 0x01000000 53#define VML_GFX_CONST_ALPHA 0x000000FF 54 55/* Graphics plane start address. Pixel aligned. */ 56#define VML_DSPCADDR 0x00072184 57 58/* Graphics plane stride register. */ 59#define VML_DSPCSTRIDE 0x00072188 60 61/* Graphics plane position register. */ 62#define VML_DSPCPOS 0x0007218C 63#define VML_POS_YMASK 0x0FFF0000 64#define VML_POS_YSHIFT 16 65#define VML_POS_XMASK 0x00000FFF 66#define VML_POS_XSHIFT 0 67 68/* Graphics plane height and width */ 69#define VML_DSPCSIZE 0x00072190 70#define VML_SIZE_HMASK 0x0FFF0000 71#define VML_SIZE_HSHIFT 16 72#define VML_SISE_WMASK 0x00000FFF 73#define VML_SIZE_WSHIFT 0 74 75/* Graphics plane gamma correction lookup table registers (129 * 32 bits) */ 76#define VML_DSPCGAMLUT 0x00072200 77 78/* Pixel video output configuration register */ 79#define VML_PVOCONFIG 0x00061140 80#define VML_CONFIG_BASE 0x80000000 81#define VML_CONFIG_PIXEL_SWAP 0x04000000 82#define VML_CONFIG_DE_INV 0x01000000 83#define VML_CONFIG_HREF_INV 0x00400000 84#define VML_CONFIG_VREF_INV 0x00100000 85#define VML_CONFIG_CLK_INV 0x00040000 86#define VML_CONFIG_CLK_DIV2 0x00010000 87#define VML_CONFIG_ESTRB_INV 0x00008000 88 89/* Pipe A Horizontal total register */ 90#define VML_HTOTAL_A 0x00060000 91#define VML_HTOTAL_MASK 0x1FFF0000 92#define VML_HTOTAL_SHIFT 16 93#define VML_HTOTAL_VAL 8192 94#define VML_HACTIVE_MASK 0x000007FF 95#define VML_HACTIVE_SHIFT 0 96#define VML_HACTIVE_VAL 4096 97 98/* Pipe A Horizontal Blank register */ 99#define VML_HBLANK_A 0x00060004 100#define VML_HBLANK_END_MASK 0x1FFF0000 101#define VML_HBLANK_END_SHIFT 16 102#define VML_HBLANK_END_VAL 8192 103#define VML_HBLANK_START_MASK 0x00001FFF 104#define VML_HBLANK_START_SHIFT 0 105#define VML_HBLANK_START_VAL 8192 106 107/* Pipe A Horizontal Sync register */ 108#define VML_HSYNC_A 0x00060008 109#define VML_HSYNC_END_MASK 0x1FFF0000 110#define VML_HSYNC_END_SHIFT 16 111#define VML_HSYNC_END_VAL 8192 112#define VML_HSYNC_START_MASK 0x00001FFF 113#define VML_HSYNC_START_SHIFT 0 114#define VML_HSYNC_START_VAL 8192 115 116/* Pipe A Vertical total register */ 117#define VML_VTOTAL_A 0x0006000C 118#define VML_VTOTAL_MASK 0x1FFF0000 119#define VML_VTOTAL_SHIFT 16 120#define VML_VTOTAL_VAL 8192 121#define VML_VACTIVE_MASK 0x000007FF 122#define VML_VACTIVE_SHIFT 0 123#define VML_VACTIVE_VAL 4096 124 125/* Pipe A Vertical Blank register */ 126#define VML_VBLANK_A 0x00060010 127#define VML_VBLANK_END_MASK 0x1FFF0000 128#define VML_VBLANK_END_SHIFT 16 129#define VML_VBLANK_END_VAL 8192 130#define VML_VBLANK_START_MASK 0x00001FFF 131#define VML_VBLANK_START_SHIFT 0 132#define VML_VBLANK_START_VAL 8192 133 134/* Pipe A Vertical Sync register */ 135#define VML_VSYNC_A 0x00060014 136#define VML_VSYNC_END_MASK 0x1FFF0000 137#define VML_VSYNC_END_SHIFT 16 138#define VML_VSYNC_END_VAL 8192 139#define VML_VSYNC_START_MASK 0x00001FFF 140#define VML_VSYNC_START_SHIFT 0 141#define VML_VSYNC_START_VAL 8192 142 143/* Pipe A Source Image size (minus one - equal to active size) 144 * Programmable while pipe is enabled. 145 */ 146#define VML_PIPEASRC 0x0006001C 147#define VML_PIPEASRC_HMASK 0x0FFF0000 148#define VML_PIPEASRC_HSHIFT 16 149#define VML_PIPEASRC_VMASK 0x00000FFF 150#define VML_PIPEASRC_VSHIFT 0 151 152/* Pipe A Border Color Pattern register (10 bit color) */ 153#define VML_BCLRPAT_A 0x00060020 154 155/* Pipe A Canvas Color register (10 bit color) */ 156#define VML_CANVSCLR_A 0x00060024 157 158/* Pipe A Configuration register */ 159#define VML_PIPEACONF 0x00070008 160#define VML_PIPE_BASE 0x00000000 161#define VML_PIPE_ENABLE 0x80000000 162#define VML_PIPE_FORCE_BORDER 0x02000000 163#define VML_PIPE_PLANES_OFF 0x00080000 164#define VML_PIPE_ARGB_OUTPUT_MODE 0x00040000 165 166/* Pipe A FIFO setting */ 167#define VML_DSPARB 0x00070030 168#define VML_FIFO_DEFAULT 0x00001D9C 169 170/* MDVO rcomp status & pads control register */ 171#define VML_RCOMPSTAT 0x00070048 172#define VML_MDVO_VDC_I_RCOMP 0x80000000 173#define VML_MDVO_POWERSAVE_OFF 0x00000008 174#define VML_MDVO_PAD_ENABLE 0x00000004 175#define VML_MDVO_PULLDOWN_ENABLE 0x00000001 176 177struct vml_par { 178 struct pci_dev *vdc; 179 u64 vdc_mem_base; 180 u64 vdc_mem_size; 181 char __iomem *vdc_mem; 182 183 struct pci_dev *gpu; 184 u64 gpu_mem_base; 185 u64 gpu_mem_size; 186 char __iomem *gpu_mem; 187 188 atomic_t refcount; 189}; 190 191struct vram_area { 192 unsigned long logical; 193 unsigned long phys; 194 unsigned long size; 195 unsigned order; 196}; 197 198struct vml_info { 199 struct fb_info info; 200 struct vml_par *par; 201 struct list_head head; 202 struct vram_area vram[VML_VRAM_AREAS]; 203 u64 vram_start; 204 u64 vram_contig_size; 205 u32 num_areas; 206 void __iomem *vram_logical; 207 u32 pseudo_palette[16]; 208 u32 stride; 209 u32 bytes_per_pixel; 210 atomic_t vmas; 211 int cur_blank_mode; 212 int pipe_disabled; 213}; 214 215/* 216 * Subsystem 217 */ 218 219struct vml_sys { 220 char *name; 221 222 /* 223 * Save / Restore; 224 */ 225 226 int (*save) (struct vml_sys * sys); 227 int (*restore) (struct vml_sys * sys); 228 229 /* 230 * PLL programming; 231 */ 232 233 int (*set_clock) (struct vml_sys * sys, int clock); 234 int (*nearest_clock) (const struct vml_sys * sys, int clock); 235}; 236 237extern int vmlfb_register_subsys(struct vml_sys *sys); 238extern void vmlfb_unregister_subsys(struct vml_sys *sys); 239 240#define VML_READ32(_par, _offset) \ 241 (ioread32((_par)->vdc_mem + (_offset))) 242#define VML_WRITE32(_par, _offset, _value) \ 243 iowrite32(_value, (_par)->vdc_mem + (_offset)) 244 245#endif 246