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23#include <linux/device.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/errno.h>
27#include <linux/string.h>
28#include <linux/mm.h>
29#include <linux/fb.h>
30#include <linux/init.h>
31#include <linux/dma-mapping.h>
32#include <linux/of_device.h>
33#include <linux/of_platform.h>
34#include <linux/of_address.h>
35#include <linux/io.h>
36#include <linux/slab.h>
37
38#ifdef CONFIG_PPC_DCR
39#include <asm/dcr.h>
40#endif
41
42#define DRIVER_NAME "xilinxfb"
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61#define NUM_REGS 2
62#define REG_FB_ADDR 0
63#define REG_CTRL 1
64#define REG_CTRL_ENABLE 0x0001
65#define REG_CTRL_ROTATE 0x0002
66
67
68
69
70
71
72
73
74
75
76#define BYTES_PER_PIXEL 4
77#define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
78
79#define RED_SHIFT 16
80#define GREEN_SHIFT 8
81#define BLUE_SHIFT 0
82
83#define PALETTE_ENTRIES_NO 16
84
85
86struct xilinxfb_platform_data {
87 u32 rotate_screen;
88 u32 screen_height_mm;
89 u32 screen_width_mm;
90 u32 xres, yres;
91 u32 xvirt, yvirt;
92
93
94
95
96
97 u32 fb_phys;
98};
99
100
101
102
103static const struct xilinxfb_platform_data xilinx_fb_default_pdata = {
104 .xres = 640,
105 .yres = 480,
106 .xvirt = 1024,
107 .yvirt = 480,
108};
109
110
111
112
113static const struct fb_fix_screeninfo xilinx_fb_fix = {
114 .id = "Xilinx",
115 .type = FB_TYPE_PACKED_PIXELS,
116 .visual = FB_VISUAL_TRUECOLOR,
117 .accel = FB_ACCEL_NONE
118};
119
120static const struct fb_var_screeninfo xilinx_fb_var = {
121 .bits_per_pixel = BITS_PER_PIXEL,
122
123 .red = { RED_SHIFT, 8, 0 },
124 .green = { GREEN_SHIFT, 8, 0 },
125 .blue = { BLUE_SHIFT, 8, 0 },
126 .transp = { 0, 0, 0 },
127
128 .activate = FB_ACTIVATE_NOW
129};
130
131#define BUS_ACCESS_FLAG 0x1
132#define LITTLE_ENDIAN_ACCESS 0x2
133
134struct xilinxfb_drvdata {
135 struct fb_info info;
136
137 phys_addr_t regs_phys;
138
139
140 void __iomem *regs;
141
142
143#ifdef CONFIG_PPC_DCR
144 dcr_host_t dcr_host;
145 unsigned int dcr_len;
146#endif
147 void *fb_virt;
148 dma_addr_t fb_phys;
149 int fb_alloced;
150
151 u8 flags;
152
153 u32 reg_ctrl_default;
154
155 u32 pseudo_palette[PALETTE_ENTRIES_NO];
156
157};
158
159#define to_xilinxfb_drvdata(_info) \
160 container_of(_info, struct xilinxfb_drvdata, info)
161
162
163
164
165
166
167static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
168 u32 val)
169{
170 if (drvdata->flags & BUS_ACCESS_FLAG) {
171 if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
172 iowrite32(val, drvdata->regs + (offset << 2));
173 else
174 iowrite32be(val, drvdata->regs + (offset << 2));
175 }
176#ifdef CONFIG_PPC_DCR
177 else
178 dcr_write(drvdata->dcr_host, offset, val);
179#endif
180}
181
182static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset)
183{
184 if (drvdata->flags & BUS_ACCESS_FLAG) {
185 if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
186 return ioread32(drvdata->regs + (offset << 2));
187 else
188 return ioread32be(drvdata->regs + (offset << 2));
189 }
190#ifdef CONFIG_PPC_DCR
191 else
192 return dcr_read(drvdata->dcr_host, offset);
193#endif
194 return 0;
195}
196
197static int
198xilinx_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
199 unsigned int blue, unsigned int transp, struct fb_info *fbi)
200{
201 u32 *palette = fbi->pseudo_palette;
202
203 if (regno >= PALETTE_ENTRIES_NO)
204 return -EINVAL;
205
206 if (fbi->var.grayscale) {
207
208
209
210 blue = (red * 77 + green * 151 + blue * 28 + 127) >> 8;
211 green = blue;
212 red = green;
213 }
214
215
216
217
218 red >>= 8;
219 green >>= 8;
220 blue >>= 8;
221 palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
222 (blue << BLUE_SHIFT);
223
224 return 0;
225}
226
227static int
228xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
229{
230 struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
231
232 switch (blank_mode) {
233 case FB_BLANK_UNBLANK:
234
235 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
236 break;
237
238 case FB_BLANK_NORMAL:
239 case FB_BLANK_VSYNC_SUSPEND:
240 case FB_BLANK_HSYNC_SUSPEND:
241 case FB_BLANK_POWERDOWN:
242
243 xilinx_fb_out32(drvdata, REG_CTRL, 0);
244 break;
245
246 default:
247 break;
248 }
249 return 0;
250}
251
252static const struct fb_ops xilinxfb_ops = {
253 .owner = THIS_MODULE,
254 .fb_setcolreg = xilinx_fb_setcolreg,
255 .fb_blank = xilinx_fb_blank,
256 .fb_fillrect = cfb_fillrect,
257 .fb_copyarea = cfb_copyarea,
258 .fb_imageblit = cfb_imageblit,
259};
260
261
262
263
264
265static int xilinxfb_assign(struct platform_device *pdev,
266 struct xilinxfb_drvdata *drvdata,
267 struct xilinxfb_platform_data *pdata)
268{
269 int rc;
270 struct device *dev = &pdev->dev;
271 int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
272
273 if (drvdata->flags & BUS_ACCESS_FLAG) {
274 struct resource *res;
275
276 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
277 drvdata->regs = devm_ioremap_resource(&pdev->dev, res);
278 if (IS_ERR(drvdata->regs))
279 return PTR_ERR(drvdata->regs);
280
281 drvdata->regs_phys = res->start;
282 }
283
284
285 if (pdata->fb_phys) {
286 drvdata->fb_phys = pdata->fb_phys;
287 drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
288 } else {
289 drvdata->fb_alloced = 1;
290 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
291 &drvdata->fb_phys,
292 GFP_KERNEL);
293 }
294
295 if (!drvdata->fb_virt) {
296 dev_err(dev, "Could not allocate frame buffer memory\n");
297 return -ENOMEM;
298 }
299
300
301 memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
302
303
304 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
305 rc = xilinx_fb_in32(drvdata, REG_FB_ADDR);
306
307 if (rc != drvdata->fb_phys) {
308 drvdata->flags |= LITTLE_ENDIAN_ACCESS;
309 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
310 }
311
312
313 drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
314 if (pdata->rotate_screen)
315 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
316 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
317
318
319 drvdata->info.device = dev;
320 drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
321 drvdata->info.fbops = &xilinxfb_ops;
322 drvdata->info.fix = xilinx_fb_fix;
323 drvdata->info.fix.smem_start = drvdata->fb_phys;
324 drvdata->info.fix.smem_len = fbsize;
325 drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
326
327 drvdata->info.pseudo_palette = drvdata->pseudo_palette;
328 drvdata->info.flags = FBINFO_DEFAULT;
329 drvdata->info.var = xilinx_fb_var;
330 drvdata->info.var.height = pdata->screen_height_mm;
331 drvdata->info.var.width = pdata->screen_width_mm;
332 drvdata->info.var.xres = pdata->xres;
333 drvdata->info.var.yres = pdata->yres;
334 drvdata->info.var.xres_virtual = pdata->xvirt;
335 drvdata->info.var.yres_virtual = pdata->yvirt;
336
337
338 rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
339 if (rc) {
340 dev_err(dev, "Fail to allocate colormap (%d entries)\n",
341 PALETTE_ENTRIES_NO);
342 goto err_cmap;
343 }
344
345
346 rc = register_framebuffer(&drvdata->info);
347 if (rc) {
348 dev_err(dev, "Could not register frame buffer\n");
349 goto err_regfb;
350 }
351
352 if (drvdata->flags & BUS_ACCESS_FLAG) {
353
354 dev_dbg(dev, "regs: phys=%pa, virt=%p\n",
355 &drvdata->regs_phys, drvdata->regs);
356 }
357
358 dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
359 (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
360
361 return 0;
362
363err_regfb:
364 fb_dealloc_cmap(&drvdata->info.cmap);
365
366err_cmap:
367 if (drvdata->fb_alloced)
368 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
369 drvdata->fb_phys);
370 else
371 iounmap(drvdata->fb_virt);
372
373
374 xilinx_fb_out32(drvdata, REG_CTRL, 0);
375
376 return rc;
377}
378
379static int xilinxfb_release(struct device *dev)
380{
381 struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
382
383#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
384 xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
385#endif
386
387 unregister_framebuffer(&drvdata->info);
388
389 fb_dealloc_cmap(&drvdata->info.cmap);
390
391 if (drvdata->fb_alloced)
392 dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
393 drvdata->fb_virt, drvdata->fb_phys);
394 else
395 iounmap(drvdata->fb_virt);
396
397
398 xilinx_fb_out32(drvdata, REG_CTRL, 0);
399
400#ifdef CONFIG_PPC_DCR
401
402 if (!(drvdata->flags & BUS_ACCESS_FLAG))
403 dcr_unmap(drvdata->dcr_host, drvdata->dcr_len);
404#endif
405
406 return 0;
407}
408
409
410
411
412
413static int xilinxfb_of_probe(struct platform_device *pdev)
414{
415 const u32 *prop;
416 u32 tft_access = 0;
417 struct xilinxfb_platform_data pdata;
418 int size;
419 struct xilinxfb_drvdata *drvdata;
420
421
422 pdata = xilinx_fb_default_pdata;
423
424
425 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
426 if (!drvdata)
427 return -ENOMEM;
428
429
430
431
432
433 of_property_read_u32(pdev->dev.of_node, "xlnx,dcr-splb-slave-if",
434 &tft_access);
435
436
437
438
439
440 if (tft_access)
441 drvdata->flags |= BUS_ACCESS_FLAG;
442#ifdef CONFIG_PPC_DCR
443 else {
444 int start;
445
446 start = dcr_resource_start(pdev->dev.of_node, 0);
447 drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0);
448 drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len);
449 if (!DCR_MAP_OK(drvdata->dcr_host)) {
450 dev_err(&pdev->dev, "invalid DCR address\n");
451 return -ENODEV;
452 }
453 }
454#endif
455
456 prop = of_get_property(pdev->dev.of_node, "phys-size", &size);
457 if ((prop) && (size >= sizeof(u32) * 2)) {
458 pdata.screen_width_mm = prop[0];
459 pdata.screen_height_mm = prop[1];
460 }
461
462 prop = of_get_property(pdev->dev.of_node, "resolution", &size);
463 if ((prop) && (size >= sizeof(u32) * 2)) {
464 pdata.xres = prop[0];
465 pdata.yres = prop[1];
466 }
467
468 prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size);
469 if ((prop) && (size >= sizeof(u32) * 2)) {
470 pdata.xvirt = prop[0];
471 pdata.yvirt = prop[1];
472 }
473
474 if (of_find_property(pdev->dev.of_node, "rotate-display", NULL))
475 pdata.rotate_screen = 1;
476
477 platform_set_drvdata(pdev, drvdata);
478 return xilinxfb_assign(pdev, drvdata, &pdata);
479}
480
481static int xilinxfb_of_remove(struct platform_device *op)
482{
483 return xilinxfb_release(&op->dev);
484}
485
486
487static const struct of_device_id xilinxfb_of_match[] = {
488 { .compatible = "xlnx,xps-tft-1.00.a", },
489 { .compatible = "xlnx,xps-tft-2.00.a", },
490 { .compatible = "xlnx,xps-tft-2.01.a", },
491 { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
492 { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
493 {},
494};
495MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
496
497static struct platform_driver xilinxfb_of_driver = {
498 .probe = xilinxfb_of_probe,
499 .remove = xilinxfb_of_remove,
500 .driver = {
501 .name = DRIVER_NAME,
502 .of_match_table = xilinxfb_of_match,
503 },
504};
505
506module_platform_driver(xilinxfb_of_driver);
507
508MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
509MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
510MODULE_LICENSE("GPL");
511