1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50#include <linux/interrupt.h>
51#include <linux/watchdog.h>
52#include <linux/cpumask.h>
53#include <linux/module.h>
54#include <linux/delay.h>
55#include <linux/cpu.h>
56#include <linux/irq.h>
57#include <linux/irqdomain.h>
58
59#include <asm/mipsregs.h>
60#include <asm/uasm.h>
61
62#include <asm/octeon/octeon.h>
63#include <asm/octeon/cvmx-boot-vector.h>
64#include <asm/octeon/cvmx-ciu2-defs.h>
65#include <asm/octeon/cvmx-rst-defs.h>
66
67
68#define WD_BLOCK_NUMBER 0x01
69
70static int divisor;
71
72
73static unsigned int timeout_cnt;
74
75
76static unsigned int max_timeout_sec;
77
78
79static unsigned int timeout_sec;
80
81
82static bool do_countdown;
83static unsigned int countdown_reset;
84static unsigned int per_cpu_countdown[NR_CPUS];
85
86static cpumask_t irq_enabled_cpus;
87
88#define WD_TIMO 60
89
90#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)
91
92static int heartbeat = WD_TIMO;
93module_param(heartbeat, int, 0444);
94MODULE_PARM_DESC(heartbeat,
95 "Watchdog heartbeat in seconds. (0 < heartbeat, default="
96 __MODULE_STRING(WD_TIMO) ")");
97
98static bool nowayout = WATCHDOG_NOWAYOUT;
99module_param(nowayout, bool, 0444);
100MODULE_PARM_DESC(nowayout,
101 "Watchdog cannot be stopped once started (default="
102 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
103
104static int disable;
105module_param(disable, int, 0444);
106MODULE_PARM_DESC(disable,
107 "Disable the watchdog entirely (default=0)");
108
109static struct cvmx_boot_vector_element *octeon_wdt_bootvector;
110
111void octeon_wdt_nmi_stage2(void);
112
113static int cpu2core(int cpu)
114{
115#ifdef CONFIG_SMP
116 return cpu_logical_map(cpu) & 0x3f;
117#else
118 return cvmx_get_core_num();
119#endif
120}
121
122
123
124
125
126
127
128
129
130static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
131{
132 int cpu = raw_smp_processor_id();
133 unsigned int core = cpu2core(cpu);
134 int node = cpu_to_node(cpu);
135
136 if (do_countdown) {
137 if (per_cpu_countdown[cpu] > 0) {
138
139 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
140 per_cpu_countdown[cpu]--;
141 } else {
142
143 disable_irq_nosync(cpl);
144 cpumask_clear_cpu(cpu, &irq_enabled_cpus);
145 }
146 } else {
147
148 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
149 }
150 return IRQ_HANDLED;
151}
152
153
154extern int prom_putchar(char c);
155
156
157
158
159
160
161static void octeon_wdt_write_string(const char *str)
162{
163
164 while (*str)
165 prom_putchar(*str++);
166}
167
168
169
170
171
172
173
174static void octeon_wdt_write_hex(u64 value, int digits)
175{
176 int d;
177 int v;
178
179 for (d = 0; d < digits; d++) {
180 v = (value >> ((digits - d - 1) * 4)) & 0xf;
181 if (v >= 10)
182 prom_putchar('a' + v - 10);
183 else
184 prom_putchar('0' + v);
185 }
186}
187
188static const char reg_name[][3] = {
189 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
190 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
191 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
192 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
193};
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210void octeon_wdt_nmi_stage3(u64 reg[32])
211{
212 u64 i;
213
214 unsigned int coreid = cvmx_get_core_num();
215
216
217
218
219 u64 cp0_cause = read_c0_cause();
220 u64 cp0_status = read_c0_status();
221 u64 cp0_error_epc = read_c0_errorepc();
222 u64 cp0_epc = read_c0_epc();
223
224
225 udelay(85000 * coreid);
226
227 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
228 octeon_wdt_write_hex(coreid, 2);
229 octeon_wdt_write_string(" ***\r\n");
230 for (i = 0; i < 32; i++) {
231 octeon_wdt_write_string("\t");
232 octeon_wdt_write_string(reg_name[i]);
233 octeon_wdt_write_string("\t0x");
234 octeon_wdt_write_hex(reg[i], 16);
235 if (i & 1)
236 octeon_wdt_write_string("\r\n");
237 }
238 octeon_wdt_write_string("\terr_epc\t0x");
239 octeon_wdt_write_hex(cp0_error_epc, 16);
240
241 octeon_wdt_write_string("\tepc\t0x");
242 octeon_wdt_write_hex(cp0_epc, 16);
243 octeon_wdt_write_string("\r\n");
244
245 octeon_wdt_write_string("\tstatus\t0x");
246 octeon_wdt_write_hex(cp0_status, 16);
247 octeon_wdt_write_string("\tcause\t0x");
248 octeon_wdt_write_hex(cp0_cause, 16);
249 octeon_wdt_write_string("\r\n");
250
251
252 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
253 octeon_wdt_write_string("\tsrc_wd\t0x");
254 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
255 octeon_wdt_write_string("\ten_wd\t0x");
256 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
257 octeon_wdt_write_string("\r\n");
258 octeon_wdt_write_string("\tsrc_rml\t0x");
259 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
260 octeon_wdt_write_string("\ten_rml\t0x");
261 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
262 octeon_wdt_write_string("\r\n");
263 octeon_wdt_write_string("\tsum\t0x");
264 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
265 octeon_wdt_write_string("\r\n");
266 } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
267 octeon_wdt_write_string("\tsum0\t0x");
268 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
269 octeon_wdt_write_string("\ten0\t0x");
270 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
271 octeon_wdt_write_string("\r\n");
272 }
273
274 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
275
276
277
278
279
280 if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
281 u64 scr;
282 unsigned int node = cvmx_get_node_num();
283 unsigned int lcore = cvmx_get_local_core_num();
284 union cvmx_ciu_wdogx ciu_wdog;
285
286
287
288
289
290
291 do {
292 ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore));
293 } while (ciu_wdog.s.cnt > 0x10000);
294
295 scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0));
296 scr |= 1 << 11;
297 cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr);
298 cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1);
299 }
300}
301
302static int octeon_wdt_cpu_to_irq(int cpu)
303{
304 unsigned int coreid;
305 int node;
306 int irq;
307
308 coreid = cpu2core(cpu);
309 node = cpu_to_node(cpu);
310
311 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
312 struct irq_domain *domain;
313 int hwirq;
314
315 domain = octeon_irq_get_block_domain(node,
316 WD_BLOCK_NUMBER);
317 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid;
318 irq = irq_find_mapping(domain, hwirq);
319 } else {
320 irq = OCTEON_IRQ_WDOG0 + coreid;
321 }
322 return irq;
323}
324
325static int octeon_wdt_cpu_pre_down(unsigned int cpu)
326{
327 unsigned int core;
328 int node;
329 union cvmx_ciu_wdogx ciu_wdog;
330
331 core = cpu2core(cpu);
332
333 node = cpu_to_node(cpu);
334
335
336 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
337
338
339 ciu_wdog.u64 = 0;
340 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
341
342 free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq);
343 return 0;
344}
345
346static int octeon_wdt_cpu_online(unsigned int cpu)
347{
348 unsigned int core;
349 unsigned int irq;
350 union cvmx_ciu_wdogx ciu_wdog;
351 int node;
352 struct irq_domain *domain;
353 int hwirq;
354
355 core = cpu2core(cpu);
356 node = cpu_to_node(cpu);
357
358 octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;
359
360
361 ciu_wdog.u64 = 0;
362 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
363
364 per_cpu_countdown[cpu] = countdown_reset;
365
366 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
367
368 domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER);
369
370
371 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core;
372 irq = irq_create_mapping(domain, hwirq);
373 irqd_set_trigger_type(irq_get_irq_data(irq),
374 IRQ_TYPE_EDGE_RISING);
375 } else
376 irq = OCTEON_IRQ_WDOG0 + core;
377
378 if (request_irq(irq, octeon_wdt_poke_irq,
379 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
380 panic("octeon_wdt: Couldn't obtain irq %d", irq);
381
382
383 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
384 cpumask_t mask;
385
386 cpumask_clear(&mask);
387 cpumask_set_cpu(cpu, &mask);
388 irq_set_affinity(irq, &mask);
389 }
390
391 cpumask_set_cpu(cpu, &irq_enabled_cpus);
392
393
394 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
395
396
397 ciu_wdog.u64 = 0;
398 ciu_wdog.s.len = timeout_cnt;
399 ciu_wdog.s.mode = 3;
400 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
401
402 return 0;
403}
404
405static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
406{
407 int cpu;
408 int coreid;
409 int node;
410
411 if (disable)
412 return 0;
413
414 for_each_online_cpu(cpu) {
415 coreid = cpu2core(cpu);
416 node = cpu_to_node(cpu);
417 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
418 per_cpu_countdown[cpu] = countdown_reset;
419 if ((countdown_reset || !do_countdown) &&
420 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
421
422 enable_irq(octeon_wdt_cpu_to_irq(cpu));
423 cpumask_set_cpu(cpu, &irq_enabled_cpus);
424 }
425 }
426 return 0;
427}
428
429static void octeon_wdt_calc_parameters(int t)
430{
431 unsigned int periods;
432
433 timeout_sec = max_timeout_sec;
434
435
436
437
438
439
440 while ((t % timeout_sec) != 0)
441 timeout_sec--;
442
443 periods = t / timeout_sec;
444
445
446
447
448
449
450 countdown_reset = periods > 2 ? periods - 2 : 0;
451 heartbeat = t;
452 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
453}
454
455static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
456 unsigned int t)
457{
458 int cpu;
459 int coreid;
460 union cvmx_ciu_wdogx ciu_wdog;
461 int node;
462
463 if (t <= 0)
464 return -1;
465
466 octeon_wdt_calc_parameters(t);
467
468 if (disable)
469 return 0;
470
471 for_each_online_cpu(cpu) {
472 coreid = cpu2core(cpu);
473 node = cpu_to_node(cpu);
474 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
475 ciu_wdog.u64 = 0;
476 ciu_wdog.s.len = timeout_cnt;
477 ciu_wdog.s.mode = 3;
478 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
479 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
480 }
481 octeon_wdt_ping(wdog);
482 return 0;
483}
484
485static int octeon_wdt_start(struct watchdog_device *wdog)
486{
487 octeon_wdt_ping(wdog);
488 do_countdown = 1;
489 return 0;
490}
491
492static int octeon_wdt_stop(struct watchdog_device *wdog)
493{
494 do_countdown = 0;
495 octeon_wdt_ping(wdog);
496 return 0;
497}
498
499static const struct watchdog_info octeon_wdt_info = {
500 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
501 .identity = "OCTEON",
502};
503
504static const struct watchdog_ops octeon_wdt_ops = {
505 .owner = THIS_MODULE,
506 .start = octeon_wdt_start,
507 .stop = octeon_wdt_stop,
508 .ping = octeon_wdt_ping,
509 .set_timeout = octeon_wdt_set_timeout,
510};
511
512static struct watchdog_device octeon_wdt = {
513 .info = &octeon_wdt_info,
514 .ops = &octeon_wdt_ops,
515};
516
517static enum cpuhp_state octeon_wdt_online;
518
519
520
521
522
523static int __init octeon_wdt_init(void)
524{
525 int ret;
526
527 octeon_wdt_bootvector = cvmx_boot_vector_get();
528 if (!octeon_wdt_bootvector) {
529 pr_err("Error: Cannot allocate boot vector.\n");
530 return -ENOMEM;
531 }
532
533 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
534 divisor = 0x200;
535 else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
536 divisor = 0x400;
537 else
538 divisor = 0x100;
539
540
541
542
543
544
545
546
547
548 max_timeout_sec = 6;
549 do {
550 max_timeout_sec--;
551 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
552 } while (timeout_cnt > 65535);
553
554 BUG_ON(timeout_cnt == 0);
555
556 octeon_wdt_calc_parameters(heartbeat);
557
558 pr_info("Initial granularity %d Sec\n", timeout_sec);
559
560 octeon_wdt.timeout = timeout_sec;
561 octeon_wdt.max_timeout = UINT_MAX;
562
563 watchdog_set_nowayout(&octeon_wdt, nowayout);
564
565 ret = watchdog_register_device(&octeon_wdt);
566 if (ret) {
567 pr_err("watchdog_register_device() failed: %d\n", ret);
568 return ret;
569 }
570
571 if (disable) {
572 pr_notice("disabled\n");
573 return 0;
574 }
575
576 cpumask_clear(&irq_enabled_cpus);
577
578 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
579 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down);
580 if (ret < 0)
581 goto err;
582 octeon_wdt_online = ret;
583 return 0;
584err:
585 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
586 watchdog_unregister_device(&octeon_wdt);
587 return ret;
588}
589
590
591
592
593static void __exit octeon_wdt_cleanup(void)
594{
595 watchdog_unregister_device(&octeon_wdt);
596
597 if (disable)
598 return;
599
600 cpuhp_remove_state(octeon_wdt_online);
601
602
603
604
605
606 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
607}
608
609MODULE_LICENSE("GPL");
610MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
611MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver.");
612module_init(octeon_wdt_init);
613module_exit(octeon_wdt_cleanup);
614