LXR linux/drivers/watchdog/sp5100

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *      sp5100_tco :    TCO timer driver for sp5100 chipsets
   4 *
   5 *      (c) Copyright 2009 Google Inc., All Rights Reserved.
   6 *
   7 *      Based on i8xx_tco.c:
   8 *      (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
   9 *      Reserved.
  10 *                              https://www.kernelconcepts.de
  11 *
  12 *      See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
  13 *          AMD Publication 45482 "AMD SB800-Series Southbridges Register
  14 *                                                            Reference Guide"
  15 *          AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
  16 *                              for AMD Family 16h Models 00h-0Fh Processors"
  17 *          AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
  18 *          AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
  19 *                              for AMD Family 16h Models 30h-3Fh Processors"
  20 *          AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
  21 *                              for AMD Family 17h Model 18h, Revision B1
  22 *                              Processors (PUB)
  23 *          AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
  24 *                              for AMD Family 17h Model 20h, Revision A1
  25 *                              Processors (PUB)
  26 */
  27
  28/*
  29 *      Includes, defines, variables, module parameters, ...
  30 */
  31
  32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34#include <linux/init.h>
  35#include <linux/io.h>
  36#include <linux/ioport.h>
  37#include <linux/module.h>
  38#include <linux/moduleparam.h>
  39#include <linux/pci.h>
  40#include <linux/platform_device.h>
  41#include <linux/types.h>
  42#include <linux/watchdog.h>
  43
  44#include "sp5100_tco.h"
  45
  46#define TCO_DRIVER_NAME "sp5100-tco"
  47
  48/* internal variables */
  49
  50enum tco_reg_layout {
  51        sp5100, sb800, efch
  52};
  53
  54struct sp5100_tco {
  55        struct watchdog_device wdd;
  56        void __iomem *tcobase;
  57        enum tco_reg_layout tco_reg_layout;
  58};
  59
  60/* the watchdog platform device */
  61static struct platform_device *sp5100_tco_platform_device;
  62/* the associated PCI device */
  63static struct pci_dev *sp5100_tco_pci;
  64
  65/* module parameters */
  66
  67#define WATCHDOG_HEARTBEAT 60   /* 60 sec default heartbeat. */
  68static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
  69module_param(heartbeat, int, 0);
  70MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
  71                 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  72
  73static bool nowayout = WATCHDOG_NOWAYOUT;
  74module_param(nowayout, bool, 0);
  75MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
  76                " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  77
  78/*
  79 * Some TCO specific functions
  80 */
  81
  82static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
  83{
  84        if (dev->vendor == PCI_VENDOR_ID_ATI &&
  85            dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
  86            dev->revision < 0x40) {
  87                return sp5100;
  88        } else if (dev->vendor == PCI_VENDOR_ID_AMD &&
  89            ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
  90             dev->revision >= 0x41) ||
  91            (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
  92             dev->revision >= 0x49))) {
  93                return efch;
  94        }
  95        return sb800;
  96}
  97
  98static int tco_timer_start(struct watchdog_device *wdd)
  99{
 100        struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 101        u32 val;
 102
 103        val = readl(SP5100_WDT_CONTROL(tco->tcobase));
 104        val |= SP5100_WDT_START_STOP_BIT;
 105        writel(val, SP5100_WDT_CONTROL(tco->tcobase));
 106
 107        return 0;
 108}
 109
 110static int tco_timer_stop(struct watchdog_device *wdd)
 111{
 112        struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 113        u32 val;
 114
 115        val = readl(SP5100_WDT_CONTROL(tco->tcobase));
 116        val &= ~SP5100_WDT_START_STOP_BIT;
 117        writel(val, SP5100_WDT_CONTROL(tco->tcobase));
 118
 119        return 0;
 120}
 121
 122static int tco_timer_ping(struct watchdog_device *wdd)
 123{
 124        struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 125        u32 val;
 126
 127        val = readl(SP5100_WDT_CONTROL(tco->tcobase));
 128        val |= SP5100_WDT_TRIGGER_BIT;
 129        writel(val, SP5100_WDT_CONTROL(tco->tcobase));
 130
 131        return 0;
 132}
 133
 134static int tco_timer_set_timeout(struct watchdog_device *wdd,
 135                                 unsigned int t)
 136{
 137        struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 138
 139        /* Write new heartbeat to watchdog */
 140        writel(t, SP5100_WDT_COUNT(tco->tcobase));
 141
 142        wdd->timeout = t;
 143
 144        return 0;
 145}
 146
 147static u8 sp5100_tco_read_pm_reg8(u8 index)
 148{
 149        outb(index, SP5100_IO_PM_INDEX_REG);
 150        return inb(SP5100_IO_PM_DATA_REG);
 151}
 152
 153static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
 154{
 155        u8 val;
 156
 157        outb(index, SP5100_IO_PM_INDEX_REG);
 158        val = inb(SP5100_IO_PM_DATA_REG);
 159        val &= reset;
 160        val |= set;
 161        outb(val, SP5100_IO_PM_DATA_REG);
 162}
 163
 164static void tco_timer_enable(struct sp5100_tco *tco)
 165{
 166        u32 val;
 167
 168        switch (tco->tco_reg_layout) {
 169        case sb800:
 170                /* For SB800 or later */
 171                /* Set the Watchdog timer resolution to 1 sec */
 172                sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
 173                                          0xff, SB800_PM_WATCHDOG_SECOND_RES);
 174
 175                /* Enable watchdog decode bit and watchdog timer */
 176                sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
 177                                          ~SB800_PM_WATCHDOG_DISABLE,
 178                                          SB800_PCI_WATCHDOG_DECODE_EN);
 179                break;
 180        case sp5100:
 181                /* For SP5100 or SB7x0 */
 182                /* Enable watchdog decode bit */
 183                pci_read_config_dword(sp5100_tco_pci,
 184                                      SP5100_PCI_WATCHDOG_MISC_REG,
 185                                      &val);
 186
 187                val |= SP5100_PCI_WATCHDOG_DECODE_EN;
 188
 189                pci_write_config_dword(sp5100_tco_pci,
 190                                       SP5100_PCI_WATCHDOG_MISC_REG,
 191                                       val);
 192
 193                /* Enable Watchdog timer and set the resolution to 1 sec */
 194                sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
 195                                          ~SP5100_PM_WATCHDOG_DISABLE,
 196                                          SP5100_PM_WATCHDOG_SECOND_RES);
 197                break;
 198        case efch:
 199                /* Set the Watchdog timer resolution to 1 sec and enable */
 200                sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
 201                                          ~EFCH_PM_WATCHDOG_DISABLE,
 202                                          EFCH_PM_DECODEEN_SECOND_RES);
 203                break;
 204        }
 205}
 206
 207static u32 sp5100_tco_read_pm_reg32(u8 index)
 208{
 209        u32 val = 0;
 210        int i;
 211
 212        for (i = 3; i >= 0; i--)
 213                val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
 214
 215        return val;
 216}
 217
 218static int sp5100_tco_setupdevice(struct device *dev,
 219                                  struct watchdog_device *wdd)
 220{
 221        struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
 222        const char *dev_name;
 223        u32 mmio_addr = 0, val;
 224        int ret;
 225
 226        /* Request the IO ports used by this driver */
 227        if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
 228                                  SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
 229                dev_err(dev, "I/O address 0x%04x already in use\n",
 230                        SP5100_IO_PM_INDEX_REG);
 231                return -EBUSY;
 232        }
 233
 234        /*
 235         * Determine type of southbridge chipset.
 236         */
 237        switch (tco->tco_reg_layout) {
 238        case sp5100:
 239                dev_name = SP5100_DEVNAME;
 240                mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
 241                                                                0xfffffff8;
 242                break;
 243        case sb800:
 244                dev_name = SB800_DEVNAME;
 245                mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
 246                                                                0xfffffff8;
 247                break;
 248        case efch:
 249                dev_name = SB800_DEVNAME;
 250                /*
 251                 * On Family 17h devices, the EFCH_PM_DECODEEN_WDT_TMREN bit of
 252                 * EFCH_PM_DECODEEN not only enables the EFCH_PM_WDT_ADDR memory
 253                 * region, it also enables the watchdog itself.
 254                 */
 255                if (boot_cpu_data.x86 == 0x17) {
 256                        val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
 257                        if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
 258                                sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN, 0xff,
 259                                                          EFCH_PM_DECODEEN_WDT_TMREN);
 260                        }
 261                }
 262                val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
 263                if (val & EFCH_PM_DECODEEN_WDT_TMREN)
 264                        mmio_addr = EFCH_PM_WDT_ADDR;
 265                break;
 266        default:
 267                return -ENODEV;
 268        }
 269
 270        /* Check MMIO address conflict */
 271        if (!mmio_addr ||
 272            !devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
 273                                     dev_name)) {
 274                if (mmio_addr)
 275                        dev_dbg(dev, "MMIO address 0x%08x already in use\n",
 276                                mmio_addr);
 277                switch (tco->tco_reg_layout) {
 278                case sp5100:
 279                        /*
 280                         * Secondly, Find the watchdog timer MMIO address
 281                         * from SBResource_MMIO register.
 282                         */
 283                        /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
 284                        pci_read_config_dword(sp5100_tco_pci,
 285                                              SP5100_SB_RESOURCE_MMIO_BASE,
 286                                              &mmio_addr);
 287                        if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
 288                                          SB800_ACPI_MMIO_SEL)) !=
 289                                                  SB800_ACPI_MMIO_DECODE_EN) {
 290                                ret = -ENODEV;
 291                                goto unreg_region;
 292                        }
 293                        mmio_addr &= ~0xFFF;
 294                        mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
 295                        break;
 296                case sb800:
 297                        /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
 298                        mmio_addr =
 299                                sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
 300                        if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
 301                                          SB800_ACPI_MMIO_SEL)) !=
 302                                                  SB800_ACPI_MMIO_DECODE_EN) {
 303                                ret = -ENODEV;
 304                                goto unreg_region;
 305                        }
 306                        mmio_addr &= ~0xFFF;
 307                        mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
 308                        break;
 309                case efch:
 310                        val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
 311                        if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
 312                                ret = -ENODEV;
 313                                goto unreg_region;
 314                        }
 315                        mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
 316                                    EFCH_PM_ACPI_MMIO_WDT_OFFSET;
 317                        break;
 318                }
 319                dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
 320                        mmio_addr);
 321                if (!devm_request_mem_region(dev, mmio_addr,
 322                                             SP5100_WDT_MEM_MAP_SIZE,
 323                                             dev_name)) {
 324                        dev_dbg(dev, "MMIO address 0x%08x already in use\n",
 325                                mmio_addr);
 326                        ret = -EBUSY;
 327                        goto unreg_region;
 328                }
 329        }
 330
 331        tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
 332        if (!tco->tcobase) {
 333                dev_err(dev, "failed to get tcobase address\n");
 334                ret = -ENOMEM;
 335                goto unreg_region;
 336        }
 337
 338        dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
 339
 340        /* Setup the watchdog timer */
 341        tco_timer_enable(tco);
 342
 343        val = readl(SP5100_WDT_CONTROL(tco->tcobase));
 344        if (val & SP5100_WDT_DISABLED) {
 345                dev_err(dev, "Watchdog hardware is disabled\n");
 346                ret = -ENODEV;
 347                goto unreg_region;
 348        }
 349
 350        /*
 351         * Save WatchDogFired status, because WatchDogFired flag is
 352         * cleared here.
 353         */
 354        if (val & SP5100_WDT_FIRED)
 355                wdd->bootstatus = WDIOF_CARDRESET;
 356        /* Set watchdog action to reset the system */
 357        val &= ~SP5100_WDT_ACTION_RESET;
 358        writel(val, SP5100_WDT_CONTROL(tco->tcobase));
 359
 360        /* Set a reasonable heartbeat before we stop the timer */
 361        tco_timer_set_timeout(wdd, wdd->timeout);
 362
 363        /*
 364         * Stop the TCO before we change anything so we don't race with
 365         * a zeroed timer.
 366         */
 367        tco_timer_stop(wdd);
 368
 369        release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
 370
 371        return 0;
 372
 373unreg_region:
 374        release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
 375        return ret;
 376}
 377
 378static struct watchdog_info sp5100_tco_wdt_info = {
 379        .identity = "SP5100 TCO timer",
 380        .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
 381};
 382
 383static const struct watchdog_ops sp5100_tco_wdt_ops = {
 384        .owner = THIS_MODULE,
 385        .start = tco_timer_start,
 386        .stop = tco_timer_stop,
 387        .ping = tco_timer_ping,
 388        .set_timeout = tco_timer_set_timeout,
 389};
 390
 391static int sp5100_tco_probe(struct platform_device *pdev)
 392{
 393        struct device *dev = &pdev->dev;
 394        struct watchdog_device *wdd;
 395        struct sp5100_tco *tco;
 396        int ret;
 397
 398        tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
 399        if (!tco)
 400                return -ENOMEM;
 401
 402        tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
 403
 404        wdd = &tco->wdd;
 405        wdd->parent = dev;
 406        wdd->info = &sp5100_tco_wdt_info;
 407        wdd->ops = &sp5100_tco_wdt_ops;
 408        wdd->timeout = WATCHDOG_HEARTBEAT;
 409        wdd->min_timeout = 1;
 410        wdd->max_timeout = 0xffff;
 411
 412        watchdog_init_timeout(wdd, heartbeat, NULL);
 413        watchdog_set_nowayout(wdd, nowayout);
 414        watchdog_stop_on_reboot(wdd);
 415        watchdog_stop_on_unregister(wdd);
 416        watchdog_set_drvdata(wdd, tco);
 417
 418        ret = sp5100_tco_setupdevice(dev, wdd);
 419        if (ret)
 420                return ret;
 421
 422        ret = devm_watchdog_register_device(dev, wdd);
 423        if (ret)
 424                return ret;
 425
 426        /* Show module parameters */
 427        dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
 428                 wdd->timeout, nowayout);
 429
 430        return 0;
 431}
 432
 433static struct platform_driver sp5100_tco_driver = {
 434        .probe          = sp5100_tco_probe,
 435        .driver         = {
 436                .name   = TCO_DRIVER_NAME,
 437        },
 438};
 439
 440/*
 441 * Data for PCI driver interface
 442 *
 443 * This data only exists for exporting the supported
 444 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 445 * register a pci_driver, because someone else might
 446 * want to register another driver on the same PCI id.
 447 */
 448static const struct pci_device_id sp5100_tco_pci_tbl[] = {
 449        { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
 450          PCI_ANY_ID, },
 451        { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
 452          PCI_ANY_ID, },
 453        { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
 454          PCI_ANY_ID, },
 455        { 0, },                 /* End of list */
 456};
 457MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
 458
 459static int __init sp5100_tco_init(void)
 460{
 461        struct pci_dev *dev = NULL;
 462        int err;
 463
 464        /* Match the PCI device */
 465        for_each_pci_dev(dev) {
 466                if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
 467                        sp5100_tco_pci = dev;
 468                        break;
 469                }
 470        }
 471
 472        if (!sp5100_tco_pci)
 473                return -ENODEV;
 474
 475        pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
 476
 477        err = platform_driver_register(&sp5100_tco_driver);
 478        if (err)
 479                return err;
 480
 481        sp5100_tco_platform_device =
 482                platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
 483        if (IS_ERR(sp5100_tco_platform_device)) {
 484                err = PTR_ERR(sp5100_tco_platform_device);
 485                goto unreg_platform_driver;
 486        }
 487
 488        return 0;
 489
 490unreg_platform_driver:
 491        platform_driver_unregister(&sp5100_tco_driver);
 492        return err;
 493}
 494
 495static void __exit sp5100_tco_exit(void)
 496{
 497        platform_device_unregister(sp5100_tco_platform_device);
 498        platform_driver_unregister(&sp5100_tco_driver);
 499}
 500
 501module_init(sp5100_tco_init);
 502module_exit(sp5100_tco_exit);
 503
 504MODULE_AUTHOR("Priyanka Gupta");
 505MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
 506MODULE_LICENSE("GPL");
 507