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10#ifndef __ACTBL1_H__
11#define __ACTBL1_H__
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26
27#define ACPI_SIG_AEST "AEST"
28#define ACPI_SIG_ASF "ASF!"
29#define ACPI_SIG_BERT "BERT"
30#define ACPI_SIG_BGRT "BGRT"
31#define ACPI_SIG_BOOT "BOOT"
32#define ACPI_SIG_CEDT "CEDT"
33#define ACPI_SIG_CPEP "CPEP"
34#define ACPI_SIG_CSRT "CSRT"
35#define ACPI_SIG_DBG2 "DBG2"
36#define ACPI_SIG_DBGP "DBGP"
37#define ACPI_SIG_DMAR "DMAR"
38#define ACPI_SIG_DRTM "DRTM"
39#define ACPI_SIG_ECDT "ECDT"
40#define ACPI_SIG_EINJ "EINJ"
41#define ACPI_SIG_ERST "ERST"
42#define ACPI_SIG_FPDT "FPDT"
43#define ACPI_SIG_GTDT "GTDT"
44#define ACPI_SIG_HEST "HEST"
45#define ACPI_SIG_HMAT "HMAT"
46#define ACPI_SIG_HPET "HPET"
47#define ACPI_SIG_IBFT "IBFT"
48
49#define ACPI_SIG_S3PT "S3PT"
50#define ACPI_SIG_PCCS "PCC"
51
52
53
54#define ACPI_SIG_MATR "MATR"
55#define ACPI_SIG_MSDM "MSDM"
56
57
58
59
60#ifdef ACPI_UNDEFINED_TABLES
61#define ACPI_SIG_ATKG "ATKG"
62#define ACPI_SIG_GSCI "GSCI"
63#define ACPI_SIG_IEIT "IEIT"
64#endif
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66
67
68
69
70#pragma pack(1)
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91
92struct acpi_subtable_header {
93 u8 type;
94 u8 length;
95};
96
97
98
99struct acpi_whea_header {
100 u8 action;
101 u8 instruction;
102 u8 flags;
103 u8 reserved;
104 struct acpi_generic_address register_region;
105 u64 value;
106 u64 mask;
107};
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116
117
118struct acpi_table_asf {
119 struct acpi_table_header header;
120};
121
122
123
124struct acpi_asf_header {
125 u8 type;
126 u8 reserved;
127 u16 length;
128};
129
130
131
132enum acpi_asf_type {
133 ACPI_ASF_TYPE_INFO = 0,
134 ACPI_ASF_TYPE_ALERT = 1,
135 ACPI_ASF_TYPE_CONTROL = 2,
136 ACPI_ASF_TYPE_BOOT = 3,
137 ACPI_ASF_TYPE_ADDRESS = 4,
138 ACPI_ASF_TYPE_RESERVED = 5
139};
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141
142
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144
145
146
147struct acpi_asf_info {
148 struct acpi_asf_header header;
149 u8 min_reset_value;
150 u8 min_poll_interval;
151 u16 system_id;
152 u32 mfg_id;
153 u8 flags;
154 u8 reserved2[3];
155};
156
157
158
159#define ACPI_ASF_SMBUS_PROTOCOLS (1)
160
161
162
163struct acpi_asf_alert {
164 struct acpi_asf_header header;
165 u8 assert_mask;
166 u8 deassert_mask;
167 u8 alerts;
168 u8 data_length;
169};
170
171struct acpi_asf_alert_data {
172 u8 address;
173 u8 command;
174 u8 mask;
175 u8 value;
176 u8 sensor_type;
177 u8 type;
178 u8 offset;
179 u8 source_type;
180 u8 severity;
181 u8 sensor_number;
182 u8 entity;
183 u8 instance;
184};
185
186
187
188struct acpi_asf_remote {
189 struct acpi_asf_header header;
190 u8 controls;
191 u8 data_length;
192 u16 reserved2;
193};
194
195struct acpi_asf_control_data {
196 u8 function;
197 u8 address;
198 u8 command;
199 u8 value;
200};
201
202
203
204struct acpi_asf_rmcp {
205 struct acpi_asf_header header;
206 u8 capabilities[7];
207 u8 completion_code;
208 u32 enterprise_id;
209 u8 command;
210 u16 parameter;
211 u16 boot_options;
212 u16 oem_parameters;
213};
214
215
216
217struct acpi_asf_address {
218 struct acpi_asf_header header;
219 u8 eprom_address;
220 u8 devices;
221};
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228
229
230struct acpi_table_bert {
231 struct acpi_table_header header;
232 u32 region_length;
233 u64 address;
234};
235
236
237
238struct acpi_bert_region {
239 u32 block_status;
240 u32 raw_data_offset;
241 u32 raw_data_length;
242 u32 data_length;
243 u32 error_severity;
244};
245
246
247
248#define ACPI_BERT_UNCORRECTABLE (1)
249#define ACPI_BERT_CORRECTABLE (1<<1)
250#define ACPI_BERT_MULTIPLE_UNCORRECTABLE (1<<2)
251#define ACPI_BERT_MULTIPLE_CORRECTABLE (1<<3)
252#define ACPI_BERT_ERROR_ENTRY_COUNT (0xFF<<4)
253
254
255
256enum acpi_bert_error_severity {
257 ACPI_BERT_ERROR_CORRECTABLE = 0,
258 ACPI_BERT_ERROR_FATAL = 1,
259 ACPI_BERT_ERROR_CORRECTED = 2,
260 ACPI_BERT_ERROR_NONE = 3,
261 ACPI_BERT_ERROR_RESERVED = 4
262};
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276struct acpi_table_bgrt {
277 struct acpi_table_header header;
278 u16 version;
279 u8 status;
280 u8 image_type;
281 u64 image_address;
282 u32 image_offset_x;
283 u32 image_offset_y;
284};
285
286
287
288#define ACPI_BGRT_DISPLAYED (1)
289#define ACPI_BGRT_ORIENTATION_OFFSET (3 << 1)
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299
300struct acpi_table_boot {
301 struct acpi_table_header header;
302 u8 cmos_index;
303 u8 reserved[3];
304};
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314
315struct acpi_table_cedt {
316 struct acpi_table_header header;
317};
318
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320
321struct acpi_cedt_header {
322 u8 type;
323 u8 reserved;
324 u16 length;
325};
326
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328
329enum acpi_cedt_type {
330 ACPI_CEDT_TYPE_CHBS = 0,
331 ACPI_CEDT_TYPE_CFMWS = 1,
332 ACPI_CEDT_TYPE_RESERVED = 2,
333};
334
335
336
337#define ACPI_CEDT_CHBS_VERSION_CXL11 (0)
338#define ACPI_CEDT_CHBS_VERSION_CXL20 (1)
339
340
341
342#define ACPI_CEDT_CHBS_LENGTH_CXL11 (0x2000)
343#define ACPI_CEDT_CHBS_LENGTH_CXL20 (0x10000)
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350
351struct acpi_cedt_chbs {
352 struct acpi_cedt_header header;
353 u32 uid;
354 u32 cxl_version;
355 u32 reserved;
356 u64 base;
357 u64 length;
358};
359
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361
362struct acpi_cedt_cfmws {
363 struct acpi_cedt_header header;
364 u32 reserved1;
365 u64 base_hpa;
366 u64 window_size;
367 u8 interleave_ways;
368 u8 interleave_arithmetic;
369 u16 reserved2;
370 u32 granularity;
371 u16 restrictions;
372 u16 qtg_id;
373 u32 interleave_targets[];
374};
375
376
377
378#define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0)
379
380
381
382#define ACPI_CEDT_CFMWS_RESTRICT_TYPE2 (1)
383#define ACPI_CEDT_CFMWS_RESTRICT_TYPE3 (1<<1)
384#define ACPI_CEDT_CFMWS_RESTRICT_VOLATILE (1<<2)
385#define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3)
386#define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4)
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394
395struct acpi_table_cpep {
396 struct acpi_table_header header;
397 u64 reserved;
398};
399
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401
402struct acpi_cpep_polling {
403 struct acpi_subtable_header header;
404 u8 id;
405 u8 eid;
406 u32 interval;
407};
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417
418struct acpi_table_csrt {
419 struct acpi_table_header header;
420};
421
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423
424struct acpi_csrt_group {
425 u32 length;
426 u32 vendor_id;
427 u32 subvendor_id;
428 u16 device_id;
429 u16 subdevice_id;
430 u16 revision;
431 u16 reserved;
432 u32 shared_info_length;
433
434
435};
436
437
438
439struct acpi_csrt_shared_info {
440 u16 major_version;
441 u16 minor_version;
442 u32 mmio_base_low;
443 u32 mmio_base_high;
444 u32 gsi_interrupt;
445 u8 interrupt_polarity;
446 u8 interrupt_mode;
447 u8 num_channels;
448 u8 dma_address_width;
449 u16 base_request_line;
450 u16 num_handshake_signals;
451 u32 max_block_size;
452
453
454};
455
456
457
458struct acpi_csrt_descriptor {
459 u32 length;
460 u16 type;
461 u16 subtype;
462 u32 uid;
463
464
465};
466
467
468
469#define ACPI_CSRT_TYPE_INTERRUPT 0x0001
470#define ACPI_CSRT_TYPE_TIMER 0x0002
471#define ACPI_CSRT_TYPE_DMA 0x0003
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473
474
475#define ACPI_CSRT_XRUPT_LINE 0x0000
476#define ACPI_CSRT_XRUPT_CONTROLLER 0x0001
477#define ACPI_CSRT_TIMER 0x0000
478#define ACPI_CSRT_DMA_CHANNEL 0x0000
479#define ACPI_CSRT_DMA_CONTROLLER 0x0001
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489
490struct acpi_table_dbg2 {
491 struct acpi_table_header header;
492 u32 info_offset;
493 u32 info_count;
494};
495
496struct acpi_dbg2_header {
497 u32 info_offset;
498 u32 info_count;
499};
500
501
502
503struct acpi_dbg2_device {
504 u8 revision;
505 u16 length;
506 u8 register_count;
507 u16 namepath_length;
508 u16 namepath_offset;
509 u16 oem_data_length;
510 u16 oem_data_offset;
511 u16 port_type;
512 u16 port_subtype;
513 u16 reserved;
514 u16 base_address_offset;
515 u16 address_size_offset;
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519
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523};
524
525
526
527#define ACPI_DBG2_SERIAL_PORT 0x8000
528#define ACPI_DBG2_1394_PORT 0x8001
529#define ACPI_DBG2_USB_PORT 0x8002
530#define ACPI_DBG2_NET_PORT 0x8003
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533
534#define ACPI_DBG2_16550_COMPATIBLE 0x0000
535#define ACPI_DBG2_16550_SUBSET 0x0001
536#define ACPI_DBG2_MAX311XE_SPI 0x0002
537#define ACPI_DBG2_ARM_PL011 0x0003
538#define ACPI_DBG2_MSM8X60 0x0004
539#define ACPI_DBG2_16550_NVIDIA 0x0005
540#define ACPI_DBG2_TI_OMAP 0x0006
541#define ACPI_DBG2_APM88XXXX 0x0008
542#define ACPI_DBG2_MSM8974 0x0009
543#define ACPI_DBG2_SAM5250 0x000A
544#define ACPI_DBG2_INTEL_USIF 0x000B
545#define ACPI_DBG2_IMX6 0x000C
546#define ACPI_DBG2_ARM_SBSA_32BIT 0x000D
547#define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E
548#define ACPI_DBG2_ARM_DCC 0x000F
549#define ACPI_DBG2_BCM2835 0x0010
550#define ACPI_DBG2_SDM845_1_8432MHZ 0x0011
551#define ACPI_DBG2_16550_WITH_GAS 0x0012
552#define ACPI_DBG2_SDM845_7_372MHZ 0x0013
553#define ACPI_DBG2_INTEL_LPSS 0x0014
554
555#define ACPI_DBG2_1394_STANDARD 0x0000
556
557#define ACPI_DBG2_USB_XHCI 0x0000
558#define ACPI_DBG2_USB_EHCI 0x0001
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568
569struct acpi_table_dbgp {
570 struct acpi_table_header header;
571 u8 type;
572 u8 reserved[3];
573 struct acpi_generic_address debug_port;
574};
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586struct acpi_table_dmar {
587 struct acpi_table_header header;
588 u8 width;
589 u8 flags;
590 u8 reserved[10];
591};
592
593
594
595#define ACPI_DMAR_INTR_REMAP (1)
596#define ACPI_DMAR_X2APIC_OPT_OUT (1<<1)
597#define ACPI_DMAR_X2APIC_MODE (1<<2)
598
599
600
601struct acpi_dmar_header {
602 u16 type;
603 u16 length;
604};
605
606
607
608enum acpi_dmar_type {
609 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0,
610 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1,
611 ACPI_DMAR_TYPE_ROOT_ATS = 2,
612 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3,
613 ACPI_DMAR_TYPE_NAMESPACE = 4,
614 ACPI_DMAR_TYPE_SATC = 5,
615 ACPI_DMAR_TYPE_RESERVED = 6
616};
617
618
619
620struct acpi_dmar_device_scope {
621 u8 entry_type;
622 u8 length;
623 u16 reserved;
624 u8 enumeration_id;
625 u8 bus;
626};
627
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629
630enum acpi_dmar_scope_type {
631 ACPI_DMAR_SCOPE_TYPE_NOT_USED = 0,
632 ACPI_DMAR_SCOPE_TYPE_ENDPOINT = 1,
633 ACPI_DMAR_SCOPE_TYPE_BRIDGE = 2,
634 ACPI_DMAR_SCOPE_TYPE_IOAPIC = 3,
635 ACPI_DMAR_SCOPE_TYPE_HPET = 4,
636 ACPI_DMAR_SCOPE_TYPE_NAMESPACE = 5,
637 ACPI_DMAR_SCOPE_TYPE_RESERVED = 6
638};
639
640struct acpi_dmar_pci_path {
641 u8 device;
642 u8 function;
643};
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651struct acpi_dmar_hardware_unit {
652 struct acpi_dmar_header header;
653 u8 flags;
654 u8 reserved;
655 u16 segment;
656 u64 address;
657};
658
659
660
661#define ACPI_DMAR_INCLUDE_ALL (1)
662
663
664
665struct acpi_dmar_reserved_memory {
666 struct acpi_dmar_header header;
667 u16 reserved;
668 u16 segment;
669 u64 base_address;
670 u64 end_address;
671};
672
673
674
675#define ACPI_DMAR_ALLOW_ALL (1)
676
677
678
679struct acpi_dmar_atsr {
680 struct acpi_dmar_header header;
681 u8 flags;
682 u8 reserved;
683 u16 segment;
684};
685
686
687
688#define ACPI_DMAR_ALL_PORTS (1)
689
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691
692struct acpi_dmar_rhsa {
693 struct acpi_dmar_header header;
694 u32 reserved;
695 u64 base_address;
696 u32 proximity_domain;
697};
698
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701struct acpi_dmar_andd {
702 struct acpi_dmar_header header;
703 u8 reserved[3];
704 u8 device_number;
705 char device_name[1];
706};
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710struct acpi_dmar_satc {
711 struct acpi_dmar_header header;
712 u8 flags;
713 u8 reserved;
714 u16 segment;
715};
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723
724struct acpi_table_drtm {
725 struct acpi_table_header header;
726 u64 entry_base_address;
727 u64 entry_length;
728 u32 entry_address32;
729 u64 entry_address64;
730 u64 exit_address;
731 u64 log_area_address;
732 u32 log_area_length;
733 u64 arch_dependent_address;
734 u32 flags;
735};
736
737
738
739#define ACPI_DRTM_ACCESS_ALLOWED (1)
740#define ACPI_DRTM_ENABLE_GAP_CODE (1<<1)
741#define ACPI_DRTM_INCOMPLETE_MEASUREMENTS (1<<2)
742#define ACPI_DRTM_AUTHORITY_ORDER (1<<3)
743
744
745
746struct acpi_drtm_vtable_list {
747 u32 validated_table_count;
748 u64 validated_tables[1];
749};
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755struct acpi_drtm_resource {
756 u8 size[7];
757 u8 type;
758 u64 address;
759};
760
761struct acpi_drtm_resource_list {
762 u32 resource_count;
763 struct acpi_drtm_resource resources[1];
764};
765
766
767
768struct acpi_drtm_dps_id {
769 u32 dps_id_length;
770 u8 dps_id[16];
771};
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780struct acpi_table_ecdt {
781 struct acpi_table_header header;
782 struct acpi_generic_address control;
783 struct acpi_generic_address data;
784 u32 uid;
785 u8 gpe;
786 u8 id[1];
787};
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795
796struct acpi_table_einj {
797 struct acpi_table_header header;
798 u32 header_length;
799 u8 flags;
800 u8 reserved[3];
801 u32 entries;
802};
803
804
805
806struct acpi_einj_entry {
807 struct acpi_whea_header whea_header;
808};
809
810
811
812#define ACPI_EINJ_PRESERVE (1)
813
814
815
816enum acpi_einj_actions {
817 ACPI_EINJ_BEGIN_OPERATION = 0,
818 ACPI_EINJ_GET_TRIGGER_TABLE = 1,
819 ACPI_EINJ_SET_ERROR_TYPE = 2,
820 ACPI_EINJ_GET_ERROR_TYPE = 3,
821 ACPI_EINJ_END_OPERATION = 4,
822 ACPI_EINJ_EXECUTE_OPERATION = 5,
823 ACPI_EINJ_CHECK_BUSY_STATUS = 6,
824 ACPI_EINJ_GET_COMMAND_STATUS = 7,
825 ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS = 8,
826 ACPI_EINJ_GET_EXECUTE_TIMINGS = 9,
827 ACPI_EINJ_ACTION_RESERVED = 10,
828 ACPI_EINJ_TRIGGER_ERROR = 0xFF
829};
830
831
832
833enum acpi_einj_instructions {
834 ACPI_EINJ_READ_REGISTER = 0,
835 ACPI_EINJ_READ_REGISTER_VALUE = 1,
836 ACPI_EINJ_WRITE_REGISTER = 2,
837 ACPI_EINJ_WRITE_REGISTER_VALUE = 3,
838 ACPI_EINJ_NOOP = 4,
839 ACPI_EINJ_FLUSH_CACHELINE = 5,
840 ACPI_EINJ_INSTRUCTION_RESERVED = 6
841};
842
843struct acpi_einj_error_type_with_addr {
844 u32 error_type;
845 u32 vendor_struct_offset;
846 u32 flags;
847 u32 apic_id;
848 u64 address;
849 u64 range;
850 u32 pcie_id;
851};
852
853struct acpi_einj_vendor {
854 u32 length;
855 u32 pcie_id;
856 u16 vendor_id;
857 u16 device_id;
858 u8 revision_id;
859 u8 reserved[3];
860};
861
862
863
864struct acpi_einj_trigger {
865 u32 header_size;
866 u32 revision;
867 u32 table_size;
868 u32 entry_count;
869};
870
871
872
873enum acpi_einj_command_status {
874 ACPI_EINJ_SUCCESS = 0,
875 ACPI_EINJ_FAILURE = 1,
876 ACPI_EINJ_INVALID_ACCESS = 2,
877 ACPI_EINJ_STATUS_RESERVED = 3
878};
879
880
881
882#define ACPI_EINJ_PROCESSOR_CORRECTABLE (1)
883#define ACPI_EINJ_PROCESSOR_UNCORRECTABLE (1<<1)
884#define ACPI_EINJ_PROCESSOR_FATAL (1<<2)
885#define ACPI_EINJ_MEMORY_CORRECTABLE (1<<3)
886#define ACPI_EINJ_MEMORY_UNCORRECTABLE (1<<4)
887#define ACPI_EINJ_MEMORY_FATAL (1<<5)
888#define ACPI_EINJ_PCIX_CORRECTABLE (1<<6)
889#define ACPI_EINJ_PCIX_UNCORRECTABLE (1<<7)
890#define ACPI_EINJ_PCIX_FATAL (1<<8)
891#define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9)
892#define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10)
893#define ACPI_EINJ_PLATFORM_FATAL (1<<11)
894#define ACPI_EINJ_VENDOR_DEFINED (1<<31)
895
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901
902
903struct acpi_table_erst {
904 struct acpi_table_header header;
905 u32 header_length;
906 u32 reserved;
907 u32 entries;
908};
909
910
911
912struct acpi_erst_entry {
913 struct acpi_whea_header whea_header;
914};
915
916
917
918#define ACPI_ERST_PRESERVE (1)
919
920
921
922enum acpi_erst_actions {
923 ACPI_ERST_BEGIN_WRITE = 0,
924 ACPI_ERST_BEGIN_READ = 1,
925 ACPI_ERST_BEGIN_CLEAR = 2,
926 ACPI_ERST_END = 3,
927 ACPI_ERST_SET_RECORD_OFFSET = 4,
928 ACPI_ERST_EXECUTE_OPERATION = 5,
929 ACPI_ERST_CHECK_BUSY_STATUS = 6,
930 ACPI_ERST_GET_COMMAND_STATUS = 7,
931 ACPI_ERST_GET_RECORD_ID = 8,
932 ACPI_ERST_SET_RECORD_ID = 9,
933 ACPI_ERST_GET_RECORD_COUNT = 10,
934 ACPI_ERST_BEGIN_DUMMY_WRIITE = 11,
935 ACPI_ERST_NOT_USED = 12,
936 ACPI_ERST_GET_ERROR_RANGE = 13,
937 ACPI_ERST_GET_ERROR_LENGTH = 14,
938 ACPI_ERST_GET_ERROR_ATTRIBUTES = 15,
939 ACPI_ERST_EXECUTE_TIMINGS = 16,
940 ACPI_ERST_ACTION_RESERVED = 17
941};
942
943
944
945enum acpi_erst_instructions {
946 ACPI_ERST_READ_REGISTER = 0,
947 ACPI_ERST_READ_REGISTER_VALUE = 1,
948 ACPI_ERST_WRITE_REGISTER = 2,
949 ACPI_ERST_WRITE_REGISTER_VALUE = 3,
950 ACPI_ERST_NOOP = 4,
951 ACPI_ERST_LOAD_VAR1 = 5,
952 ACPI_ERST_LOAD_VAR2 = 6,
953 ACPI_ERST_STORE_VAR1 = 7,
954 ACPI_ERST_ADD = 8,
955 ACPI_ERST_SUBTRACT = 9,
956 ACPI_ERST_ADD_VALUE = 10,
957 ACPI_ERST_SUBTRACT_VALUE = 11,
958 ACPI_ERST_STALL = 12,
959 ACPI_ERST_STALL_WHILE_TRUE = 13,
960 ACPI_ERST_SKIP_NEXT_IF_TRUE = 14,
961 ACPI_ERST_GOTO = 15,
962 ACPI_ERST_SET_SRC_ADDRESS_BASE = 16,
963 ACPI_ERST_SET_DST_ADDRESS_BASE = 17,
964 ACPI_ERST_MOVE_DATA = 18,
965 ACPI_ERST_INSTRUCTION_RESERVED = 19
966};
967
968
969
970enum acpi_erst_command_status {
971 ACPI_ERST_SUCCESS = 0,
972 ACPI_ERST_NO_SPACE = 1,
973 ACPI_ERST_NOT_AVAILABLE = 2,
974 ACPI_ERST_FAILURE = 3,
975 ACPI_ERST_RECORD_EMPTY = 4,
976 ACPI_ERST_NOT_FOUND = 5,
977 ACPI_ERST_STATUS_RESERVED = 6
978};
979
980
981
982struct acpi_erst_info {
983 u16 signature;
984 u8 data[48];
985};
986
987
988
989
990
991
992
993
994struct acpi_table_fpdt {
995 struct acpi_table_header header;
996};
997
998
999
1000struct acpi_fpdt_header {
1001 u16 type;
1002 u8 length;
1003 u8 revision;
1004};
1005
1006
1007
1008enum acpi_fpdt_type {
1009 ACPI_FPDT_TYPE_BOOT = 0,
1010 ACPI_FPDT_TYPE_S3PERF = 1
1011};
1012
1013
1014
1015
1016
1017
1018
1019struct acpi_fpdt_boot_pointer {
1020 struct acpi_fpdt_header header;
1021 u8 reserved[4];
1022 u64 address;
1023};
1024
1025
1026
1027struct acpi_fpdt_s3pt_pointer {
1028 struct acpi_fpdt_header header;
1029 u8 reserved[4];
1030 u64 address;
1031};
1032
1033
1034
1035
1036
1037struct acpi_table_s3pt {
1038 u8 signature[4];
1039 u32 length;
1040};
1041
1042
1043
1044
1045
1046
1047
1048enum acpi_s3pt_type {
1049 ACPI_S3PT_TYPE_RESUME = 0,
1050 ACPI_S3PT_TYPE_SUSPEND = 1,
1051 ACPI_FPDT_BOOT_PERFORMANCE = 2
1052};
1053
1054struct acpi_s3pt_resume {
1055 struct acpi_fpdt_header header;
1056 u32 resume_count;
1057 u64 full_resume;
1058 u64 average_resume;
1059};
1060
1061struct acpi_s3pt_suspend {
1062 struct acpi_fpdt_header header;
1063 u64 suspend_start;
1064 u64 suspend_end;
1065};
1066
1067
1068
1069
1070struct acpi_fpdt_boot {
1071 struct acpi_fpdt_header header;
1072 u8 reserved[4];
1073 u64 reset_end;
1074 u64 load_start;
1075 u64 startup_start;
1076 u64 exit_services_entry;
1077 u64 exit_services_exit;
1078};
1079
1080
1081
1082
1083
1084
1085
1086
1087struct acpi_table_gtdt {
1088 struct acpi_table_header header;
1089 u64 counter_block_addresss;
1090 u32 reserved;
1091 u32 secure_el1_interrupt;
1092 u32 secure_el1_flags;
1093 u32 non_secure_el1_interrupt;
1094 u32 non_secure_el1_flags;
1095 u32 virtual_timer_interrupt;
1096 u32 virtual_timer_flags;
1097 u32 non_secure_el2_interrupt;
1098 u32 non_secure_el2_flags;
1099 u64 counter_read_block_address;
1100 u32 platform_timer_count;
1101 u32 platform_timer_offset;
1102};
1103
1104
1105
1106#define ACPI_GTDT_INTERRUPT_MODE (1)
1107#define ACPI_GTDT_INTERRUPT_POLARITY (1<<1)
1108#define ACPI_GTDT_ALWAYS_ON (1<<2)
1109
1110struct acpi_gtdt_el2 {
1111 u32 virtual_el2_timer_gsiv;
1112 u32 virtual_el2_timer_flags;
1113};
1114
1115
1116
1117struct acpi_gtdt_header {
1118 u8 type;
1119 u16 length;
1120};
1121
1122
1123
1124enum acpi_gtdt_type {
1125 ACPI_GTDT_TYPE_TIMER_BLOCK = 0,
1126 ACPI_GTDT_TYPE_WATCHDOG = 1,
1127 ACPI_GTDT_TYPE_RESERVED = 2
1128};
1129
1130
1131
1132
1133
1134struct acpi_gtdt_timer_block {
1135 struct acpi_gtdt_header header;
1136 u8 reserved;
1137 u64 block_address;
1138 u32 timer_count;
1139 u32 timer_offset;
1140};
1141
1142
1143
1144struct acpi_gtdt_timer_entry {
1145 u8 frame_number;
1146 u8 reserved[3];
1147 u64 base_address;
1148 u64 el0_base_address;
1149 u32 timer_interrupt;
1150 u32 timer_flags;
1151 u32 virtual_timer_interrupt;
1152 u32 virtual_timer_flags;
1153 u32 common_flags;
1154};
1155
1156
1157
1158#define ACPI_GTDT_GT_IRQ_MODE (1)
1159#define ACPI_GTDT_GT_IRQ_POLARITY (1<<1)
1160
1161
1162
1163#define ACPI_GTDT_GT_IS_SECURE_TIMER (1)
1164#define ACPI_GTDT_GT_ALWAYS_ON (1<<1)
1165
1166
1167
1168struct acpi_gtdt_watchdog {
1169 struct acpi_gtdt_header header;
1170 u8 reserved;
1171 u64 refresh_frame_address;
1172 u64 control_frame_address;
1173 u32 timer_interrupt;
1174 u32 timer_flags;
1175};
1176
1177
1178
1179#define ACPI_GTDT_WATCHDOG_IRQ_MODE (1)
1180#define ACPI_GTDT_WATCHDOG_IRQ_POLARITY (1<<1)
1181#define ACPI_GTDT_WATCHDOG_SECURE (1<<2)
1182
1183
1184
1185
1186
1187
1188
1189
1190struct acpi_table_hest {
1191 struct acpi_table_header header;
1192 u32 error_source_count;
1193};
1194
1195
1196
1197struct acpi_hest_header {
1198 u16 type;
1199 u16 source_id;
1200};
1201
1202
1203
1204enum acpi_hest_types {
1205 ACPI_HEST_TYPE_IA32_CHECK = 0,
1206 ACPI_HEST_TYPE_IA32_CORRECTED_CHECK = 1,
1207 ACPI_HEST_TYPE_IA32_NMI = 2,
1208 ACPI_HEST_TYPE_NOT_USED3 = 3,
1209 ACPI_HEST_TYPE_NOT_USED4 = 4,
1210 ACPI_HEST_TYPE_NOT_USED5 = 5,
1211 ACPI_HEST_TYPE_AER_ROOT_PORT = 6,
1212 ACPI_HEST_TYPE_AER_ENDPOINT = 7,
1213 ACPI_HEST_TYPE_AER_BRIDGE = 8,
1214 ACPI_HEST_TYPE_GENERIC_ERROR = 9,
1215 ACPI_HEST_TYPE_GENERIC_ERROR_V2 = 10,
1216 ACPI_HEST_TYPE_IA32_DEFERRED_CHECK = 11,
1217 ACPI_HEST_TYPE_RESERVED = 12
1218};
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228struct acpi_hest_ia_error_bank {
1229 u8 bank_number;
1230 u8 clear_status_on_init;
1231 u8 status_format;
1232 u8 reserved;
1233 u32 control_register;
1234 u64 control_data;
1235 u32 status_register;
1236 u32 address_register;
1237 u32 misc_register;
1238};
1239
1240
1241
1242struct acpi_hest_aer_common {
1243 u16 reserved1;
1244 u8 flags;
1245 u8 enabled;
1246 u32 records_to_preallocate;
1247 u32 max_sections_per_record;
1248 u32 bus;
1249 u16 device;
1250 u16 function;
1251 u16 device_control;
1252 u16 reserved2;
1253 u32 uncorrectable_mask;
1254 u32 uncorrectable_severity;
1255 u32 correctable_mask;
1256 u32 advanced_capabilities;
1257};
1258
1259
1260
1261#define ACPI_HEST_FIRMWARE_FIRST (1)
1262#define ACPI_HEST_GLOBAL (1<<1)
1263#define ACPI_HEST_GHES_ASSIST (1<<2)
1264
1265
1266
1267
1268
1269
1270#define ACPI_HEST_BUS(bus) ((bus) & 0xFF)
1271#define ACPI_HEST_SEGMENT(bus) (((bus) >> 8) & 0xFFFF)
1272
1273
1274
1275struct acpi_hest_notify {
1276 u8 type;
1277 u8 length;
1278 u16 config_write_enable;
1279 u32 poll_interval;
1280 u32 vector;
1281 u32 polling_threshold_value;
1282 u32 polling_threshold_window;
1283 u32 error_threshold_value;
1284 u32 error_threshold_window;
1285};
1286
1287
1288
1289enum acpi_hest_notify_types {
1290 ACPI_HEST_NOTIFY_POLLED = 0,
1291 ACPI_HEST_NOTIFY_EXTERNAL = 1,
1292 ACPI_HEST_NOTIFY_LOCAL = 2,
1293 ACPI_HEST_NOTIFY_SCI = 3,
1294 ACPI_HEST_NOTIFY_NMI = 4,
1295 ACPI_HEST_NOTIFY_CMCI = 5,
1296 ACPI_HEST_NOTIFY_MCE = 6,
1297 ACPI_HEST_NOTIFY_GPIO = 7,
1298 ACPI_HEST_NOTIFY_SEA = 8,
1299 ACPI_HEST_NOTIFY_SEI = 9,
1300 ACPI_HEST_NOTIFY_GSIV = 10,
1301 ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11,
1302 ACPI_HEST_NOTIFY_RESERVED = 12
1303};
1304
1305
1306
1307#define ACPI_HEST_TYPE (1)
1308#define ACPI_HEST_POLL_INTERVAL (1<<1)
1309#define ACPI_HEST_POLL_THRESHOLD_VALUE (1<<2)
1310#define ACPI_HEST_POLL_THRESHOLD_WINDOW (1<<3)
1311#define ACPI_HEST_ERR_THRESHOLD_VALUE (1<<4)
1312#define ACPI_HEST_ERR_THRESHOLD_WINDOW (1<<5)
1313
1314
1315
1316
1317
1318
1319
1320struct acpi_hest_ia_machine_check {
1321 struct acpi_hest_header header;
1322 u16 reserved1;
1323 u8 flags;
1324 u8 enabled;
1325 u32 records_to_preallocate;
1326 u32 max_sections_per_record;
1327 u64 global_capability_data;
1328 u64 global_control_data;
1329 u8 num_hardware_banks;
1330 u8 reserved3[7];
1331};
1332
1333
1334
1335struct acpi_hest_ia_corrected {
1336 struct acpi_hest_header header;
1337 u16 reserved1;
1338 u8 flags;
1339 u8 enabled;
1340 u32 records_to_preallocate;
1341 u32 max_sections_per_record;
1342 struct acpi_hest_notify notify;
1343 u8 num_hardware_banks;
1344 u8 reserved2[3];
1345};
1346
1347
1348
1349struct acpi_hest_ia_nmi {
1350 struct acpi_hest_header header;
1351 u32 reserved;
1352 u32 records_to_preallocate;
1353 u32 max_sections_per_record;
1354 u32 max_raw_data_length;
1355};
1356
1357
1358
1359
1360
1361struct acpi_hest_aer_root {
1362 struct acpi_hest_header header;
1363 struct acpi_hest_aer_common aer;
1364 u32 root_error_command;
1365};
1366
1367
1368
1369struct acpi_hest_aer {
1370 struct acpi_hest_header header;
1371 struct acpi_hest_aer_common aer;
1372};
1373
1374
1375
1376struct acpi_hest_aer_bridge {
1377 struct acpi_hest_header header;
1378 struct acpi_hest_aer_common aer;
1379 u32 uncorrectable_mask2;
1380 u32 uncorrectable_severity2;
1381 u32 advanced_capabilities2;
1382};
1383
1384
1385
1386struct acpi_hest_generic {
1387 struct acpi_hest_header header;
1388 u16 related_source_id;
1389 u8 reserved;
1390 u8 enabled;
1391 u32 records_to_preallocate;
1392 u32 max_sections_per_record;
1393 u32 max_raw_data_length;
1394 struct acpi_generic_address error_status_address;
1395 struct acpi_hest_notify notify;
1396 u32 error_block_length;
1397};
1398
1399
1400
1401struct acpi_hest_generic_v2 {
1402 struct acpi_hest_header header;
1403 u16 related_source_id;
1404 u8 reserved;
1405 u8 enabled;
1406 u32 records_to_preallocate;
1407 u32 max_sections_per_record;
1408 u32 max_raw_data_length;
1409 struct acpi_generic_address error_status_address;
1410 struct acpi_hest_notify notify;
1411 u32 error_block_length;
1412 struct acpi_generic_address read_ack_register;
1413 u64 read_ack_preserve;
1414 u64 read_ack_write;
1415};
1416
1417
1418
1419struct acpi_hest_generic_status {
1420 u32 block_status;
1421 u32 raw_data_offset;
1422 u32 raw_data_length;
1423 u32 data_length;
1424 u32 error_severity;
1425};
1426
1427
1428
1429#define ACPI_HEST_UNCORRECTABLE (1)
1430#define ACPI_HEST_CORRECTABLE (1<<1)
1431#define ACPI_HEST_MULTIPLE_UNCORRECTABLE (1<<2)
1432#define ACPI_HEST_MULTIPLE_CORRECTABLE (1<<3)
1433#define ACPI_HEST_ERROR_ENTRY_COUNT (0xFF<<4)
1434
1435
1436
1437struct acpi_hest_generic_data {
1438 u8 section_type[16];
1439 u32 error_severity;
1440 u16 revision;
1441 u8 validation_bits;
1442 u8 flags;
1443 u32 error_data_length;
1444 u8 fru_id[16];
1445 u8 fru_text[20];
1446};
1447
1448
1449
1450struct acpi_hest_generic_data_v300 {
1451 u8 section_type[16];
1452 u32 error_severity;
1453 u16 revision;
1454 u8 validation_bits;
1455 u8 flags;
1456 u32 error_data_length;
1457 u8 fru_id[16];
1458 u8 fru_text[20];
1459 u64 time_stamp;
1460};
1461
1462
1463
1464#define ACPI_HEST_GEN_ERROR_RECOVERABLE 0
1465#define ACPI_HEST_GEN_ERROR_FATAL 1
1466#define ACPI_HEST_GEN_ERROR_CORRECTED 2
1467#define ACPI_HEST_GEN_ERROR_NONE 3
1468
1469
1470
1471#define ACPI_HEST_GEN_VALID_FRU_ID (1)
1472#define ACPI_HEST_GEN_VALID_FRU_STRING (1<<1)
1473#define ACPI_HEST_GEN_VALID_TIMESTAMP (1<<2)
1474
1475
1476
1477struct acpi_hest_ia_deferred_check {
1478 struct acpi_hest_header header;
1479 u16 reserved1;
1480 u8 flags;
1481 u8 enabled;
1482 u32 records_to_preallocate;
1483 u32 max_sections_per_record;
1484 struct acpi_hest_notify notify;
1485 u8 num_hardware_banks;
1486 u8 reserved2[3];
1487};
1488
1489
1490
1491
1492
1493
1494
1495
1496struct acpi_table_hmat {
1497 struct acpi_table_header header;
1498 u32 reserved;
1499};
1500
1501
1502
1503enum acpi_hmat_type {
1504 ACPI_HMAT_TYPE_PROXIMITY = 0,
1505 ACPI_HMAT_TYPE_LOCALITY = 1,
1506 ACPI_HMAT_TYPE_CACHE = 2,
1507 ACPI_HMAT_TYPE_RESERVED = 3
1508};
1509
1510struct acpi_hmat_structure {
1511 u16 type;
1512 u16 reserved;
1513 u32 length;
1514};
1515
1516
1517
1518
1519
1520
1521
1522struct acpi_hmat_proximity_domain {
1523 struct acpi_hmat_structure header;
1524 u16 flags;
1525 u16 reserved1;
1526 u32 processor_PD;
1527 u32 memory_PD;
1528 u32 reserved2;
1529 u64 reserved3;
1530 u64 reserved4;
1531};
1532
1533
1534
1535#define ACPI_HMAT_PROCESSOR_PD_VALID (1)
1536#define ACPI_HMAT_MEMORY_PD_VALID (1<<1)
1537#define ACPI_HMAT_RESERVATION_HINT (1<<2)
1538
1539
1540
1541struct acpi_hmat_locality {
1542 struct acpi_hmat_structure header;
1543 u8 flags;
1544 u8 data_type;
1545 u8 min_transfer_size;
1546 u8 reserved1;
1547 u32 number_of_initiator_Pds;
1548 u32 number_of_target_Pds;
1549 u32 reserved2;
1550 u64 entry_base_unit;
1551};
1552
1553
1554
1555#define ACPI_HMAT_MEMORY_HIERARCHY (0x0F)
1556
1557
1558
1559#define ACPI_HMAT_MEMORY 0
1560#define ACPI_HMAT_LAST_LEVEL_CACHE 1
1561#define ACPI_HMAT_1ST_LEVEL_CACHE 2
1562#define ACPI_HMAT_2ND_LEVEL_CACHE 3
1563#define ACPI_HMAT_3RD_LEVEL_CACHE 4
1564#define ACPI_HMAT_MINIMUM_XFER_SIZE 0x10
1565#define ACPI_HMAT_NON_SEQUENTIAL_XFERS 0x20
1566
1567
1568
1569
1570#define ACPI_HMAT_ACCESS_LATENCY 0
1571#define ACPI_HMAT_READ_LATENCY 1
1572#define ACPI_HMAT_WRITE_LATENCY 2
1573#define ACPI_HMAT_ACCESS_BANDWIDTH 3
1574#define ACPI_HMAT_READ_BANDWIDTH 4
1575#define ACPI_HMAT_WRITE_BANDWIDTH 5
1576
1577
1578
1579struct acpi_hmat_cache {
1580 struct acpi_hmat_structure header;
1581 u32 memory_PD;
1582 u32 reserved1;
1583 u64 cache_size;
1584 u32 cache_attributes;
1585 u16 reserved2;
1586 u16 number_of_SMBIOShandles;
1587};
1588
1589
1590
1591#define ACPI_HMAT_TOTAL_CACHE_LEVEL (0x0000000F)
1592#define ACPI_HMAT_CACHE_LEVEL (0x000000F0)
1593#define ACPI_HMAT_CACHE_ASSOCIATIVITY (0x00000F00)
1594#define ACPI_HMAT_WRITE_POLICY (0x0000F000)
1595#define ACPI_HMAT_CACHE_LINE_SIZE (0xFFFF0000)
1596
1597
1598
1599#define ACPI_HMAT_CA_NONE (0)
1600#define ACPI_HMAT_CA_DIRECT_MAPPED (1)
1601#define ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING (2)
1602
1603
1604
1605#define ACPI_HMAT_CP_NONE (0)
1606#define ACPI_HMAT_CP_WB (1)
1607#define ACPI_HMAT_CP_WT (2)
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619struct acpi_table_hpet {
1620 struct acpi_table_header header;
1621 u32 id;
1622 struct acpi_generic_address address;
1623 u8 sequence;
1624 u16 minimum_tick;
1625 u8 flags;
1626};
1627
1628
1629
1630#define ACPI_HPET_PAGE_PROTECT_MASK (3)
1631
1632
1633
1634enum acpi_hpet_page_protect {
1635 ACPI_HPET_NO_PAGE_PROTECT = 0,
1636 ACPI_HPET_PAGE_PROTECT4 = 1,
1637 ACPI_HPET_PAGE_PROTECT64 = 2
1638};
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653struct acpi_table_ibft {
1654 struct acpi_table_header header;
1655 u8 reserved[12];
1656};
1657
1658
1659
1660struct acpi_ibft_header {
1661 u8 type;
1662 u8 version;
1663 u16 length;
1664 u8 index;
1665 u8 flags;
1666};
1667
1668
1669
1670enum acpi_ibft_type {
1671 ACPI_IBFT_TYPE_NOT_USED = 0,
1672 ACPI_IBFT_TYPE_CONTROL = 1,
1673 ACPI_IBFT_TYPE_INITIATOR = 2,
1674 ACPI_IBFT_TYPE_NIC = 3,
1675 ACPI_IBFT_TYPE_TARGET = 4,
1676 ACPI_IBFT_TYPE_EXTENSIONS = 5,
1677 ACPI_IBFT_TYPE_RESERVED = 6
1678};
1679
1680
1681
1682struct acpi_ibft_control {
1683 struct acpi_ibft_header header;
1684 u16 extensions;
1685 u16 initiator_offset;
1686 u16 nic0_offset;
1687 u16 target0_offset;
1688 u16 nic1_offset;
1689 u16 target1_offset;
1690};
1691
1692struct acpi_ibft_initiator {
1693 struct acpi_ibft_header header;
1694 u8 sns_server[16];
1695 u8 slp_server[16];
1696 u8 primary_server[16];
1697 u8 secondary_server[16];
1698 u16 name_length;
1699 u16 name_offset;
1700};
1701
1702struct acpi_ibft_nic {
1703 struct acpi_ibft_header header;
1704 u8 ip_address[16];
1705 u8 subnet_mask_prefix;
1706 u8 origin;
1707 u8 gateway[16];
1708 u8 primary_dns[16];
1709 u8 secondary_dns[16];
1710 u8 dhcp[16];
1711 u16 vlan;
1712 u8 mac_address[6];
1713 u16 pci_address;
1714 u16 name_length;
1715 u16 name_offset;
1716};
1717
1718struct acpi_ibft_target {
1719 struct acpi_ibft_header header;
1720 u8 target_ip_address[16];
1721 u16 target_ip_socket;
1722 u8 target_boot_lun[8];
1723 u8 chap_type;
1724 u8 nic_association;
1725 u16 target_name_length;
1726 u16 target_name_offset;
1727 u16 chap_name_length;
1728 u16 chap_name_offset;
1729 u16 chap_secret_length;
1730 u16 chap_secret_offset;
1731 u16 reverse_chap_name_length;
1732 u16 reverse_chap_name_offset;
1733 u16 reverse_chap_secret_length;
1734 u16 reverse_chap_secret_offset;
1735};
1736
1737
1738
1739#pragma pack()
1740
1741#endif
1742