1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/delay.h>
27#include <linux/i2c.h>
28#include <linux/types.h>
29#include <drm/drm_connector.h>
30
31struct drm_device;
32struct drm_dp_aux;
33struct drm_panel;
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51#define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
52#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
53#define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
54#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
55#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
56
57#define DP_MSA_MISC_6_BPC (0 << 5)
58#define DP_MSA_MISC_8_BPC (1 << 5)
59#define DP_MSA_MISC_10_BPC (2 << 5)
60#define DP_MSA_MISC_12_BPC (3 << 5)
61#define DP_MSA_MISC_16_BPC (4 << 5)
62
63#define DP_MSA_MISC_RAW_6_BPC (1 << 5)
64#define DP_MSA_MISC_RAW_7_BPC (2 << 5)
65#define DP_MSA_MISC_RAW_8_BPC (3 << 5)
66#define DP_MSA_MISC_RAW_10_BPC (4 << 5)
67#define DP_MSA_MISC_RAW_12_BPC (5 << 5)
68#define DP_MSA_MISC_RAW_14_BPC (6 << 5)
69#define DP_MSA_MISC_RAW_16_BPC (7 << 5)
70
71#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
72 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
73#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
74#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
75#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
76#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
77#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
78#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
79#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
80#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
81#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
82#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
83#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
84#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
85#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
86#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
87#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
88#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
89#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
90#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
91
92#define DP_AUX_MAX_PAYLOAD_BYTES 16
93
94#define DP_AUX_I2C_WRITE 0x0
95#define DP_AUX_I2C_READ 0x1
96#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
97#define DP_AUX_I2C_MOT 0x4
98#define DP_AUX_NATIVE_WRITE 0x8
99#define DP_AUX_NATIVE_READ 0x9
100
101#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
102#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
103#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
104#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
105
106#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
107#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
108#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
109#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
110
111
112
113
114#define DP_DPCD_REV 0x000
115# define DP_DPCD_REV_10 0x10
116# define DP_DPCD_REV_11 0x11
117# define DP_DPCD_REV_12 0x12
118# define DP_DPCD_REV_13 0x13
119# define DP_DPCD_REV_14 0x14
120
121#define DP_MAX_LINK_RATE 0x001
122
123#define DP_MAX_LANE_COUNT 0x002
124# define DP_MAX_LANE_COUNT_MASK 0x1f
125# define DP_TPS3_SUPPORTED (1 << 6)
126# define DP_ENHANCED_FRAME_CAP (1 << 7)
127
128#define DP_MAX_DOWNSPREAD 0x003
129# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
130# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1)
131# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
132# define DP_TPS4_SUPPORTED (1 << 7)
133
134#define DP_NORP 0x004
135
136#define DP_DOWNSTREAMPORT_PRESENT 0x005
137# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
138# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
139# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
140# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
141# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
142# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
143# define DP_FORMAT_CONVERSION (1 << 3)
144# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4)
145
146#define DP_MAIN_LINK_CHANNEL_CODING 0x006
147# define DP_CAP_ANSI_8B10B (1 << 0)
148# define DP_CAP_ANSI_128B132B (1 << 1)
149
150#define DP_DOWN_STREAM_PORT_COUNT 0x007
151# define DP_PORT_COUNT_MASK 0x0f
152# define DP_MSA_TIMING_PAR_IGNORED (1 << 6)
153# define DP_OUI_SUPPORT (1 << 7)
154
155#define DP_RECEIVE_PORT_0_CAP_0 0x008
156# define DP_LOCAL_EDID_PRESENT (1 << 1)
157# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
158
159#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
160
161#define DP_RECEIVE_PORT_1_CAP_0 0x00a
162#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
163
164#define DP_I2C_SPEED_CAP 0x00c
165# define DP_I2C_SPEED_1K 0x01
166# define DP_I2C_SPEED_5K 0x02
167# define DP_I2C_SPEED_10K 0x04
168# define DP_I2C_SPEED_100K 0x08
169# define DP_I2C_SPEED_400K 0x10
170# define DP_I2C_SPEED_1M 0x20
171
172#define DP_EDP_CONFIGURATION_CAP 0x00d
173# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
174# define DP_FRAMING_CHANGE_CAP (1 << 1)
175# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3)
176
177#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
178# define DP_TRAINING_AUX_RD_MASK 0x7F
179# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)
180
181#define DP_ADAPTER_CAP 0x00f
182# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
183# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
184
185#define DP_SUPPORTED_LINK_RATES 0x010
186# define DP_MAX_SUPPORTED_RATES 8
187
188
189#define DP_FAUX_CAP 0x020
190# define DP_FAUX_CAP_1 (1 << 0)
191
192#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
193# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
194# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
195# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
196
197#define DP_MSTM_CAP 0x021
198# define DP_MST_CAP (1 << 0)
199# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1)
200
201#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022
202
203
204#define DP_AV_GRANULARITY 0x023
205# define DP_AG_FACTOR_MASK (0xf << 0)
206# define DP_AG_FACTOR_3MS (0 << 0)
207# define DP_AG_FACTOR_2MS (1 << 0)
208# define DP_AG_FACTOR_1MS (2 << 0)
209# define DP_AG_FACTOR_500US (3 << 0)
210# define DP_AG_FACTOR_200US (4 << 0)
211# define DP_AG_FACTOR_100US (5 << 0)
212# define DP_AG_FACTOR_10US (6 << 0)
213# define DP_AG_FACTOR_1US (7 << 0)
214# define DP_VG_FACTOR_MASK (0xf << 4)
215# define DP_VG_FACTOR_3MS (0 << 4)
216# define DP_VG_FACTOR_2MS (1 << 4)
217# define DP_VG_FACTOR_1MS (2 << 4)
218# define DP_VG_FACTOR_500US (3 << 4)
219# define DP_VG_FACTOR_200US (4 << 4)
220# define DP_VG_FACTOR_100US (5 << 4)
221
222#define DP_AUD_DEC_LAT0 0x024
223#define DP_AUD_DEC_LAT1 0x025
224
225#define DP_AUD_PP_LAT0 0x026
226#define DP_AUD_PP_LAT1 0x027
227
228#define DP_VID_INTER_LAT 0x028
229
230#define DP_VID_PROG_LAT 0x029
231
232#define DP_REP_LAT 0x02a
233
234#define DP_AUD_DEL_INS0 0x02b
235#define DP_AUD_DEL_INS1 0x02c
236#define DP_AUD_DEL_INS2 0x02d
237
238
239#define DP_RECEIVER_ALPM_CAP 0x02e
240# define DP_ALPM_CAP (1 << 0)
241
242#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f
243# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
244
245#define DP_GUID 0x030
246
247#define DP_DSC_SUPPORT 0x060
248# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
249
250#define DP_DSC_REV 0x061
251# define DP_DSC_MAJOR_MASK (0xf << 0)
252# define DP_DSC_MINOR_MASK (0xf << 4)
253# define DP_DSC_MAJOR_SHIFT 0
254# define DP_DSC_MINOR_SHIFT 4
255
256#define DP_DSC_RC_BUF_BLK_SIZE 0x062
257# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
258# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
259# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
260# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
261
262#define DP_DSC_RC_BUF_SIZE 0x063
263
264#define DP_DSC_SLICE_CAP_1 0x064
265# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
266# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
267# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
268# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
269# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
270# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
271# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
272
273#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
274# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
275# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
276# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
277# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
278# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
279# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
280# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
281# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
282# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
283# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
284
285#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
286# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
287
288#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067
289
290#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068
291# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
292# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
293
294#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
295# define DP_DSC_RGB (1 << 0)
296# define DP_DSC_YCbCr444 (1 << 1)
297# define DP_DSC_YCbCr422_Simple (1 << 2)
298# define DP_DSC_YCbCr422_Native (1 << 3)
299# define DP_DSC_YCbCr420_Native (1 << 4)
300
301#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
302# define DP_DSC_8_BPC (1 << 1)
303# define DP_DSC_10_BPC (1 << 2)
304# define DP_DSC_12_BPC (1 << 3)
305
306#define DP_DSC_PEAK_THROUGHPUT 0x06B
307# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
308# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
309# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
310# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
311# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
312# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
313# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
314# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
315# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
316# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
317# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
318# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
319# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
320# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
321# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
322# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
323# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
324# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0)
325# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
326# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
327# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
328# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
329# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
330# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
331# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
332# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
333# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
334# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
335# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
336# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
337# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
338# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
339# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
340# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
341# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
342# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
343
344#define DP_DSC_MAX_SLICE_WIDTH 0x06C
345#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
346#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
347
348#define DP_DSC_SLICE_CAP_2 0x06D
349# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
350# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
351# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
352
353#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
354# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
355# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
356# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
357# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
358# define DP_DSC_BITS_PER_PIXEL_1 0x4
359
360#define DP_PSR_SUPPORT 0x070
361# define DP_PSR_IS_SUPPORTED 1
362# define DP_PSR2_IS_SUPPORTED 2
363# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3
364
365#define DP_PSR_CAPS 0x071
366# define DP_PSR_NO_TRAIN_ON_EXIT 1
367# define DP_PSR_SETUP_TIME_330 (0 << 1)
368# define DP_PSR_SETUP_TIME_275 (1 << 1)
369# define DP_PSR_SETUP_TIME_220 (2 << 1)
370# define DP_PSR_SETUP_TIME_165 (3 << 1)
371# define DP_PSR_SETUP_TIME_110 (4 << 1)
372# define DP_PSR_SETUP_TIME_55 (5 << 1)
373# define DP_PSR_SETUP_TIME_0 (6 << 1)
374# define DP_PSR_SETUP_TIME_MASK (7 << 1)
375# define DP_PSR_SETUP_TIME_SHIFT 1
376# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4)
377# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5)
378
379#define DP_PSR2_SU_X_GRANULARITY 0x072
380#define DP_PSR2_SU_Y_GRANULARITY 0x074
381
382
383
384
385
386
387
388
389
390
391#define DP_DOWNSTREAM_PORT_0 0x80
392# define DP_DS_PORT_TYPE_MASK (7 << 0)
393# define DP_DS_PORT_TYPE_DP 0
394# define DP_DS_PORT_TYPE_VGA 1
395# define DP_DS_PORT_TYPE_DVI 2
396# define DP_DS_PORT_TYPE_HDMI 3
397# define DP_DS_PORT_TYPE_NON_EDID 4
398# define DP_DS_PORT_TYPE_DP_DUALMODE 5
399# define DP_DS_PORT_TYPE_WIRELESS 6
400# define DP_DS_PORT_HPD (1 << 3)
401# define DP_DS_NON_EDID_MASK (0xf << 4)
402# define DP_DS_NON_EDID_720x480i_60 (1 << 4)
403# define DP_DS_NON_EDID_720x480i_50 (2 << 4)
404# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
405# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
406# define DP_DS_NON_EDID_1280x720_60 (5 << 4)
407# define DP_DS_NON_EDID_1280x720_50 (7 << 4)
408
409
410
411# define DP_DS_MAX_BPC_MASK (3 << 0)
412# define DP_DS_8BPC 0
413# define DP_DS_10BPC 1
414# define DP_DS_12BPC 2
415# define DP_DS_16BPC 3
416
417# define DP_PCON_MAX_FRL_BW (7 << 2)
418# define DP_PCON_MAX_0GBPS (0 << 2)
419# define DP_PCON_MAX_9GBPS (1 << 2)
420# define DP_PCON_MAX_18GBPS (2 << 2)
421# define DP_PCON_MAX_24GBPS (3 << 2)
422# define DP_PCON_MAX_32GBPS (4 << 2)
423# define DP_PCON_MAX_40GBPS (5 << 2)
424# define DP_PCON_MAX_48GBPS (6 << 2)
425# define DP_PCON_SOURCE_CTL_MODE (1 << 5)
426
427
428# define DP_DS_DVI_DUAL_LINK (1 << 1)
429# define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
430
431# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
432# define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
433# define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
434# define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
435# define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
436
437
438
439
440
441
442
443
444# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5)
445# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6)
446# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
447
448#define DP_MAX_DOWNSTREAM_PORTS 0x10
449
450
451#define DP_FEC_CAPABILITY 0x090
452# define DP_FEC_CAPABLE (1 << 0)
453# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
454# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
455# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
456
457
458#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC
459#define DP_PCON_DSC_ENCODER 0x092
460# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
461# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
462
463
464#define DP_PCON_DSC_VERSION 0x093
465# define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
466# define DP_PCON_DSC_MINOR_MASK (0xF << 4)
467# define DP_PCON_DSC_MAJOR_SHIFT 0
468# define DP_PCON_DSC_MINOR_SHIFT 4
469
470
471#define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
472# define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
473# define DP_PCON_DSC_RC_BUF_BLK_1KB 0
474# define DP_PCON_DSC_RC_BUF_BLK_4KB 1
475# define DP_PCON_DSC_RC_BUF_BLK_16KB 2
476# define DP_PCON_DSC_RC_BUF_BLK_64KB 3
477
478
479#define DP_PCON_DSC_RC_BUF_SIZE 0x095
480
481
482#define DP_PCON_DSC_SLICE_CAP_1 0x096
483# define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
484# define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
485# define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
486# define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
487# define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
488# define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
489# define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
490
491#define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
492# define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
493# define DP_PCON_DSC_DEPTH_9_BITS 0
494# define DP_PCON_DSC_DEPTH_10_BITS 1
495# define DP_PCON_DSC_DEPTH_11_BITS 2
496# define DP_PCON_DSC_DEPTH_12_BITS 3
497# define DP_PCON_DSC_DEPTH_13_BITS 4
498# define DP_PCON_DSC_DEPTH_14_BITS 5
499# define DP_PCON_DSC_DEPTH_15_BITS 6
500# define DP_PCON_DSC_DEPTH_16_BITS 7
501# define DP_PCON_DSC_DEPTH_8_BITS 8
502
503#define DP_PCON_DSC_BLOCK_PREDICTION 0x098
504# define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
505
506#define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
507# define DP_PCON_DSC_ENC_RGB (0x1 << 0)
508# define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
509# define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
510# define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
511# define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
512
513#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
514# define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
515# define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
516# define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
517
518#define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
519
520
521#define DP_PCON_DSC_SLICE_CAP_2 0x09C
522# define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
523# define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
524# define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
525
526
527#define DP_PCON_DSC_BPP_INCR 0x09E
528# define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
529# define DP_PCON_DSC_ONE_16TH_BPP 0
530# define DP_PCON_DSC_ONE_8TH_BPP 1
531# define DP_PCON_DSC_ONE_4TH_BPP 2
532# define DP_PCON_DSC_ONE_HALF_BPP 3
533# define DP_PCON_DSC_ONE_BPP 4
534
535
536#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0
537#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
538#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
539
540
541#define DP_LINK_BW_SET 0x100
542# define DP_LINK_RATE_TABLE 0x00
543# define DP_LINK_BW_1_62 0x06
544# define DP_LINK_BW_2_7 0x0a
545# define DP_LINK_BW_5_4 0x14
546# define DP_LINK_BW_8_1 0x1e
547# define DP_LINK_BW_10 0x01
548# define DP_LINK_BW_13_5 0x04
549# define DP_LINK_BW_20 0x02
550
551#define DP_LANE_COUNT_SET 0x101
552# define DP_LANE_COUNT_MASK 0x0f
553# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
554
555#define DP_TRAINING_PATTERN_SET 0x102
556# define DP_TRAINING_PATTERN_DISABLE 0
557# define DP_TRAINING_PATTERN_1 1
558# define DP_TRAINING_PATTERN_2 2
559# define DP_TRAINING_PATTERN_3 3
560# define DP_TRAINING_PATTERN_4 7
561# define DP_TRAINING_PATTERN_MASK 0x3
562# define DP_TRAINING_PATTERN_MASK_1_4 0xf
563
564
565# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
566# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
567# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
568# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
569# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
570
571# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
572# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
573
574# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
575# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
576# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
577# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
578
579#define DP_TRAINING_LANE0_SET 0x103
580#define DP_TRAINING_LANE1_SET 0x104
581#define DP_TRAINING_LANE2_SET 0x105
582#define DP_TRAINING_LANE3_SET 0x106
583
584# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
585# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
586# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
587# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
588# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
589# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
590# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
591
592# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
593# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
594# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
595# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
596# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
597
598# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
599# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
600
601# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0)
602
603#define DP_DOWNSPREAD_CTRL 0x107
604# define DP_SPREAD_AMP_0_5 (1 << 4)
605# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7)
606
607#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
608# define DP_SET_ANSI_8B10B (1 << 0)
609# define DP_SET_ANSI_128B132B (1 << 1)
610
611#define DP_I2C_SPEED_CONTROL_STATUS 0x109
612
613
614#define DP_EDP_CONFIGURATION_SET 0x10a
615# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
616# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
617# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
618
619#define DP_LINK_QUAL_LANE0_SET 0x10b
620#define DP_LINK_QUAL_LANE1_SET 0x10c
621#define DP_LINK_QUAL_LANE2_SET 0x10d
622#define DP_LINK_QUAL_LANE3_SET 0x10e
623# define DP_LINK_QUAL_PATTERN_DISABLE 0
624# define DP_LINK_QUAL_PATTERN_D10_2 1
625# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
626# define DP_LINK_QUAL_PATTERN_PRBS7 3
627# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
628# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
629# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
630# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
631
632# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
633# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
634# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
635# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
636# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
637# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
638# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
639# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
640# define DP_LINK_QUAL_PATTERN_SQUARE 0x48
641
642#define DP_TRAINING_LANE0_1_SET2 0x10f
643#define DP_TRAINING_LANE2_3_SET2 0x110
644# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
645# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
646# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
647# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
648
649#define DP_MSTM_CTRL 0x111
650# define DP_MST_EN (1 << 0)
651# define DP_UP_REQ_EN (1 << 1)
652# define DP_UPSTREAM_IS_SRC (1 << 2)
653
654#define DP_AUDIO_DELAY0 0x112
655#define DP_AUDIO_DELAY1 0x113
656#define DP_AUDIO_DELAY2 0x114
657
658#define DP_LINK_RATE_SET 0x115
659# define DP_LINK_RATE_SET_SHIFT 0
660# define DP_LINK_RATE_SET_MASK (7 << 0)
661
662#define DP_RECEIVER_ALPM_CONFIG 0x116
663# define DP_ALPM_ENABLE (1 << 0)
664# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
665
666#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117
667# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
668# define DP_IRQ_HPD_ENABLE (1 << 1)
669
670#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118
671# define DP_PWR_NOT_NEEDED (1 << 0)
672
673#define DP_FEC_CONFIGURATION 0x120
674# define DP_FEC_READY (1 << 0)
675# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
676# define DP_FEC_ERR_COUNT_DIS (0 << 1)
677# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
678# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
679# define DP_FEC_BIT_ERROR_COUNT (3 << 1)
680# define DP_FEC_LANE_SELECT_MASK (3 << 4)
681# define DP_FEC_LANE_0_SELECT (0 << 4)
682# define DP_FEC_LANE_1_SELECT (1 << 4)
683# define DP_FEC_LANE_2_SELECT (2 << 4)
684# define DP_FEC_LANE_3_SELECT (3 << 4)
685
686#define DP_AUX_FRAME_SYNC_VALUE 0x15c
687# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
688
689#define DP_DSC_ENABLE 0x160
690# define DP_DECOMPRESSION_EN (1 << 0)
691
692#define DP_PSR_EN_CFG 0x170
693# define DP_PSR_ENABLE BIT(0)
694# define DP_PSR_MAIN_LINK_ACTIVE BIT(1)
695# define DP_PSR_CRC_VERIFICATION BIT(2)
696# define DP_PSR_FRAME_CAPTURE BIT(3)
697# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4)
698# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5)
699# define DP_PSR_ENABLE_PSR2 BIT(6)
700
701#define DP_ADAPTER_CTRL 0x1a0
702# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
703
704#define DP_BRANCH_DEVICE_CTRL 0x1a1
705# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
706
707#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
708#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
709#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
710
711
712#define DP_SINK_COUNT 0x200
713
714# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
715# define DP_SINK_CP_READY (1 << 6)
716
717#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
718# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
719# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
720# define DP_CP_IRQ (1 << 2)
721# define DP_MCCS_IRQ (1 << 3)
722# define DP_DOWN_REP_MSG_RDY (1 << 4)
723# define DP_UP_REQ_MSG_RDY (1 << 5)
724# define DP_SINK_SPECIFIC_IRQ (1 << 6)
725
726#define DP_LANE0_1_STATUS 0x202
727#define DP_LANE2_3_STATUS 0x203
728# define DP_LANE_CR_DONE (1 << 0)
729# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
730# define DP_LANE_SYMBOL_LOCKED (1 << 2)
731
732#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
733 DP_LANE_CHANNEL_EQ_DONE | \
734 DP_LANE_SYMBOL_LOCKED)
735
736#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
737
738#define DP_INTERLANE_ALIGN_DONE (1 << 0)
739#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
740#define DP_LINK_STATUS_UPDATED (1 << 7)
741
742#define DP_SINK_STATUS 0x205
743# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
744# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
745# define DP_STREAM_REGENERATION_STATUS (1 << 2)
746
747#define DP_ADJUST_REQUEST_LANE0_1 0x206
748#define DP_ADJUST_REQUEST_LANE2_3 0x207
749# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
750# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
751# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
752# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
753# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
754# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
755# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
756# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
757
758
759# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
760# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
761# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
762# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
763
764#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
765# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
766# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
767# define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
768# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
769# define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
770# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
771# define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
772# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
773
774#define DP_TEST_REQUEST 0x218
775# define DP_TEST_LINK_TRAINING (1 << 0)
776# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
777# define DP_TEST_LINK_EDID_READ (1 << 2)
778# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3)
779# define DP_TEST_LINK_FAUX_PATTERN (1 << 4)
780# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5)
781# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6)
782
783#define DP_TEST_LINK_RATE 0x219
784# define DP_LINK_RATE_162 (0x6)
785# define DP_LINK_RATE_27 (0xa)
786
787#define DP_TEST_LANE_COUNT 0x220
788
789#define DP_TEST_PATTERN 0x221
790# define DP_NO_TEST_PATTERN 0x0
791# define DP_COLOR_RAMP 0x1
792# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
793# define DP_COLOR_SQUARE 0x3
794
795#define DP_TEST_H_TOTAL_HI 0x222
796#define DP_TEST_H_TOTAL_LO 0x223
797
798#define DP_TEST_V_TOTAL_HI 0x224
799#define DP_TEST_V_TOTAL_LO 0x225
800
801#define DP_TEST_H_START_HI 0x226
802#define DP_TEST_H_START_LO 0x227
803
804#define DP_TEST_V_START_HI 0x228
805#define DP_TEST_V_START_LO 0x229
806
807#define DP_TEST_HSYNC_HI 0x22A
808# define DP_TEST_HSYNC_POLARITY (1 << 7)
809# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
810#define DP_TEST_HSYNC_WIDTH_LO 0x22B
811
812#define DP_TEST_VSYNC_HI 0x22C
813# define DP_TEST_VSYNC_POLARITY (1 << 7)
814# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
815#define DP_TEST_VSYNC_WIDTH_LO 0x22D
816
817#define DP_TEST_H_WIDTH_HI 0x22E
818#define DP_TEST_H_WIDTH_LO 0x22F
819
820#define DP_TEST_V_HEIGHT_HI 0x230
821#define DP_TEST_V_HEIGHT_LO 0x231
822
823#define DP_TEST_MISC0 0x232
824# define DP_TEST_SYNC_CLOCK (1 << 0)
825# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
826# define DP_TEST_COLOR_FORMAT_SHIFT 1
827# define DP_COLOR_FORMAT_RGB (0 << 1)
828# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
829# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
830# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
831# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
832# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
833# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
834# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
835# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
836# define DP_TEST_BIT_DEPTH_SHIFT 5
837# define DP_TEST_BIT_DEPTH_6 (0 << 5)
838# define DP_TEST_BIT_DEPTH_8 (1 << 5)
839# define DP_TEST_BIT_DEPTH_10 (2 << 5)
840# define DP_TEST_BIT_DEPTH_12 (3 << 5)
841# define DP_TEST_BIT_DEPTH_16 (4 << 5)
842
843#define DP_TEST_MISC1 0x233
844# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
845# define DP_TEST_INTERLACED (1 << 1)
846
847#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
848
849#define DP_TEST_MISC0 0x232
850
851#define DP_TEST_CRC_R_CR 0x240
852#define DP_TEST_CRC_G_Y 0x242
853#define DP_TEST_CRC_B_CB 0x244
854
855#define DP_TEST_SINK_MISC 0x246
856# define DP_TEST_CRC_SUPPORTED (1 << 5)
857# define DP_TEST_COUNT_MASK 0xf
858
859#define DP_PHY_TEST_PATTERN 0x248
860# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
861# define DP_PHY_TEST_PATTERN_NONE 0x0
862# define DP_PHY_TEST_PATTERN_D10_2 0x1
863# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
864# define DP_PHY_TEST_PATTERN_PRBS7 0x3
865# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
866# define DP_PHY_TEST_PATTERN_CP2520 0x5
867
868#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
869#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
870#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
871#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
872#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
873#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
874#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
875#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
876#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
877#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
878#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
879
880#define DP_TEST_RESPONSE 0x260
881# define DP_TEST_ACK (1 << 0)
882# define DP_TEST_NAK (1 << 1)
883# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
884
885#define DP_TEST_EDID_CHECKSUM 0x261
886
887#define DP_TEST_SINK 0x270
888# define DP_TEST_SINK_START (1 << 0)
889#define DP_TEST_AUDIO_MODE 0x271
890#define DP_TEST_AUDIO_PATTERN_TYPE 0x272
891#define DP_TEST_AUDIO_PERIOD_CH1 0x273
892#define DP_TEST_AUDIO_PERIOD_CH2 0x274
893#define DP_TEST_AUDIO_PERIOD_CH3 0x275
894#define DP_TEST_AUDIO_PERIOD_CH4 0x276
895#define DP_TEST_AUDIO_PERIOD_CH5 0x277
896#define DP_TEST_AUDIO_PERIOD_CH6 0x278
897#define DP_TEST_AUDIO_PERIOD_CH7 0x279
898#define DP_TEST_AUDIO_PERIOD_CH8 0x27A
899
900#define DP_FEC_STATUS 0x280
901# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
902# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
903
904#define DP_FEC_ERROR_COUNT_LSB 0x0281
905
906#define DP_FEC_ERROR_COUNT_MSB 0x0282
907# define DP_FEC_ERROR_COUNT_MASK 0x7F
908# define DP_FEC_ERR_COUNT_VALID (1 << 7)
909
910#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0
911# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
912# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
913
914#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1
915
916
917
918#define DP_SOURCE_OUI 0x300
919
920
921#define DP_SINK_OUI 0x400
922
923
924#define DP_BRANCH_OUI 0x500
925#define DP_BRANCH_ID 0x503
926#define DP_BRANCH_REVISION_START 0x509
927#define DP_BRANCH_HW_REV 0x509
928#define DP_BRANCH_SW_REV 0x50A
929
930
931#define DP_SET_POWER 0x600
932# define DP_SET_POWER_D0 0x1
933# define DP_SET_POWER_D3 0x2
934# define DP_SET_POWER_MASK 0x3
935# define DP_SET_POWER_D3_AUX_ON 0x5
936
937
938#define DP_EDP_DPCD_REV 0x700
939# define DP_EDP_11 0x00
940# define DP_EDP_12 0x01
941# define DP_EDP_13 0x02
942# define DP_EDP_14 0x03
943# define DP_EDP_14a 0x04
944# define DP_EDP_14b 0x05
945
946#define DP_EDP_GENERAL_CAP_1 0x701
947# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
948# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
949# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
950# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
951# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
952# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
953# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
954# define DP_EDP_SET_POWER_CAP (1 << 7)
955
956#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
957# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
958# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
959# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
960# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
961# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
962# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
963# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
964# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
965
966#define DP_EDP_GENERAL_CAP_2 0x703
967# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
968
969#define DP_EDP_GENERAL_CAP_3 0x704
970# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
971# define DP_EDP_X_REGION_CAP_SHIFT 0
972# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
973# define DP_EDP_Y_REGION_CAP_SHIFT 4
974
975#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
976# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
977# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
978# define DP_EDP_FRC_ENABLE (1 << 2)
979# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
980# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
981
982#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
983# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
984# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
985# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
986# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
987# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
988# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
989# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
990# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
991# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
992# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6)
993
994#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
995#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
996
997#define DP_EDP_PWMGEN_BIT_COUNT 0x724
998#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
999#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
1000# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
1001
1002#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
1003
1004#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
1005# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
1006
1007#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
1008#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
1009#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
1010
1011#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
1012#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
1013#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
1014
1015#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
1016#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
1017
1018#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740
1019#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741
1020
1021#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4
1022# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
1023# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
1024# define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3)
1025
1026
1027#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000
1028#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200
1029#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400
1030#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600
1031
1032
1033#define DP_SINK_COUNT_ESI 0x2002
1034
1035# define DP_SINK_COUNT_CP_READY (1 << 6)
1036
1037#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003
1038
1039#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004
1040# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
1041# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
1042# define DP_CEC_IRQ (1 << 2)
1043
1044#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005
1045# define RX_CAP_CHANGED (1 << 0)
1046# define LINK_STATUS_CHANGED (1 << 1)
1047# define STREAM_STATUS_CHANGED (1 << 2)
1048# define HDMI_LINK_STATUS_CHANGED (1 << 3)
1049# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
1050
1051#define DP_PSR_ERROR_STATUS 0x2006
1052# define DP_PSR_LINK_CRC_ERROR (1 << 0)
1053# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
1054# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2)
1055
1056#define DP_PSR_ESI 0x2007
1057# define DP_PSR_CAPS_CHANGE (1 << 0)
1058
1059#define DP_PSR_STATUS 0x2008
1060# define DP_PSR_SINK_INACTIVE 0
1061# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
1062# define DP_PSR_SINK_ACTIVE_RFB 2
1063# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
1064# define DP_PSR_SINK_ACTIVE_RESYNC 4
1065# define DP_PSR_SINK_INTERNAL_ERROR 7
1066# define DP_PSR_SINK_STATE_MASK 0x07
1067
1068#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009
1069# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
1070# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
1071# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
1072# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
1073
1074#define DP_LAST_RECEIVED_PSR_SDP 0x200a
1075# define DP_PSR_STATE_BIT (1 << 0)
1076# define DP_UPDATE_RFB_BIT (1 << 1)
1077# define DP_CRC_VALID_BIT (1 << 2)
1078# define DP_SU_VALID (1 << 3)
1079# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4)
1080# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5)
1081# define DP_Y_COORDINATE_VALID (1 << 6)
1082
1083#define DP_RECEIVER_ALPM_STATUS 0x200b
1084# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
1085
1086#define DP_LANE0_1_STATUS_ESI 0x200c
1087#define DP_LANE2_3_STATUS_ESI 0x200d
1088#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e
1089#define DP_SINK_STATUS_ESI 0x200f
1090
1091
1092#define DP_DP13_DPCD_REV 0x2200
1093
1094#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210
1095# define DP_GTC_CAP (1 << 0)
1096# define DP_SST_SPLIT_SDP_CAP (1 << 1)
1097# define DP_AV_SYNC_CAP (1 << 2)
1098# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3)
1099# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4)
1100# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5)
1101# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6)
1102# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7)
1103
1104#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215
1105# define DP_UHBR10 (1 << 0)
1106# define DP_UHBR20 (1 << 1)
1107# define DP_UHBR13_5 (1 << 2)
1108
1109#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216
1110# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1111
1112
1113
1114#define DP_CEC_TUNNELING_CAPABILITY 0x3000
1115# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
1116# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
1117# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
1118
1119#define DP_CEC_TUNNELING_CONTROL 0x3001
1120# define DP_CEC_TUNNELING_ENABLE (1 << 0)
1121# define DP_CEC_SNOOPING_ENABLE (1 << 1)
1122
1123#define DP_CEC_RX_MESSAGE_INFO 0x3002
1124# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
1125# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
1126# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
1127# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
1128# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
1129# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
1130
1131#define DP_CEC_TX_MESSAGE_INFO 0x3003
1132# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
1133# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
1134# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
1135# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
1136# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
1137
1138#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
1139# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
1140# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
1141# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
1142# define DP_CEC_TX_LINE_ERROR (1 << 5)
1143# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
1144# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
1145
1146#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E
1147# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
1148# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
1149# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
1150# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
1151# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
1152# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
1153# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
1154# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
1155#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F
1156# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1157# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
1158# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
1159# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
1160# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
1161# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
1162# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
1163# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
1164
1165#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1166#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1167#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1168
1169
1170#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
1171# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
1172# define DP_PCON_ENABLE_MAX_BW_0GBPS 0
1173# define DP_PCON_ENABLE_MAX_BW_9GBPS 1
1174# define DP_PCON_ENABLE_MAX_BW_18GBPS 2
1175# define DP_PCON_ENABLE_MAX_BW_24GBPS 3
1176# define DP_PCON_ENABLE_MAX_BW_32GBPS 4
1177# define DP_PCON_ENABLE_MAX_BW_40GBPS 5
1178# define DP_PCON_ENABLE_MAX_BW_48GBPS 6
1179# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
1180# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
1181# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
1182# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
1183# define DP_PCON_ENABLE_HPD_READY (1 << 6)
1184# define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
1185
1186
1187#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
1188# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
1189# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
1190# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1)
1191# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2)
1192# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3)
1193# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
1194# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
1195# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
1196# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
1197
1198
1199#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
1200# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
1201# define DP_PCON_FRL_READY (1 << 1)
1202
1203
1204#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
1205# define DP_PCON_HDMI_LINK_MODE (1 << 0)
1206# define DP_PCON_HDMI_MODE_TMDS 0
1207# define DP_PCON_HDMI_MODE_FRL 1
1208# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
1209# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1)
1210# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2)
1211# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3)
1212# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4)
1213# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5)
1214# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6)
1215
1216#define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050
1217# define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0)
1218#define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051
1219# define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0)
1220# define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1)
1221# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2)
1222# define DP_HDMI_FORCE_SCRAMBLING (1 << 3)
1223#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052
1224# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0)
1225# define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)
1226# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
1227# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
1228# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1
1229# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2
1230# define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4)
1231# define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4)
1232# define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5)
1233# define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)
1234
1235
1236#define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
1237#define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
1238#define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
1239#define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
1240# define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
1241# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
1242# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)
1243# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
1244
1245
1246
1247
1248#define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
1249
1250
1251
1252
1253
1254#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
1255
1256
1257
1258
1259
1260#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
1261
1262
1263
1264
1265
1266#define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
1267
1268
1269#define DP_AUX_HDCP_BKSV 0x68000
1270#define DP_AUX_HDCP_RI_PRIME 0x68005
1271#define DP_AUX_HDCP_AKSV 0x68007
1272#define DP_AUX_HDCP_AN 0x6800C
1273#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1274#define DP_AUX_HDCP_BCAPS 0x68028
1275# define DP_BCAPS_REPEATER_PRESENT BIT(1)
1276# define DP_BCAPS_HDCP_CAPABLE BIT(0)
1277#define DP_AUX_HDCP_BSTATUS 0x68029
1278# define DP_BSTATUS_REAUTH_REQ BIT(3)
1279# define DP_BSTATUS_LINK_FAILURE BIT(2)
1280# define DP_BSTATUS_R0_PRIME_READY BIT(1)
1281# define DP_BSTATUS_READY BIT(0)
1282#define DP_AUX_HDCP_BINFO 0x6802A
1283#define DP_AUX_HDCP_KSV_FIFO 0x6802C
1284#define DP_AUX_HDCP_AINFO 0x6803B
1285
1286
1287#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1288#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1289#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1290#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1291#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1292#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1293#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1294#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1295#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1296#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1297#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1298#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1299#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1300#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1301#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1302#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1303#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1304#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1305#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1306#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1307#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1308#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1309#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1310#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1311#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1312#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1313
1314
1315#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000
1316#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001
1317#define DP_PHY_REPEATER_CNT 0xf0002
1318#define DP_PHY_REPEATER_MODE 0xf0003
1319#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004
1320#define DP_Repeater_FEC_CAPABILITY 0xf0004
1321#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005
1322
1323enum drm_dp_phy {
1324 DP_PHY_DPRX,
1325
1326 DP_PHY_LTTPR1,
1327 DP_PHY_LTTPR2,
1328 DP_PHY_LTTPR3,
1329 DP_PHY_LTTPR4,
1330 DP_PHY_LTTPR5,
1331 DP_PHY_LTTPR6,
1332 DP_PHY_LTTPR7,
1333 DP_PHY_LTTPR8,
1334
1335 DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
1336};
1337
1338#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
1339
1340#define __DP_LTTPR1_BASE 0xf0010
1341#define __DP_LTTPR2_BASE 0xf0060
1342#define DP_LTTPR_BASE(dp_phy) \
1343 (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
1344 ((dp_phy) - DP_PHY_LTTPR1))
1345
1346#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
1347 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1348
1349#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010
1350#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
1351 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1352
1353#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011
1354#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
1355 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1356
1357#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012
1358#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013
1359#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014
1360#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020
1361#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1362 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1363
1364#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021
1365# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
1366# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
1367
1368#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030
1369#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
1370 DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
1371
1372#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031
1373
1374#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032
1375#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033
1376#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034
1377#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035
1378#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037
1379#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039
1380#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b
1381
1382#define __DP_FEC1_BASE 0xf0290
1383#define __DP_FEC2_BASE 0xf0298
1384#define DP_FEC_BASE(dp_phy) \
1385 (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
1386 ((dp_phy) - DP_PHY_LTTPR1)))
1387
1388#define DP_FEC_REG(dp_phy, fec1_reg) \
1389 (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
1390
1391#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290
1392#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
1393 DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
1394
1395#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291
1396#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294
1397
1398#define DP_LTTPR_MAX_ADD 0xf02ff
1399
1400#define DP_DPCD_MAX_ADD 0xfffff
1401
1402
1403#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55
1404#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa
1405
1406
1407#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
1408#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
1409#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1410#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1411#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
1412#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1413 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1414#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
1415#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
1416#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1417#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1418#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
1419#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1420#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
1421
1422#define HDCP_2_2_DP_RXSTATUS_LEN 1
1423#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1424#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
1425#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
1426#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
1427#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
1428
1429
1430
1431#define DP_PEER_DEVICE_NONE 0x0
1432#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1433#define DP_PEER_DEVICE_MST_BRANCHING 0x2
1434#define DP_PEER_DEVICE_SST_SINK 0x3
1435#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1436
1437
1438#define DP_GET_MSG_TRANSACTION_VERSION 0x00
1439#define DP_LINK_ADDRESS 0x01
1440#define DP_CONNECTION_STATUS_NOTIFY 0x02
1441#define DP_ENUM_PATH_RESOURCES 0x10
1442#define DP_ALLOCATE_PAYLOAD 0x11
1443#define DP_QUERY_PAYLOAD 0x12
1444#define DP_RESOURCE_STATUS_NOTIFY 0x13
1445#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1446#define DP_REMOTE_DPCD_READ 0x20
1447#define DP_REMOTE_DPCD_WRITE 0x21
1448#define DP_REMOTE_I2C_READ 0x22
1449#define DP_REMOTE_I2C_WRITE 0x23
1450#define DP_POWER_UP_PHY 0x24
1451#define DP_POWER_DOWN_PHY 0x25
1452#define DP_SINK_EVENT_NOTIFY 0x30
1453#define DP_QUERY_STREAM_ENC_STATUS 0x38
1454#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1455#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
1456#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
1457
1458
1459#define DP_SIDEBAND_REPLY_ACK 0x00
1460#define DP_SIDEBAND_REPLY_NAK 0x01
1461
1462
1463#define DP_NAK_WRITE_FAILURE 0x01
1464#define DP_NAK_INVALID_READ 0x02
1465#define DP_NAK_CRC_FAILURE 0x03
1466#define DP_NAK_BAD_PARAM 0x04
1467#define DP_NAK_DEFER 0x05
1468#define DP_NAK_LINK_FAILURE 0x06
1469#define DP_NAK_NO_RESOURCES 0x07
1470#define DP_NAK_DPCD_FAIL 0x08
1471#define DP_NAK_I2C_NAK 0x09
1472#define DP_NAK_ALLOCATE_FAIL 0x0a
1473
1474#define MODE_I2C_START 1
1475#define MODE_I2C_WRITE 2
1476#define MODE_I2C_READ 4
1477#define MODE_I2C_STOP 8
1478
1479
1480#define DP_MST_PHYSICAL_PORT_0 0
1481#define DP_MST_LOGICAL_PORT_0 8
1482
1483#define DP_LINK_CONSTANT_N_VALUE 0x8000
1484#define DP_LINK_STATUS_SIZE 6
1485bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1486 int lane_count);
1487bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1488 int lane_count);
1489u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
1490 int lane);
1491u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
1492 int lane);
1493u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
1494 unsigned int lane);
1495
1496#define DP_BRANCH_OUI_HEADER_SIZE 0xc
1497#define DP_RECEIVER_CAP_SIZE 0xf
1498#define DP_DSC_RECEIVER_CAP_SIZE 0xf
1499#define EDP_PSR_RECEIVER_CAP_SIZE 2
1500#define EDP_DISPLAY_CTL_CAP_SIZE 3
1501#define DP_LTTPR_COMMON_CAP_SIZE 8
1502#define DP_LTTPR_PHY_CAP_SIZE 3
1503
1504void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
1505 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1506void drm_dp_lttpr_link_train_clock_recovery_delay(void);
1507void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
1508 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1509void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
1510 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
1511
1512u8 drm_dp_link_rate_to_bw_code(int link_rate);
1513int drm_dp_bw_code_to_link_rate(u8 link_bw);
1514
1515#define DP_SDP_AUDIO_TIMESTAMP 0x01
1516#define DP_SDP_AUDIO_STREAM 0x02
1517#define DP_SDP_EXTENSION 0x04
1518#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05
1519#define DP_SDP_ISRC 0x06
1520#define DP_SDP_VSC 0x07
1521#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i))
1522#define DP_SDP_PPS 0x10
1523#define DP_SDP_VSC_EXT_VESA 0x20
1524#define DP_SDP_VSC_EXT_CEA 0x21
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534struct dp_sdp_header {
1535 u8 HB0;
1536 u8 HB1;
1537 u8 HB2;
1538 u8 HB3;
1539} __packed;
1540
1541#define EDP_SDP_HEADER_REVISION_MASK 0x1F
1542#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1543#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566struct dp_sdp {
1567 struct dp_sdp_header sdp_header;
1568 u8 db[32];
1569} __packed;
1570
1571#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1572#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1573#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590enum dp_pixelformat {
1591 DP_PIXELFORMAT_RGB = 0,
1592 DP_PIXELFORMAT_YUV444 = 0x1,
1593 DP_PIXELFORMAT_YUV422 = 0x2,
1594 DP_PIXELFORMAT_YUV420 = 0x3,
1595 DP_PIXELFORMAT_Y_ONLY = 0x4,
1596 DP_PIXELFORMAT_RAW = 0x5,
1597 DP_PIXELFORMAT_RESERVED = 0x6,
1598};
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624enum dp_colorimetry {
1625 DP_COLORIMETRY_DEFAULT = 0,
1626 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1627 DP_COLORIMETRY_BT709_YCC = 0x1,
1628 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1629 DP_COLORIMETRY_XVYCC_601 = 0x2,
1630 DP_COLORIMETRY_OPRGB = 0x3,
1631 DP_COLORIMETRY_XVYCC_709 = 0x3,
1632 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1633 DP_COLORIMETRY_SYCC_601 = 0x4,
1634 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1635 DP_COLORIMETRY_OPYCC_601 = 0x5,
1636 DP_COLORIMETRY_BT2020_RGB = 0x6,
1637 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1638 DP_COLORIMETRY_BT2020_YCC = 0x7,
1639};
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651enum dp_dynamic_range {
1652 DP_DYNAMIC_RANGE_VESA = 0,
1653 DP_DYNAMIC_RANGE_CTA = 1,
1654};
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670enum dp_content_type {
1671 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1672 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1673 DP_CONTENT_TYPE_PHOTO = 0x02,
1674 DP_CONTENT_TYPE_VIDEO = 0x03,
1675 DP_CONTENT_TYPE_GAME = 0x04,
1676};
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694struct drm_dp_vsc_sdp {
1695 unsigned char sdp_type;
1696 unsigned char revision;
1697 unsigned char length;
1698 enum dp_pixelformat pixelformat;
1699 enum dp_colorimetry colorimetry;
1700 int bpc;
1701 enum dp_dynamic_range dynamic_range;
1702 enum dp_content_type content_type;
1703};
1704
1705void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
1706 const struct drm_dp_vsc_sdp *vsc);
1707
1708int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1709
1710static inline int
1711drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1712{
1713 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1714}
1715
1716static inline u8
1717drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1718{
1719 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1720}
1721
1722static inline bool
1723drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1724{
1725 return dpcd[DP_DPCD_REV] >= 0x11 &&
1726 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1727}
1728
1729static inline bool
1730drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1731{
1732 return dpcd[DP_DPCD_REV] >= 0x11 &&
1733 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
1734}
1735
1736static inline bool
1737drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1738{
1739 return dpcd[DP_DPCD_REV] >= 0x12 &&
1740 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1741}
1742
1743static inline bool
1744drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1745{
1746 return dpcd[DP_DPCD_REV] >= 0x14 &&
1747 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1748}
1749
1750static inline u8
1751drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1752{
1753 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1754 DP_TRAINING_PATTERN_MASK;
1755}
1756
1757static inline bool
1758drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1759{
1760 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1761}
1762
1763
1764u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1765 bool is_edp);
1766u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
1767int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
1768 u8 dsc_bpc[3]);
1769
1770static inline bool
1771drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1772{
1773 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
1774 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
1775}
1776
1777static inline u16
1778drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1779{
1780 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
1781 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
1782 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
1783 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
1784}
1785
1786static inline u32
1787drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1788{
1789
1790 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
1791 DP_DSC_SLICE_WIDTH_MULTIPLIER;
1792}
1793
1794
1795static inline bool
1796drm_dp_sink_supports_fec(const u8 fec_capable)
1797{
1798 return fec_capable & DP_FEC_CAPABLE;
1799}
1800
1801static inline bool
1802drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1803{
1804 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
1805}
1806
1807static inline bool
1808drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1809{
1810 return dpcd[DP_EDP_CONFIGURATION_CAP] &
1811 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
1812}
1813
1814
1815static inline bool
1816drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1817{
1818 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1819 DP_MSA_TIMING_PAR_IGNORED;
1820}
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833static inline bool
1834drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
1835{
1836 return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
1837 (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
1838}
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852struct drm_dp_aux_msg {
1853 unsigned int address;
1854 u8 request;
1855 u8 reply;
1856 void *buffer;
1857 size_t size;
1858};
1859
1860struct cec_adapter;
1861struct edid;
1862struct drm_connector;
1863
1864
1865
1866
1867
1868
1869
1870
1871struct drm_dp_aux_cec {
1872 struct mutex lock;
1873 struct cec_adapter *adap;
1874 struct drm_connector *connector;
1875 struct delayed_work unregister_work;
1876};
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891struct drm_dp_aux {
1892
1893
1894
1895
1896
1897
1898
1899 const char *name;
1900
1901
1902
1903
1904
1905 struct i2c_adapter ddc;
1906
1907
1908
1909
1910
1911 struct device *dev;
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924 struct drm_device *drm_dev;
1925
1926
1927
1928
1929
1930 struct drm_crtc *crtc;
1931
1932
1933
1934
1935
1936
1937
1938
1939 struct mutex hw_mutex;
1940
1941
1942
1943
1944 struct work_struct crc_work;
1945
1946
1947
1948
1949 u8 crc_count;
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977 ssize_t (*transfer)(struct drm_dp_aux *aux,
1978 struct drm_dp_aux_msg *msg);
1979
1980
1981
1982
1983 unsigned i2c_nack_count;
1984
1985
1986
1987 unsigned i2c_defer_count;
1988
1989
1990
1991 struct drm_dp_aux_cec cec;
1992
1993
1994
1995 bool is_remote;
1996};
1997
1998ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1999 void *buffer, size_t size);
2000ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
2001 void *buffer, size_t size);
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
2013 unsigned int offset, u8 *valuep)
2014{
2015 return drm_dp_dpcd_read(aux, offset, valuep, 1);
2016}
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
2028 unsigned int offset, u8 value)
2029{
2030 return drm_dp_dpcd_write(aux, offset, &value, 1);
2031}
2032
2033int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
2034 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
2035
2036int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
2037 u8 status[DP_LINK_STATUS_SIZE]);
2038
2039int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
2040 enum drm_dp_phy dp_phy,
2041 u8 link_status[DP_LINK_STATUS_SIZE]);
2042
2043bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
2044 u8 real_edid_checksum);
2045
2046int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
2047 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2048 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
2049bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2050 const u8 port_cap[4], u8 type);
2051bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2052 const u8 port_cap[4],
2053 const struct edid *edid);
2054int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2055 const u8 port_cap[4]);
2056int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2057 const u8 port_cap[4],
2058 const struct edid *edid);
2059int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2060 const u8 port_cap[4],
2061 const struct edid *edid);
2062int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2063 const u8 port_cap[4],
2064 const struct edid *edid);
2065bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2066 const u8 port_cap[4]);
2067bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2068 const u8 port_cap[4]);
2069struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
2070 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2071 const u8 port_cap[4]);
2072int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
2073void drm_dp_downstream_debug(struct seq_file *m,
2074 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2075 const u8 port_cap[4],
2076 const struct edid *edid,
2077 struct drm_dp_aux *aux);
2078enum drm_mode_subconnector
2079drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2080 const u8 port_cap[4]);
2081void drm_dp_set_subconnector_property(struct drm_connector *connector,
2082 enum drm_connector_status status,
2083 const u8 *dpcd,
2084 const u8 port_cap[4]);
2085
2086struct drm_dp_desc;
2087bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
2088 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2089 const struct drm_dp_desc *desc);
2090int drm_dp_read_sink_count(struct drm_dp_aux *aux);
2091
2092int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2093 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2094int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2095 enum drm_dp_phy dp_phy,
2096 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2097int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
2098int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2099int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
2100bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2101bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
2102
2103void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
2104void drm_dp_aux_init(struct drm_dp_aux *aux);
2105int drm_dp_aux_register(struct drm_dp_aux *aux);
2106void drm_dp_aux_unregister(struct drm_dp_aux *aux);
2107
2108int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
2109int drm_dp_stop_crc(struct drm_dp_aux *aux);
2110
2111struct drm_dp_dpcd_ident {
2112 u8 oui[3];
2113 u8 device_id[6];
2114 u8 hw_rev;
2115 u8 sw_major_rev;
2116 u8 sw_minor_rev;
2117} __packed;
2118
2119
2120
2121
2122
2123
2124struct drm_dp_desc {
2125 struct drm_dp_dpcd_ident ident;
2126 u32 quirks;
2127};
2128
2129int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2130 bool is_branch);
2131
2132
2133
2134
2135
2136
2137
2138
2139enum drm_dp_quirk {
2140
2141
2142
2143
2144
2145
2146 DP_DPCD_QUIRK_CONSTANT_N,
2147
2148
2149
2150
2151
2152
2153 DP_DPCD_QUIRK_NO_PSR,
2154
2155
2156
2157
2158
2159
2160
2161 DP_DPCD_QUIRK_NO_SINK_COUNT,
2162
2163
2164
2165
2166
2167
2168 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
2169
2170
2171
2172
2173
2174
2175 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
2176};
2177
2178
2179
2180
2181
2182
2183
2184
2185static inline bool
2186drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
2187{
2188 return desc->quirks & BIT(quirk);
2189}
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202struct drm_edp_backlight_info {
2203 u8 pwmgen_bit_count;
2204 u8 pwm_freq_pre_divider;
2205 u16 max;
2206
2207 bool lsb_reg_used : 1;
2208 bool aux_enable : 1;
2209};
2210
2211int
2212drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
2213 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
2214 u16 *current_level, u8 *current_mode);
2215int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
2216 u16 level);
2217int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
2218 u16 level);
2219int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
2220
2221#if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
2222 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
2223
2224int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
2225
2226#else
2227
2228static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
2229 struct drm_dp_aux *aux)
2230{
2231 return 0;
2232}
2233
2234#endif
2235
2236#ifdef CONFIG_DRM_DP_CEC
2237void drm_dp_cec_irq(struct drm_dp_aux *aux);
2238void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
2239 struct drm_connector *connector);
2240void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
2241void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
2242void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
2243#else
2244static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
2245{
2246}
2247
2248static inline void
2249drm_dp_cec_register_connector(struct drm_dp_aux *aux,
2250 struct drm_connector *connector)
2251{
2252}
2253
2254static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
2255{
2256}
2257
2258static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
2259 const struct edid *edid)
2260{
2261}
2262
2263static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
2264{
2265}
2266
2267#endif
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278struct drm_dp_phy_test_params {
2279 int link_rate;
2280 u8 num_lanes;
2281 u8 phy_pattern;
2282 u8 hbr2_reset[2];
2283 u8 custom80[10];
2284 bool enhanced_frame_cap;
2285};
2286
2287int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2288 struct drm_dp_phy_test_params *data);
2289int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2290 struct drm_dp_phy_test_params *data, u8 dp_rev);
2291int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2292 const u8 port_cap[4]);
2293int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
2294bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
2295int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2296 u8 frl_mode);
2297int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
2298 u8 frl_type);
2299int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
2300int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
2301
2302bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
2303int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
2304void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
2305 struct drm_connector *connector);
2306bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2307int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2308int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2309int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
2310int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
2311int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
2312int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
2313bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2314 const u8 port_cap[4], u8 color_spc);
2315int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
2316
2317#endif
2318